It was incorrectly comparing the OpenGL version and the GLSL
version, plus the pointer arithmetic broke with debug builds
Also rename the misleadingly-named array and fix logging
- properly order the elements in QGridLayouts
- add non-generic names to text labels and some layouts
- fix enums for Qt 5 Designer compatibility
- fix tab order on some settings dialog pages
1. The S3 968-based Diamond Stealth 64 Video VRAM, using a 14mhz reference clock, now has its RGB528 fixed Pixel PLL reference divider set to its default value (0x07) per manual and reference clock. Fixes wrong refresh rates on said cards and others.
2. Added the ICS2494-324 clock generator to the ET4000AX. Fixes wrong refresh rates on this one too.
* Add two 430FX-based Vectras code.
* Add two 430FX-based Vectras machine table entries.
* Organize the 430FX-based Vectras code.
* Add machine definitions for the two 430FX-based Vectras.
* Add the Vectra 500 Series xxx/MT to the GPIO values from the VL/5...
makes it report CPU clocks properly.
* Darn, forgot something.
* Updated and fix the BIOS selector for VE 5/xxx Series 2
1. In the STG code, separated the STG1703 without its built-in clock as 1702 while keeping the one with the clock as 1703.
2. Added the ICS2494AN-324 clock generator used by the et4000w32 series.
3. Return 0x98 as the ID of the ATT498 ramdac.
4. Corrected the pixel clocks of the IBM RGB528 while keeping its current compatibility and exactness of the refresh rates of its clocks.
5. Added a variable reference clock of the SDAC/GenDAC for future use.
6. The clocks of the TVP3026 have been implemented for a while. Some corrections have been made (plus color key r/w).
7. Mach64 enhanced mode doesn't use scrollcache (bits 0-3 of attrregs 0x13), fixes some pixels being off (mainly in win3.1x)
8. Reorganized the cirrus 54xx built-in clock for proper refresh rates.
9. Proper reorganization of the et4000w32 series of chipsets and their cards supporting them, from cursor to clocks to ramdacs plus a 24bpp acceleration fix for the w32p series (about pixels being processed in bitblt).
10. Removed the PCI videomagic card as its bios doesn't have the PCIR header while making sure the plain ISA/VLB w32 and ISA only w32i (now named Axis Microdevice) support 2mb of vram properly.
11. Added the Hercules Dynamite VL Pro based on the w32i chip (and VLB).
12. Initialize the et4000w32 cards with misc bit 0 set as well as crtc31 bit 6 for rs2 connection to the ramdac.
13. Refactored the S3 Pre-ViRGE code to have proper refresh rates and clocks and added the 805I as a member of the chips (ID 0xa8).
14. Replaced the S3 805I Elsa Winner 1000 ISA bios with a more supported one for our code using the SDAC.
15. Added proper 24bpp acceleration to the Visionx68 chips.
16. Fixed wrong colors in the 911/924 15/16bpp acceleration when used for the first time.
17. Match the ViRGE mapping to the pre-ViRGE one per manual/datasheet.
18. Correct as best as possible the TGUI9400 clocks.
1. In the STG code, separated the STG1703 without its built-in clock as 1702 while keeping the one with the clock as 1703.
2. Added the ICS2494AN-324 clock generator used by the et4000w32 series.
3. Return 0x98 as the ID of the ATT498 ramdac.
4. Corrected the pixel clocks of the IBM RGB528 while keeping its current compatibility and exactness of the refresh rates of its clocks.
5. Added a variable reference clock of the SDAC/GenDAC for future use.
6. The clocks of the TVP3026 have been implemented for a while. Some corrections have been made (plus color key r/w).
7. Mach64 enhanced mode doesn't use scrollcache (bits 0-3 of attrregs 0x13), fixes some pixels being off (mainly in win3.1x)
8. Reorganized the cirrus 54xx built-in clock for proper refresh rates.
9. Proper reorganization of the et4000w32 series of chipsets and their cards supporting them, from cursor to clocks to ramdacs plus a 24bpp acceleration fix for the w32p series (about pixels being processed in bitblt).
10. Removed the PCI videomagic card as its bios doesn't have the PCIR header while making sure the plain ISA/VLB w32 and ISA only w32i (now named Axis Microdevice) support 2mb of vram properly.
11. Added the Hercules Dynamite VL Pro based on the w32i chip (and VLB).
12. Initialize the et4000w32 cards with misc bit 0 set as well as crtc31 bit 6 for rs2 connection to the ramdac.
13. Refactored the S3 Pre-ViRGE code to have proper refresh rates and clocks and added the 805I as a member of the chips (ID 0xa8).
14. Replaced the S3 805I Elsa Winner 1000 ISA bios with a more supported one for our code using the SDAC.
15. Added proper 24bpp acceleration to the Visionx68 chips.
16. Fixed wrong colors in the 911/924 15/16bpp acceleration when used for the first time.
17. Match the ViRGE mapping to the pre-ViRGE one per manual/datasheet.
18. Correct as best as possible the TGUI9400 clocks.
* Added beta v4.51G BIOS to P5MP3
* Added the earliest 4.51PG BIOS to AX59 Pro
Also internal_name corrections
* Added the non-OEM(?) BIOS to 6110Zu
* Added the non-OEM 4.51PG and unofficial 6.00PG
BIOSes to Compaq Compaq ProSignia S31x, which is renamed into ECS P6BXT-A+.
Also unblock Cyrix CPUs as well as unofficial 6.00PG BIOS supports them.
* Removed the v4.51PG due to POST failure
Also slightly changed the maximum voltage bus to 124MHz per unofficial v6.00 BIOS, corrected the BIOS name per the BIOS screen on that BIOS, and added the author credit.
Also lowered the minimum memory on LG IBM MS-6106 to 8mb.
* Added the 050591 BIOS to DataExpert 386WB
* Renamed 386WB to 386C
* Make configurations intact
Per OBattler.
* sio_fdc37m60x.c: FDC37C93x -> FDC37M60x
Rename the Super I/O chip name "SMC FDC37C93x Super I/O" to "SMC FDC37M60x Super I/O".
* sio_w83977.c: SMC FDC37C93x -> Winbond W83977
Rename "SMC FDC37C93x Super I/O" to "Winbond W83977 Super I/O".
* sio_w83977.c: W83977 -> W83977F/TF/EF
* Switch CD audio and OPL3 filters on AZT2316 mode switch, fixes FM and CD volume control on Windows
* Add support for I/O port 630h (as used on PB Forte16 cards) to the MKE/Panasonic interface
