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Implement pixel mask registers.

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This commit is contained in:
starfrost013
2025-02-05 18:46:38 +00:00
parent 655f1f202f
commit acd0dc40bb
3 changed files with 9 additions and 1 deletions
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2
src/include/86box/nv/vid_nv3.h
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@@ -593,6 +593,8 @@ extern const device_config_t nv3_config[];
#define NV3_PRAMDAC_END 0x680FFF
#define NV3_PDAC_END 0x680FFF // OPTIONAL external DAC
#define NV3_VGA_DAC_START 0x6813C6
#define NV3_VGA_DAC_END 0x6813C9
#define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO (up to 0x880000?)
#define NV3_USER_END 0xFFFFFF

3
src/video/nv/nv3/nv3_core.c
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@@ -46,7 +46,8 @@ bool nv3_is_svga_redirect_address(uint32_t addr)
|| addr == NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR
|| addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR
|| addr == NV3_PRMCIO_CRTC_REGISTER_CUR_MONO
|| addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO);
|| addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO
|| (addr >= NV3_VGA_DAC_START && addr <= NV3_VGA_DAC_END));
}
// All MMIO regs are 32-bit i believe internally

5
src/video/nv/nv3/subsystems/nv3_pfb.c
View File

@@ -144,10 +144,15 @@ void nv3_pfb_config0_write(uint32_t val)
// so we don't update things here for now
uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5;
// i don't think 16:9 is supported
uint32_t new_pfb_vtotal = new_pfb_htotal * (4/3);
uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03;
nv_log("NV3: Framebuffer Config Change\n");
nv_log("NV3: Horizontal Size=%d pixels\n", new_pfb_htotal);
nv_log("NV3: Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal);
if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_8BPP)
nv_log("NV3: Bit Depth=8bpp\n");
else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_16BPP)