diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index 3d4bd9b0a..5bc967911 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -593,6 +593,8 @@ extern const device_config_t nv3_config[]; #define NV3_PRAMDAC_END 0x680FFF #define NV3_PDAC_END 0x680FFF // OPTIONAL external DAC +#define NV3_VGA_DAC_START 0x6813C6 +#define NV3_VGA_DAC_END 0x6813C9 #define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO (up to 0x880000?) #define NV3_USER_END 0xFFFFFF diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c index c6944ad28..c185af738 100644 --- a/src/video/nv/nv3/nv3_core.c +++ b/src/video/nv/nv3/nv3_core.c @@ -46,7 +46,8 @@ bool nv3_is_svga_redirect_address(uint32_t addr) || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_MONO - || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO); + || addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO + || (addr >= NV3_VGA_DAC_START && addr <= NV3_VGA_DAC_END)); } // All MMIO regs are 32-bit i believe internally diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c index 510c61e6a..ba42c1734 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfb.c +++ b/src/video/nv/nv3/subsystems/nv3_pfb.c @@ -144,10 +144,15 @@ void nv3_pfb_config0_write(uint32_t val) // so we don't update things here for now uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5; + // i don't think 16:9 is supported + uint32_t new_pfb_vtotal = new_pfb_htotal * (4/3); + uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03; nv_log("NV3: Framebuffer Config Change\n"); nv_log("NV3: Horizontal Size=%d pixels\n", new_pfb_htotal); + nv_log("NV3: Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal); + if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_8BPP) nv_log("NV3: Bit Depth=8bpp\n"); else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_16BPP)