mirror of
https://github.com/86Box/86Box.git
synced 2026-02-22 09:35:32 -07:00
Rewrote the disc sector poller again for simplified code and more accuracy;
Floppy formats are now accurately timed and also more accurately implemented; Applied all mainline PCem commits.
This commit is contained in:
81
src/386.c
81
src/386.c
@@ -1,6 +1,3 @@
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/* Copyright holders: Sarah Walker
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see COPYING for more details
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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@@ -18,8 +15,6 @@
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extern int codegen_flags_changed;
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x86seg *ea_seg;
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extern int nmi_enable;
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int inscounts[256];
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@@ -44,7 +39,7 @@ int cgate32;
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uint8_t romext[32768];
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uint8_t *ram,*rom;
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uint32_t biosmask;
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uint16_t biosmask;
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uint32_t rmdat32;
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#define rmdat rmdat32
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@@ -56,8 +51,6 @@ int inttype,abrt;
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uint32_t oldcs2;
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uint32_t oldecx;
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uint32_t op32;
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uint32_t *eal_r, *eal_w;
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@@ -67,8 +60,8 @@ uint32_t *mod1seg[8];
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static inline void fetch_ea_32_long(uint32_t rmdat)
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{
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eal_r = eal_w = NULL;
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easeg = ea_seg->base;
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ea_rseg = ea_seg->seg;
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easeg = cpu_state.ea_seg->base;
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ea_rseg = cpu_state.ea_seg->seg;
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if (cpu_rm == 4)
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{
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uint8_t sib = rmdat >> 8;
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@@ -76,60 +69,60 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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switch (cpu_mod)
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{
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case 0:
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eaaddr = cpu_state.regs[sib & 7].l;
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cpu_state.eaaddr = cpu_state.regs[sib & 7].l;
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cpu_state.pc++;
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break;
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case 1:
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cpu_state.pc++;
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eaaddr = ((uint32_t)(int8_t)getbyte()) + cpu_state.regs[sib & 7].l;
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cpu_state.eaaddr = ((uint32_t)(int8_t)getbyte()) + cpu_state.regs[sib & 7].l;
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// pc++;
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break;
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case 2:
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eaaddr = (fastreadl(cs + cpu_state.pc + 1)) + cpu_state.regs[sib & 7].l;
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cpu_state.eaaddr = (fastreadl(cs + cpu_state.pc + 1)) + cpu_state.regs[sib & 7].l;
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cpu_state.pc += 5;
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break;
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}
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/*SIB byte present*/
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if ((sib & 7) == 5 && !cpu_mod)
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eaaddr = getlong();
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else if ((sib & 6) == 4 && !ssegs)
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cpu_state.eaaddr = getlong();
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else if ((sib & 6) == 4 && !cpu_state.ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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ea_seg = &_ss;
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cpu_state.ea_seg = &_ss;
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}
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if (((sib >> 3) & 7) != 4)
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eaaddr += cpu_state.regs[(sib >> 3) & 7].l << (sib >> 6);
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cpu_state.eaaddr += cpu_state.regs[(sib >> 3) & 7].l << (sib >> 6);
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}
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else
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{
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eaaddr = cpu_state.regs[cpu_rm].l;
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cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
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if (cpu_mod)
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{
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if (cpu_rm == 5 && !ssegs)
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if (cpu_rm == 5 && !cpu_state.ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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ea_seg = &_ss;
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cpu_state.ea_seg = &_ss;
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}
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if (cpu_mod == 1)
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{
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eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
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cpu_state.eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
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cpu_state.pc++;
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}
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else
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{
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eaaddr += getlong();
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cpu_state.eaaddr += getlong();
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}
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}
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else if (cpu_rm == 5)
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{
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eaaddr = getlong();
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cpu_state.eaaddr = getlong();
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}
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}
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if (easeg != 0xFFFFFFFF && ((easeg + eaaddr) & 0xFFF) <= 0xFFC)
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if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
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{
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uint32_t addr = easeg + eaaddr;
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uint32_t addr = easeg + cpu_state.eaaddr;
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if ( readlookup2[addr >> 12] != -1)
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eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
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if (writelookup2[addr >> 12] != -1)
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@@ -140,38 +133,38 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
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static inline void fetch_ea_16_long(uint32_t rmdat)
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{
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eal_r = eal_w = NULL;
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easeg = ea_seg->base;
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ea_rseg = ea_seg->seg;
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easeg = cpu_state.ea_seg->base;
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ea_rseg = cpu_state.ea_seg->seg;
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if (!cpu_mod && cpu_rm == 6)
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{
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eaaddr = getword();
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cpu_state.eaaddr = getword();
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}
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else
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{
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switch (cpu_mod)
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{
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case 0:
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eaaddr = 0;
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cpu_state.eaaddr = 0;
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break;
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case 1:
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eaaddr = (uint16_t)(int8_t)(rmdat >> 8); cpu_state.pc++;
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cpu_state.eaaddr = (uint16_t)(int8_t)(rmdat >> 8); cpu_state.pc++;
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break;
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case 2:
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eaaddr = getword();
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cpu_state.eaaddr = getword();
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break;
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}
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eaaddr += (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
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if (mod1seg[cpu_rm] == &ss && !ssegs)
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cpu_state.eaaddr += (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
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if (mod1seg[cpu_rm] == &ss && !cpu_state.ssegs)
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{
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easeg = ss;
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ea_rseg = SS;
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ea_seg = &_ss;
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cpu_state.ea_seg = &_ss;
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}
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eaaddr &= 0xFFFF;
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cpu_state.eaaddr &= 0xFFFF;
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}
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if (easeg != 0xFFFFFFFF && ((easeg + eaaddr) & 0xFFF) <= 0xFFC)
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if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
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{
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uint32_t addr = easeg + eaaddr;
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uint32_t addr = easeg + cpu_state.eaaddr;
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if ( readlookup2[addr >> 12] != -1)
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eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
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if (writelookup2[addr >> 12] != -1)
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@@ -241,14 +234,14 @@ void exec386(int cycs)
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// oldpc2=oldpc;
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opcode_realstart:
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oldcs=CS;
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oldpc=cpu_state.pc;
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cpu_state.oldpc = cpu_state.pc;
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oldcpl=CPL;
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op32=use32;
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cpu_state.op32 = use32;
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dontprint=0;
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ea_seg = &_ds;
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ssegs = 0;
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cpu_state.ea_seg = &_ds;
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cpu_state.ssegs = 0;
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opcodestart:
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fetchdat = fastreadl(cs + cpu_state.pc);
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@@ -264,7 +257,7 @@ opcodestart:
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pclog("%04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X %08X %i %i %02X %02X %02X %02X %02X %f %02X%02X %02X%02X %02X%02X %02X\n",CS,cs,cpu_state.pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, pit.c[0], ram[0xB270+0x3F5], ram[0xB270+0x3F4], ram[0xB270+0x3F7], ram[0xB270+0x3F6], ram[0xB270+0x3F9], ram[0xB270+0x3F8], ram[0x4430+0x0D49]);
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}
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cpu_state.pc++;
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x86_opcodes[(opcode | op32) & 0x3ff](fetchdat);
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x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
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}
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if (!use32) cpu_state.pc &= 0xffff;
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@@ -290,7 +283,7 @@ opcodestart:
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{
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abrt = 0;
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CS = oldcs;
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cpu_state.pc = oldpc;
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cpu_state.pc = cpu_state.oldpc;
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pclog("Double fault %i\n", ins);
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pmodeint(8, 0);
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if (abrt)
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@@ -327,7 +320,7 @@ opcodestart:
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}
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else if (nmi && nmi_enable)
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{
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oldpc = cpu_state.pc;
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cpu_state.oldpc = cpu_state.pc;
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oldcs = CS;
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// pclog("NMI\n");
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x86_int(2);
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@@ -266,7 +266,7 @@ static inline uint8_t geteab()
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return (cpu_rm & 4) ? cpu_state.regs[cpu_rm & 3].b.h : cpu_state.regs[cpu_rm&3].b.l;
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if (eal_r)
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return *(uint8_t *)eal_r;
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return readmemb(easeg, eaaddr);
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return readmemb(easeg, cpu_state.eaaddr);
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}
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static inline uint16_t geteaw()
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@@ -276,7 +276,7 @@ static inline uint16_t geteaw()
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// cycles-=3;
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if (eal_r)
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return *(uint16_t *)eal_r;
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return readmemw(easeg, eaaddr);
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return readmemw(easeg, cpu_state.eaaddr);
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}
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static inline uint32_t geteal()
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@@ -286,43 +286,43 @@ static inline uint32_t geteal()
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// cycles-=3;
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if (eal_r)
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return *eal_r;
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return readmeml(easeg, eaaddr);
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return readmeml(easeg, cpu_state.eaaddr);
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}
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static inline uint64_t geteaq()
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{
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return readmemq(easeg, eaaddr);
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return readmemq(easeg, cpu_state.eaaddr);
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}
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static inline uint8_t geteab_mem()
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{
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if (eal_r) return *(uint8_t *)eal_r;
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return readmemb(easeg,eaaddr);
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return readmemb(easeg,cpu_state.eaaddr);
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}
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static inline uint16_t geteaw_mem()
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{
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if (eal_r) return *(uint16_t *)eal_r;
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return readmemw(easeg,eaaddr);
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return readmemw(easeg,cpu_state.eaaddr);
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}
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static inline uint32_t geteal_mem()
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{
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if (eal_r) return *eal_r;
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return readmeml(easeg,eaaddr);
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return readmeml(easeg,cpu_state.eaaddr);
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}
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static inline void seteaq(uint64_t v)
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{
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writememql(easeg, eaaddr, v);
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writememql(easeg, cpu_state.eaaddr, v);
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}
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#define seteab(v) if (cpu_mod!=3) { if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,eaaddr,v); } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
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#define seteaw(v) if (cpu_mod!=3) { if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,eaaddr,v); } else cpu_state.regs[cpu_rm].w=v
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#define seteal(v) if (cpu_mod!=3) { if (eal_w) *eal_w=v; else writememll(easeg,eaaddr,v); } else cpu_state.regs[cpu_rm].l=v
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#define seteab_mem(v) if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,eaaddr,v);
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#define seteaw_mem(v) if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,eaaddr,v);
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#define seteal_mem(v) if (eal_w) *eal_w=v; else writememll(easeg,eaaddr,v);
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#define seteab(v) if (cpu_mod!=3) { if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,cpu_state.eaaddr,v); } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
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#define seteaw(v) if (cpu_mod!=3) { if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].w=v
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#define seteal(v) if (cpu_mod!=3) { if (eal_w) *eal_w=v; else writememll(easeg,cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].l=v
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|
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#define seteab_mem(v) if (eal_w) *(uint8_t *)eal_w=v; else writememb386l(easeg,cpu_state.eaaddr,v);
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#define seteaw_mem(v) if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg,cpu_state.eaaddr,v);
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#define seteal_mem(v) if (eal_w) *eal_w=v; else writememll(easeg,cpu_state.eaaddr,v);
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|
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#define getbytef() ((uint8_t)(fetchdat)); cpu_state.pc++
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#define getwordf() ((uint16_t)(fetchdat)); cpu_state.pc+=2
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#define getbyte2f() ((uint8_t)(fetchdat>>8)); cpu_state.pc++
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|
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@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
@@ -27,8 +24,6 @@ int cpu_recomp_blocks_latched, cpu_recomp_ins_latched, cpu_recomp_full_ins_latch
|
||||
|
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int cpu_block_end = 0;
|
||||
|
||||
x86seg *ea_seg;
|
||||
|
||||
int nmi_enable = 1;
|
||||
|
||||
int inscounts[256];
|
||||
@@ -52,7 +47,7 @@ int cgate32;
|
||||
|
||||
uint8_t romext[32768];
|
||||
uint8_t *ram,*rom;
|
||||
uint32_t biosmask;
|
||||
uint16_t biosmask;
|
||||
|
||||
uint32_t rmdat32;
|
||||
uint32_t backupregs[16];
|
||||
@@ -62,10 +57,6 @@ int inttype,abrt;
|
||||
|
||||
uint32_t oldcs2;
|
||||
uint32_t oldecx;
|
||||
uint32_t op32;
|
||||
|
||||
|
||||
|
||||
|
||||
uint32_t *eal_r, *eal_w;
|
||||
|
||||
@@ -75,8 +66,8 @@ uint32_t *mod1seg[8];
|
||||
static inline void fetch_ea_32_long(uint32_t rmdat)
|
||||
{
|
||||
eal_r = eal_w = NULL;
|
||||
easeg = ea_seg->base;
|
||||
ea_rseg = ea_seg->seg;
|
||||
easeg = cpu_state.ea_seg->base;
|
||||
ea_rseg = cpu_state.ea_seg->seg;
|
||||
if (cpu_rm == 4)
|
||||
{
|
||||
uint8_t sib = rmdat >> 8;
|
||||
@@ -84,109 +75,107 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
|
||||
switch (cpu_mod)
|
||||
{
|
||||
case 0:
|
||||
eaaddr = cpu_state.regs[sib & 7].l;
|
||||
cpu_state.eaaddr = cpu_state.regs[sib & 7].l;
|
||||
cpu_state.pc++;
|
||||
break;
|
||||
case 1:
|
||||
cpu_state.pc++;
|
||||
eaaddr = ((uint32_t)(int8_t)getbyte()) + cpu_state.regs[sib & 7].l;
|
||||
cpu_state.eaaddr = ((uint32_t)(int8_t)getbyte()) + cpu_state.regs[sib & 7].l;
|
||||
// cpu_state.pc++;
|
||||
break;
|
||||
case 2:
|
||||
eaaddr = (fastreadl(cs + cpu_state.pc + 1)) + cpu_state.regs[sib & 7].l;
|
||||
cpu_state.eaaddr = (fastreadl(cs + cpu_state.pc + 1)) + cpu_state.regs[sib & 7].l;
|
||||
cpu_state.pc += 5;
|
||||
break;
|
||||
}
|
||||
/*SIB byte present*/
|
||||
if ((sib & 7) == 5 && !cpu_mod)
|
||||
eaaddr = getlong();
|
||||
else if ((sib & 6) == 4 && !ssegs)
|
||||
cpu_state.eaaddr = getlong();
|
||||
else if ((sib & 6) == 4 && !cpu_state.ssegs)
|
||||
{
|
||||
easeg = ss;
|
||||
ea_rseg = SS;
|
||||
ea_seg = &_ss;
|
||||
cpu_state.ea_seg = &_ss;
|
||||
}
|
||||
if (((sib >> 3) & 7) != 4)
|
||||
eaaddr += cpu_state.regs[(sib >> 3) & 7].l << (sib >> 6);
|
||||
cpu_state.eaaddr += cpu_state.regs[(sib >> 3) & 7].l << (sib >> 6);
|
||||
}
|
||||
else
|
||||
{
|
||||
eaaddr = cpu_state.regs[cpu_rm].l;
|
||||
cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
|
||||
if (cpu_mod)
|
||||
{
|
||||
if (cpu_rm == 5 && !ssegs)
|
||||
if (cpu_rm == 5 && !cpu_state.ssegs)
|
||||
{
|
||||
easeg = ss;
|
||||
ea_rseg = SS;
|
||||
ea_seg = &_ss;
|
||||
cpu_state.ea_seg = &_ss;
|
||||
}
|
||||
if (cpu_mod == 1)
|
||||
{
|
||||
eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
|
||||
cpu_state.eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
|
||||
cpu_state.pc++;
|
||||
}
|
||||
else
|
||||
{
|
||||
eaaddr += getlong();
|
||||
cpu_state.eaaddr += getlong();
|
||||
}
|
||||
}
|
||||
else if (cpu_rm == 5)
|
||||
{
|
||||
eaaddr = getlong();
|
||||
cpu_state.eaaddr = getlong();
|
||||
}
|
||||
}
|
||||
if (easeg != 0xFFFFFFFF && ((easeg + eaaddr) & 0xFFF) <= 0xFFC)
|
||||
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
|
||||
{
|
||||
uint32_t addr = easeg + eaaddr;
|
||||
uint32_t addr = easeg + cpu_state.eaaddr;
|
||||
if ( readlookup2[addr >> 12] != -1)
|
||||
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
|
||||
if (writelookup2[addr >> 12] != -1)
|
||||
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
|
||||
}
|
||||
cpu_state.last_ea = eaaddr;
|
||||
}
|
||||
|
||||
static inline void fetch_ea_16_long(uint32_t rmdat)
|
||||
{
|
||||
eal_r = eal_w = NULL;
|
||||
easeg = ea_seg->base;
|
||||
ea_rseg = ea_seg->seg;
|
||||
easeg = cpu_state.ea_seg->base;
|
||||
ea_rseg = cpu_state.ea_seg->seg;
|
||||
if (!cpu_mod && cpu_rm == 6)
|
||||
{
|
||||
eaaddr = getword();
|
||||
cpu_state.eaaddr = getword();
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (cpu_mod)
|
||||
{
|
||||
case 0:
|
||||
eaaddr = 0;
|
||||
cpu_state.eaaddr = 0;
|
||||
break;
|
||||
case 1:
|
||||
eaaddr = (uint16_t)(int8_t)(rmdat >> 8); cpu_state.pc++;
|
||||
cpu_state.eaaddr = (uint16_t)(int8_t)(rmdat >> 8); cpu_state.pc++;
|
||||
break;
|
||||
case 2:
|
||||
eaaddr = getword();
|
||||
cpu_state.eaaddr = getword();
|
||||
break;
|
||||
}
|
||||
eaaddr += (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
|
||||
if (mod1seg[cpu_rm] == &ss && !ssegs)
|
||||
cpu_state.eaaddr += (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
|
||||
if (mod1seg[cpu_rm] == &ss && !cpu_state.ssegs)
|
||||
{
|
||||
easeg = ss;
|
||||
ea_rseg = SS;
|
||||
ea_seg = &_ss;
|
||||
cpu_state.ea_seg = &_ss;
|
||||
}
|
||||
eaaddr &= 0xFFFF;
|
||||
cpu_state.eaaddr &= 0xFFFF;
|
||||
}
|
||||
if (easeg != 0xFFFFFFFF && ((easeg + eaaddr) & 0xFFF) <= 0xFFC)
|
||||
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
|
||||
{
|
||||
uint32_t addr = easeg + eaaddr;
|
||||
uint32_t addr = easeg + cpu_state.eaaddr;
|
||||
if ( readlookup2[addr >> 12] != -1)
|
||||
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
|
||||
if (writelookup2[addr >> 12] != -1)
|
||||
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
|
||||
}
|
||||
cpu_state.last_ea = eaaddr;
|
||||
}
|
||||
|
||||
#define fetch_ea_16(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_16_long(rmdat); if (abrt) return 1; }
|
||||
@@ -199,7 +188,7 @@ void x86_int(int num)
|
||||
uint32_t addr;
|
||||
// pclog("x86_int %02x %04x:%04x\n", num, CS,pc);
|
||||
flags_rebuild();
|
||||
cpu_state.pc=oldpc;
|
||||
cpu_state.pc=cpu_state.oldpc;
|
||||
if (msw&1)
|
||||
{
|
||||
pmodeint(num,0);
|
||||
@@ -272,13 +261,10 @@ void x86_int_sw(int num)
|
||||
CPU_BLOCK_END();
|
||||
}
|
||||
|
||||
int prev_prev_opcode = 0;
|
||||
int prev_opcode = 0;
|
||||
|
||||
void x86illegal()
|
||||
{
|
||||
uint16_t addr;
|
||||
pclog("x86 illegal %04X %08X %04X:%08X %02X (prev. %02X, prev. prev. %02X)\n",msw,cr0,CS,cpu_state.pc,opcode,prev_opcode,prev_prev_opcode);
|
||||
// pclog("x86 illegal %04X %08X %04X:%08X %02X\n",msw,cr0,CS,pc,opcode);
|
||||
|
||||
// if (output)
|
||||
// {
|
||||
@@ -295,9 +281,9 @@ int rep386(int fv)
|
||||
uint32_t c;//=CX;
|
||||
uint8_t temp2;
|
||||
uint16_t tempw,tempw2,of;
|
||||
uint32_t ipc=oldpc;//pc-1;
|
||||
uint32_t ipc = cpu_state.oldpc;//pc-1;
|
||||
uint32_t oldds;
|
||||
uint32_t rep32=op32;
|
||||
uint32_t rep32 = cpu_state.op32;
|
||||
uint32_t templ,templ2;
|
||||
int tempz;
|
||||
int tempi;
|
||||
@@ -307,8 +293,8 @@ int rep386(int fv)
|
||||
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100);
|
||||
|
||||
if (trap)
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/
|
||||
|
||||
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/
|
||||
|
||||
cpu_reps++;
|
||||
|
||||
flags_rebuild();
|
||||
@@ -332,23 +318,23 @@ int rep386(int fv)
|
||||
cpu_state.pc=ipc+1;
|
||||
break;
|
||||
case 0x26: case 0x126: case 0x226: case 0x326: /*ES:*/
|
||||
ea_seg = &_es;
|
||||
cpu_state.ea_seg = &_es;
|
||||
goto startrep;
|
||||
break;
|
||||
case 0x2E: case 0x12E: case 0x22E: case 0x32E: /*CS:*/
|
||||
ea_seg = &_cs;
|
||||
cpu_state.ea_seg = &_cs;
|
||||
goto startrep;
|
||||
case 0x36: case 0x136: case 0x236: case 0x336: /*SS:*/
|
||||
ea_seg = &_ss;
|
||||
cpu_state.ea_seg = &_ss;
|
||||
goto startrep;
|
||||
case 0x3E: case 0x13E: case 0x23E: case 0x33E: /*DS:*/
|
||||
ea_seg = &_ds;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
goto startrep;
|
||||
case 0x64: case 0x164: case 0x264: case 0x364: /*FS:*/
|
||||
ea_seg = &_fs;
|
||||
cpu_state.ea_seg = &_fs;
|
||||
goto startrep;
|
||||
case 0x65: case 0x165: case 0x265: case 0x365: /*GS:*/
|
||||
ea_seg = &_gs;
|
||||
cpu_state.ea_seg = &_gs;
|
||||
goto startrep;
|
||||
case 0x66: case 0x166: case 0x266: case 0x366: /*Data size prefix*/
|
||||
rep32 = (rep32 & 0x200) | ((use32 ^ 0x100) & 0x100);
|
||||
@@ -453,7 +439,7 @@ int rep386(int fv)
|
||||
// cpu_notreps++;
|
||||
if (c>0)
|
||||
{
|
||||
temp2 = readmemb(ea_seg->base, SI);
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
checkio_perm(DX);
|
||||
outb(DX,temp2);
|
||||
@@ -469,7 +455,7 @@ int rep386(int fv)
|
||||
// cpu_notreps++;
|
||||
if (c>0)
|
||||
{
|
||||
temp2 = readmemb(ea_seg->base, ESI);
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
checkio_perm(DX);
|
||||
outb(DX,temp2);
|
||||
@@ -485,7 +471,7 @@ int rep386(int fv)
|
||||
// cpu_notreps++;
|
||||
if (c>0)
|
||||
{
|
||||
tempw = readmemw(ea_seg->base, SI);
|
||||
tempw = readmemw(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
// pclog("OUTSW %04X -> %04X\n",SI,tempw);
|
||||
outw(DX,tempw);
|
||||
@@ -501,7 +487,7 @@ int rep386(int fv)
|
||||
// cpu_notreps++;
|
||||
if (c > 0)
|
||||
{
|
||||
templ = readmeml(ea_seg->base, SI);
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
outl(DX, templ);
|
||||
if (flags & D_FLAG) SI -= 4;
|
||||
@@ -516,7 +502,7 @@ int rep386(int fv)
|
||||
// cpu_notreps++;
|
||||
if (c>0)
|
||||
{
|
||||
tempw = readmemw(ea_seg->base, ESI);
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
outw(DX,tempw);
|
||||
if (flags&D_FLAG) ESI-=2;
|
||||
@@ -531,7 +517,7 @@ int rep386(int fv)
|
||||
// cpu_notreps++;
|
||||
if (c > 0)
|
||||
{
|
||||
templ = readmeml(ea_seg->base, ESI);
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
outl(DX, templ);
|
||||
if (flags & D_FLAG) ESI -= 4;
|
||||
@@ -550,7 +536,7 @@ int rep386(int fv)
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI);
|
||||
temp2 = readmemb(ea_seg->base, SI); if (abrt) break;
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, SI); if (abrt) break;
|
||||
writememb(es,DI,temp2); if (abrt) break;
|
||||
// if (output==3) pclog("MOVSB %08X:%04X -> %08X:%04X %02X\n",ds,SI,es,DI,temp2);
|
||||
if (flags&D_FLAG) { DI--; SI--; }
|
||||
@@ -569,7 +555,7 @@ int rep386(int fv)
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI);
|
||||
temp2 = readmemb(ea_seg->base, ESI); if (abrt) break;
|
||||
temp2 = readmemb(cpu_state.ea_seg->base, ESI); if (abrt) break;
|
||||
writememb(es,EDI,temp2); if (abrt) break;
|
||||
if (flags&D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
@@ -587,7 +573,7 @@ int rep386(int fv)
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+1);
|
||||
tempw = readmemw(ea_seg->base, SI); if (abrt) break;
|
||||
tempw = readmemw(cpu_state.ea_seg->base, SI); if (abrt) break;
|
||||
writememw(es,DI,tempw); if (abrt) break;
|
||||
if (flags&D_FLAG) { DI-=2; SI-=2; }
|
||||
else { DI+=2; SI+=2; }
|
||||
@@ -605,7 +591,7 @@ int rep386(int fv)
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+3);
|
||||
templ = readmeml(ea_seg->base, SI); if (abrt) break;
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI); if (abrt) break;
|
||||
// pclog("MOVSD %08X from %08X to %08X (%04X:%08X)\n", templ, ds+SI, es+DI, CS, pc);
|
||||
writememl(es,DI,templ); if (abrt) break;
|
||||
if (flags&D_FLAG) { DI-=4; SI-=4; }
|
||||
@@ -624,7 +610,7 @@ int rep386(int fv)
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+1);
|
||||
tempw = readmemw(ea_seg->base, ESI); if (abrt) break;
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI); if (abrt) break;
|
||||
writememw(es,EDI,tempw); if (abrt) break;
|
||||
// if (output) pclog("Written %04X from %08X to %08X %i %08X %04X %08X %04X\n",tempw,ds+ESI,es+EDI,c,ds,ES,es,ES);
|
||||
if (flags&D_FLAG) { EDI-=2; ESI-=2; }
|
||||
@@ -643,7 +629,7 @@ int rep386(int fv)
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+3);
|
||||
templ = readmeml(ea_seg->base, ESI); if (abrt) break;
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI); if (abrt) break;
|
||||
// if ((EDI&0xFFFF0000)==0xA0000) cycles-=12;
|
||||
writememl(es,EDI,templ); if (abrt) break;
|
||||
// if (output) pclog("Load %08X from %08X to %08X %04X %08X %04X %08X\n",templ,ESI,EDI,DS,ds,ES,es);
|
||||
@@ -664,7 +650,7 @@ int rep386(int fv)
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
temp = readmemb(ea_seg->base, SI);
|
||||
temp = readmemb(cpu_state.ea_seg->base, SI);
|
||||
temp2=readmemb(es,DI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { DI--; SI--; }
|
||||
@@ -682,7 +668,7 @@ int rep386(int fv)
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
temp = readmemb(ea_seg->base, ESI);
|
||||
temp = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
temp2=readmemb(es,EDI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI--; ESI--; }
|
||||
@@ -701,7 +687,7 @@ int rep386(int fv)
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
// pclog("CMPSW (%04x:%04x)%05X (%04x:%04x)%05X ", DS,SI, ds+SI, ES,DI, es+DI);
|
||||
tempw = readmemw(ea_seg->base, SI);
|
||||
tempw = readmemw(cpu_state.ea_seg->base, SI);
|
||||
tempw2=readmemw(es,DI);
|
||||
// pclog("%04X %04X %c%c %c%c\n", tempw, tempw2, tempw & 0xff, tempw >> 8, tempw2 & 0xff, tempw2 >> 8);
|
||||
|
||||
@@ -721,7 +707,7 @@ int rep386(int fv)
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
templ = readmeml(ea_seg->base, SI);
|
||||
templ = readmeml(cpu_state.ea_seg->base, SI);
|
||||
templ2=readmeml(es,DI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { DI-=4; SI-=4; }
|
||||
@@ -739,7 +725,7 @@ int rep386(int fv)
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
tempw = readmemw(ea_seg->base, ESI);
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
tempw2=readmemw(es,EDI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI-=2; ESI-=2; }
|
||||
@@ -757,7 +743,7 @@ int rep386(int fv)
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
templ = readmeml(ea_seg->base, ESI);
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
templ2=readmeml(es,EDI);
|
||||
if (abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI-=4; ESI-=4; }
|
||||
@@ -884,7 +870,7 @@ int rep386(int fv)
|
||||
// if (ds==0xFFFFFFFF) pclog("Null selector REP LODSB %04X(%06X):%06X\n",CS,cs,pc);
|
||||
if (c>0)
|
||||
{
|
||||
AL = readmemb(ea_seg->base, SI);
|
||||
AL = readmemb(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
if (flags&D_FLAG) SI--;
|
||||
else SI++;
|
||||
@@ -899,7 +885,7 @@ int rep386(int fv)
|
||||
// if (ds==0xFFFFFFFF) pclog("Null selector REP LODSB %04X(%06X):%06X\n",CS,cs,pc);
|
||||
if (c>0)
|
||||
{
|
||||
AL = readmemb(ea_seg->base, ESI);
|
||||
AL = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
if (flags&D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
@@ -914,7 +900,7 @@ int rep386(int fv)
|
||||
// if (ds==0xFFFFFFFF) pclog("Null selector REP LODSW %04X(%06X):%06X\n",CS,cs,pc);
|
||||
if (c>0)
|
||||
{
|
||||
AX = readmemw(ea_seg->base, SI);
|
||||
AX = readmemw(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
if (flags&D_FLAG) SI-=2;
|
||||
else SI+=2;
|
||||
@@ -929,7 +915,7 @@ int rep386(int fv)
|
||||
// if (ds==0xFFFFFFFF) pclog("Null selector REP LODSL %04X(%06X):%06X\n",CS,cs,pc);
|
||||
if (c>0)
|
||||
{
|
||||
EAX = readmeml(ea_seg->base, SI);
|
||||
EAX = readmeml(cpu_state.ea_seg->base, SI);
|
||||
if (abrt) break;
|
||||
if (flags&D_FLAG) SI-=4;
|
||||
else SI+=4;
|
||||
@@ -944,7 +930,7 @@ int rep386(int fv)
|
||||
// if (ds==0xFFFFFFFF) pclog("Null selector REP LODSW %04X(%06X):%06X\n",CS,cs,pc);
|
||||
if (c>0)
|
||||
{
|
||||
AX = readmemw(ea_seg->base, ESI);
|
||||
AX = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
if (flags&D_FLAG) ESI-=2;
|
||||
else ESI+=2;
|
||||
@@ -959,7 +945,7 @@ int rep386(int fv)
|
||||
// if (ds==0xFFFFFFFF) pclog("Null selector REP LODSL %04X(%06X):%06X\n",CS,cs,pc);
|
||||
if (c>0)
|
||||
{
|
||||
EAX = readmeml(ea_seg->base, ESI);
|
||||
EAX = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
if (abrt) break;
|
||||
if (flags&D_FLAG) ESI-=4;
|
||||
else ESI+=4;
|
||||
@@ -1131,14 +1117,10 @@ int checkio(int port)
|
||||
// pclog("CheckIO %04X %01X %01X %02X %04X %04X %08X ",CS,CPL,IOPL,port,t,t+(port>>3),tr.base+t+(port>>3));
|
||||
if ((t+(port>>3))>tr.limit) return 1;
|
||||
cpl_override = 1;
|
||||
// d = readmemb386l(0, tr.base + t + (port >> 3));
|
||||
d=readmemb(tr.base,t+(port>>3));
|
||||
d = readmemb386l(0, tr.base + t + (port >> 3));
|
||||
// d=readmemb(tr.base,t+(port>>3));
|
||||
cpl_override = 0;
|
||||
// if (d&(1<<(port&7))) pclog("%02X %02X %08X:%04X\n",d,d&(1<<(port&7)), tr.base, t);
|
||||
if ((port & 0xfff8) == 0x1f0)
|
||||
{
|
||||
// if (d&(1<<(port&7))) fatal("Trying to read from IDE port %04X without permission\n", port);
|
||||
}
|
||||
// pclog("%02X %02X\n",d,d&(1<<(port&7)));
|
||||
return d&(1<<(port&7));
|
||||
}
|
||||
|
||||
@@ -1152,19 +1134,15 @@ int xout=0;
|
||||
|
||||
int divl(uint32_t val)
|
||||
{
|
||||
uint64_t num;
|
||||
uint64_t quo;
|
||||
uint32_t rem;
|
||||
uint32_t quo32;
|
||||
if (val==0)
|
||||
{
|
||||
divexcp();
|
||||
return 1;
|
||||
}
|
||||
num=(((uint64_t)EDX)<<32)|EAX;
|
||||
quo=num/val;
|
||||
rem=num%val;
|
||||
quo32=(uint32_t)(quo&0xFFFFFFFF);
|
||||
uint64_t num=(((uint64_t)EDX)<<32)|EAX;
|
||||
uint64_t quo=num/val;
|
||||
uint32_t rem=num%val;
|
||||
uint32_t quo32=(uint32_t)(quo&0xFFFFFFFF);
|
||||
if (quo!=(uint64_t)quo32)
|
||||
{
|
||||
divexcp();
|
||||
@@ -1176,19 +1154,15 @@ int divl(uint32_t val)
|
||||
}
|
||||
int idivl(int32_t val)
|
||||
{
|
||||
int64_t num;
|
||||
int64_t quo;
|
||||
int32_t rem;
|
||||
int32_t quo32;
|
||||
if (val==0)
|
||||
{
|
||||
divexcp();
|
||||
return 1;
|
||||
}
|
||||
num=(((uint64_t)EDX)<<32)|EAX;
|
||||
quo=num/val;
|
||||
rem=num%val;
|
||||
quo32=(int32_t)(quo&0xFFFFFFFF);
|
||||
int64_t num=(((uint64_t)EDX)<<32)|EAX;
|
||||
int64_t quo=num/val;
|
||||
int32_t rem=num%val;
|
||||
int32_t quo32=(int32_t)(quo&0xFFFFFFFF);
|
||||
if (quo!=(int64_t)quo32)
|
||||
{
|
||||
divexcp();
|
||||
@@ -1247,9 +1221,9 @@ void exec386_dynarec(int cycs)
|
||||
while (cycles>0)
|
||||
{
|
||||
oldcs = CS;
|
||||
oldpc = cpu_state.pc;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
oldcpl = CPL;
|
||||
op32 = use32;
|
||||
cpu_state.op32 = use32;
|
||||
|
||||
|
||||
cycdiff=0;
|
||||
@@ -1262,12 +1236,12 @@ void exec386_dynarec(int cycs)
|
||||
while (!cpu_block_end)
|
||||
{
|
||||
oldcs=CS;
|
||||
oldpc=cpu_state.pc;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
oldcpl=CPL;
|
||||
op32=use32;
|
||||
cpu_state.op32 = use32;
|
||||
|
||||
ea_seg = &_ds;
|
||||
ssegs = 0;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
cpu_state.ssegs = 0;
|
||||
|
||||
opcodestart:
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
@@ -1276,8 +1250,6 @@ void exec386_dynarec(int cycs)
|
||||
if (!abrt)
|
||||
{
|
||||
trap = flags & T_FLAG;
|
||||
prev_prev_opcode = prev_opcode;
|
||||
prev_opcode = opcode;
|
||||
opcode = fetchdat & 0xFF;
|
||||
fetchdat >>= 8;
|
||||
|
||||
@@ -1285,7 +1257,7 @@ void exec386_dynarec(int cycs)
|
||||
// pclog("int %04X(%06X):%04X : %08X %08X %08X %08X %04X %04X %04X(%08X) %04X %04X %04X(%08X) %08X %08X %08X SP=%04X:%08X %02X %04X %i %08X %08X %i %i %02X %02X %02X %02X %02X %f %02X%02X %02X%02X\n",CS,cs,pc,EAX,EBX,ECX,EDX,CS,DS,ES,es,FS,GS,SS,ss,EDI,ESI,EBP,SS,ESP,opcode,flags,ins,0, ldt.base, CPL, stack32, pic.pend, pic.mask, pic.mask2, pic2.pend, pic2.mask, pit.c[0], ram[0x8f13f], ram[0x8f13e], ram[0x8f141], ram[0x8f140]);
|
||||
|
||||
cpu_state.pc++;
|
||||
x86_opcodes[(opcode | op32) & 0x3ff](fetchdat);
|
||||
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
|
||||
}
|
||||
|
||||
if (!use32) cpu_state.pc &= 0xffff;
|
||||
@@ -1413,12 +1385,12 @@ inrecomp=0;
|
||||
while (!cpu_block_end)
|
||||
{
|
||||
oldcs=CS;
|
||||
oldpc=cpu_state.pc;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
oldcpl=CPL;
|
||||
op32=use32;
|
||||
cpu_state.op32 = use32;
|
||||
|
||||
ea_seg = &_ds;
|
||||
ssegs = 0;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
cpu_state.ssegs = 0;
|
||||
|
||||
opcodestart_compile:
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
@@ -1429,8 +1401,6 @@ inrecomp=0;
|
||||
if (!abrt)
|
||||
{
|
||||
trap = flags & T_FLAG;
|
||||
prev_prev_opcode = prev_opcode;
|
||||
prev_opcode = opcode;
|
||||
opcode = fetchdat & 0xFF;
|
||||
fetchdat >>= 8;
|
||||
|
||||
@@ -1439,9 +1409,9 @@ inrecomp=0;
|
||||
|
||||
cpu_state.pc++;
|
||||
|
||||
codegen_generate_call(opcode, x86_opcodes[(opcode | op32) & 0x3ff], fetchdat, cpu_state.pc, cpu_state.pc-1);
|
||||
codegen_generate_call(opcode, x86_opcodes[(opcode | cpu_state.op32) & 0x3ff], fetchdat, cpu_state.pc, cpu_state.pc-1);
|
||||
|
||||
x86_opcodes[(opcode | op32) & 0x3ff](fetchdat);
|
||||
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
|
||||
|
||||
if (x86_was_reset)
|
||||
break;
|
||||
@@ -1472,7 +1442,7 @@ inrecomp=0;
|
||||
|
||||
if (!abrt && !x86_was_reset)
|
||||
codegen_block_end_recompile(block);
|
||||
|
||||
|
||||
if (x86_was_reset)
|
||||
codegen_reset();
|
||||
|
||||
@@ -1490,19 +1460,19 @@ inrecomp=0;
|
||||
x86_was_reset = 0;
|
||||
|
||||
// cpu_new_blocks++;
|
||||
|
||||
|
||||
codegen_block_init(phys_addr);
|
||||
|
||||
// if (output) pclog("Recompile block at %04x:%04x %04x %04x %04x %04x %04x %04x ESP=%04x %04x %02x%02x:%02x%02x %02x%02x:%02x%02x %02x%02x:%02x%02x\n", CS, pc, AX, BX, CX, DX, SI, DI, ESP, BP, ram[0x116330+0x6df4+0xa+3], ram[0x116330+0x6df4+0xa+2], ram[0x116330+0x6df4+0xa+1], ram[0x116330+0x6df4+0xa+0], ram[0x11d136+3],ram[0x11d136+2],ram[0x11d136+1],ram[0x11d136+0], ram[(0x119abe)+0x3],ram[(0x119abe)+0x2],ram[(0x119abe)+0x1],ram[(0x119abe)+0x0]);
|
||||
while (!cpu_block_end)
|
||||
{
|
||||
oldcs=CS;
|
||||
oldpc=cpu_state.pc;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
oldcpl=CPL;
|
||||
op32=use32;
|
||||
cpu_state.op32 = use32;
|
||||
|
||||
ea_seg = &_ds;
|
||||
ssegs = 0;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
cpu_state.ssegs = 0;
|
||||
|
||||
codegen_endpc = (cs + cpu_state.pc) + 8;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
@@ -1510,8 +1480,6 @@ inrecomp=0;
|
||||
if (!abrt)
|
||||
{
|
||||
trap = flags & T_FLAG;
|
||||
prev_prev_opcode = prev_opcode;
|
||||
prev_opcode = opcode;
|
||||
opcode = fetchdat & 0xFF;
|
||||
fetchdat >>= 8;
|
||||
|
||||
@@ -1520,7 +1488,7 @@ inrecomp=0;
|
||||
|
||||
cpu_state.pc++;
|
||||
|
||||
x86_opcodes[(opcode | op32) & 0x3ff](fetchdat);
|
||||
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
|
||||
|
||||
if (x86_was_reset)
|
||||
break;
|
||||
@@ -1548,7 +1516,7 @@ inrecomp=0;
|
||||
ins++;
|
||||
insc++;
|
||||
}
|
||||
|
||||
|
||||
if (!abrt && !x86_was_reset)
|
||||
codegen_block_end();
|
||||
|
||||
@@ -1576,7 +1544,7 @@ inrecomp=0;
|
||||
{
|
||||
abrt = 0;
|
||||
CS = oldcs;
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
pclog("Double fault %i\n", ins);
|
||||
pmodeint(8, 0);
|
||||
if (abrt)
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#include "ibm.h"
|
||||
#include "cpu.h"
|
||||
#include "x86.h"
|
||||
@@ -21,38 +18,38 @@ extern uint32_t *mod1seg[8];
|
||||
static inline void fetch_ea_32_long(uint32_t rmdat)
|
||||
{
|
||||
eal_r = eal_w = NULL;
|
||||
easeg = ea_seg->base;
|
||||
ea_rseg = ea_seg->seg;
|
||||
if (easeg != 0xFFFFFFFF && ((easeg + eaaddr) & 0xFFF) <= 0xFFC)
|
||||
easeg = cpu_state.ea_seg->base;
|
||||
ea_rseg = cpu_state.ea_seg->seg;
|
||||
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
|
||||
{
|
||||
uint32_t addr = easeg + eaaddr;
|
||||
uint32_t addr = easeg + cpu_state.eaaddr;
|
||||
if ( readlookup2[addr >> 12] != -1)
|
||||
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
|
||||
if (writelookup2[addr >> 12] != -1)
|
||||
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
|
||||
}
|
||||
cpu_state.last_ea = eaaddr;
|
||||
}
|
||||
|
||||
static inline void fetch_ea_16_long(uint32_t rmdat)
|
||||
{
|
||||
eal_r = eal_w = NULL;
|
||||
easeg = ea_seg->base;
|
||||
ea_rseg = ea_seg->seg;
|
||||
if (easeg != 0xFFFFFFFF && ((easeg + eaaddr) & 0xFFF) <= 0xFFC)
|
||||
easeg = cpu_state.ea_seg->base;
|
||||
ea_rseg = cpu_state.ea_seg->seg;
|
||||
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
|
||||
{
|
||||
uint32_t addr = easeg + eaaddr;
|
||||
uint32_t addr = easeg + cpu_state.eaaddr;
|
||||
if ( readlookup2[addr >> 12] != -1)
|
||||
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
|
||||
if (writelookup2[addr >> 12] != -1)
|
||||
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
|
||||
}
|
||||
cpu_state.last_ea = eaaddr;
|
||||
}
|
||||
|
||||
#define fetch_ea_16(rmdat) cpu_state.pc++; if (cpu_mod != 3) fetch_ea_16_long(rmdat);
|
||||
#define fetch_ea_32(rmdat) cpu_state.pc++; if (cpu_mod != 3) fetch_ea_32_long(rmdat);
|
||||
|
||||
|
||||
|
||||
#define OP_TABLE(name) dynarec_ops_ ## name
|
||||
#define CLOCK_CYCLES(c)
|
||||
#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
{ \
|
||||
if ((cond)) \
|
||||
{ \
|
||||
cpu_state.pc = oldpc; \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
x86illegal(); \
|
||||
return 0; \
|
||||
} \
|
||||
@@ -160,7 +160,7 @@ static int fopcode;
|
||||
|
||||
static int ILLEGAL(uint32_t fetchdat)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
|
||||
// fatal("Illegal instruction %08X\n", fetchdat);
|
||||
pclog("Illegal instruction %08X (%02X)\n", fetchdat, fopcode);
|
||||
|
||||
150
src/808x.c
150
src/808x.c
@@ -112,8 +112,6 @@ int shadowbios=0;
|
||||
int ins=0;
|
||||
//#define readmemb(a) (((a)<0xA0000)?ram[a]:readmembl(a))
|
||||
|
||||
int ssegs;
|
||||
|
||||
int fetchcycles=0,memcycs,fetchclocks;
|
||||
|
||||
uint8_t prefetchqueue[6];
|
||||
@@ -344,7 +342,7 @@ reg = If mod=11, (depending on data size, 16 bits/8 bits, 32 bits=extend 16 bit
|
||||
*/
|
||||
|
||||
int cycles=0;
|
||||
uint32_t easeg,eaaddr;
|
||||
uint32_t easeg;
|
||||
int rmdat;
|
||||
|
||||
uint16_t zero=0;
|
||||
@@ -366,42 +364,40 @@ void makemod1table()
|
||||
|
||||
static void fetcheal()
|
||||
{
|
||||
if (!cpu_mod && cpu_rm==6) { eaaddr=getword(); easeg=ds; FETCHADD(6); }
|
||||
if (!cpu_mod && cpu_rm==6) { cpu_state.eaaddr=getword(); easeg=ds; FETCHADD(6); }
|
||||
else
|
||||
{
|
||||
switch (cpu_mod)
|
||||
{
|
||||
case 0:
|
||||
eaaddr=0;
|
||||
cpu_state.eaaddr=0;
|
||||
if (cpu_rm&4) FETCHADD(5);
|
||||
else FETCHADD(7+slowrm[cpu_rm]);
|
||||
break;
|
||||
case 1:
|
||||
eaaddr=(uint16_t)(int8_t)FETCH();
|
||||
cpu_state.eaaddr=(uint16_t)(int8_t)FETCH();
|
||||
if (cpu_rm&4) FETCHADD(9);
|
||||
else FETCHADD(11+slowrm[cpu_rm]);
|
||||
break;
|
||||
case 2:
|
||||
eaaddr=getword();
|
||||
cpu_state.eaaddr=getword();
|
||||
if (cpu_rm&4) FETCHADD(9);
|
||||
else FETCHADD(11+slowrm[cpu_rm]);
|
||||
break;
|
||||
case 3:
|
||||
if (!(cpu_rm&4)) FETCHADD(2+slowrm[cpu_rm]);
|
||||
return;
|
||||
}
|
||||
eaaddr+=(*mod1add[0][cpu_rm])+(*mod1add[1][cpu_rm]);
|
||||
cpu_state.eaaddr+=(*mod1add[0][cpu_rm])+(*mod1add[1][cpu_rm]);
|
||||
easeg=*mod1seg[cpu_rm];
|
||||
eaaddr&=0xFFFF;
|
||||
cpu_state.eaaddr&=0xFFFF;
|
||||
}
|
||||
cpu_state.last_ea = eaaddr;
|
||||
|
||||
cpu_state.last_ea = cpu_state.eaaddr;
|
||||
}
|
||||
|
||||
static inline uint8_t geteab()
|
||||
{
|
||||
if (cpu_mod == 3)
|
||||
return (cpu_rm & 4) ? cpu_state.regs[cpu_rm & 3].b.h : cpu_state.regs[cpu_rm & 3].b.l;
|
||||
return readmemb(easeg+eaaddr);
|
||||
return readmemb(easeg+cpu_state.eaaddr);
|
||||
}
|
||||
|
||||
static inline uint16_t geteaw()
|
||||
@@ -409,7 +405,7 @@ static inline uint16_t geteaw()
|
||||
if (cpu_mod == 3)
|
||||
return cpu_state.regs[cpu_rm].w;
|
||||
// if (output==3) printf("GETEAW %04X:%08X\n",easeg,eaaddr);
|
||||
return readmemw(easeg,eaaddr);
|
||||
return readmemw(easeg,cpu_state.eaaddr);
|
||||
}
|
||||
|
||||
static inline uint16_t geteaw2()
|
||||
@@ -417,7 +413,7 @@ static inline uint16_t geteaw2()
|
||||
if (cpu_mod == 3)
|
||||
return cpu_state.regs[cpu_rm].w;
|
||||
// printf("Getting addr from %04X:%04X %05X\n",easeg,eaaddr+2,easeg+eaaddr+2);
|
||||
return readmemw(easeg,(eaaddr+2)&0xFFFF);
|
||||
return readmemw(easeg,(cpu_state.eaaddr+2)&0xFFFF);
|
||||
}
|
||||
|
||||
static inline void seteab(uint8_t val)
|
||||
@@ -431,7 +427,7 @@ static inline void seteab(uint8_t val)
|
||||
}
|
||||
else
|
||||
{
|
||||
writememb(easeg+eaaddr,val);
|
||||
writememb(easeg+cpu_state.eaaddr,val);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -441,7 +437,7 @@ static inline void seteaw(uint16_t val)
|
||||
cpu_state.regs[cpu_rm].w = val;
|
||||
else
|
||||
{
|
||||
writememw(easeg,eaaddr,val);
|
||||
writememw(easeg,cpu_state.eaaddr,val);
|
||||
// writememb(easeg+eaaddr+1,val>>8);
|
||||
}
|
||||
}
|
||||
@@ -593,7 +589,7 @@ chdir(pcempath);
|
||||
else
|
||||
printf("AX=%04X BX=%04X CX=%04X DX=%04X DI=%04X SI=%04X BP=%04X SP=%04X\n",AX,BX,CX,DX,DI,SI,BP,SP);
|
||||
printf("PC=%04X CS=%04X DS=%04X ES=%04X SS=%04X FLAGS=%04X\n",cpu_state.pc,CS,DS,ES,SS,flags);
|
||||
printf("%04X:%04X %04X:%04X\n",oldcs,oldpc, oldcs2, oldpc2);
|
||||
printf("%04X:%04X %04X:%04X\n",oldcs,cpu_state.oldpc, oldcs2, oldpc2);
|
||||
printf("%i ins\n",ins);
|
||||
if (is386)
|
||||
printf("In %s mode\n",(msw&1)?((eflags&VM_FLAG)?"V86":"protected"):"real");
|
||||
@@ -831,7 +827,7 @@ void rep(int fv)
|
||||
int c=CX;
|
||||
uint8_t temp2;
|
||||
uint16_t tempw,tempw2;
|
||||
uint16_t ipc=oldpc;//pc-1;
|
||||
uint16_t ipc=cpu_state.oldpc;//pc-1;
|
||||
int changeds=0;
|
||||
uint32_t oldds;
|
||||
startrep:
|
||||
@@ -877,7 +873,7 @@ void rep(int fv)
|
||||
c--;
|
||||
cycles-=5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xA4: /*REP MOVSB*/
|
||||
@@ -894,7 +890,7 @@ void rep(int fv)
|
||||
FETCHADD(17-memcycs);
|
||||
}
|
||||
if (IRQTEST && c>0) cpu_state.pc=ipc;
|
||||
// if (c>0) { firstrepcycle=0; pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
|
||||
// if (c>0) { firstrepcycle=0; pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
|
||||
// else firstrepcycle=1;
|
||||
// }
|
||||
break;
|
||||
@@ -912,7 +908,7 @@ void rep(int fv)
|
||||
FETCHADD(17 - memcycs);
|
||||
}
|
||||
if (IRQTEST && c>0) cpu_state.pc=ipc;
|
||||
// if (c>0) { firstrepcycle=0; pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
|
||||
// if (c>0) { firstrepcycle=0; pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
|
||||
// else firstrepcycle=1;
|
||||
// }
|
||||
break;
|
||||
@@ -934,7 +930,7 @@ void rep(int fv)
|
||||
FETCHADD(30 - memcycs);
|
||||
}
|
||||
if (IRQTEST && c>0 && (fv==((flags&Z_FLAG)?1:0))) cpu_state.pc=ipc;
|
||||
// if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
|
||||
// if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { pc=ipc; firstrepcycle=0; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
|
||||
// else firstrepcycle=1;
|
||||
break;
|
||||
case 0xA7: /*REP CMPSW*/
|
||||
@@ -954,7 +950,7 @@ void rep(int fv)
|
||||
FETCHADD(30 - memcycs);
|
||||
}
|
||||
if (IRQTEST && c>0 && (fv==((flags&Z_FLAG)?1:0))) cpu_state.pc=ipc;
|
||||
// if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
|
||||
// if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { pc=ipc; firstrepcycle=0; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
|
||||
// else firstrepcycle=1;
|
||||
// if (firstrepcycle) printf("REP CMPSW %06X:%04X %06X:%04X %04X %04X\n",ds,SI,es,DI,tempw,tempw2);
|
||||
break;
|
||||
@@ -999,7 +995,7 @@ void rep(int fv)
|
||||
c--;
|
||||
cycles-=4;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAD: /*REP LODSW*/
|
||||
@@ -1011,7 +1007,7 @@ void rep(int fv)
|
||||
c--;
|
||||
cycles-=4;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (ssegs) ssegs++; FETCHCLEAR(); }
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAE: /*REP SCASB*/
|
||||
@@ -1029,7 +1025,7 @@ void rep(int fv)
|
||||
cycles -= 15;
|
||||
}
|
||||
//if (output) printf("%i %i %i %i\n",c,(c>0),(fv==((flags&Z_FLAG)?1:0)),((c>0) && (fv==((flags&Z_FLAG)?1:0))));
|
||||
if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { cpu_state.pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
|
||||
if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { cpu_state.pc=ipc; firstrepcycle=0; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
|
||||
else firstrepcycle=1;
|
||||
// cycles-=120;
|
||||
break;
|
||||
@@ -1045,7 +1041,7 @@ void rep(int fv)
|
||||
c--;
|
||||
cycles -= 15;
|
||||
}
|
||||
if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { cpu_state.pc=ipc; firstrepcycle=0; if (ssegs) ssegs++; FETCHCLEAR(); }
|
||||
if ((c>0) && (fv==((flags&Z_FLAG)?1:0))) { cpu_state.pc=ipc; firstrepcycle=0; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
default:
|
||||
@@ -1102,7 +1098,7 @@ void execx86(int cycs)
|
||||
// if (output) printf("CLOCK %i %i\n",cycdiff,cycles);
|
||||
fetchclocks=0;
|
||||
oldcs=CS;
|
||||
oldpc=cpu_state.pc;
|
||||
cpu_state.oldpc=cpu_state.pc;
|
||||
opcodestart:
|
||||
opcode=FETCH();
|
||||
tempc=flags&C_FLAG;
|
||||
@@ -1177,14 +1173,14 @@ void execx86(int cycs)
|
||||
break;
|
||||
|
||||
case 0x06: /*PUSH ES*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
writememw(ss,((SP-2)&0xFFFF),ES);
|
||||
SP-=2;
|
||||
cpu_state.last_ea = SP;
|
||||
cycles-=14;
|
||||
break;
|
||||
case 0x07: /*POP ES*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
tempw=readmemw(ss,SP);
|
||||
loadseg(tempw,&_es);
|
||||
SP+=2;
|
||||
@@ -1242,14 +1238,14 @@ void execx86(int cycs)
|
||||
break;
|
||||
|
||||
case 0x0E: /*PUSH CS*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
writememw(ss,((SP-2)&0xFFFF),CS);
|
||||
SP-=2;
|
||||
cpu_state.last_ea = SP;
|
||||
cycles-=14;
|
||||
break;
|
||||
case 0x0F: /*POP CS - 8088/8086 only*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
tempw=readmemw(ss,SP);
|
||||
loadseg(tempw,&_cs);
|
||||
SP+=2;
|
||||
@@ -1303,14 +1299,14 @@ void execx86(int cycs)
|
||||
break;
|
||||
|
||||
case 0x16: /*PUSH SS*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
writememw(ss,((SP-2)&0xFFFF),SS);
|
||||
SP-=2;
|
||||
cycles-=14;
|
||||
cpu_state.last_ea = SP;
|
||||
break;
|
||||
case 0x17: /*POP SS*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
tempw=readmemw(ss,SP);
|
||||
loadseg(tempw,&_ss);
|
||||
SP+=2;
|
||||
@@ -1370,17 +1366,17 @@ void execx86(int cycs)
|
||||
break;
|
||||
|
||||
case 0x1E: /*PUSH DS*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
writememw(ss,((SP-2)&0xFFFF),DS);
|
||||
SP-=2;
|
||||
cpu_state.last_ea = SP;
|
||||
cycles-=14;
|
||||
break;
|
||||
case 0x1F: /*POP DS*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
tempw=readmemw(ss,SP);
|
||||
loadseg(tempw,&_ds);
|
||||
if (ssegs) oldds=ds;
|
||||
if (cpu_state.ssegs) oldds=ds;
|
||||
SP+=2;
|
||||
cpu_state.last_ea = SP;
|
||||
cycles-=12;
|
||||
@@ -1439,7 +1435,7 @@ void execx86(int cycs)
|
||||
oldss=ss;
|
||||
oldds=ds;
|
||||
ds=ss=es;
|
||||
ssegs=2;
|
||||
cpu_state.ssegs=2;
|
||||
cycles-=4;
|
||||
goto opcodestart;
|
||||
// break;
|
||||
@@ -1515,7 +1511,7 @@ void execx86(int cycs)
|
||||
oldss=ss;
|
||||
oldds=ds;
|
||||
ds=ss=cs;
|
||||
ssegs=2;
|
||||
cpu_state.ssegs=2;
|
||||
cycles-=4;
|
||||
goto opcodestart;
|
||||
case 0x2F: /*DAS*/
|
||||
@@ -1591,7 +1587,7 @@ void execx86(int cycs)
|
||||
oldss=ss;
|
||||
oldds=ds;
|
||||
ds=ss=ss;
|
||||
ssegs=2;
|
||||
cpu_state.ssegs=2;
|
||||
cycles-=4;
|
||||
goto opcodestart;
|
||||
// break;
|
||||
@@ -1652,7 +1648,7 @@ void execx86(int cycs)
|
||||
oldss=ss;
|
||||
oldds=ds;
|
||||
ds=ss=ds;
|
||||
ssegs=2;
|
||||
cpu_state.ssegs=2;
|
||||
cycles-=4;
|
||||
goto opcodestart;
|
||||
// break;
|
||||
@@ -1685,7 +1681,7 @@ void execx86(int cycs)
|
||||
|
||||
case 0x50: case 0x51: case 0x52: case 0x53: /*PUSH r16*/
|
||||
case 0x54: case 0x55: case 0x56: case 0x57:
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
SP-=2;
|
||||
cpu_state.last_ea = SP;
|
||||
writememw(ss,SP,cpu_state.regs[opcode&7].w);
|
||||
@@ -1693,7 +1689,7 @@ void execx86(int cycs)
|
||||
break;
|
||||
case 0x58: case 0x59: case 0x5A: case 0x5B: /*POP r16*/
|
||||
case 0x5C: case 0x5D: case 0x5E: case 0x5F:
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
SP+=2;
|
||||
cpu_state.last_ea = SP;
|
||||
cpu_state.regs[opcode&7].w=readmemw(ss,(SP-2)&0xFFFF);
|
||||
@@ -2063,11 +2059,11 @@ void execx86(int cycs)
|
||||
seteaw(CS);
|
||||
break;
|
||||
case 0x18: /*DS*/
|
||||
if (ssegs) ds=oldds;
|
||||
if (cpu_state.ssegs) ds=oldds;
|
||||
seteaw(DS);
|
||||
break;
|
||||
case 0x10: /*SS*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
seteaw(SS);
|
||||
break;
|
||||
}
|
||||
@@ -2076,7 +2072,7 @@ void execx86(int cycs)
|
||||
|
||||
case 0x8D: /*LEA*/
|
||||
fetchea();
|
||||
cpu_state.regs[cpu_reg].w=(cpu_mod == 3)?cpu_state.last_ea:eaaddr;
|
||||
cpu_state.regs[cpu_reg].w=(cpu_mod == 3)?cpu_state.last_ea:cpu_state.eaaddr;
|
||||
cycles-=2;
|
||||
break;
|
||||
|
||||
@@ -2097,12 +2093,12 @@ void execx86(int cycs)
|
||||
case 0x18: /*DS*/
|
||||
tempw=geteaw();
|
||||
loadseg(tempw,&_ds);
|
||||
if (ssegs) oldds=ds;
|
||||
if (cpu_state.ssegs) oldds=ds;
|
||||
break;
|
||||
case 0x10: /*SS*/
|
||||
tempw=geteaw();
|
||||
loadseg(tempw,&_ss);
|
||||
if (ssegs) oldss=ss;
|
||||
if (cpu_state.ssegs) oldss=ss;
|
||||
// printf("LOAD SS %04X %04X\n",tempw,SS);
|
||||
// printf("SS loaded with %04X %04X:%04X %04X %04X %04X\n",ss>>4,cs>>4,pc,CX,DX,es>>4);
|
||||
break;
|
||||
@@ -2114,7 +2110,7 @@ void execx86(int cycs)
|
||||
|
||||
case 0x8F: /*POPW*/
|
||||
fetchea();
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
tempw=readmemw(ss,SP);
|
||||
SP+=2;
|
||||
cpu_state.last_ea = SP;
|
||||
@@ -2147,7 +2143,7 @@ void execx86(int cycs)
|
||||
tempw2=getword();
|
||||
tempw3=CS;
|
||||
tempw4=cpu_state.pc;
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
cpu_state.pc=tempw;
|
||||
// printf("0x9a");
|
||||
loadcs(tempw2);
|
||||
@@ -2162,14 +2158,14 @@ void execx86(int cycs)
|
||||
cycles-=4;
|
||||
break;
|
||||
case 0x9C: /*PUSHF*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
writememw(ss,((SP-2)&0xFFFF),flags|0xF000);
|
||||
SP-=2;
|
||||
cpu_state.last_ea = SP;
|
||||
cycles-=14;
|
||||
break;
|
||||
case 0x9D: /*POPF*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
flags=readmemw(ss,SP)&0xFFF;
|
||||
SP+=2;
|
||||
cpu_state.last_ea = SP;
|
||||
@@ -2332,7 +2328,7 @@ void execx86(int cycs)
|
||||
case 0xC0: /*RET alias*/
|
||||
case 0xC2: /*RET*/
|
||||
tempw=getword();
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
cpu_state.pc=readmemw(ss,SP);
|
||||
// printf("C2\n");
|
||||
// printf("RET to %04X\n",pc);
|
||||
@@ -2342,7 +2338,7 @@ void execx86(int cycs)
|
||||
break;
|
||||
case 0xC1: /*RET alias*/
|
||||
case 0xC3: /*RET*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
cpu_state.pc=readmemw(ss,SP);
|
||||
// printf("C3\n");
|
||||
// if (output) printf("RET to %04X %05X\n",pc,ss+SP);
|
||||
@@ -2352,17 +2348,17 @@ void execx86(int cycs)
|
||||
break;
|
||||
case 0xC4: /*LES*/
|
||||
fetchea();
|
||||
cpu_state.regs[cpu_reg].w=readmemw(easeg,eaaddr); //geteaw();
|
||||
tempw=readmemw(easeg,(eaaddr+2)&0xFFFF); //geteaw2();
|
||||
cpu_state.regs[cpu_reg].w=readmemw(easeg,cpu_state.eaaddr); //geteaw();
|
||||
tempw=readmemw(easeg,(cpu_state.eaaddr+2)&0xFFFF); //geteaw2();
|
||||
loadseg(tempw,&_es);
|
||||
cycles-=24;
|
||||
break;
|
||||
case 0xC5: /*LDS*/
|
||||
fetchea();
|
||||
cpu_state.regs[cpu_reg].w=readmemw(easeg,eaaddr);
|
||||
tempw=readmemw(easeg,(eaaddr+2)&0xFFFF);
|
||||
cpu_state.regs[cpu_reg].w=readmemw(easeg,cpu_state.eaaddr);
|
||||
tempw=readmemw(easeg,(cpu_state.eaaddr+2)&0xFFFF);
|
||||
loadseg(tempw,&_ds);
|
||||
if (ssegs) oldds=ds;
|
||||
if (cpu_state.ssegs) oldds=ds;
|
||||
cycles-=24;
|
||||
break;
|
||||
case 0xC6: /*MOV b,#8*/
|
||||
@@ -2381,7 +2377,7 @@ void execx86(int cycs)
|
||||
case 0xC8: /*RETF alias*/
|
||||
case 0xCA: /*RETF*/
|
||||
tempw=getword();
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
cpu_state.pc=readmemw(ss,SP);
|
||||
// printf("CA\n");
|
||||
loadcs(readmemw(ss,SP+2));
|
||||
@@ -2392,7 +2388,7 @@ void execx86(int cycs)
|
||||
break;
|
||||
case 0xC9: /*RETF alias*/
|
||||
case 0xCB: /*RETF*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
cpu_state.pc=readmemw(ss,SP);
|
||||
// printf("CB\n");
|
||||
loadcs(readmemw(ss,SP+2));
|
||||
@@ -2401,7 +2397,7 @@ void execx86(int cycs)
|
||||
FETCHCLEAR();
|
||||
break;
|
||||
case 0xCC: /*INT 3*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
writememw(ss,((SP-2)&0xFFFF),flags|0xF000);
|
||||
writememw(ss,((SP-4)&0xFFFF),CS);
|
||||
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
|
||||
@@ -2421,7 +2417,7 @@ void execx86(int cycs)
|
||||
lastcs=CS;
|
||||
temp=FETCH();
|
||||
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
writememw(ss,((SP-2)&0xFFFF),flags|0xF000);
|
||||
writememw(ss,((SP-4)&0xFFFF),CS);
|
||||
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
|
||||
@@ -2436,7 +2432,7 @@ void execx86(int cycs)
|
||||
cycles-=71;
|
||||
break;
|
||||
case 0xCF: /*IRET*/
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
tempw=CS;
|
||||
tempw2=cpu_state.pc;
|
||||
cpu_state.pc=readmemw(ss,SP);
|
||||
@@ -2963,7 +2959,7 @@ void execx86(int cycs)
|
||||
|
||||
case 0xE8: /*CALL rel 16*/
|
||||
tempw=getword();
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
// writememb(ss+((SP-1)&0xFFFF),pc>>8);
|
||||
writememw(ss,((SP-2)&0xFFFF),cpu_state.pc);
|
||||
SP-=2;
|
||||
@@ -3366,7 +3362,7 @@ void execx86(int cycs)
|
||||
break;
|
||||
case 0x10: /*CALL*/
|
||||
tempw=geteaw();
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
writememw(ss,(SP-2)&0xFFFF,cpu_state.pc);
|
||||
SP-=2;
|
||||
cpu_state.last_ea = SP;
|
||||
@@ -3376,11 +3372,11 @@ void execx86(int cycs)
|
||||
FETCHCLEAR();
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
tempw=readmemw(easeg,eaaddr);
|
||||
tempw2=readmemw(easeg,(eaaddr+2)&0xFFFF); //geteaw2();
|
||||
tempw=readmemw(easeg,cpu_state.eaaddr);
|
||||
tempw2=readmemw(easeg,(cpu_state.eaaddr+2)&0xFFFF); //geteaw2();
|
||||
tempw3=CS;
|
||||
tempw4=cpu_state.pc;
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
cpu_state.pc=tempw;
|
||||
// printf("FF 18\n");
|
||||
loadcs(tempw2);
|
||||
@@ -3398,9 +3394,9 @@ void execx86(int cycs)
|
||||
FETCHCLEAR();
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
cpu_state.pc=readmemw(easeg,eaaddr); //geteaw();
|
||||
cpu_state.pc=readmemw(easeg,cpu_state.eaaddr); //geteaw();
|
||||
// printf("FF 28\n");
|
||||
loadcs(readmemw(easeg,(eaaddr+2)&0xFFFF)); //geteaw2();
|
||||
loadcs(readmemw(easeg,(cpu_state.eaaddr+2)&0xFFFF)); //geteaw2();
|
||||
// cs=loadcs(CS);
|
||||
// cs=CS<<4;
|
||||
cycles-=24;
|
||||
@@ -3410,7 +3406,7 @@ void execx86(int cycs)
|
||||
case 0x38: /*PUSH w alias, reported by reenigne*/
|
||||
tempw=geteaw();
|
||||
// if (output) printf("PUSH %04X %i %02X %04X %04X %02X %02X\n",tempw,rm,rmdat,easeg,eaaddr,ram[0x22340+0x5638],ram[0x22340+0x5639]);
|
||||
if (ssegs) ss=oldss;
|
||||
if (cpu_state.ssegs) ss=oldss;
|
||||
writememw(ss,((SP-2)&0xFFFF),tempw);
|
||||
SP-=2;
|
||||
cpu_state.last_ea = SP;
|
||||
@@ -3447,11 +3443,11 @@ void execx86(int cycs)
|
||||
exit(-1);
|
||||
}
|
||||
output = 3;*/
|
||||
if (ssegs)
|
||||
if (cpu_state.ssegs)
|
||||
{
|
||||
ds=oldds;
|
||||
ss=oldss;
|
||||
ssegs=0;
|
||||
cpu_state.ssegs=0;
|
||||
}
|
||||
|
||||
// output = 3;
|
||||
@@ -3502,7 +3498,7 @@ void execx86(int cycs)
|
||||
FETCHCLEAR();
|
||||
nmi_enable = 0;
|
||||
}
|
||||
else if (takeint && !ssegs && !noint)
|
||||
else if (takeint && !cpu_state.ssegs && !noint)
|
||||
{
|
||||
temp=picinterrupt();
|
||||
if (temp!=0xFF)
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static uint32_t ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
|
||||
{
|
||||
int host_reg;
|
||||
@@ -155,7 +152,7 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
|
||||
else \
|
||||
{ \
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
MEM_LOAD_ADDR_EA_B(target_seg); \
|
||||
src_reg = 0; \
|
||||
} \
|
||||
@@ -184,7 +181,7 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
|
||||
else \
|
||||
{ \
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
MEM_LOAD_ADDR_EA_W(target_seg); \
|
||||
src_reg = 0; \
|
||||
} \
|
||||
@@ -213,7 +210,7 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
|
||||
else \
|
||||
{ \
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
MEM_LOAD_ADDR_EA_L(target_seg); \
|
||||
src_reg = 0; \
|
||||
} \
|
||||
@@ -248,7 +245,7 @@ static uint32_t ropCMP_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_B(target_seg);
|
||||
src_reg = 0;
|
||||
}
|
||||
@@ -276,7 +273,7 @@ static uint32_t ropCMP_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_W(target_seg);
|
||||
src_reg = 0;
|
||||
}
|
||||
@@ -304,7 +301,7 @@ static uint32_t ropCMP_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
src_reg = 0;
|
||||
}
|
||||
@@ -333,7 +330,7 @@ static uint32_t ropCMP_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_B(target_seg);
|
||||
dst_reg = 0;
|
||||
}
|
||||
@@ -361,7 +358,7 @@ static uint32_t ropCMP_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_W(target_seg);
|
||||
dst_reg = 0;
|
||||
} \
|
||||
@@ -389,7 +386,7 @@ static uint32_t ropCMP_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
dst_reg = 0;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static uint32_t ropFXCH(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
|
||||
{
|
||||
FP_ENTER();
|
||||
@@ -46,7 +43,7 @@ static uint32_t ropFLDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
||||
op_pc--;
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
@@ -63,7 +60,7 @@ static uint32_t ropFLDd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
||||
op_pc--;
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
MEM_LOAD_ADDR_EA_Q(target_seg);
|
||||
@@ -81,7 +78,7 @@ static uint32_t ropFILDw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
op_pc--;
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
MEM_LOAD_ADDR_EA_W(target_seg);
|
||||
@@ -98,7 +95,7 @@ static uint32_t ropFILDl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
op_pc--;
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
@@ -115,7 +112,7 @@ static uint32_t ropFILDq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
op_pc--;
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
MEM_LOAD_ADDR_EA_Q(target_seg);
|
||||
@@ -138,7 +135,7 @@ static uint32_t ropFSTs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
||||
|
||||
host_reg = FP_LOAD_REG(0);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
|
||||
@@ -157,7 +154,7 @@ static uint32_t ropFSTd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
||||
|
||||
FP_LOAD_REG_D(0, &host_reg1, &host_reg2);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
CHECK_SEG_LIMITS(target_seg, 7);
|
||||
@@ -193,7 +190,7 @@ static uint32_t ropF ## name ## size(uint8_t opcode, uint32_t fetchdat, uint32_t
|
||||
op_pc--; \
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
|
||||
\
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
\
|
||||
CHECK_SEG_READ(target_seg); \
|
||||
load(target_seg); \
|
||||
@@ -237,7 +234,7 @@ static uint32_t ropF ## name ## size(uint8_t opcode, uint32_t fetchdat, uint32_t
|
||||
op_pc--; \
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
|
||||
\
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
\
|
||||
CHECK_SEG_READ(target_seg); \
|
||||
load(target_seg); \
|
||||
@@ -268,7 +265,7 @@ ropFcompare(COM, il, MEM_LOAD_ADDR_EA_L, FP_COMPARE_IL);
|
||||
op_pc--;
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
@@ -285,7 +282,7 @@ static uint32_t ropFDIVs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
op_pc--;
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
@@ -302,7 +299,7 @@ static uint32_t ropFMULs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
op_pc--;
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
@@ -319,7 +316,7 @@ static uint32_t ropFSUBs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
op_pc--;
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
@@ -504,7 +501,7 @@ static uint32_t ropFISTw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
|
||||
host_reg = FP_LOAD_REG_INT_W(0);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
|
||||
@@ -523,7 +520,7 @@ static uint32_t ropFISTl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
|
||||
host_reg = FP_LOAD_REG_INT(0);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
|
||||
@@ -559,7 +556,7 @@ static uint32_t ropFISTPq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
|
||||
|
||||
FP_LOAD_REG_INT_Q(0, &host_reg1, &host_reg2);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#define ROP_LOGIC(name, op, writeback) \
|
||||
static uint32_t rop ## name ## _b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
|
||||
{ \
|
||||
@@ -67,7 +64,7 @@
|
||||
else \
|
||||
{ \
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
MEM_LOAD_ADDR_EA_B(target_seg); \
|
||||
src_reg = 0; \
|
||||
} \
|
||||
@@ -93,7 +90,7 @@
|
||||
else \
|
||||
{ \
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
MEM_LOAD_ADDR_EA_W(target_seg); \
|
||||
src_reg = 0; \
|
||||
} \
|
||||
@@ -119,7 +116,7 @@
|
||||
else \
|
||||
{ \
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
MEM_LOAD_ADDR_EA_L(target_seg); \
|
||||
src_reg = 0; \
|
||||
} \
|
||||
@@ -150,7 +147,7 @@ static uint32_t ropTEST_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_B(target_seg);
|
||||
src_reg = 0;
|
||||
}
|
||||
@@ -175,7 +172,7 @@ static uint32_t ropTEST_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_W(target_seg);
|
||||
src_reg = 0;
|
||||
}
|
||||
@@ -200,7 +197,7 @@ static uint32_t ropTEST_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
src_reg = 0;
|
||||
}
|
||||
@@ -373,7 +370,7 @@ static uint32_t ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
|
||||
{
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
imm = fastreadb(cs + op_pc + 1);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_B(target_seg);
|
||||
host_reg = 0;
|
||||
}
|
||||
@@ -424,7 +421,7 @@ static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
||||
{
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
imm = fastreadw(cs + op_pc + 1);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_W(target_seg);
|
||||
host_reg = 0;
|
||||
}
|
||||
@@ -475,7 +472,7 @@ static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
|
||||
{
|
||||
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
imm = fastreadl(cs + op_pc + 1);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
host_reg = 0;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static uint32_t ropNOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
|
||||
{
|
||||
return op_pc;
|
||||
@@ -32,7 +29,7 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_W(target_seg);
|
||||
host_reg = 0;
|
||||
}
|
||||
@@ -43,7 +40,7 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
STORE_HOST_REG_ADDR_W((uintptr_t)&codegen_temp, host_reg);
|
||||
RELEASE_REG(host_reg);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-2);
|
||||
host_reg = LOAD_REG_IMM(op_pc + 1);
|
||||
MEM_STORE_ADDR_EA_W(&_ss, host_reg);
|
||||
@@ -60,7 +57,7 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
case 0x30: /*PUSH*/
|
||||
if (!host_reg)
|
||||
host_reg = LOAD_HOST_REG(host_reg);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-2);
|
||||
MEM_STORE_ADDR_EA_W(&_ss, host_reg);
|
||||
SP_MODIFY(-2);
|
||||
@@ -81,7 +78,7 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
else
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
MEM_LOAD_ADDR_EA_L(target_seg);
|
||||
host_reg = 0;
|
||||
}
|
||||
@@ -92,7 +89,7 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
STORE_HOST_REG_ADDR((uintptr_t)&codegen_temp, host_reg);
|
||||
RELEASE_REG(host_reg);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-4);
|
||||
host_reg = LOAD_REG_IMM(op_pc + 1);
|
||||
MEM_STORE_ADDR_EA_L(&_ss, host_reg);
|
||||
@@ -109,7 +106,7 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
|
||||
case 0x30: /*PUSH*/
|
||||
if (!host_reg)
|
||||
host_reg = LOAD_HOST_REG(host_reg);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-4);
|
||||
MEM_STORE_ADDR_EA_L(&_ss, host_reg);
|
||||
SP_MODIFY(-4);
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static uint32_t ropMOVQ_q_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
|
||||
{
|
||||
int host_reg1, host_reg2;
|
||||
@@ -17,7 +14,7 @@ static uint32_t ropMOVQ_q_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
CHECK_SEG_LIMITS(target_seg, 7);
|
||||
@@ -43,7 +40,7 @@ static uint32_t ropMOVQ_mm_q(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -70,7 +67,7 @@ static uint32_t ropMOVD_l_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
CHECK_SEG_LIMITS(target_seg, 3);
|
||||
@@ -93,7 +90,7 @@ static uint32_t ropMOVD_mm_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -120,7 +117,7 @@ static uint32_t name(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t
|
||||
{ \
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
|
||||
\
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
\
|
||||
CHECK_SEG_READ(target_seg); \
|
||||
\
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static uint32_t ropMOV_rb_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
|
||||
{
|
||||
STORE_IMM_REG_B(opcode & 7, fetchdat & 0xff);
|
||||
@@ -35,7 +32,7 @@ static uint32_t ropMOV_b_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
CHECK_SEG_LIMITS(target_seg, 0);
|
||||
@@ -58,7 +55,7 @@ static uint32_t ropMOV_w_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
CHECK_SEG_LIMITS(target_seg, 1);
|
||||
@@ -84,7 +81,7 @@ static uint32_t ropMOV_l_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
CHECK_SEG_LIMITS(target_seg, 3);
|
||||
@@ -108,7 +105,7 @@ static uint32_t ropMOV_r_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -129,7 +126,7 @@ static uint32_t ropMOV_r_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -150,7 +147,7 @@ static uint32_t ropMOV_r_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -173,7 +170,7 @@ static uint32_t ropMOV_b_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
uint32_t imm = fastreadb(cs + op_pc + 1);
|
||||
int host_reg = LOAD_REG_IMM(imm);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
|
||||
MEM_STORE_ADDR_EA_B(target_seg, host_reg);
|
||||
@@ -194,7 +191,7 @@ static uint32_t ropMOV_w_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
uint32_t imm = fastreadw(cs + op_pc + 1);
|
||||
int host_reg = LOAD_REG_IMM(imm);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
|
||||
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
|
||||
@@ -217,7 +214,7 @@ static uint32_t ropMOV_l_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
uint32_t imm = fastreadl(cs + op_pc + 1);
|
||||
int host_reg = LOAD_REG_IMM(imm);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
CHECK_SEG_WRITE(target_seg);
|
||||
|
||||
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
|
||||
@@ -238,7 +235,7 @@ static uint32_t ropMOV_AL_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
addr = fastreadw(cs + op_pc);
|
||||
|
||||
CHECK_SEG_READ(op_ea_seg);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
MEM_LOAD_ADDR_IMM_B(op_ea_seg, addr);
|
||||
STORE_REG_TARGET_B_RELEASE(0, REG_AL);
|
||||
@@ -255,7 +252,7 @@ static uint32_t ropMOV_AX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
addr = fastreadw(cs + op_pc);
|
||||
|
||||
CHECK_SEG_READ(op_ea_seg);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
MEM_LOAD_ADDR_IMM_W(op_ea_seg, addr);
|
||||
STORE_REG_TARGET_W_RELEASE(0, REG_AX);
|
||||
@@ -272,7 +269,7 @@ static uint32_t ropMOV_EAX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
addr = fastreadw(cs + op_pc);
|
||||
|
||||
CHECK_SEG_READ(op_ea_seg);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
MEM_LOAD_ADDR_IMM_L(op_ea_seg, addr);
|
||||
STORE_REG_TARGET_L_RELEASE(0, REG_EAX);
|
||||
@@ -291,7 +288,7 @@ static uint32_t ropMOV_a_AL(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
addr = fastreadw(cs + op_pc);
|
||||
|
||||
CHECK_SEG_WRITE(op_ea_seg);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
host_reg = LOAD_REG_B(REG_AL);
|
||||
|
||||
@@ -311,7 +308,7 @@ static uint32_t ropMOV_a_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
addr = fastreadw(cs + op_pc);
|
||||
|
||||
CHECK_SEG_WRITE(op_ea_seg);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
host_reg = LOAD_REG_W(REG_AX);
|
||||
|
||||
@@ -331,7 +328,7 @@ static uint32_t ropMOV_a_EAX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
addr = fastreadw(cs + op_pc);
|
||||
|
||||
CHECK_SEG_WRITE(op_ea_seg);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
host_reg = LOAD_REG_L(REG_EAX);
|
||||
|
||||
@@ -380,7 +377,7 @@ static uint32_t ropMOVZX_w_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -403,7 +400,7 @@ static uint32_t ropMOVZX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -426,7 +423,7 @@ static uint32_t ropMOVZX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -450,7 +447,7 @@ static uint32_t ropMOVSX_w_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -473,7 +470,7 @@ static uint32_t ropMOVSX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
@@ -496,7 +493,7 @@ static uint32_t ropMOVSX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
{
|
||||
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
|
||||
CHECK_SEG_READ(target_seg);
|
||||
|
||||
|
||||
@@ -1,11 +1,8 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static uint32_t ropPUSH_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
|
||||
{
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-2);
|
||||
host_reg = LOAD_REG_W(opcode & 7);
|
||||
MEM_STORE_ADDR_EA_W(&_ss, host_reg);
|
||||
@@ -17,7 +14,7 @@ static uint32_t ropPUSH_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
|
||||
{
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-4);
|
||||
host_reg = LOAD_REG_L(opcode & 7);
|
||||
MEM_STORE_ADDR_EA_L(&_ss, host_reg);
|
||||
@@ -31,7 +28,7 @@ static uint32_t ropPUSH_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
|
||||
uint16_t imm = fetchdat & 0xffff;
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-2);
|
||||
host_reg = LOAD_REG_IMM(imm);
|
||||
MEM_STORE_ADDR_EA_W(&_ss, host_reg);
|
||||
@@ -44,7 +41,7 @@ static uint32_t ropPUSH_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
|
||||
uint32_t imm = fastreadl(cs + op_pc);
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-4);
|
||||
host_reg = LOAD_REG_IMM(imm);
|
||||
MEM_STORE_ADDR_EA_L(&_ss, host_reg);
|
||||
@@ -61,7 +58,7 @@ static uint32_t ropPUSH_imm_b16(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
|
||||
if (imm & 0x80)
|
||||
imm |= 0xff00;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-2);
|
||||
host_reg = LOAD_REG_IMM(imm);
|
||||
MEM_STORE_ADDR_EA_W(&_ss, host_reg);
|
||||
@@ -77,7 +74,7 @@ static uint32_t ropPUSH_imm_b32(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
|
||||
if (imm & 0x80)
|
||||
imm |= 0xffffff00;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-4);
|
||||
host_reg = LOAD_REG_IMM(imm);
|
||||
MEM_STORE_ADDR_EA_L(&_ss, host_reg);
|
||||
@@ -90,7 +87,7 @@ static uint32_t ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
|
||||
{
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(0);
|
||||
MEM_LOAD_ADDR_EA_W(&_ss);
|
||||
SP_MODIFY(2);
|
||||
@@ -102,7 +99,7 @@ static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
|
||||
{
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(0);
|
||||
MEM_LOAD_ADDR_EA_L(&_ss);
|
||||
SP_MODIFY(4);
|
||||
@@ -115,7 +112,7 @@ static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
|
||||
{
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(0);
|
||||
MEM_LOAD_ADDR_EA_W(&_ss);
|
||||
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
|
||||
@@ -127,7 +124,7 @@ static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
|
||||
{
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(0);
|
||||
MEM_LOAD_ADDR_EA_L(&_ss);
|
||||
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
|
||||
@@ -141,7 +138,7 @@ static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
uint16_t offset = fetchdat & 0xffff;
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(0);
|
||||
MEM_LOAD_ADDR_EA_W(&_ss);
|
||||
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
|
||||
@@ -154,7 +151,7 @@ static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
|
||||
uint16_t offset = fetchdat & 0xffff;
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(0);
|
||||
MEM_LOAD_ADDR_EA_L(&_ss);
|
||||
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
|
||||
@@ -168,7 +165,7 @@ static uint32_t ropCALL_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
uint16_t offset = fetchdat & 0xffff;
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-2);
|
||||
host_reg = LOAD_REG_IMM(op_pc+2);
|
||||
MEM_STORE_ADDR_EA_W(&_ss, host_reg);
|
||||
@@ -182,7 +179,7 @@ static uint32_t ropCALL_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
uint32_t offset = fastreadl(cs + op_pc);
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_STACK_TO_EA(-4);
|
||||
host_reg = LOAD_REG_IMM(op_pc+4);
|
||||
MEM_STORE_ADDR_EA_L(&_ss, host_reg);
|
||||
@@ -196,7 +193,7 @@ static uint32_t ropLEAVE_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
{
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_EBP_TO_EA(0);
|
||||
MEM_LOAD_ADDR_EA_W(&_ss);
|
||||
host_reg = LOAD_REG_W(REG_BP); /*SP = BP + 2*/
|
||||
@@ -210,7 +207,7 @@ static uint32_t ropLEAVE_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
|
||||
{
|
||||
int host_reg;
|
||||
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc);
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
|
||||
LOAD_EBP_TO_EA(0);
|
||||
MEM_LOAD_ADDR_EA_L(&_ss);
|
||||
host_reg = LOAD_REG_L(REG_EBP); /*ESP = EBP + 4*/
|
||||
@@ -226,7 +223,7 @@ static uint32_t ropPUSH_ ## seg ## _16(uint8_t opcode, uint32_t fetchdat, uint32
|
||||
{ \
|
||||
int host_reg; \
|
||||
\
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
LOAD_STACK_TO_EA(-2); \
|
||||
host_reg = LOAD_VAR_W((uintptr_t)&seg); \
|
||||
MEM_STORE_ADDR_EA_W(&_ss, host_reg); \
|
||||
@@ -238,7 +235,7 @@ static uint32_t ropPUSH_ ## seg ## _32(uint8_t opcode, uint32_t fetchdat, uint32
|
||||
{ \
|
||||
int host_reg; \
|
||||
\
|
||||
STORE_IMM_ADDR_L((uintptr_t)&oldpc, op_old_pc); \
|
||||
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
|
||||
LOAD_STACK_TO_EA(-4); \
|
||||
host_reg = LOAD_VAR_W((uintptr_t)&seg); \
|
||||
MEM_STORE_ADDR_EA_L(&_ss, host_reg); \
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
/*Register allocation :
|
||||
R8-R15 - emulated registers
|
||||
*/
|
||||
@@ -22,8 +19,7 @@ static inline int find_host_xmm_reg()
|
||||
}
|
||||
static void call(codeblock_t *block, uintptr_t func)
|
||||
{
|
||||
// uintptr_t diff = func - (uintptr_t)&block->data[block_pos + 5];
|
||||
intptr_t diff = func - (intptr_t)&block->data[block_pos + 5];
|
||||
uintptr_t diff = func - (uintptr_t)&block->data[block_pos + 5];
|
||||
|
||||
codegen_reg_loaded[0] = codegen_reg_loaded[1] = codegen_reg_loaded[2] = codegen_reg_loaded[3] = 0;
|
||||
codegen_reg_loaded[4] = codegen_reg_loaded[5] = codegen_reg_loaded[6] = codegen_reg_loaded[7] = 0;
|
||||
@@ -502,7 +498,14 @@ static void STORE_IMM_REG_L(int reg, uint32_t val)
|
||||
|
||||
static void STORE_IMM_ADDR_L(uintptr_t addr, uint32_t val)
|
||||
{
|
||||
if (addr < 0x100000000)
|
||||
if (addr >= (uintptr_t)&cpu_state && addr < ((uintptr_t)&cpu_state)+0x80)
|
||||
{
|
||||
addbyte(0xC7); /*MOVL [addr],val*/
|
||||
addbyte(0x45);
|
||||
addbyte(addr - (uintptr_t)&cpu_state);
|
||||
addlong(val);
|
||||
}
|
||||
else if (addr < 0x100000000)
|
||||
{
|
||||
addbyte(0xC7); /*MOVL [addr],val*/
|
||||
addbyte(0x04);
|
||||
@@ -3342,11 +3345,10 @@ static void FP_ENTER()
|
||||
addlong((uintptr_t)&cr0);
|
||||
addbyte(0xc);
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(11+5+12+5);
|
||||
addbyte(7+5+12+5);
|
||||
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&oldpc);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addlong(op_old_pc);
|
||||
load_param_1_32(&codeblock[block_current], 7);
|
||||
CALL_FUNC(x86_int);
|
||||
@@ -4404,11 +4406,10 @@ static void MMX_ENTER()
|
||||
addlong((uintptr_t)&cr0);
|
||||
addbyte(0xc);
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(11+5+12+5);
|
||||
addbyte(7+5+12+5);
|
||||
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uintptr_t)&oldpc);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addlong(op_old_pc);
|
||||
load_param_1_32(&codeblock[block_current], 7);
|
||||
CALL_FUNC(x86_int);
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
/*Register allocation :
|
||||
EBX, ECX, EDX - emulated registers
|
||||
EAX - work register, EA storage
|
||||
@@ -1324,7 +1321,7 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
|
||||
addbyte(0x8b); /*MOVL EAX, regs[rm].l*/
|
||||
addbyte(0x45);
|
||||
addbyte((uint32_t)&cpu_state.regs[rm].l - (uint32_t)&EAX);
|
||||
eaaddr = cpu_state.regs[rm].l;
|
||||
cpu_state.eaaddr = cpu_state.regs[rm].l;
|
||||
if (mod)
|
||||
{
|
||||
if (rm == 5 && !op_ssegs)
|
||||
@@ -1822,10 +1819,10 @@ static void FP_ENTER()
|
||||
addlong((uintptr_t)&cr0);
|
||||
addbyte(0xc);
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(10+7+5+5);
|
||||
addbyte(7+7+5+5);
|
||||
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
|
||||
addbyte(0x05);
|
||||
addlong((uintptr_t)&oldpc);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addlong(op_old_pc);
|
||||
addbyte(0xc7); /*MOV [ESP], 7*/
|
||||
addbyte(0x04);
|
||||
@@ -3066,10 +3063,10 @@ static void MMX_ENTER()
|
||||
addlong((uintptr_t)&cr0);
|
||||
addbyte(0xc);
|
||||
addbyte(0x74); /*JZ +*/
|
||||
addbyte(10+7+5+5);
|
||||
addbyte(7+7+5+5);
|
||||
addbyte(0xC7); /*MOVL [oldpc],op_old_pc*/
|
||||
addbyte(0x05);
|
||||
addlong((uintptr_t)&oldpc);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addlong(op_old_pc);
|
||||
addbyte(0xc7); /*MOV [ESP], 7*/
|
||||
addbyte(0x04);
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#ifdef __amd64__
|
||||
|
||||
#include <stdlib.h>
|
||||
@@ -592,7 +589,7 @@ int opcode_0f_modrm[256] =
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*90*/
|
||||
0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, /*a0*/
|
||||
0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, /*a0*/
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, /*b0*/
|
||||
|
||||
1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
|
||||
@@ -614,9 +611,8 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
if (!cpu_mod && cpu_rm == 6)
|
||||
{
|
||||
addbyte(0xC7); /*MOVL $0,(ssegs)*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addlong((fetchdat >> 8) & 0xffff);
|
||||
(*op_pc) += 2;
|
||||
}
|
||||
@@ -725,9 +721,8 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
addlong(0xffff);
|
||||
}
|
||||
addbyte(0x89); /*MOV eaaddr, EAX*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
|
||||
if (mod1seg[cpu_rm] == &ss && !op_ssegs)
|
||||
op_ea_seg = &_ss;
|
||||
@@ -881,9 +876,8 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
op_ea_seg = &_ss;
|
||||
|
||||
addbyte(0x89); /*MOV eaaddr, EAX*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -893,9 +887,8 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
{
|
||||
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
|
||||
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addlong(new_eaaddr);
|
||||
(*op_pc) += 4;
|
||||
return op_ea_seg;
|
||||
@@ -925,17 +918,15 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
(*op_pc) += 4;
|
||||
}
|
||||
addbyte(0x89); /*MOV eaaddr, EAX*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
}
|
||||
else
|
||||
{
|
||||
addbyte(0x44); /*MOV eaaddr, base_reg*/
|
||||
addbyte(0x89);
|
||||
addbyte(4 | (base_reg << 3));
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addbyte(0x45 | (base_reg << 3));
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
}
|
||||
}
|
||||
return op_ea_seg;
|
||||
@@ -1154,11 +1145,10 @@ generate_call:
|
||||
if (op_ssegs != last_ssegs)
|
||||
{
|
||||
last_ssegs = op_ssegs;
|
||||
addbyte(0xC7); /*MOVL $0,(ssegs)*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&ssegs);
|
||||
addlong(op_ssegs);
|
||||
addbyte(0xC6); /*MOVB $0,(ssegs)*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.ssegs - (uintptr_t)&cpu_state);
|
||||
addbyte(op_ssegs);
|
||||
}
|
||||
//#if 0
|
||||
if ((!test_modrm ||
|
||||
@@ -1187,15 +1177,14 @@ generate_call:
|
||||
op_pc -= pc_off;
|
||||
}
|
||||
//#endif
|
||||
// if (op_ea_seg != last_ea_seg)
|
||||
// {
|
||||
if (op_ea_seg != last_ea_seg)
|
||||
{
|
||||
// last_ea_seg = op_ea_seg;
|
||||
addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&ea_seg);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.ea_seg - (uintptr_t)&cpu_state);
|
||||
addlong((uint32_t)op_ea_seg);
|
||||
// }
|
||||
}
|
||||
|
||||
|
||||
addbyte(0xC7); /*MOVL [pc],new_pc*/
|
||||
@@ -1203,17 +1192,15 @@ generate_call:
|
||||
addbyte((uintptr_t)&cpu_state.pc - (uintptr_t)&cpu_state);
|
||||
addlong(op_pc + pc_off);
|
||||
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&oldpc);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addlong(old_pc);
|
||||
if (op_32 != last_op32)
|
||||
{
|
||||
last_op32 = op_32;
|
||||
addbyte(0xC7); /*MOVL $use32,(op32)*/
|
||||
addbyte(0x04);
|
||||
addbyte(0x25);
|
||||
addlong((uint32_t)&op32);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.op32 - (uintptr_t)&cpu_state);
|
||||
addlong(op_32);
|
||||
}
|
||||
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined WIN32 || defined _WIN32 || defined _WIN32
|
||||
|
||||
#include <stdlib.h>
|
||||
@@ -553,7 +550,7 @@ int opcode_0f_modrm[256] =
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*90*/
|
||||
0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, /*a0*/
|
||||
0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, /*a0*/
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, /*b0*/
|
||||
|
||||
1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
|
||||
@@ -575,8 +572,8 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
if (!cpu_mod && cpu_rm == 6)
|
||||
{
|
||||
addbyte(0xC7); /*MOVL $0,(ssegs)*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addlong((fetchdat >> 8) & 0xffff);
|
||||
(*op_pc) += 2;
|
||||
}
|
||||
@@ -617,7 +614,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
addbyte(0x25); /*ANDL $0xffff, %eax*/
|
||||
addlong(0xffff);
|
||||
addbyte(0xa3);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addlong((uint32_t)&cpu_state.eaaddr);
|
||||
|
||||
if (mod1seg[cpu_rm] == &ss && !op_ssegs)
|
||||
op_ea_seg = &_ss;
|
||||
@@ -704,7 +701,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
}
|
||||
}
|
||||
addbyte(0xa3);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addlong((uint32_t)&cpu_state.eaaddr);
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -712,8 +709,8 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
{
|
||||
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
|
||||
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.eaaddr - (uintptr_t)&cpu_state);
|
||||
addlong(new_eaaddr);
|
||||
(*op_pc) += 4;
|
||||
return op_ea_seg;
|
||||
@@ -723,7 +720,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
addbyte((uintptr_t)&cpu_state.regs[cpu_rm].l - (uintptr_t)&cpu_state);
|
||||
// addbyte(0xa1); /*MOVL regs[cpu_rm].l, %eax*/
|
||||
// addlong((uint32_t)&cpu_state.regs[cpu_rm].l);
|
||||
eaaddr = cpu_state.regs[cpu_rm].l;
|
||||
cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
|
||||
if (cpu_mod)
|
||||
{
|
||||
if (cpu_rm == 5 && !op_ssegs)
|
||||
@@ -743,7 +740,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
|
||||
}
|
||||
}
|
||||
addbyte(0xa3);
|
||||
addlong((uint32_t)&eaaddr);
|
||||
addlong((uint32_t)&cpu_state.eaaddr);
|
||||
}
|
||||
return op_ea_seg;
|
||||
}
|
||||
@@ -961,10 +958,11 @@ generate_call:
|
||||
if (op_ssegs != last_ssegs)
|
||||
{
|
||||
last_ssegs = op_ssegs;
|
||||
addbyte(0xC7); /*MOVL $0,(ssegs)*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&ssegs);
|
||||
addlong(op_ssegs);
|
||||
|
||||
addbyte(0xC6); /*MOVB [ssegs],op_ssegs*/
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.ssegs - (uintptr_t)&cpu_state);
|
||||
addbyte(op_pc + pc_off);
|
||||
}
|
||||
|
||||
if (!test_modrm ||
|
||||
@@ -993,14 +991,14 @@ generate_call:
|
||||
op_pc -= pc_off;
|
||||
}
|
||||
|
||||
// if (op_ea_seg != last_ea_seg)
|
||||
// {
|
||||
// last_ea_seg = op_ea_seg;
|
||||
if (op_ea_seg != last_ea_seg)
|
||||
{
|
||||
last_ea_seg = op_ea_seg;
|
||||
addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&ea_seg);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.ea_seg - (uintptr_t)&cpu_state);
|
||||
addlong((uint32_t)op_ea_seg);
|
||||
// }
|
||||
}
|
||||
|
||||
addbyte(0xC7); /*MOVL pc,new_pc*/
|
||||
addbyte(0x45);
|
||||
@@ -1008,15 +1006,16 @@ generate_call:
|
||||
addlong(op_pc + pc_off);
|
||||
|
||||
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&oldpc);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.oldpc - (uintptr_t)&cpu_state);
|
||||
addlong(old_pc);
|
||||
|
||||
if (op_32 != last_op32)
|
||||
{
|
||||
last_op32 = op_32;
|
||||
addbyte(0xC7); /*MOVL $use32,(op32)*/
|
||||
addbyte(0x05);
|
||||
addlong((uint32_t)&op32);
|
||||
addbyte(0x45);
|
||||
addbyte((uintptr_t)&cpu_state.op32 - (uintptr_t)&cpu_state);
|
||||
addlong(op_32);
|
||||
}
|
||||
|
||||
|
||||
1194
src/disc_86f.c
Normal file
1194
src/disc_86f.c
Normal file
File diff suppressed because it is too large
Load Diff
52
src/disc_86f.h
Normal file
52
src/disc_86f.h
Normal file
@@ -0,0 +1,52 @@
|
||||
/* Copyright holders: Sarah Walker, Tenshi
|
||||
see COPYING for more details
|
||||
*/
|
||||
void d86f_init();
|
||||
void d86f_load(int drive, char *fn);
|
||||
void d86f_close(int drive);
|
||||
void d86f_seek(int drive, int track);
|
||||
void d86f_readsector(int drive, int sector, int track, int side, int density);
|
||||
void d86f_writesector(int drive, int sector, int track, int side, int density);
|
||||
void d86f_readaddress(int drive, int sector, int side, int density);
|
||||
void d86f_format(int drive, int sector, int side, int density);
|
||||
int d86f_hole(int drive);
|
||||
int d86f_byteperiod(int drive);
|
||||
void d86f_stop(int drive);
|
||||
void d86f_poll();
|
||||
int d86f_realtrack(int track, int drive);
|
||||
void d86f_reset(int drive, int side);
|
||||
void d86f_add(int drive, int side, uint8_t c, uint8_t h, uint8_t r, uint8_t n, int rate, uint8_t *data);
|
||||
void d86f_readsector(int drive, int sector, int track, int side, int density, int sector_size);
|
||||
void d86f_writesector(int drive, int sector, int track, int side, int density, int sector_size);
|
||||
void d86f_readaddress(int drive, int sector, int side, int density);
|
||||
void d86f_format(int drive, int sector, int side, int density, uint8_t fill);
|
||||
void d86f_stop();
|
||||
void d86f_poll();
|
||||
void d86f_stop();
|
||||
|
||||
extern void (*d86f_writeback[2])(int drive, int track);
|
||||
void d86f_prepare_track_layout(int drive, int side);
|
||||
|
||||
#define length_gap0 80
|
||||
#define length_gap1 50
|
||||
#define length_sync 12
|
||||
#define length_am 4
|
||||
#define length_crc 2
|
||||
|
||||
#define IBM
|
||||
#define MFM
|
||||
#ifdef IBM
|
||||
#define pre_gap1 length_gap0 + length_sync + length_am
|
||||
#else
|
||||
#define pre_gap1 0
|
||||
#endif
|
||||
|
||||
#define pre_track pre_gap1 + length_gap1
|
||||
#define pre_gap length_sync + length_am + 4 + length_crc
|
||||
#define pre_data length_sync + length_am
|
||||
#define post_gap length_crc
|
||||
|
||||
extern int raw_tsize[2];
|
||||
extern int gap2_size[2];
|
||||
extern int gap3_size[2];
|
||||
extern int gap4_size[2];
|
||||
@@ -125,7 +125,7 @@ void disc_sector_readsector(int drive, int sector, int track, int side, int rate
|
||||
|
||||
void disc_sector_writesector(int drive, int sector, int track, int side, int rate, int sector_size)
|
||||
{
|
||||
// pclog("disc_sector_writesector: fdc_period=%i img_period=%i rate=%i\n", fdc_get_bitcell_period(), get_bitcell_period(), rate);
|
||||
// pclog("disc_sector_writesector: fdc_period=%i img_period=%i rate=%i\n", fdc_get_bitcell_period(), get_bitcell_period(drive), rate);
|
||||
|
||||
disc_sector_track[drive] = track;
|
||||
disc_sector_side[drive] = side;
|
||||
@@ -138,7 +138,7 @@ void disc_sector_writesector(int drive, int sector, int track, int side, int rat
|
||||
|
||||
void disc_sector_readaddress(int drive, int track, int side, int rate)
|
||||
{
|
||||
// pclog("disc_sector_readaddress: fdc_period=%i img_period=%i rate=%i track=%i side=%i\n", fdc_get_bitcell_period(), get_bitcell_period(), rate, track, side);
|
||||
// pclog("disc_sector_readaddress: fdc_period=%i img_period=%i rate=%i track=%i side=%i\n", fdc_get_bitcell_period(), get_bitcell_period(drive), rate, track, side);
|
||||
|
||||
disc_sector_track[drive] = track;
|
||||
disc_sector_side[drive] = side;
|
||||
@@ -176,19 +176,38 @@ int id_positions[2][2][MAX_SECTORS];
|
||||
/* 4 = ISO, 0 = IBM */
|
||||
int media_type = 0;
|
||||
|
||||
#define BYTE_GAP 0
|
||||
#define BYTE_SYNC 1
|
||||
#define BYTE_IAM 2
|
||||
#define BYTE_IDAM 3
|
||||
#define BYTE_ID 4
|
||||
#define BYTE_ID_CRC 5
|
||||
#define BYTE_DATA_AM 6
|
||||
#define BYTE_DATA 7
|
||||
#define BYTE_DATA_CRC 8
|
||||
#define BYTE_SECTOR_GAP 9
|
||||
#define BYTE_GAP3 10
|
||||
#define BYTE_AM_SYNC 11
|
||||
#define BYTE_INDEX_HOLE 12
|
||||
/* Bits 0-3 define byte type, bit 5 defines whether it is a per-track (0) or per-sector (1) byte, if bit 7 is set, the byte is the index hole. */
|
||||
#define BYTE_GAP0 0x00
|
||||
#define BYTE_GAP1 0x10
|
||||
#define BYTE_GAP4 0x20
|
||||
#define BYTE_GAP2 0x40
|
||||
#define BYTE_GAP3 0x50
|
||||
#define BYTE_I_SYNC 0x01
|
||||
#define BYTE_ID_SYNC 0x41
|
||||
#define BYTE_DATA_SYNC 0x51
|
||||
#define BYTE_IAM_SYNC 0x02
|
||||
#define BYTE_IDAM_SYNC 0x42
|
||||
#define BYTE_DATAAM_SYNC 0x52
|
||||
#define BYTE_IAM 0x03
|
||||
#define BYTE_IDAM 0x43
|
||||
#define BYTE_DATAAM 0x53
|
||||
#define BYTE_ID 0x44
|
||||
#define BYTE_DATA 0x54
|
||||
#define BYTE_ID_CRC 0x45
|
||||
#define BYTE_DATA_CRC 0x55
|
||||
|
||||
#define BYTE_INDEX_HOLE 0x80 /* 1 = index hole, 0 = regular byte */
|
||||
#define BYTE_IS_SECTOR 0x40 /* 1 = per-sector, 0 = per-track */
|
||||
#define BYTE_IS_POST_TRACK 0x20 /* 1 = after all sectors, 0 = before or during all sectors */
|
||||
#define BYTE_IS_DATA 0x10 /* 1 = data, 0 = id */
|
||||
#define BYTE_TYPE 0x0F /* 5 = crc, 4 = data, 3 = address mark, 2 = address mark sync, 1 = sync, 0 = gap */
|
||||
|
||||
#define BYTE_TYPE_GAP 0x00
|
||||
#define BYTE_TYPE_SYNC 0x01
|
||||
#define BYTE_TYPE_AM_SYNC 0x02
|
||||
#define BYTE_TYPE_AM 0x03
|
||||
#define BYTE_TYPE_DATA 0x04
|
||||
#define BYTE_TYPE_CRC 0x05
|
||||
|
||||
void disc_sector_prepare_track_layout(int drive, int side)
|
||||
{
|
||||
@@ -201,62 +220,59 @@ void disc_sector_prepare_track_layout(int drive, int side)
|
||||
int real_gap1_len = ((media_type & 3) == 1) ? 26 : 50;
|
||||
// track_layout[drive][side] = (char *) malloc(raw_tsize[drive]);
|
||||
// id_positions[drive][side] = (int *) malloc(disc_sector_count[drive][side] * 4);
|
||||
memset(track_layout[drive][side], BYTE_GAP, raw_tsize[drive]);
|
||||
memset(track_layout[drive][side], BYTE_GAP4, raw_tsize[drive]);
|
||||
memset(id_positions[drive][side], 0, 1024);
|
||||
i = 0;
|
||||
if (!(media_type & 4))
|
||||
{
|
||||
memset(track_layout[drive][side] + i, BYTE_INDEX_HOLE, 1);
|
||||
i++;
|
||||
memset(track_layout[drive][side] + i, BYTE_GAP, real_gap0_len - 1);
|
||||
memset(track_layout[drive][side] + i, BYTE_GAP0, real_gap0_len);
|
||||
i += real_gap0_len - 1;
|
||||
memset(track_layout[drive][side] + i, BYTE_SYNC, sync_len);
|
||||
memset(track_layout[drive][side] + i, BYTE_I_SYNC, sync_len);
|
||||
i += sync_len;
|
||||
if ((media_type & 3) != 1)
|
||||
{
|
||||
memset(track_layout[drive][side] + i, BYTE_AM_SYNC, 3);
|
||||
memset(track_layout[drive][side] + i, BYTE_IAM_SYNC, 3);
|
||||
i += 3;
|
||||
}
|
||||
memset(track_layout[drive][side] + i, BYTE_IAM, 1);
|
||||
i++;
|
||||
memset(track_layout[drive][side] + i, BYTE_GAP, real_gap1_len);
|
||||
memset(track_layout[drive][side] + i, BYTE_GAP1, real_gap1_len);
|
||||
i += real_gap1_len;
|
||||
}
|
||||
else
|
||||
{
|
||||
memset(track_layout[drive][side] + i, BYTE_INDEX_HOLE, 1);
|
||||
i++;
|
||||
memset(track_layout[drive][side] + i, BYTE_GAP, real_gap1_len - 1);
|
||||
memset(track_layout[drive][side] + i, BYTE_GAP1, real_gap1_len);
|
||||
i += real_gap1_len - 1;
|
||||
}
|
||||
track_layout[drive][side][0] |= BYTE_INDEX_HOLE;
|
||||
for (j = 0; j < disc_sector_count[drive][side]; j++)
|
||||
{
|
||||
s = &disc_sector_data[drive][side][j];
|
||||
// pclog("Sector %i (%i)\n", j, s->n);
|
||||
memset(track_layout[drive][side] + i, BYTE_SYNC, sync_len);
|
||||
memset(track_layout[drive][side] + i, BYTE_ID_SYNC, sync_len);
|
||||
i += sync_len;
|
||||
if ((media_type & 3) != 1)
|
||||
{
|
||||
memset(track_layout[drive][side] + i, BYTE_AM_SYNC, 3);
|
||||
memset(track_layout[drive][side] + i, BYTE_IDAM_SYNC, 3);
|
||||
i += 3;
|
||||
}
|
||||
id_positions[drive][side][j] = i;
|
||||
memset(track_layout[drive][side] + i, BYTE_IDAM, 1);
|
||||
i++;
|
||||
memset(track_layout[drive][side] + i, BYTE_ID, 4);
|
||||
i += 4;
|
||||
memset(track_layout[drive][side] + i, BYTE_ID_CRC, 2);
|
||||
i += 2;
|
||||
memset(track_layout[drive][side] + i, BYTE_SECTOR_GAP, gap2_size[drive]);
|
||||
id_positions[drive][side][j] = i;
|
||||
memset(track_layout[drive][side] + i, BYTE_GAP2, gap2_size[drive]);
|
||||
i += gap2_size[drive];
|
||||
memset(track_layout[drive][side] + i, BYTE_SYNC, sync_len);
|
||||
memset(track_layout[drive][side] + i, BYTE_DATA_SYNC, sync_len);
|
||||
i += sync_len;
|
||||
if ((media_type & 3) != 1)
|
||||
{
|
||||
memset(track_layout[drive][side] + i, BYTE_AM_SYNC, 3);
|
||||
memset(track_layout[drive][side] + i, BYTE_DATAAM_SYNC, 3);
|
||||
i += 3;
|
||||
}
|
||||
memset(track_layout[drive][side] + i, BYTE_DATA_AM, 1);
|
||||
memset(track_layout[drive][side] + i, BYTE_DATAAM, 1);
|
||||
i++;
|
||||
memset(track_layout[drive][side] + i, BYTE_DATA, (128 << ((int) s->n)));
|
||||
i += (128 << ((int) s->n));
|
||||
@@ -349,6 +365,16 @@ int disc_sector_read_state(int drive)
|
||||
return temp;
|
||||
}
|
||||
|
||||
int id_pos = 0;
|
||||
|
||||
typedef union
|
||||
{
|
||||
uint32_t dword;
|
||||
uint8_t byte_array[4];
|
||||
} sector_id;
|
||||
|
||||
sector_id format_sector_id;
|
||||
|
||||
void disc_sector_poll()
|
||||
{
|
||||
sector_t *s;
|
||||
@@ -358,6 +384,18 @@ void disc_sector_poll()
|
||||
int found_sector = 0;
|
||||
int b = 0;
|
||||
|
||||
int cur_id_pos = 0;
|
||||
|
||||
uint8_t track_byte = 0;
|
||||
uint8_t track_index = 0;
|
||||
uint8_t track_sector = 0;
|
||||
uint8_t track_byte_type = 0;
|
||||
|
||||
uint8_t old_track_byte = 0;
|
||||
uint8_t old_track_index = 0;
|
||||
uint8_t old_track_sector = 0;
|
||||
uint8_t old_track_byte_type = 0;
|
||||
|
||||
if (disc_sector_state[drive] == STATE_SEEK)
|
||||
{
|
||||
cur_track_pos[drive]++;
|
||||
@@ -371,12 +409,12 @@ void disc_sector_poll()
|
||||
{
|
||||
if (disc_sector_can_read_address(drive))
|
||||
{
|
||||
pclog("disc_sector_poll(): Disk is write protected or attempting to format wrong number of sectors per track\n");
|
||||
// pclog("disc_sector_poll(): Disk is write protected or attempting to format wrong number of sectors per track\n");
|
||||
fdc_writeprotect();
|
||||
}
|
||||
else
|
||||
{
|
||||
pclog("disc_sector_poll(): Unable to format at the requested density or bitcell period\n");
|
||||
// pclog("disc_sector_poll(): Unable to format at the requested density or bitcell period\n");
|
||||
fdc_notfound();
|
||||
}
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
@@ -386,191 +424,134 @@ void disc_sector_poll()
|
||||
return;
|
||||
}
|
||||
}
|
||||
// if (disc_sector_state[drive] != STATE_IDLE) pclog("%04X: %01X\n", cur_track_pos[drive], track_layout[drive][side][cur_track_pos[drive]]);
|
||||
if (track_layout[drive][side][cur_track_pos[drive]] == BYTE_GAP)
|
||||
|
||||
track_byte = track_layout[drive][side][cur_track_pos[drive]];
|
||||
track_index = track_byte & BYTE_INDEX_HOLE;
|
||||
track_sector = track_byte & BYTE_IS_SECTOR;
|
||||
track_byte_type = track_byte & BYTE_TYPE;
|
||||
|
||||
if (track_index)
|
||||
{
|
||||
if (disc_sector_read_state(drive) || (disc_sector_state[drive] == STATE_WRITE_SECTOR) || (disc_sector_state[drive] == STATE_FORMAT))
|
||||
if (disc_sector_state[drive] != STATE_IDLE)
|
||||
{
|
||||
/* We're at GAP4b or even GAP4a and still in a read, write, or format state, this means we've overrun the gap.
|
||||
Return with sector not found. */
|
||||
// pclog("disc_sector_poll(): Gap overrun at GAP4\n");
|
||||
fdc_notfound();
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
disc_sector_reset_state(drive);
|
||||
cur_track_pos[drive]++;
|
||||
cur_track_pos[drive] %= raw_tsize[drive];
|
||||
return;
|
||||
index_pulse(drive);
|
||||
index_count[drive]++;
|
||||
}
|
||||
if (disc_sector_state[drive] == STATE_FORMAT)
|
||||
{
|
||||
// pclog("Index hole hit again, format finished\n");
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
if (!disable_write) disc_sector_writeback[drive](drive, disc_sector_track[drive]);
|
||||
fdc_finishread(drive);
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_FORMAT_FIND) && disc_sector_can_read_address(drive))
|
||||
{
|
||||
// pclog("Index hole hit, formatting track...\n");
|
||||
disc_sector_state[drive] = STATE_FORMAT;
|
||||
}
|
||||
}
|
||||
else if (track_layout[drive][side][cur_track_pos[drive]] == BYTE_INDEX_HOLE)
|
||||
|
||||
switch(track_byte)
|
||||
{
|
||||
index_pulse(drive);
|
||||
if (disc_sector_state[drive] != STATE_IDLE) index_count[drive]++;
|
||||
if (disc_sector_read_state(drive) || (disc_sector_state[drive] == STATE_WRITE_SECTOR) || (disc_sector_state[drive] == STATE_FORMAT))
|
||||
{
|
||||
/* We're at the index address mark and still in a read, write, or format state, this means we've overrun the gap.
|
||||
Return with sector not found. */
|
||||
// pclog("disc_sector_poll(): Gap overrun at IAM\n");
|
||||
fdc_notfound();
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
disc_sector_reset_state(drive);
|
||||
cur_track_pos[drive]++;
|
||||
cur_track_pos[drive] %= raw_tsize[drive];
|
||||
return;
|
||||
}
|
||||
}
|
||||
else if (track_layout[drive][side][cur_track_pos[drive]] == BYTE_IDAM)
|
||||
{
|
||||
found_sector = disc_sector_find_sector(drive);
|
||||
// pclog("Found sector: %i\n", found_sector);
|
||||
cur_sector[drive] = found_sector;
|
||||
last_sector[drive] = &disc_sector_data[drive][disc_sector_side[drive]][found_sector];
|
||||
cur_rate[drive] = last_sector[drive]->rate;
|
||||
if (!(disc_sector_can_read_address(drive))) last_sector[drive] = NULL;
|
||||
if (disc_sector_read_state(drive) || (disc_sector_state[drive] == STATE_WRITE_SECTOR) || (disc_sector_state[drive] == STATE_FORMAT))
|
||||
{
|
||||
/* We're at a sector ID address mark and still in a read, write, or format state, this means we've overrun the gap.
|
||||
Return with sector not found. */
|
||||
pclog("disc_sector_poll(): Gap (%i) overrun at IDAM\n", fdc_get_gap());
|
||||
fdc_notfound();
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
disc_sector_reset_state(drive);
|
||||
cur_track_pos[drive]++;
|
||||
cur_track_pos[drive] %= raw_tsize[drive];
|
||||
return;
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_FORMAT_FIND) && disc_sector_can_read_address(drive)) disc_sector_state[drive] = STATE_FORMAT;
|
||||
id_counter[drive] = 0;
|
||||
}
|
||||
else if (track_layout[drive][side][cur_track_pos[drive]] == BYTE_ID)
|
||||
{
|
||||
id_counter[drive]++;
|
||||
}
|
||||
else if (track_layout[drive][side][cur_track_pos[drive]] == BYTE_ID_CRC)
|
||||
{
|
||||
id_counter[drive]++;
|
||||
if (id_counter[drive] == 6)
|
||||
{
|
||||
/* ID CRC read, if state is read address, return address */
|
||||
if ((disc_sector_state[drive] == STATE_READ_FIND_ADDRESS) && !(disc_sector_can_read_address(drive)))
|
||||
{
|
||||
if (fdc_get_bitcell_period() != get_bitcell_period(drive))
|
||||
{
|
||||
pclog("Unable to read sector ID: Bitcell period mismatch (%i != %i)...\n", fdc_get_bitcell_period(), get_bitcell_period(drive));
|
||||
}
|
||||
else
|
||||
{
|
||||
pclog("Unable to read sector ID: Media type not supported by the drive...\n");
|
||||
}
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_READ_FIND_ADDRESS) && disc_sector_can_read_address(drive))
|
||||
{
|
||||
// pclog("Reading sector ID...\n");
|
||||
fdc_sectorid(last_sector[drive]->c, last_sector[drive]->h, last_sector[drive]->r, last_sector[drive]->n, 0, 0);
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
}
|
||||
id_counter[drive] = 0;
|
||||
}
|
||||
}
|
||||
else if (track_layout[drive][side][cur_track_pos[drive]] == BYTE_DATA_AM)
|
||||
{
|
||||
data_counter[drive] = 0;
|
||||
switch (disc_sector_state[drive])
|
||||
{
|
||||
case STATE_READ_FIND_SECTOR:
|
||||
if (disc_sector_match(drive) && disc_sector_can_read_address(drive)) disc_sector_state[drive] = STATE_READ_SECTOR;
|
||||
break;
|
||||
case STATE_READ_FIND_FIRST_SECTOR:
|
||||
if ((cur_sector[drive] == 0) && disc_sector_can_read_address(drive)) disc_sector_state[drive] = STATE_READ_FIRST_SECTOR;
|
||||
break;
|
||||
case STATE_READ_FIND_NEXT_SECTOR:
|
||||
if (disc_sector_can_read_address(drive)) disc_sector_state[drive] = STATE_READ_NEXT_SECTOR;
|
||||
break;
|
||||
case STATE_WRITE_FIND_SECTOR:
|
||||
if (disc_sector_match(drive) && disc_sector_can_read_address(drive)) disc_sector_state[drive] = STATE_WRITE_SECTOR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (track_layout[drive][side][cur_track_pos[drive]] == BYTE_DATA)
|
||||
{
|
||||
if (disc_sector_read_state(drive) && (last_sector[drive] != NULL))
|
||||
{
|
||||
if (fdc_data(last_sector[drive]->data[data_counter[drive]]))
|
||||
{
|
||||
/* Data failed to be sent to the FDC, abort. */
|
||||
pclog("disc_sector_poll(): Unable to send further data to the FDC\n");
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
disc_sector_reset_state(drive);
|
||||
cur_track_pos[drive]++;
|
||||
cur_track_pos[drive] %= raw_tsize[drive];
|
||||
return;
|
||||
}
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_WRITE_SECTOR) && (last_sector[drive] != NULL))
|
||||
{
|
||||
data = fdc_getdata(cur_byte[drive] == ((128 << ((uint32_t) last_sector[drive]->n)) - 1));
|
||||
if (data == -1)
|
||||
case BYTE_ID_SYNC:
|
||||
if (disc_sector_state[drive] != STATE_FORMAT) break;
|
||||
cur_id_pos = cur_track_pos[drive] - id_pos;
|
||||
if (cur_id_pos > 3) break;
|
||||
data = fdc_getdata(0);
|
||||
if ((data == -1) && (cur_id_pos < 3))
|
||||
{
|
||||
/* Data failed to be sent from the FDC, abort. */
|
||||
pclog("disc_sector_poll(): Unable to receive further data from the FDC\n");
|
||||
// pclog("disc_sector_poll(): Unable to receive further data from the FDC\n");
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
disc_sector_reset_state(drive);
|
||||
cur_track_pos[drive]++;
|
||||
cur_track_pos[drive] %= raw_tsize[drive];
|
||||
return;
|
||||
}
|
||||
if (!disable_write) last_sector[drive]->data[data_counter[drive]] = data;
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_FORMAT) && (last_sector[drive] != NULL))
|
||||
{
|
||||
if (!disable_write) last_sector[drive]->data[data_counter[drive]] = disc_sector_fill[drive];
|
||||
}
|
||||
data_counter[drive]++;
|
||||
if (last_sector[drive] == NULL)
|
||||
{
|
||||
data_counter[drive] = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
data_counter[drive] %= (128 << ((uint32_t) last_sector[drive]->n));
|
||||
if (!data_counter[drive])
|
||||
format_sector_id.byte_array[cur_id_pos] = data & 0xff;
|
||||
// pclog("format_sector_id[%i] = %i\n", cur_id_pos, format_sector_id.byte_array[cur_id_pos]);
|
||||
if (cur_id_pos == 3)
|
||||
{
|
||||
if (disc_sector_read_state(drive) && (last_sector[drive] != NULL))
|
||||
fdc_stop_id_request();
|
||||
// pclog("Formatting sector: %08X...\n", format_sector_id.dword);
|
||||
}
|
||||
break;
|
||||
case BYTE_DATA:
|
||||
if (disc_sector_read_state(drive) && (last_sector[drive] != NULL))
|
||||
{
|
||||
if (fdc_data(last_sector[drive]->data[data_counter[drive]]))
|
||||
{
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
fdc_finishread(drive);
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_WRITE_SECTOR) && (last_sector[drive] != NULL))
|
||||
{
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
if (!disable_write) disc_sector_writeback[drive](drive, disc_sector_track[drive]);
|
||||
fdc_finishread(drive);
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_FORMAT) && (last_sector[drive] != NULL))
|
||||
{
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
if (!disable_write) disc_sector_writeback[drive](drive, disc_sector_track[drive]);
|
||||
fdc_finishread(drive);
|
||||
/* Data failed to be sent to the FDC, abort. */
|
||||
// pclog("disc_sector_poll(): Unable to send further data to the FDC\n");
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
disc_sector_reset_state(drive);
|
||||
cur_track_pos[drive]++;
|
||||
cur_track_pos[drive] %= raw_tsize[drive];
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_WRITE_SECTOR) && (last_sector[drive] != NULL))
|
||||
{
|
||||
data = fdc_getdata(cur_byte[drive] == ((128 << ((uint32_t) last_sector[drive]->n)) - 1));
|
||||
if (data == -1)
|
||||
{
|
||||
/* Data failed to be sent from the FDC, abort. */
|
||||
// pclog("disc_sector_poll(): Unable to receive further data from the FDC\n");
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
disc_sector_reset_state(drive);
|
||||
cur_track_pos[drive]++;
|
||||
cur_track_pos[drive] %= raw_tsize[drive];
|
||||
return;
|
||||
}
|
||||
if (!disable_write) last_sector[drive]->data[data_counter[drive]] = data;
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_FORMAT) && (last_sector[drive] != NULL))
|
||||
{
|
||||
if (!disable_write) last_sector[drive]->data[data_counter[drive]] = disc_sector_fill[drive];
|
||||
}
|
||||
data_counter[drive]++;
|
||||
if (last_sector[drive] == NULL)
|
||||
{
|
||||
data_counter[drive] = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
data_counter[drive] %= (128 << ((uint32_t) last_sector[drive]->n));
|
||||
if (!data_counter[drive])
|
||||
{
|
||||
if (disc_sector_read_state(drive) && (last_sector[drive] != NULL))
|
||||
{
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
fdc_finishread(drive);
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_WRITE_SECTOR) && (last_sector[drive] != NULL))
|
||||
{
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
if (!disable_write) disc_sector_writeback[drive](drive, disc_sector_track[drive]);
|
||||
fdc_finishread(drive);
|
||||
}
|
||||
/* if (disc_sector_state[drive] == STATE_FORMAT && (last_sector[drive] != NULL))
|
||||
{
|
||||
// pclog("Format: Sector fill finished\n");
|
||||
} */
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
else if (track_layout[drive][side][cur_track_pos[drive]] == BYTE_GAP3)
|
||||
{
|
||||
if (gap3_counter[drive] == fdc_get_gap())
|
||||
{
|
||||
}
|
||||
gap3_counter[drive]++;
|
||||
gap3_counter[drive] %= gap3_size[drive];
|
||||
// pclog("GAP3 counter = %i\n", gap3_counter[drive]);
|
||||
}
|
||||
else if (track_layout[drive][side][cur_track_pos[drive]] == BYTE_GAP)
|
||||
{
|
||||
if (last_sector[drive] != NULL) last_sector[drive] = NULL;
|
||||
}
|
||||
b = track_layout[drive][side][cur_track_pos[drive]];
|
||||
|
||||
old_track_byte = track_byte;
|
||||
old_track_index = track_index;
|
||||
old_track_sector = track_sector;
|
||||
old_track_byte_type = track_byte_type;
|
||||
|
||||
cur_track_pos[drive]++;
|
||||
cur_track_pos[drive] %= raw_tsize[drive];
|
||||
|
||||
track_byte = track_layout[drive][side][cur_track_pos[drive]];
|
||||
track_index = track_byte & BYTE_INDEX_HOLE;
|
||||
track_sector = track_byte & BYTE_IS_SECTOR;
|
||||
track_byte_type = track_byte & BYTE_TYPE;
|
||||
|
||||
if ((disc_sector_state[drive] != STATE_IDLE) && (disc_sector_state[drive] != STATE_SEEK))
|
||||
{
|
||||
if (index_count[drive] > 1)
|
||||
@@ -588,8 +569,71 @@ void disc_sector_poll()
|
||||
}
|
||||
}
|
||||
}
|
||||
if ((b != BYTE_GAP3) && (track_layout[drive][side][cur_track_pos[drive]] == BYTE_GAP3))
|
||||
|
||||
if (track_byte != old_track_byte)
|
||||
{
|
||||
gap3_counter[drive] = 0;
|
||||
// if (disc_sector_state[drive] == STATE_FORMAT) pclog("Track byte: %02X, old: %02X\n", track_byte, old_track_byte);
|
||||
switch(track_byte)
|
||||
{
|
||||
case BYTE_ID_SYNC:
|
||||
id_pos = cur_track_pos[drive];
|
||||
if (disc_sector_state[drive] == STATE_FORMAT)
|
||||
{
|
||||
// pclog("Requesting next sector ID...\n");
|
||||
fdc_request_next_sector_id();
|
||||
}
|
||||
break;
|
||||
case BYTE_GAP2:
|
||||
found_sector = disc_sector_find_sector(drive);
|
||||
// pclog("Found sector: %i\n", found_sector);
|
||||
cur_sector[drive] = found_sector;
|
||||
last_sector[drive] = &disc_sector_data[drive][disc_sector_side[drive]][found_sector];
|
||||
cur_rate[drive] = last_sector[drive]->rate;
|
||||
if (!(disc_sector_can_read_address(drive))) last_sector[drive] = NULL;
|
||||
|
||||
/* ID CRC read, if state is read address, return address */
|
||||
if ((disc_sector_state[drive] == STATE_READ_FIND_ADDRESS) && !(disc_sector_can_read_address(drive)))
|
||||
{
|
||||
if (fdc_get_bitcell_period() != get_bitcell_period(drive))
|
||||
{
|
||||
// pclog("Unable to read sector ID: Bitcell period mismatch (%i != %i)...\n", fdc_get_bitcell_period(), get_bitcell_period(drive));
|
||||
}
|
||||
else
|
||||
{
|
||||
// pclog("Unable to read sector ID: Media type not supported by the drive...\n");
|
||||
}
|
||||
}
|
||||
if ((disc_sector_state[drive] == STATE_READ_FIND_ADDRESS) && disc_sector_can_read_address(drive))
|
||||
{
|
||||
// pclog("Reading sector ID...\n");
|
||||
fdc_sectorid(last_sector[drive]->c, last_sector[drive]->h, last_sector[drive]->r, last_sector[drive]->n, 0, 0);
|
||||
disc_sector_state[drive] = STATE_IDLE;
|
||||
}
|
||||
break;
|
||||
case BYTE_DATA:
|
||||
data_counter[drive] = 0;
|
||||
switch (disc_sector_state[drive])
|
||||
{
|
||||
case STATE_READ_FIND_SECTOR:
|
||||
if (disc_sector_match(drive) && disc_sector_can_read_address(drive)) disc_sector_state[drive] = STATE_READ_SECTOR;
|
||||
break;
|
||||
case STATE_READ_FIND_FIRST_SECTOR:
|
||||
if ((cur_sector[drive] == 0) && disc_sector_can_read_address(drive)) disc_sector_state[drive] = STATE_READ_FIRST_SECTOR;
|
||||
break;
|
||||
case STATE_READ_FIND_NEXT_SECTOR:
|
||||
if (disc_sector_can_read_address(drive)) disc_sector_state[drive] = STATE_READ_NEXT_SECTOR;
|
||||
break;
|
||||
case STATE_WRITE_FIND_SECTOR:
|
||||
if (disc_sector_match(drive) && disc_sector_can_read_address(drive)) disc_sector_state[drive] = STATE_WRITE_SECTOR;
|
||||
break;
|
||||
/* case STATE_FORMAT:
|
||||
// pclog("Format: Starting sector fill...\n");
|
||||
break; */
|
||||
}
|
||||
break;
|
||||
case BYTE_GAP4:
|
||||
if (last_sector[drive] != NULL) last_sector[drive] = NULL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
25
src/fdc.c
25
src/fdc.c
@@ -101,6 +101,23 @@ void fdc_reset()
|
||||
|
||||
int ins;
|
||||
|
||||
void fdc_request_next_sector_id()
|
||||
{
|
||||
if (fdc.pcjr || !fdc.dma)
|
||||
{
|
||||
fdc.stat = 0xf0;
|
||||
}
|
||||
else
|
||||
{
|
||||
fdc.stat = 0xd0;
|
||||
}
|
||||
}
|
||||
|
||||
void fdc_stop_id_request()
|
||||
{
|
||||
fdc.stat &= 0x7f;
|
||||
}
|
||||
|
||||
int fdc_get_gap()
|
||||
{
|
||||
return fdc.gap;
|
||||
@@ -1070,6 +1087,7 @@ void fdc_callback()
|
||||
disctime = 128 * (1 << TIMER_SHIFT);
|
||||
timer_update_outstanding();
|
||||
}
|
||||
#if 0
|
||||
else if (fdc.format_state == 2)
|
||||
{
|
||||
temp = fdc_getdata(fdc.pos == ((fdc.params[2] * 4) - 1));
|
||||
@@ -1088,10 +1106,15 @@ void fdc_callback()
|
||||
timer_update_outstanding();
|
||||
}
|
||||
else if (fdc.format_state == 3)
|
||||
#endif
|
||||
else if (fdc.format_state == 2)
|
||||
{
|
||||
// pclog("Format next stage track %i head %i\n", fdc.track[fdc.drive], fdc.head);
|
||||
pclog("Format next stage track %i head %i\n", fdc.track[fdc.drive], fdc.head);
|
||||
disc_format(fdc.drive, fdc.track[fdc.drive], fdc.head, fdc.rate, fdc.params[4]);
|
||||
#if 0
|
||||
fdc.format_state = 4;
|
||||
#endif
|
||||
fdc.format_state = 3;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
73
src/ibm.h
73
src/ibm.h
@@ -102,36 +102,6 @@ typedef union
|
||||
} b;
|
||||
} x86reg;
|
||||
|
||||
struct
|
||||
{
|
||||
x86reg regs[8];
|
||||
|
||||
int flags_op;
|
||||
uint32_t flags_res;
|
||||
uint32_t flags_op1, flags_op2;
|
||||
|
||||
uint32_t pc;
|
||||
uint32_t last_ea;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
int8_t rm, mod, reg;
|
||||
} rm_mod_reg;
|
||||
uint32_t rm_mod_reg_data;
|
||||
} rm_data;
|
||||
} cpu_state;
|
||||
|
||||
/*x86reg regs[8];*/
|
||||
|
||||
uint16_t flags,eflags;
|
||||
uint32_t /*cs,ds,es,ss,*/oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw;
|
||||
//uint16_t msw;
|
||||
|
||||
extern int ins,output;
|
||||
extern int cycdiff;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t base;
|
||||
@@ -142,12 +112,51 @@ typedef struct
|
||||
int checked; /*Non-zero if selector is known to be valid*/
|
||||
} x86seg;
|
||||
|
||||
struct
|
||||
{
|
||||
x86reg regs[8];
|
||||
|
||||
x86seg *ea_seg;
|
||||
uint32_t eaaddr;
|
||||
|
||||
int flags_op;
|
||||
uint32_t flags_res;
|
||||
uint32_t flags_op1, flags_op2;
|
||||
|
||||
uint32_t pc;
|
||||
uint32_t oldpc;
|
||||
uint32_t op32;
|
||||
uint32_t last_ea;
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
int8_t rm, mod, reg;
|
||||
} rm_mod_reg;
|
||||
uint32_t rm_mod_reg_data;
|
||||
} rm_data;
|
||||
|
||||
int8_t ssegs;
|
||||
} cpu_state;
|
||||
|
||||
#define COMPILE_TIME_ASSERT(expr) typedef char COMP_TIME_ASSERT[(expr) ? 1 : 0];
|
||||
|
||||
COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128);
|
||||
|
||||
/*x86reg regs[8];*/
|
||||
|
||||
uint16_t flags,eflags;
|
||||
uint32_t /*cs,ds,es,ss,*/oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw;
|
||||
//uint16_t msw;
|
||||
|
||||
extern int ins,output;
|
||||
extern int cycdiff;
|
||||
|
||||
x86seg gdt,ldt,idt,tr;
|
||||
x86seg _cs,_ds,_es,_ss,_fs,_gs;
|
||||
x86seg _oldds;
|
||||
|
||||
extern x86seg *ea_seg;
|
||||
|
||||
uint32_t pccache;
|
||||
uint8_t *pccache2;
|
||||
/*Segments -
|
||||
|
||||
@@ -125,9 +125,9 @@ uint8_t keyboard_xt_read(uint16_t port, void *priv)
|
||||
if (romset == ROM_IBMPC)
|
||||
{
|
||||
if (keyboard_xt.pb & 0x04)
|
||||
temp = 0x02;
|
||||
temp = ((mem_size-64) / 32) & 0xf;
|
||||
else
|
||||
temp = 0x01;
|
||||
temp = ((mem_size-64) / 32) >> 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
@@ -30,4 +30,4 @@ void memregs_init()
|
||||
pclog("Memory Registers Init\n");
|
||||
|
||||
io_sethandler(0x00e1, 0x0002, memregs_read, NULL, NULL, memregs_write, NULL, NULL, NULL);
|
||||
}
|
||||
}
|
||||
@@ -531,8 +531,14 @@ gus->curx[gus->voice]=(gus->curx[gus->voice]&0xFFF8000)|((val&0x7F)<<8);
|
||||
if (gus->latch_enable == 2)
|
||||
{
|
||||
gus->irq = gus_irqs[val & 7];
|
||||
|
||||
if (val & 0x40)
|
||||
gus->irq_midi = gus->irq;
|
||||
{
|
||||
if (gus->irq == -1)
|
||||
gus->irq = gus->irq_midi = gus_irqs[(val >> 3) & 7];
|
||||
else
|
||||
gus->irq_midi = gus->irq;
|
||||
}
|
||||
else
|
||||
gus->irq_midi = gus_irqs_midi[(val >> 3) & 7];
|
||||
|
||||
@@ -941,19 +947,18 @@ void gus_poll_wave(void *p)
|
||||
if (gus->cur[d] <= gus->start[d])
|
||||
{
|
||||
int diff = gus->start[d] - gus->cur[d];
|
||||
if (!(gus->rctrl[d]&4))
|
||||
|
||||
if (gus->ctrl[d]&8)
|
||||
{
|
||||
if (!(gus->ctrl[d]&8))
|
||||
{
|
||||
gus->ctrl[d] |= 1;
|
||||
gus->cur[d] = (gus->ctrl[d] & 0x40) ? gus->end[d] : gus->start[d];
|
||||
}
|
||||
else
|
||||
{
|
||||
if (gus->ctrl[d]&0x10) gus->ctrl[d]^=0x40;
|
||||
gus->cur[d] = (gus->ctrl[d] & 0x40) ? (gus->end[d] - diff) : (gus->start[d] + diff);
|
||||
}
|
||||
if (gus->ctrl[d]&0x10) gus->ctrl[d]^=0x40;
|
||||
gus->cur[d] = (gus->ctrl[d] & 0x40) ? (gus->end[d] - diff) : (gus->start[d] + diff);
|
||||
}
|
||||
else if (!(gus->rctrl[d]&4))
|
||||
{
|
||||
gus->ctrl[d] |= 1;
|
||||
gus->cur[d] = (gus->ctrl[d] & 0x40) ? gus->end[d] : gus->start[d];
|
||||
}
|
||||
|
||||
if ((gus->ctrl[d] & 0x20) && !gus->waveirqs[d])
|
||||
{
|
||||
gus->waveirqs[d] = 1;
|
||||
@@ -969,18 +974,15 @@ void gus_poll_wave(void *p)
|
||||
if (gus->cur[d] >= gus->end[d])
|
||||
{
|
||||
int diff = gus->cur[d] - gus->end[d];
|
||||
if (!(gus->rctrl[d]&4))
|
||||
if (gus->ctrl[d]&8)
|
||||
{
|
||||
if (!(gus->ctrl[d]&8))
|
||||
{
|
||||
gus->ctrl[d] |= 1;
|
||||
gus->cur[d] = (gus->ctrl[d] & 0x40) ? gus->end[d] : gus->start[d];
|
||||
}
|
||||
else
|
||||
{
|
||||
if (gus->ctrl[d]&0x10) gus->ctrl[d]^=0x40;
|
||||
gus->cur[d] = (gus->ctrl[d] & 0x40) ? (gus->end[d] - diff) : (gus->start[d] + diff);
|
||||
}
|
||||
if (gus->ctrl[d]&0x10) gus->ctrl[d]^=0x40;
|
||||
gus->cur[d] = (gus->ctrl[d] & 0x40) ? (gus->end[d] - diff) : (gus->start[d] + diff);
|
||||
}
|
||||
else if (!(gus->rctrl[d]&4))
|
||||
{
|
||||
gus->ctrl[d] |= 1;
|
||||
gus->cur[d] = (gus->ctrl[d] & 0x40) ? gus->end[d] : gus->start[d];
|
||||
}
|
||||
if ((gus->ctrl[d] & 0x20) && !gus->waveirqs[d])
|
||||
{
|
||||
|
||||
@@ -1,8 +1,4 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
uint16_t oldcs;
|
||||
uint32_t oldpc;
|
||||
extern uint32_t rmdat32;
|
||||
int oldcpl;
|
||||
|
||||
@@ -10,10 +6,9 @@ extern int nmi_enable;
|
||||
|
||||
int tempc;
|
||||
int cycles,output;
|
||||
int ssegs;
|
||||
int firstrepcycle;
|
||||
|
||||
uint32_t easeg,eaaddr,ealimit,ealimitw;
|
||||
uint32_t easeg,ealimit,ealimitw;
|
||||
|
||||
int skipnextprint;
|
||||
int inhlt;
|
||||
|
||||
@@ -1,12 +1,9 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opCMPXCHG_b_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp, temp2 = AL;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -24,7 +21,7 @@ static int opCMPXCHG_b_a32(uint32_t fetchdat)
|
||||
uint8_t temp, temp2 = AL;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -43,7 +40,7 @@ static int opCMPXCHG_w_a16(uint32_t fetchdat)
|
||||
uint16_t temp, temp2 = AX;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -61,7 +58,7 @@ static int opCMPXCHG_w_a32(uint32_t fetchdat)
|
||||
uint16_t temp, temp2 = AX;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -80,7 +77,7 @@ static int opCMPXCHG_l_a16(uint32_t fetchdat)
|
||||
uint32_t temp, temp2 = EAX;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -98,7 +95,7 @@ static int opCMPXCHG_l_a32(uint32_t fetchdat)
|
||||
uint32_t temp, temp2 = EAX;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -117,17 +114,17 @@ static int opCMPXCHG8B_a16(uint32_t fetchdat)
|
||||
uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 0;
|
||||
}
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = geteal();
|
||||
temp_hi = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
if (EAX == temp && EDX == temp_hi)
|
||||
{
|
||||
seteal(EBX);
|
||||
writememl(easeg, eaaddr+4, ECX);
|
||||
writememl(easeg, cpu_state.eaaddr+4, ECX);
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -148,17 +145,17 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat)
|
||||
uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 0;
|
||||
}
|
||||
fetch_ea_32(fetchdat);
|
||||
temp = geteal();
|
||||
temp_hi = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
temp_hi = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
if (EAX == temp && EDX == temp_hi)
|
||||
{
|
||||
seteal(EBX);
|
||||
writememl(easeg, eaaddr+4, ECX);
|
||||
writememl(easeg, cpu_state.eaaddr+4, ECX);
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -180,7 +177,7 @@ static int opXADD_b_a16(uint32_t fetchdat)
|
||||
uint8_t temp;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -197,7 +194,7 @@ static int opXADD_b_a32(uint32_t fetchdat)
|
||||
uint8_t temp;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -215,7 +212,7 @@ static int opXADD_w_a16(uint32_t fetchdat)
|
||||
uint16_t temp;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -232,7 +229,7 @@ static int opXADD_w_a32(uint32_t fetchdat)
|
||||
uint16_t temp;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -250,7 +247,7 @@ static int opXADD_l_a16(uint32_t fetchdat)
|
||||
uint32_t temp;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -267,7 +264,7 @@ static int opXADD_l_a32(uint32_t fetchdat)
|
||||
uint32_t temp;
|
||||
if (!is486)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
|
||||
@@ -1,13 +1,10 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opBT_w_r_a16(uint32_t fetchdat)
|
||||
{
|
||||
int tempc;
|
||||
uint16_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG;
|
||||
@@ -21,7 +18,7 @@ static int opBT_w_r_a32(uint32_t fetchdat)
|
||||
uint16_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0;
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG;
|
||||
@@ -35,7 +32,7 @@ static int opBT_l_r_a16(uint32_t fetchdat)
|
||||
uint32_t temp;
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG;
|
||||
@@ -49,7 +46,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
||||
uint32_t temp;
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0;
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
flags_rebuild();
|
||||
if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG;
|
||||
@@ -66,7 +63,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
||||
uint16_t temp; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].w & 15)); \
|
||||
@@ -84,7 +81,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
||||
uint16_t temp; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].w & 15)); \
|
||||
@@ -102,7 +99,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
||||
uint32_t temp; \
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].l & 31)); \
|
||||
@@ -120,7 +117,7 @@ static int opBT_l_r_a32(uint32_t fetchdat)
|
||||
uint32_t temp; \
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
|
||||
temp operation (1 << (cpu_state.regs[cpu_reg].l & 31)); \
|
||||
@@ -167,7 +164,7 @@ static int opBA_w_a16(uint32_t fetchdat)
|
||||
|
||||
default:
|
||||
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
}
|
||||
@@ -207,7 +204,7 @@ static int opBA_w_a32(uint32_t fetchdat)
|
||||
|
||||
default:
|
||||
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
}
|
||||
@@ -248,7 +245,7 @@ static int opBA_l_a16(uint32_t fetchdat)
|
||||
|
||||
default:
|
||||
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
}
|
||||
@@ -288,7 +285,7 @@ static int opBA_l_a32(uint32_t fetchdat)
|
||||
|
||||
default:
|
||||
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#define CALL_FAR_w(new_seg, new_pc) \
|
||||
old_cs = CS; \
|
||||
old_pc = cpu_state.pc; \
|
||||
@@ -120,8 +117,8 @@ static int opFF_w_a16(uint32_t fetchdat)
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmemw(easeg, eaaddr);
|
||||
new_cs = readmemw(easeg, (eaaddr + 2)); if (abrt) return 1;
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 2)); if (abrt) return 1;
|
||||
|
||||
CALL_FAR_w(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
@@ -135,8 +132,8 @@ static int opFF_w_a16(uint32_t fetchdat)
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmemw(easeg, eaaddr);
|
||||
new_cs = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
|
||||
CPU_BLOCK_END();
|
||||
@@ -185,8 +182,8 @@ static int opFF_w_a32(uint32_t fetchdat)
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmemw(easeg, eaaddr);
|
||||
new_cs = readmemw(easeg, (eaaddr + 2)); if (abrt) return 1;
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 2)); if (abrt) return 1;
|
||||
|
||||
CALL_FAR_w(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
@@ -200,8 +197,8 @@ static int opFF_w_a32(uint32_t fetchdat)
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmemw(easeg, eaaddr);
|
||||
new_cs = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
new_pc = readmemw(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
|
||||
CPU_BLOCK_END();
|
||||
@@ -251,8 +248,8 @@ static int opFF_l_a16(uint32_t fetchdat)
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmeml(easeg, eaaddr);
|
||||
new_cs = readmemw(easeg, (eaaddr + 4)); if (abrt) return 1;
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 4)); if (abrt) return 1;
|
||||
|
||||
CALL_FAR_l(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
@@ -266,8 +263,8 @@ static int opFF_l_a16(uint32_t fetchdat)
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmeml(easeg, eaaddr);
|
||||
new_cs = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
|
||||
CPU_BLOCK_END();
|
||||
@@ -316,8 +313,8 @@ static int opFF_l_a32(uint32_t fetchdat)
|
||||
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
|
||||
break;
|
||||
case 0x18: /*CALL far*/
|
||||
new_pc = readmeml(easeg, eaaddr);
|
||||
new_cs = readmemw(easeg, (eaaddr + 4)); if (abrt) return 1;
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, (cpu_state.eaaddr + 4)); if (abrt) return 1;
|
||||
|
||||
CALL_FAR_l(new_cs, new_pc);
|
||||
CPU_BLOCK_END();
|
||||
@@ -331,8 +328,8 @@ static int opFF_l_a32(uint32_t fetchdat)
|
||||
break;
|
||||
case 0x28: /*JMP far*/
|
||||
oxpc = cpu_state.pc;
|
||||
new_pc = readmeml(easeg, eaaddr);
|
||||
new_cs = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
new_pc = readmeml(easeg, cpu_state.eaaddr);
|
||||
new_cs = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
cpu_state.pc = new_pc;
|
||||
loadcsjmp(new_cs, oxpc); if (abrt) return 1;
|
||||
CPU_BLOCK_END();
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
*/
|
||||
static int internal_illegal(char *s)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86gpf(s, 0);
|
||||
return abrt;
|
||||
}
|
||||
@@ -149,9 +149,9 @@ static int opFXSAVESTOR_a16(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
|
||||
if (eaaddr & 0xf)
|
||||
if (cpu_state.eaaddr & 0xf)
|
||||
{
|
||||
pclog("Effective address %04X not on 16-byte boundary\n", eaaddr);
|
||||
pclog("Effective address %04X not on 16-byte boundary\n", cpu_state.eaaddr);
|
||||
x86gpf(NULL, 0);
|
||||
return abrt;
|
||||
}
|
||||
@@ -169,30 +169,30 @@ static int opFXSAVESTOR_a16(uint32_t fetchdat)
|
||||
|
||||
FP_ENTER();
|
||||
|
||||
old_eaaddr = eaaddr;
|
||||
old_eaaddr = cpu_state.eaaddr;
|
||||
|
||||
if (fxinst == 1)
|
||||
{
|
||||
/* FXRSTOR */
|
||||
// pclog("FXRSTOR issued\n");
|
||||
|
||||
npxc = readmemw(easeg, eaaddr);
|
||||
fpus = readmemw(easeg, eaaddr + 2);
|
||||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
fpus = readmemw(easeg, cpu_state.eaaddr + 2);
|
||||
npxc = (npxc & ~FPU_CW_Reserved_Bits) | 0x0040;
|
||||
TOP = (fpus >> 11) & 7;
|
||||
npxs &= fpus & ~0x3800;
|
||||
|
||||
/* foo = readmemw(easeg, eaaddr + 6) & 0x7FF; */
|
||||
/* foo = readmemw(easeg, cpu_state.eaaddr + 6) & 0x7FF; */
|
||||
|
||||
x87_pc_off = readmeml(easeg, eaaddr+8);
|
||||
x87_pc_seg = readmemw(easeg, eaaddr+12);
|
||||
x87_pc_off = readmeml(easeg, cpu_state.eaaddr+8);
|
||||
x87_pc_seg = readmemw(easeg, cpu_state.eaaddr+12);
|
||||
/* if (cr0 & 1)
|
||||
{
|
||||
x87_pc_seg &= 0xFFFC;
|
||||
x87_pc_seg |= ((_cs.access >> 5) & 3);
|
||||
} */
|
||||
|
||||
ftwb = readmemb(easeg, eaaddr + 4);
|
||||
ftwb = readmemb(easeg, cpu_state.eaaddr + 4);
|
||||
|
||||
if (ftwb & 0x01) rec_ftw |= 0x0003;
|
||||
if (ftwb & 0x02) rec_ftw |= 0x000C;
|
||||
@@ -203,37 +203,37 @@ static int opFXSAVESTOR_a16(uint32_t fetchdat)
|
||||
if (ftwb & 0x40) rec_ftw |= 0x3000;
|
||||
if (ftwb & 0x80) rec_ftw |= 0xC000;
|
||||
|
||||
x87_op_off = readmeml(easeg, eaaddr+16);
|
||||
x87_op_off |= (readmemw(easeg, eaaddr + 6) >> 12) << 16;
|
||||
x87_op_seg = readmemw(easeg, eaaddr+20);
|
||||
x87_op_off = readmeml(easeg, cpu_state.eaaddr+16);
|
||||
x87_op_off |= (readmemw(easeg, cpu_state.eaaddr + 6) >> 12) << 16;
|
||||
x87_op_seg = readmemw(easeg, cpu_state.eaaddr+20);
|
||||
/* if (cr0 & 1)
|
||||
{
|
||||
x87_op_seg &= 0xFFFC;
|
||||
x87_op_seg |= ((_ds.access >> 5) & 3);
|
||||
} */
|
||||
|
||||
eaaddr = old_eaaddr + 32;
|
||||
cpu_state.eaaddr = old_eaaddr + 32;
|
||||
x87_ldmmx(&MM[0]); x87_ld_frstor(0);
|
||||
|
||||
eaaddr = old_eaaddr + 48;
|
||||
cpu_state.eaaddr = old_eaaddr + 48;
|
||||
x87_ldmmx(&MM[1]); x87_ld_frstor(1);
|
||||
|
||||
eaaddr = old_eaaddr + 64;
|
||||
cpu_state.eaaddr = old_eaaddr + 64;
|
||||
x87_ldmmx(&MM[2]); x87_ld_frstor(2);
|
||||
|
||||
eaaddr = old_eaaddr + 80;
|
||||
cpu_state.eaaddr = old_eaaddr + 80;
|
||||
x87_ldmmx(&MM[3]); x87_ld_frstor(3);
|
||||
|
||||
eaaddr = old_eaaddr + 96;
|
||||
cpu_state.eaaddr = old_eaaddr + 96;
|
||||
x87_ldmmx(&MM[4]); x87_ld_frstor(4);
|
||||
|
||||
eaaddr = old_eaaddr + 112;
|
||||
cpu_state.eaaddr = old_eaaddr + 112;
|
||||
x87_ldmmx(&MM[5]); x87_ld_frstor(5);
|
||||
|
||||
eaaddr = old_eaaddr + 128;
|
||||
cpu_state.eaaddr = old_eaaddr + 128;
|
||||
x87_ldmmx(&MM[6]); x87_ld_frstor(6);
|
||||
|
||||
eaaddr = old_eaaddr + 144;
|
||||
cpu_state.eaaddr = old_eaaddr + 144;
|
||||
x87_ldmmx(&MM[7]); x87_ld_frstor(7);
|
||||
|
||||
ismmx = 0;
|
||||
@@ -264,42 +264,42 @@ static int opFXSAVESTOR_a16(uint32_t fetchdat)
|
||||
if (twd & 0x3000 == 0x3000) ftwb |= 0x40;
|
||||
if (twd & 0xC000 == 0xC000) ftwb |= 0x80;
|
||||
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+2,npxs);
|
||||
writememb(easeg,eaaddr+4,ftwb);
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+2,npxs);
|
||||
writememb(easeg,cpu_state.eaaddr+4,ftwb);
|
||||
|
||||
writememw(easeg,eaaddr+6,(x87_op_off>>16)<<12);
|
||||
writememl(easeg,eaaddr+8,x87_pc_off);
|
||||
writememw(easeg,eaaddr+12,x87_pc_seg);
|
||||
writememw(easeg,cpu_state.eaaddr+6,(x87_op_off>>16)<<12);
|
||||
writememl(easeg,cpu_state.eaaddr+8,x87_pc_off);
|
||||
writememw(easeg,cpu_state.eaaddr+12,x87_pc_seg);
|
||||
|
||||
writememl(easeg,eaaddr+16,x87_op_off);
|
||||
writememw(easeg,eaaddr+20,x87_op_seg);
|
||||
writememl(easeg,cpu_state.eaaddr+16,x87_op_off);
|
||||
writememw(easeg,cpu_state.eaaddr+20,x87_op_seg);
|
||||
|
||||
eaaddr = old_eaaddr + 32;
|
||||
cpu_state.eaaddr = old_eaaddr + 32;
|
||||
ismmx ? x87_stmmx(MM[0]) : x87_st_fsave(0);
|
||||
|
||||
eaaddr = old_eaaddr + 48;
|
||||
cpu_state.eaaddr = old_eaaddr + 48;
|
||||
ismmx ? x87_stmmx(MM[1]) : x87_st_fsave(1);
|
||||
|
||||
eaaddr = old_eaaddr + 64;
|
||||
cpu_state.eaaddr = old_eaaddr + 64;
|
||||
ismmx ? x87_stmmx(MM[2]) : x87_st_fsave(2);
|
||||
|
||||
eaaddr = old_eaaddr + 80;
|
||||
cpu_state.eaaddr = old_eaaddr + 80;
|
||||
ismmx ? x87_stmmx(MM[3]) : x87_st_fsave(3);
|
||||
|
||||
eaaddr = old_eaaddr + 96;
|
||||
cpu_state.eaaddr = old_eaaddr + 96;
|
||||
ismmx ? x87_stmmx(MM[4]) : x87_st_fsave(4);
|
||||
|
||||
eaaddr = old_eaaddr + 112;
|
||||
cpu_state.eaaddr = old_eaaddr + 112;
|
||||
ismmx ? x87_stmmx(MM[5]) : x87_st_fsave(5);
|
||||
|
||||
eaaddr = old_eaaddr + 128;
|
||||
cpu_state.eaaddr = old_eaaddr + 128;
|
||||
ismmx ? x87_stmmx(MM[6]) : x87_st_fsave(6);
|
||||
|
||||
eaaddr = old_eaaddr + 144;
|
||||
cpu_state.eaaddr = old_eaaddr + 144;
|
||||
ismmx ? x87_stmmx(MM[7]) : x87_st_fsave(7);
|
||||
|
||||
eaaddr = old_eaaddr;
|
||||
cpu_state.eaaddr = old_eaaddr;
|
||||
|
||||
CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
|
||||
|
||||
@@ -325,9 +325,9 @@ static int opFXSAVESTOR_a32(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
|
||||
if (eaaddr & 0xf)
|
||||
if (cpu_state.eaaddr & 0xf)
|
||||
{
|
||||
pclog("Effective address %08X not on 16-byte boundary\n", eaaddr);
|
||||
pclog("Effective address %08X not on 16-byte boundary\n", cpu_state.eaaddr);
|
||||
x86gpf(NULL, 0);
|
||||
return abrt;
|
||||
}
|
||||
@@ -345,30 +345,30 @@ static int opFXSAVESTOR_a32(uint32_t fetchdat)
|
||||
|
||||
FP_ENTER();
|
||||
|
||||
old_eaaddr = eaaddr;
|
||||
old_eaaddr = cpu_state.eaaddr;
|
||||
|
||||
if (fxinst == 1)
|
||||
{
|
||||
/* FXRSTOR */
|
||||
// pclog("FXRSTOR issued\n");
|
||||
|
||||
npxc = readmemw(easeg, eaaddr);
|
||||
fpus = readmemw(easeg, eaaddr + 2);
|
||||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
fpus = readmemw(easeg, cpu_state.eaaddr + 2);
|
||||
npxc = (npxc & ~FPU_CW_Reserved_Bits) | 0x0040;
|
||||
TOP = (fpus >> 11) & 7;
|
||||
npxs &= fpus & ~0x3800;
|
||||
|
||||
/* foo = readmemw(easeg, eaaddr + 6) & 0x7FF; */
|
||||
/* foo = readmemw(easeg, cpu_state.eaaddr + 6) & 0x7FF; */
|
||||
|
||||
x87_pc_off = readmeml(easeg, eaaddr+8);
|
||||
x87_pc_seg = readmemw(easeg, eaaddr+12);
|
||||
x87_pc_off = readmeml(easeg, cpu_state.eaaddr+8);
|
||||
x87_pc_seg = readmemw(easeg, cpu_state.eaaddr+12);
|
||||
/* if (cr0 & 1)
|
||||
{
|
||||
x87_pc_seg &= 0xFFFC;
|
||||
x87_pc_seg |= ((_cs.access >> 5) & 3);
|
||||
} */
|
||||
|
||||
ftwb = readmemb(easeg, eaaddr + 4);
|
||||
ftwb = readmemb(easeg, cpu_state.eaaddr + 4);
|
||||
|
||||
if (ftwb & 0x01) rec_ftw |= 0x0003;
|
||||
if (ftwb & 0x02) rec_ftw |= 0x000C;
|
||||
@@ -379,37 +379,37 @@ static int opFXSAVESTOR_a32(uint32_t fetchdat)
|
||||
if (ftwb & 0x40) rec_ftw |= 0x3000;
|
||||
if (ftwb & 0x80) rec_ftw |= 0xC000;
|
||||
|
||||
x87_op_off = readmeml(easeg, eaaddr+16);
|
||||
x87_op_off |= (readmemw(easeg, eaaddr + 6) >> 12) << 16;
|
||||
x87_op_seg = readmemw(easeg, eaaddr+20);
|
||||
x87_op_off = readmeml(easeg, cpu_state.eaaddr+16);
|
||||
x87_op_off |= (readmemw(easeg, cpu_state.eaaddr + 6) >> 12) << 16;
|
||||
x87_op_seg = readmemw(easeg, cpu_state.eaaddr+20);
|
||||
/* if (cr0 & 1)
|
||||
{
|
||||
x87_op_seg &= 0xFFFC;
|
||||
x87_op_seg |= ((_ds.access >> 5) & 3);
|
||||
} */
|
||||
|
||||
eaaddr = old_eaaddr + 32;
|
||||
cpu_state.eaaddr = old_eaaddr + 32;
|
||||
x87_ldmmx(&MM[0]); x87_ld_frstor(0);
|
||||
|
||||
eaaddr = old_eaaddr + 48;
|
||||
cpu_state.eaaddr = old_eaaddr + 48;
|
||||
x87_ldmmx(&MM[1]); x87_ld_frstor(1);
|
||||
|
||||
eaaddr = old_eaaddr + 64;
|
||||
cpu_state.eaaddr = old_eaaddr + 64;
|
||||
x87_ldmmx(&MM[2]); x87_ld_frstor(2);
|
||||
|
||||
eaaddr = old_eaaddr + 80;
|
||||
cpu_state.eaaddr = old_eaaddr + 80;
|
||||
x87_ldmmx(&MM[3]); x87_ld_frstor(3);
|
||||
|
||||
eaaddr = old_eaaddr + 96;
|
||||
cpu_state.eaaddr = old_eaaddr + 96;
|
||||
x87_ldmmx(&MM[4]); x87_ld_frstor(4);
|
||||
|
||||
eaaddr = old_eaaddr + 112;
|
||||
cpu_state.eaaddr = old_eaaddr + 112;
|
||||
x87_ldmmx(&MM[5]); x87_ld_frstor(5);
|
||||
|
||||
eaaddr = old_eaaddr + 128;
|
||||
cpu_state.eaaddr = old_eaaddr + 128;
|
||||
x87_ldmmx(&MM[6]); x87_ld_frstor(6);
|
||||
|
||||
eaaddr = old_eaaddr + 144;
|
||||
cpu_state.eaaddr = old_eaaddr + 144;
|
||||
x87_ldmmx(&MM[7]); x87_ld_frstor(7);
|
||||
|
||||
ismmx = 0;
|
||||
@@ -440,42 +440,42 @@ static int opFXSAVESTOR_a32(uint32_t fetchdat)
|
||||
if (twd & 0x3000 == 0x3000) ftwb |= 0x40;
|
||||
if (twd & 0xC000 == 0xC000) ftwb |= 0x80;
|
||||
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+2,npxs);
|
||||
writememb(easeg,eaaddr+4,ftwb);
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+2,npxs);
|
||||
writememb(easeg,cpu_state.eaaddr+4,ftwb);
|
||||
|
||||
writememw(easeg,eaaddr+6,(x87_op_off>>16)<<12);
|
||||
writememl(easeg,eaaddr+8,x87_pc_off);
|
||||
writememw(easeg,eaaddr+12,x87_pc_seg);
|
||||
writememw(easeg,cpu_state.eaaddr+6,(x87_op_off>>16)<<12);
|
||||
writememl(easeg,cpu_state.eaaddr+8,x87_pc_off);
|
||||
writememw(easeg,cpu_state.eaaddr+12,x87_pc_seg);
|
||||
|
||||
writememl(easeg,eaaddr+16,x87_op_off);
|
||||
writememw(easeg,eaaddr+20,x87_op_seg);
|
||||
writememl(easeg,cpu_state.eaaddr+16,x87_op_off);
|
||||
writememw(easeg,cpu_state.eaaddr+20,x87_op_seg);
|
||||
|
||||
eaaddr = old_eaaddr + 32;
|
||||
cpu_state.eaaddr = old_eaaddr + 32;
|
||||
ismmx ? x87_stmmx(MM[0]) : x87_st_fsave(0);
|
||||
|
||||
eaaddr = old_eaaddr + 48;
|
||||
cpu_state.eaaddr = old_eaaddr + 48;
|
||||
ismmx ? x87_stmmx(MM[1]) : x87_st_fsave(1);
|
||||
|
||||
eaaddr = old_eaaddr + 64;
|
||||
cpu_state.eaaddr = old_eaaddr + 64;
|
||||
ismmx ? x87_stmmx(MM[2]) : x87_st_fsave(2);
|
||||
|
||||
eaaddr = old_eaaddr + 80;
|
||||
cpu_state.eaaddr = old_eaaddr + 80;
|
||||
ismmx ? x87_stmmx(MM[3]) : x87_st_fsave(3);
|
||||
|
||||
eaaddr = old_eaaddr + 96;
|
||||
cpu_state.eaaddr = old_eaaddr + 96;
|
||||
ismmx ? x87_stmmx(MM[4]) : x87_st_fsave(4);
|
||||
|
||||
eaaddr = old_eaaddr + 112;
|
||||
cpu_state.eaaddr = old_eaaddr + 112;
|
||||
ismmx ? x87_stmmx(MM[5]) : x87_st_fsave(5);
|
||||
|
||||
eaaddr = old_eaaddr + 128;
|
||||
cpu_state.eaaddr = old_eaaddr + 128;
|
||||
ismmx ? x87_stmmx(MM[6]) : x87_st_fsave(6);
|
||||
|
||||
eaaddr = old_eaaddr + 144;
|
||||
cpu_state.eaaddr = old_eaaddr + 144;
|
||||
ismmx ? x87_stmmx(MM[7]) : x87_st_fsave(7);
|
||||
|
||||
eaaddr = old_eaaddr;
|
||||
cpu_state.eaaddr = old_eaaddr;
|
||||
|
||||
CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
|
||||
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opINT3(uint32_t fetchdat)
|
||||
{
|
||||
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
|
||||
@@ -70,7 +67,7 @@ static int opINTO(uint32_t fetchdat)
|
||||
}
|
||||
if (VF_SET())
|
||||
{
|
||||
oldpc = cpu_state.pc;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
x86_int_sw(4);
|
||||
return 1;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker, Tenshi
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opCBW(uint32_t fetchdat)
|
||||
{
|
||||
AH = (AL & 0x80) ? 0xff : 0;
|
||||
@@ -551,7 +548,7 @@ static int opLOCK(uint32_t fetchdat)
|
||||
cpu_state.pc++;
|
||||
|
||||
CLOCK_CYCLES(4);
|
||||
return x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
|
||||
|
||||
@@ -563,7 +560,7 @@ static int opBOUND_w_a16(uint32_t fetchdat)
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteaw();
|
||||
high = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
high = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
|
||||
if (((int16_t)cpu_state.regs[cpu_reg].w < low) || ((int16_t)cpu_state.regs[cpu_reg].w > high))
|
||||
{
|
||||
@@ -581,7 +578,7 @@ static int opBOUND_w_a32(uint32_t fetchdat)
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteaw();
|
||||
high = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
high = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
|
||||
if (((int16_t)cpu_state.regs[cpu_reg].w < low) || ((int16_t)cpu_state.regs[cpu_reg].w > high))
|
||||
{
|
||||
@@ -600,7 +597,7 @@ static int opBOUND_l_a16(uint32_t fetchdat)
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteal();
|
||||
high = readmeml(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
high = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
|
||||
if (((int32_t)cpu_state.regs[cpu_reg].l < low) || ((int32_t)cpu_state.regs[cpu_reg].l > high))
|
||||
{
|
||||
@@ -618,7 +615,7 @@ static int opBOUND_l_a32(uint32_t fetchdat)
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
low = geteal();
|
||||
high = readmeml(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
high = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
|
||||
if (((int32_t)cpu_state.regs[cpu_reg].l < low) || ((int32_t)cpu_state.regs[cpu_reg].l > high))
|
||||
{
|
||||
@@ -775,7 +772,7 @@ static int opCPUID(uint32_t fetchdat)
|
||||
CLOCK_CYCLES(9);
|
||||
return 0;
|
||||
}
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -788,7 +785,7 @@ static int opRDMSR(uint32_t fetchdat)
|
||||
CLOCK_CYCLES(9);
|
||||
return 0;
|
||||
}
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
@@ -801,7 +798,7 @@ static int opWRMSR(uint32_t fetchdat)
|
||||
CLOCK_CYCLES(9);
|
||||
return 0;
|
||||
}
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#define SSATB(val) (((val) < -128) ? -128 : (((val) > 127) ? 127 : (val)))
|
||||
#define SSATW(val) (((val) < -32768) ? -32768 : (((val) > 32767) ? 32767 : (val)))
|
||||
#define USATB(val) (((val) < 0) ? 0 : (((val) > 255) ? 255 : (val)))
|
||||
@@ -14,14 +11,14 @@
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
src.q = readmemq(easeg, eaaddr); if (abrt) return 1; \
|
||||
src.q = readmemq(easeg, cpu_state.eaaddr); if (abrt) return 1; \
|
||||
CLOCK_CYCLES(2); \
|
||||
}
|
||||
|
||||
#define MMX_ENTER() \
|
||||
if (!cpu_hasMMX) \
|
||||
{ \
|
||||
cpu_state.pc = oldpc; \
|
||||
cpu_state.pc = cpu_state.oldpc; \
|
||||
x86illegal(); \
|
||||
return 1; \
|
||||
} \
|
||||
@@ -36,7 +33,7 @@ static int opEMMS(uint32_t fetchdat)
|
||||
{
|
||||
if (!cpu_hasMMX)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opPADDB_a16(uint32_t fetchdat)
|
||||
{
|
||||
MMX_REG src;
|
||||
@@ -297,8 +294,8 @@ static int opPMULLW_a16(uint32_t fetchdat)
|
||||
{
|
||||
MMX_REG src;
|
||||
|
||||
src.l[0] = readmeml(easeg, eaaddr);
|
||||
src.l[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
MM[cpu_reg].w[0] *= src.w[0];
|
||||
MM[cpu_reg].w[1] *= src.w[1];
|
||||
MM[cpu_reg].w[2] *= src.w[2];
|
||||
@@ -324,8 +321,8 @@ static int opPMULLW_a32(uint32_t fetchdat)
|
||||
{
|
||||
MMX_REG src;
|
||||
|
||||
src.l[0] = readmeml(easeg, eaaddr);
|
||||
src.l[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
MM[cpu_reg].w[0] *= src.w[0];
|
||||
MM[cpu_reg].w[1] *= src.w[1];
|
||||
MM[cpu_reg].w[2] *= src.w[2];
|
||||
@@ -352,8 +349,8 @@ static int opPMULHW_a16(uint32_t fetchdat)
|
||||
{
|
||||
MMX_REG src;
|
||||
|
||||
src.l[0] = readmeml(easeg, eaaddr);
|
||||
src.l[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
@@ -379,8 +376,8 @@ static int opPMULHW_a32(uint32_t fetchdat)
|
||||
{
|
||||
MMX_REG src;
|
||||
|
||||
src.l[0] = readmeml(easeg, eaaddr);
|
||||
src.l[1] = readmeml(easeg, eaaddr + 4); if (abrt) return 0;
|
||||
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (abrt) return 0;
|
||||
MM[cpu_reg].w[0] = ((int32_t)MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
||||
MM[cpu_reg].w[1] = ((int32_t)MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
||||
MM[cpu_reg].w[2] = ((int32_t)MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opMOVD_l_mm_a16(uint32_t fetchdat)
|
||||
{
|
||||
MMX_ENTER();
|
||||
@@ -16,7 +13,7 @@ static int opMOVD_l_mm_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t dst;
|
||||
|
||||
dst = readmeml(easeg, eaaddr); if (abrt) return 1;
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (abrt) return 1;
|
||||
MM[cpu_reg].l[0] = dst;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
|
||||
@@ -39,7 +36,7 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t dst;
|
||||
|
||||
dst = readmeml(easeg, eaaddr); if (abrt) return 1;
|
||||
dst = readmeml(easeg, cpu_state.eaaddr); if (abrt) return 1;
|
||||
MM[cpu_reg].l[0] = dst;
|
||||
MM[cpu_reg].l[1] = 0;
|
||||
|
||||
@@ -60,8 +57,8 @@ static int opMOVD_mm_l_a16(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 3);
|
||||
writememl(easeg, eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
||||
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
@@ -78,8 +75,8 @@ static int opMOVD_mm_l_a32(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 3);
|
||||
writememl(easeg, eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
||||
writememl(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
@@ -99,7 +96,7 @@ static int opMOVQ_q_mm_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint64_t dst;
|
||||
|
||||
dst = readmemq(easeg, eaaddr); if (abrt) return 1;
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (abrt) return 1;
|
||||
MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
@@ -119,7 +116,7 @@ static int opMOVQ_q_mm_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint64_t dst;
|
||||
|
||||
dst = readmemq(easeg, eaaddr); if (abrt) return 1;
|
||||
dst = readmemq(easeg, cpu_state.eaaddr); if (abrt) return 1;
|
||||
MM[cpu_reg].q = dst;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
@@ -138,8 +135,8 @@ static int opMOVQ_mm_q_a16(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
|
||||
writememq(easeg, eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].l[0]); if (abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
@@ -156,8 +153,8 @@ static int opMOVQ_mm_q_a32(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
|
||||
writememq(easeg, eaaddr, MM[cpu_reg].q); if (abrt) return 1;
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
writememq(easeg, cpu_state.eaaddr, MM[cpu_reg].q); if (abrt) return 1;
|
||||
CLOCK_CYCLES(2);
|
||||
}
|
||||
return 0;
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opPUNPCKLDQ_a16(uint32_t fetchdat)
|
||||
{
|
||||
MMX_ENTER();
|
||||
@@ -15,7 +12,7 @@ static int opPUNPCKLDQ_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src;
|
||||
|
||||
src = readmeml(easeg, eaaddr); if (abrt) return 0;
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (abrt) return 0;
|
||||
MM[cpu_reg].l[1] = src;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
@@ -36,7 +33,7 @@ static int opPUNPCKLDQ_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src;
|
||||
|
||||
src = readmeml(easeg, eaaddr); if (abrt) return 0;
|
||||
src = readmeml(easeg, cpu_state.eaaddr); if (abrt) return 0;
|
||||
MM[cpu_reg].l[1] = src;
|
||||
|
||||
CLOCK_CYCLES(2);
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#define MMX_GETSHIFT() \
|
||||
if (cpu_mod == 3) \
|
||||
{ \
|
||||
@@ -9,7 +6,7 @@
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
shift = readmemb(easeg, eaaddr); if (abrt) return 0; \
|
||||
shift = readmemb(easeg, cpu_state.eaaddr); if (abrt) return 0; \
|
||||
CLOCK_CYCLES(2); \
|
||||
}
|
||||
|
||||
@@ -56,7 +53,7 @@ static int opPSxxW_imm(uint32_t fetchdat)
|
||||
break;
|
||||
default:
|
||||
pclog("Bad PSxxW (0F 71) instruction %02X\n", op);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 0;
|
||||
}
|
||||
@@ -227,7 +224,7 @@ static int opPSxxD_imm(uint32_t fetchdat)
|
||||
break;
|
||||
default:
|
||||
pclog("Bad PSxxD (0F 72) instruction %02X\n", op);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 0;
|
||||
}
|
||||
@@ -379,7 +376,7 @@ static int opPSxxQ_imm(uint32_t fetchdat)
|
||||
break;
|
||||
default:
|
||||
pclog("Bad PSxxQ (0F 73) instruction %02X\n", op);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker, leilei
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opMOV_AL_imm(uint32_t fetchdat)
|
||||
{
|
||||
AL = getbytef();
|
||||
@@ -161,7 +158,7 @@ static int opMOV_b_imm_a16(uint32_t fetchdat)
|
||||
uint8_t temp;
|
||||
fetch_ea_16(fetchdat);
|
||||
temp = readmemb(cs,cpu_state.pc); cpu_state.pc++; if (abrt) return 1;
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
seteab(temp);
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return abrt;
|
||||
@@ -217,7 +214,7 @@ static int opMOV_l_imm_a32(uint32_t fetchdat)
|
||||
static int opMOV_AL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint8_t temp = readmemb(ea_seg->base, addr); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
@@ -225,7 +222,7 @@ static int opMOV_AL_a16(uint32_t fetchdat)
|
||||
static int opMOV_AL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
uint8_t temp = readmemb(ea_seg->base, addr); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
@@ -233,7 +230,7 @@ static int opMOV_AL_a32(uint32_t fetchdat)
|
||||
static int opMOV_AX_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint16_t temp = readmemw(ea_seg->base, addr); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
AX = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
@@ -241,7 +238,7 @@ static int opMOV_AX_a16(uint32_t fetchdat)
|
||||
static int opMOV_AX_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
uint16_t temp = readmemw(ea_seg->base, addr); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
AX = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
@@ -249,7 +246,7 @@ static int opMOV_AX_a32(uint32_t fetchdat)
|
||||
static int opMOV_EAX_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
uint32_t temp = readmeml(ea_seg->base, addr); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
EAX = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
@@ -257,7 +254,7 @@ static int opMOV_EAX_a16(uint32_t fetchdat)
|
||||
static int opMOV_EAX_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
uint32_t temp = readmeml(ea_seg->base, addr); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
EAX = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
return 0;
|
||||
@@ -266,42 +263,42 @@ static int opMOV_EAX_a32(uint32_t fetchdat)
|
||||
static int opMOV_a16_AL(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
writememb(ea_seg->base, addr, AL);
|
||||
writememb(cpu_state.ea_seg->base, addr, AL);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
}
|
||||
static int opMOV_a32_AL(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong();
|
||||
writememb(ea_seg->base, addr, AL);
|
||||
writememb(cpu_state.ea_seg->base, addr, AL);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
}
|
||||
static int opMOV_a16_AX(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
writememw(ea_seg->base, addr, AX);
|
||||
writememw(cpu_state.ea_seg->base, addr, AX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
}
|
||||
static int opMOV_a32_AX(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong(); if (abrt) return 1;
|
||||
writememw(ea_seg->base, addr, AX);
|
||||
writememw(cpu_state.ea_seg->base, addr, AX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
}
|
||||
static int opMOV_a16_EAX(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t addr = getwordf();
|
||||
writememl(ea_seg->base, addr, EAX);
|
||||
writememl(cpu_state.ea_seg->base, addr, EAX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
}
|
||||
static int opMOV_a32_EAX(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = getlong(); if (abrt) return 1;
|
||||
writememl(ea_seg->base, addr, EAX);
|
||||
writememl(cpu_state.ea_seg->base, addr, EAX);
|
||||
CLOCK_CYCLES((is486) ? 1 : 2);
|
||||
return abrt;
|
||||
}
|
||||
@@ -311,7 +308,7 @@ static int opLEA_w_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
cpu_state.regs[cpu_reg].w = eaaddr;
|
||||
cpu_state.regs[cpu_reg].w = cpu_state.eaaddr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
@@ -319,7 +316,7 @@ static int opLEA_w_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
cpu_state.regs[cpu_reg].w = eaaddr;
|
||||
cpu_state.regs[cpu_reg].w = cpu_state.eaaddr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
@@ -328,7 +325,7 @@ static int opLEA_l_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
cpu_state.regs[cpu_reg].l = eaaddr & 0xffff;
|
||||
cpu_state.regs[cpu_reg].l = cpu_state.eaaddr & 0xffff;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
@@ -336,7 +333,7 @@ static int opLEA_l_a32(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
cpu_state.regs[cpu_reg].l = eaaddr;
|
||||
cpu_state.regs[cpu_reg].l = cpu_state.eaaddr;
|
||||
CLOCK_CYCLES(timing_rr);
|
||||
return 0;
|
||||
}
|
||||
@@ -346,7 +343,7 @@ static int opLEA_l_a32(uint32_t fetchdat)
|
||||
static int opXLAT_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = (BX + AL)&0xFFFF;
|
||||
uint8_t temp = readmemb(ea_seg->base, addr); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES(5);
|
||||
return 0;
|
||||
@@ -354,7 +351,7 @@ static int opXLAT_a16(uint32_t fetchdat)
|
||||
static int opXLAT_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t addr = EBX + AL;
|
||||
uint8_t temp = readmemb(ea_seg->base, addr); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, addr); if (abrt) return 1;
|
||||
AL = temp;
|
||||
CLOCK_CYCLES(5);
|
||||
return 0;
|
||||
@@ -370,7 +367,7 @@ static int opMOV_b_r_a16(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
@@ -386,7 +383,7 @@ static int opMOV_b_r_a32(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
seteab(getr8(cpu_reg));
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
@@ -402,7 +399,7 @@ static int opMOV_w_r_a16(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr+1);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
@@ -418,7 +415,7 @@ static int opMOV_w_r_a32(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr+1);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
seteaw(cpu_state.regs[cpu_reg].w);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
@@ -434,7 +431,7 @@ static int opMOV_l_r_a16(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr+3);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
@@ -450,7 +447,7 @@ static int opMOV_l_r_a32(uint32_t fetchdat)
|
||||
}
|
||||
else
|
||||
{
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr+3);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
seteal(cpu_state.regs[cpu_reg].l);
|
||||
CLOCK_CYCLES(is486 ? 1 : 2);
|
||||
}
|
||||
@@ -468,7 +465,7 @@ static int opMOV_r_b_a16(uint32_t fetchdat)
|
||||
else
|
||||
{
|
||||
uint8_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
@@ -486,7 +483,7 @@ static int opMOV_r_b_a32(uint32_t fetchdat)
|
||||
else
|
||||
{
|
||||
uint8_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
||||
temp = geteab(); if (abrt) return 1;
|
||||
setr8(cpu_reg, temp);
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
@@ -504,7 +501,7 @@ static int opMOV_r_w_a16(uint32_t fetchdat)
|
||||
else
|
||||
{
|
||||
uint16_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+1);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
@@ -522,7 +519,7 @@ static int opMOV_r_w_a32(uint32_t fetchdat)
|
||||
else
|
||||
{
|
||||
uint16_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+1);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = temp;
|
||||
CLOCK_CYCLES((is486) ? 1 : 4);
|
||||
@@ -540,7 +537,7 @@ static int opMOV_r_l_a16(uint32_t fetchdat)
|
||||
else
|
||||
{
|
||||
uint32_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+3);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
@@ -558,7 +555,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
||||
else
|
||||
{
|
||||
uint32_t temp;
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+3);
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3);
|
||||
temp = geteal(); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = temp;
|
||||
CLOCK_CYCLES(is486 ? 1 : 4);
|
||||
@@ -577,7 +574,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
||||
else \
|
||||
{ \
|
||||
uint16_t temp; \
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+1); \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1); \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = temp; \
|
||||
} \
|
||||
@@ -595,7 +592,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
||||
else \
|
||||
{ \
|
||||
uint16_t temp; \
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+1); \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+1); \
|
||||
temp = geteaw(); if (abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = temp; \
|
||||
} \
|
||||
@@ -613,7 +610,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
||||
else \
|
||||
{ \
|
||||
uint32_t temp; \
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+3); \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3); \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = temp; \
|
||||
} \
|
||||
@@ -631,7 +628,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat)
|
||||
else \
|
||||
{ \
|
||||
uint32_t temp; \
|
||||
CHECK_READ(ea_seg, eaaddr, eaaddr+3); \
|
||||
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr+3); \
|
||||
temp = geteal(); if (abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = temp; \
|
||||
} \
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opMOV_r_CRx_a16(uint32_t fetchdat)
|
||||
{
|
||||
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
|
||||
@@ -31,7 +28,7 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat)
|
||||
}
|
||||
default:
|
||||
pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
}
|
||||
@@ -68,7 +65,7 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat)
|
||||
}
|
||||
default:
|
||||
pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
}
|
||||
@@ -139,7 +136,7 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
|
||||
|
||||
default:
|
||||
pclog("Bad load CR%i\n", cpu_reg);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
}
|
||||
@@ -182,7 +179,7 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat)
|
||||
|
||||
default:
|
||||
pclog("Bad load CR%i\n", cpu_reg);
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opMOV_w_seg_a16(uint32_t fetchdat)
|
||||
{
|
||||
fetch_ea_16(fetchdat);
|
||||
@@ -150,14 +147,14 @@ static int opMOV_seg_w_a16(uint32_t fetchdat)
|
||||
case 0x10: /*SS*/
|
||||
loadseg(new_seg, &_ss);
|
||||
if (abrt) return 1;
|
||||
oldpc = cpu_state.pc;
|
||||
op32 = use32;
|
||||
ssegs = 0;
|
||||
ea_seg = &_ds;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
cpu_state.op32 = use32;
|
||||
cpu_state.ssegs = 0;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
cpu_state.pc++;
|
||||
if (abrt) return 1;
|
||||
x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
|
||||
x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return 1;
|
||||
case 0x20: /*FS*/
|
||||
loadseg(new_seg, &_fs);
|
||||
@@ -189,14 +186,14 @@ static int opMOV_seg_w_a32(uint32_t fetchdat)
|
||||
case 0x10: /*SS*/
|
||||
loadseg(new_seg, &_ss);
|
||||
if (abrt) return 1;
|
||||
oldpc = cpu_state.pc;
|
||||
op32 = use32;
|
||||
ssegs = 0;
|
||||
ea_seg = &_ds;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
cpu_state.op32 = use32;
|
||||
cpu_state.ssegs = 0;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
cpu_state.pc++;
|
||||
if (abrt) return 1;
|
||||
x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
|
||||
x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
return 1;
|
||||
case 0x20: /*FS*/
|
||||
loadseg(new_seg, &_fs);
|
||||
@@ -217,8 +214,8 @@ static int opLDS_w_a16(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
@@ -231,8 +228,8 @@ static int opLDS_w_a32(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
@@ -246,8 +243,8 @@ static int opLDS_l_a16(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
@@ -261,8 +258,8 @@ static int opLDS_l_a32(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ds); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
@@ -276,8 +273,8 @@ static int opLSS_w_a16(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
@@ -290,8 +287,8 @@ static int opLSS_w_a32(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmemw(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
|
||||
addr = readmemw(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].w = addr;
|
||||
|
||||
@@ -305,8 +302,8 @@ static int opLSS_l_a16(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_16(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
@@ -320,8 +317,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
||||
|
||||
fetch_ea_32(fetchdat);
|
||||
ILLEGAL_ON(cpu_mod == 3);
|
||||
addr = readmeml(easeg, eaaddr);
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
|
||||
addr = readmeml(easeg, cpu_state.eaaddr);
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1;
|
||||
loadseg(seg, &_ss); if (abrt) return 1;
|
||||
cpu_state.regs[cpu_reg].l = addr;
|
||||
|
||||
@@ -336,8 +333,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmemw(easeg, eaaddr); \
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
|
||||
addr = readmemw(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = addr; \
|
||||
\
|
||||
@@ -351,8 +348,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmemw(easeg, eaaddr); \
|
||||
seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
|
||||
addr = readmemw(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].w = addr; \
|
||||
\
|
||||
@@ -367,8 +364,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
||||
\
|
||||
fetch_ea_16(fetchdat); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmeml(easeg, eaaddr); \
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
|
||||
addr = readmeml(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = addr; \
|
||||
\
|
||||
@@ -383,8 +380,8 @@ static int opLSS_l_a32(uint32_t fetchdat)
|
||||
\
|
||||
fetch_ea_32(fetchdat); \
|
||||
ILLEGAL_ON(cpu_mod == 3); \
|
||||
addr = readmeml(easeg, eaaddr); \
|
||||
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
|
||||
addr = readmeml(easeg, cpu_state.eaaddr); \
|
||||
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (abrt) return 1; \
|
||||
loadseg(seg, &sel); if (abrt) return 1; \
|
||||
cpu_state.regs[cpu_reg].l = addr; \
|
||||
\
|
||||
|
||||
@@ -1,11 +1,8 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opRDTSC(uint32_t fetchdat)
|
||||
{
|
||||
if (!cpu_hasrdtsc)
|
||||
{
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
x86illegal();
|
||||
return 1;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opARPL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp_seg;
|
||||
@@ -294,7 +291,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
|
||||
base = gdt.base; //is32 ? gdt.base : (gdt.base & 0xffffff);
|
||||
if (is286)
|
||||
base |= 0xff000000;
|
||||
writememl(easeg, eaaddr + 2, base);
|
||||
writememl(easeg, cpu_state.eaaddr + 2, base);
|
||||
CLOCK_CYCLES(7);
|
||||
break;
|
||||
case 0x08: /*SIDT*/
|
||||
@@ -302,7 +299,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
|
||||
base = idt.base;
|
||||
if (is286)
|
||||
base |= 0xff000000;
|
||||
writememl(easeg, eaaddr + 2, base);
|
||||
writememl(easeg, cpu_state.eaaddr + 2, base);
|
||||
CLOCK_CYCLES(7);
|
||||
break;
|
||||
case 0x10: /*LGDT*/
|
||||
@@ -314,7 +311,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
|
||||
}
|
||||
// pclog("LGDT %08X:%08X\n", easeg, eaaddr);
|
||||
limit = geteaw();
|
||||
base = readmeml(0, easeg + eaaddr + 2); if (abrt) return 1;
|
||||
base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
// pclog(" %08X %04X\n", base, limit);
|
||||
gdt.limit = limit;
|
||||
gdt.base = base;
|
||||
@@ -330,7 +327,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
|
||||
}
|
||||
// pclog("LIDT %08X:%08X\n", easeg, eaaddr);
|
||||
limit = geteaw();
|
||||
base = readmeml(0, easeg + eaaddr + 2); if (abrt) return 1;
|
||||
base = readmeml(0, easeg + cpu_state.eaaddr + 2); if (abrt) return 1;
|
||||
// pclog(" %08X %04X\n", base, limit);
|
||||
idt.limit = limit;
|
||||
idt.base = base;
|
||||
@@ -364,7 +361,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286)
|
||||
x86gpf(NULL, 0);
|
||||
break;
|
||||
}
|
||||
mmu_invalidate(ds + eaaddr);
|
||||
mmu_invalidate(ds + cpu_state.eaaddr);
|
||||
CLOCK_CYCLES(12);
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#define op_seg(name, seg) \
|
||||
static int op ## name ## _w_a16(uint32_t fetchdat) \
|
||||
{ \
|
||||
@@ -8,8 +5,8 @@ static int op ## name ## _w_a16(uint32_t fetchdat) \
|
||||
if (abrt) return 1; \
|
||||
cpu_state.pc++; \
|
||||
\
|
||||
ea_seg = &seg; \
|
||||
ssegs = 1; \
|
||||
cpu_state.ea_seg = &seg; \
|
||||
cpu_state.ssegs = 1; \
|
||||
CLOCK_CYCLES(4); \
|
||||
\
|
||||
return x86_opcodes[fetchdat & 0xff](fetchdat >> 8); \
|
||||
@@ -21,8 +18,8 @@ static int op ## name ## _l_a16(uint32_t fetchdat) \
|
||||
if (abrt) return 1; \
|
||||
cpu_state.pc++; \
|
||||
\
|
||||
ea_seg = &seg; \
|
||||
ssegs = 1; \
|
||||
cpu_state.ea_seg = &seg; \
|
||||
cpu_state.ssegs = 1; \
|
||||
CLOCK_CYCLES(4); \
|
||||
\
|
||||
return x86_opcodes[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
|
||||
@@ -34,8 +31,8 @@ static int op ## name ## _w_a32(uint32_t fetchdat) \
|
||||
if (abrt) return 1; \
|
||||
cpu_state.pc++; \
|
||||
\
|
||||
ea_seg = &seg; \
|
||||
ssegs = 1; \
|
||||
cpu_state.ea_seg = &seg; \
|
||||
cpu_state.ssegs = 1; \
|
||||
CLOCK_CYCLES(4); \
|
||||
\
|
||||
return x86_opcodes[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
|
||||
@@ -47,8 +44,8 @@ static int op ## name ## _l_a32(uint32_t fetchdat) \
|
||||
if (abrt) return 1; \
|
||||
cpu_state.pc++; \
|
||||
\
|
||||
ea_seg = &seg; \
|
||||
ssegs = 1; \
|
||||
cpu_state.ea_seg = &seg; \
|
||||
cpu_state.ssegs = 1; \
|
||||
CLOCK_CYCLES(4); \
|
||||
\
|
||||
return x86_opcodes[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
|
||||
@@ -67,9 +64,9 @@ static int op_66(uint32_t fetchdat) /*Data size select*/
|
||||
if (abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
op32 = ((use32 & 0x100) ^ 0x100) | (op32 & 0x200);
|
||||
cpu_state.op32 = ((use32 & 0x100) ^ 0x100) | (cpu_state.op32 & 0x200);
|
||||
CLOCK_CYCLES(2);
|
||||
return x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
static int op_67(uint32_t fetchdat) /*Address size select*/
|
||||
{
|
||||
@@ -77,7 +74,7 @@ static int op_67(uint32_t fetchdat) /*Address size select*/
|
||||
if (abrt) return 1;
|
||||
cpu_state.pc++;
|
||||
|
||||
op32 = ((use32 & 0x200) ^ 0x200) | (op32 & 0x100);
|
||||
cpu_state.op32 = ((use32 & 0x200) ^ 0x200) | (cpu_state.op32 & 0x100);
|
||||
CLOCK_CYCLES(2);
|
||||
return x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
|
||||
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
}
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
#define PUSH_W_OP(reg) \
|
||||
static int opPUSH_ ## reg (uint32_t fetchdat) \
|
||||
{ \
|
||||
@@ -447,14 +444,14 @@ static int opPOP_SS_w(uint32_t fetchdat)
|
||||
loadseg(temp_seg, &_ss); if (abrt) { ESP = temp_esp; return 1; }
|
||||
CLOCK_CYCLES(is486 ? 3 : 7);
|
||||
|
||||
oldpc = cpu_state.pc;
|
||||
op32 = use32;
|
||||
ssegs = 0;
|
||||
ea_seg = &_ds;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
cpu_state.op32 = use32;
|
||||
cpu_state.ssegs = 0;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
cpu_state.pc++;
|
||||
if (abrt) return 1;
|
||||
x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
|
||||
x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
|
||||
return 1;
|
||||
}
|
||||
@@ -466,14 +463,14 @@ static int opPOP_SS_l(uint32_t fetchdat)
|
||||
loadseg(temp_seg & 0xffff, &_ss); if (abrt) { ESP = temp_esp; return 1; }
|
||||
CLOCK_CYCLES(is486 ? 3 : 7);
|
||||
|
||||
oldpc = cpu_state.pc;
|
||||
op32 = use32;
|
||||
ssegs = 0;
|
||||
ea_seg = &_ds;
|
||||
cpu_state.oldpc = cpu_state.pc;
|
||||
cpu_state.op32 = use32;
|
||||
cpu_state.ssegs = 0;
|
||||
cpu_state.ea_seg = &_ds;
|
||||
fetchdat = fastreadl(cs + cpu_state.pc);
|
||||
cpu_state.pc++;
|
||||
if (abrt) return 1;
|
||||
x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
|
||||
x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
@@ -1,9 +1,6 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opMOVSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(ea_seg->base, SI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
writememb(es, DI, temp); if (abrt) return 1;
|
||||
if (flags & D_FLAG) { DI--; SI--; }
|
||||
else { DI++; SI++; }
|
||||
@@ -12,7 +9,7 @@ static int opMOVSB_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opMOVSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
writememb(es, EDI, temp); if (abrt) return 1;
|
||||
if (flags & D_FLAG) { EDI--; ESI--; }
|
||||
else { EDI++; ESI++; }
|
||||
@@ -22,7 +19,7 @@ static int opMOVSB_a32(uint32_t fetchdat)
|
||||
|
||||
static int opMOVSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(ea_seg->base, SI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
writememw(es, DI, temp); if (abrt) return 1;
|
||||
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
|
||||
else { DI += 2; SI += 2; }
|
||||
@@ -31,7 +28,7 @@ static int opMOVSW_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opMOVSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
writememw(es, EDI, temp); if (abrt) return 1;
|
||||
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
|
||||
else { EDI += 2; ESI += 2; }
|
||||
@@ -41,7 +38,7 @@ static int opMOVSW_a32(uint32_t fetchdat)
|
||||
|
||||
static int opMOVSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(ea_seg->base, SI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
writememl(es, DI, temp); if (abrt) return 1;
|
||||
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
|
||||
else { DI += 4; SI += 4; }
|
||||
@@ -50,7 +47,7 @@ static int opMOVSL_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opMOVSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
writememl(es, EDI, temp); if (abrt) return 1;
|
||||
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
|
||||
else { EDI += 4; ESI += 4; }
|
||||
@@ -61,7 +58,7 @@ static int opMOVSL_a32(uint32_t fetchdat)
|
||||
|
||||
static int opCMPSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t src = readmemb(ea_seg->base, SI);
|
||||
uint8_t src = readmemb(cpu_state.ea_seg->base, SI);
|
||||
uint8_t dst = readmemb(es, DI); if (abrt) return 1;
|
||||
setsub8(src, dst);
|
||||
if (flags & D_FLAG) { DI--; SI--; }
|
||||
@@ -71,7 +68,7 @@ static int opCMPSB_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opCMPSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t src = readmemb(ea_seg->base, ESI);
|
||||
uint8_t src = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
uint8_t dst = readmemb(es, EDI); if (abrt) return 1;
|
||||
setsub8(src, dst);
|
||||
if (flags & D_FLAG) { EDI--; ESI--; }
|
||||
@@ -82,7 +79,7 @@ static int opCMPSB_a32(uint32_t fetchdat)
|
||||
|
||||
static int opCMPSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src = readmemw(ea_seg->base, SI);
|
||||
uint16_t src = readmemw(cpu_state.ea_seg->base, SI);
|
||||
uint16_t dst = readmemw(es, DI); if (abrt) return 1;
|
||||
setsub16(src, dst);
|
||||
if (flags & D_FLAG) { DI -= 2; SI -= 2; }
|
||||
@@ -92,7 +89,7 @@ static int opCMPSW_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opCMPSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t src = readmemw(ea_seg->base, ESI);
|
||||
uint16_t src = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
uint16_t dst = readmemw(es, EDI); if (abrt) return 1;
|
||||
setsub16(src, dst);
|
||||
if (flags & D_FLAG) { EDI -= 2; ESI -= 2; }
|
||||
@@ -103,7 +100,7 @@ static int opCMPSW_a32(uint32_t fetchdat)
|
||||
|
||||
static int opCMPSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src = readmeml(ea_seg->base, SI);
|
||||
uint32_t src = readmeml(cpu_state.ea_seg->base, SI);
|
||||
uint32_t dst = readmeml(es, DI); if (abrt) return 1;
|
||||
setsub32(src, dst);
|
||||
if (flags & D_FLAG) { DI -= 4; SI -= 4; }
|
||||
@@ -113,7 +110,7 @@ static int opCMPSL_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opCMPSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t src = readmeml(ea_seg->base, ESI);
|
||||
uint32_t src = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
uint32_t dst = readmeml(es, EDI); if (abrt) return 1;
|
||||
setsub32(src, dst);
|
||||
if (flags & D_FLAG) { EDI -= 4; ESI -= 4; }
|
||||
@@ -176,7 +173,7 @@ static int opSTOSL_a32(uint32_t fetchdat)
|
||||
|
||||
static int opLODSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(ea_seg->base, SI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
AL = temp;
|
||||
if (flags & D_FLAG) SI--;
|
||||
else SI++;
|
||||
@@ -185,7 +182,7 @@ static int opLODSB_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opLODSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
AL = temp;
|
||||
if (flags & D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
@@ -195,7 +192,7 @@ static int opLODSB_a32(uint32_t fetchdat)
|
||||
|
||||
static int opLODSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(ea_seg->base, SI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
AX = temp;
|
||||
if (flags & D_FLAG) SI -= 2;
|
||||
else SI += 2;
|
||||
@@ -204,7 +201,7 @@ static int opLODSW_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opLODSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
AX = temp;
|
||||
if (flags & D_FLAG) ESI -= 2;
|
||||
else ESI += 2;
|
||||
@@ -214,7 +211,7 @@ static int opLODSW_a32(uint32_t fetchdat)
|
||||
|
||||
static int opLODSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(ea_seg->base, SI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
EAX = temp;
|
||||
if (flags & D_FLAG) SI -= 4;
|
||||
else SI += 4;
|
||||
@@ -223,7 +220,7 @@ static int opLODSL_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opLODSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
EAX = temp;
|
||||
if (flags & D_FLAG) ESI -= 4;
|
||||
else ESI += 4;
|
||||
@@ -368,7 +365,7 @@ static int opINSL_a32(uint32_t fetchdat)
|
||||
|
||||
static int opOUTSB_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(ea_seg->base, SI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
if (flags & D_FLAG) SI--;
|
||||
else SI++;
|
||||
@@ -378,7 +375,7 @@ static int opOUTSB_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opOUTSB_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint8_t temp = readmemb(ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint8_t temp = readmemb(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
if (flags & D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
@@ -389,7 +386,7 @@ static int opOUTSB_a32(uint32_t fetchdat)
|
||||
|
||||
static int opOUTSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(ea_seg->base, SI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
if (flags & D_FLAG) SI -= 2;
|
||||
@@ -400,7 +397,7 @@ static int opOUTSW_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opOUTSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint16_t temp = readmemw(ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint16_t temp = readmemw(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
if (flags & D_FLAG) ESI -= 2;
|
||||
@@ -412,7 +409,7 @@ static int opOUTSW_a32(uint32_t fetchdat)
|
||||
|
||||
static int opOUTSL_a16(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(ea_seg->base, SI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, SI); if (abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
check_io_perm(DX + 2);
|
||||
@@ -425,7 +422,7 @@ static int opOUTSL_a16(uint32_t fetchdat)
|
||||
}
|
||||
static int opOUTSL_a32(uint32_t fetchdat)
|
||||
{
|
||||
uint32_t temp = readmeml(ea_seg->base, ESI); if (abrt) return 1;
|
||||
uint32_t temp = readmeml(cpu_state.ea_seg->base, ESI); if (abrt) return 1;
|
||||
check_io_perm(DX);
|
||||
check_io_perm(DX + 1);
|
||||
check_io_perm(DX + 2);
|
||||
|
||||
@@ -75,7 +75,7 @@ void x86_doabrt(int x86_abrt)
|
||||
{
|
||||
// ingpf = 1;
|
||||
CS = oldcs;
|
||||
cpu_state.pc = oldpc;
|
||||
cpu_state.pc = cpu_state.oldpc;
|
||||
_cs.access = (oldcpl << 5) | 0x80;
|
||||
// pclog("x86_doabrt - %02X %08X %04X:%08X %i\n", x86_abrt, abrt_error, CS, pc, ins);
|
||||
|
||||
@@ -637,7 +637,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
|
||||
cgate32=(type&0x800);
|
||||
cgate16=!cgate32;
|
||||
oldcs=CS;
|
||||
oldpc=cpu_state.pc;
|
||||
cpu_state.oldpc=cpu_state.pc;
|
||||
count=segdat[2]&31;
|
||||
#if 0
|
||||
if ((DPL < CPL) || (DPL < (seg&3)))
|
||||
|
||||
@@ -1,9 +1,5 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
uint32_t x87_pc_off,x87_op_off;
|
||||
uint16_t x87_pc_seg,x87_op_seg;
|
||||
extern uint32_t op32;
|
||||
extern int TOP;
|
||||
extern uint16_t npxs, npxc;
|
||||
extern uint8_t tag[8];
|
||||
|
||||
@@ -111,9 +111,9 @@ static inline double x87_ld80()
|
||||
int64_t mant64;
|
||||
int64_t sign;
|
||||
|
||||
test.eind.ll = readmeml(easeg,eaaddr);
|
||||
test.eind.ll |= (uint64_t)readmeml(easeg,eaaddr+4)<<32;
|
||||
test.begin = readmemw(easeg,eaaddr+8);
|
||||
test.eind.ll = readmeml(easeg,cpu_state.eaaddr);
|
||||
test.eind.ll |= (uint64_t)readmeml(easeg,cpu_state.eaaddr+4)<<32;
|
||||
test.begin = readmemw(easeg,cpu_state.eaaddr+8);
|
||||
|
||||
exp64 = (((test.begin&0x7fff) - BIAS80));
|
||||
blah = ((exp64 >0)?exp64:-exp64)&0x3ff;
|
||||
@@ -173,9 +173,9 @@ static inline void x87_st80(double d)
|
||||
test.begin = (((int16_t)sign80)<<15)| (int16_t)exp80final;
|
||||
test.eind.ll = mant80final;
|
||||
|
||||
writememl(easeg,eaaddr,test.eind.ll);
|
||||
writememl(easeg,eaaddr+4,test.eind.ll>>32);
|
||||
writememw(easeg,eaaddr+8,test.begin);
|
||||
writememl(easeg,cpu_state.eaaddr,test.eind.ll);
|
||||
writememl(easeg,cpu_state.eaaddr+4,test.eind.ll>>32);
|
||||
writememw(easeg,cpu_state.eaaddr+8,test.begin);
|
||||
}
|
||||
|
||||
static inline void x87_st_fsave(int reg)
|
||||
@@ -184,9 +184,9 @@ static inline void x87_st_fsave(int reg)
|
||||
|
||||
if (tag[reg] & TAG_UINT64)
|
||||
{
|
||||
writememl(easeg, eaaddr, ST_i64[reg] & 0xffffffff);
|
||||
writememl(easeg, eaaddr + 4, ST_i64[reg] >> 32);
|
||||
writememw(easeg, eaaddr + 8, 0x5555);
|
||||
writememl(easeg, cpu_state.eaaddr, ST_i64[reg] & 0xffffffff);
|
||||
writememl(easeg, cpu_state.eaaddr + 4, ST_i64[reg] >> 32);
|
||||
writememw(easeg, cpu_state.eaaddr + 8, 0x5555);
|
||||
}
|
||||
else
|
||||
x87_st80(ST[reg]);
|
||||
@@ -198,13 +198,13 @@ static inline void x87_ld_frstor(int reg)
|
||||
|
||||
reg = (TOP + reg) & 7;
|
||||
|
||||
temp = readmemw(easeg, eaaddr + 8);
|
||||
temp = readmemw(easeg, cpu_state.eaaddr + 8);
|
||||
|
||||
if (temp == 0x5555 && tag[reg] == 2)
|
||||
{
|
||||
tag[reg] = TAG_UINT64;
|
||||
ST_i64[reg] = readmeml(easeg, eaaddr);
|
||||
ST_i64[reg] |= ((uint64_t)readmeml(easeg, eaaddr + 4) << 32);
|
||||
ST_i64[reg] = readmeml(easeg, cpu_state.eaaddr);
|
||||
ST_i64[reg] |= ((uint64_t)readmeml(easeg, cpu_state.eaaddr + 4) << 32);
|
||||
ST[reg] = (double)ST_i64[reg];
|
||||
}
|
||||
else
|
||||
@@ -213,16 +213,16 @@ static inline void x87_ld_frstor(int reg)
|
||||
|
||||
static inline void x87_ldmmx(MMX_REG *r)
|
||||
{
|
||||
r->l[0] = readmeml(easeg, eaaddr);
|
||||
r->l[1] = readmeml(easeg, eaaddr + 4);
|
||||
r->w[4] = readmemw(easeg, eaaddr + 8);
|
||||
r->l[0] = readmeml(easeg, cpu_state.eaaddr);
|
||||
r->l[1] = readmeml(easeg, cpu_state.eaaddr + 4);
|
||||
r->w[4] = readmemw(easeg, cpu_state.eaaddr + 8);
|
||||
}
|
||||
|
||||
static inline void x87_stmmx(MMX_REG r)
|
||||
{
|
||||
writememl(easeg, eaaddr, r.l[0]);
|
||||
writememl(easeg, eaaddr + 4, r.l[1]);
|
||||
writememw(easeg, eaaddr + 8, 0xffff);
|
||||
writememl(easeg, cpu_state.eaaddr, r.l[0]);
|
||||
writememl(easeg, cpu_state.eaaddr + 4, r.l[1]);
|
||||
writememw(easeg, cpu_state.eaaddr + 8, 0xffff);
|
||||
}
|
||||
|
||||
static inline uint16_t x87_compare(double a, double b)
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker, leilei
|
||||
see COPYING for more details
|
||||
*/
|
||||
#define opFPU(name, optype, a_size, load_var, get, use_var) \
|
||||
static int opFADD ## name ## _a ## a_size(uint32_t fetchdat) \
|
||||
{ \
|
||||
@@ -186,7 +183,7 @@ static int opFUCOMPP(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
cpu_state.pc++;
|
||||
if (fplog) pclog("FUCOMPP\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FUCOMPP\n", easeg, cpu_state.eaaddr);
|
||||
npxs &= ~(C0|C2|C3);
|
||||
npxs |= x87_ucompare(ST(0), ST(1));
|
||||
x87_pop();
|
||||
|
||||
@@ -1,12 +1,9 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opFILDiw_a16(uint32_t fetchdat)
|
||||
{
|
||||
int16_t temp;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FILDw %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FILDw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", (double)temp);
|
||||
x87_push((double)temp);
|
||||
@@ -18,7 +15,7 @@ static int opFILDiw_a32(uint32_t fetchdat)
|
||||
int16_t temp;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FILDw %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FILDw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp = geteaw(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", (double)temp);
|
||||
x87_push((double)temp);
|
||||
@@ -31,7 +28,7 @@ static int opFISTiw_a16(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
fatal("FISTw overflow %i\n", temp64);*/
|
||||
@@ -44,7 +41,7 @@ static int opFISTiw_a32(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
fatal("FISTw overflow %i\n", temp64);*/
|
||||
@@ -58,7 +55,7 @@ static int opFISTPiw_a16(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
fatal("FISTw overflow %i\n", temp64);*/
|
||||
@@ -72,7 +69,7 @@ static int opFISTPiw_a32(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTw %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 32767 || temp64 < -32768)
|
||||
fatal("FISTw overflow %i\n", temp64);*/
|
||||
@@ -87,9 +84,9 @@ static int opFILDiq_a16(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FILDl %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FILDl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = geteaq(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,eaaddr), readmeml(easeg,eaaddr+4));
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,cpu_state.eaaddr), readmeml(easeg,cpu_state.eaaddr+4));
|
||||
x87_push((double)temp64);
|
||||
ST_i64[TOP] = temp64;
|
||||
tag[TOP] |= TAG_UINT64;
|
||||
@@ -102,9 +99,9 @@ static int opFILDiq_a32(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FILDl %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FILDl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = geteaq(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,eaaddr), readmeml(easeg,eaaddr+4));
|
||||
if (fplog) pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg,cpu_state.eaaddr), readmeml(easeg,cpu_state.eaaddr+4));
|
||||
x87_push((double)temp64);
|
||||
ST_i64[TOP] = temp64;
|
||||
tag[TOP] |= TAG_UINT64;
|
||||
@@ -119,7 +116,7 @@ static int FBSTP_a16(uint32_t fetchdat)
|
||||
int c;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FBSTP %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FBSTP %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempd = ST(0);
|
||||
if (tempd < 0.0)
|
||||
tempd = -tempd;
|
||||
@@ -131,11 +128,11 @@ static int FBSTP_a16(uint32_t fetchdat)
|
||||
tempc |= ((uint8_t)floor(fmod(tempd, 10.0))) << 4;
|
||||
tempd -= floor(fmod(tempd, 10.0));
|
||||
tempd /= 10.0;
|
||||
writememb(easeg, eaaddr + c, tempc);
|
||||
writememb(easeg, cpu_state.eaaddr + c, tempc);
|
||||
}
|
||||
tempc = (uint8_t)floor(fmod(tempd, 10.0));
|
||||
if (ST(0) < 0.0) tempc |= 0x80;
|
||||
writememb(easeg, eaaddr + 9, tempc); if (abrt) return 1;
|
||||
writememb(easeg, cpu_state.eaaddr + 9, tempc); if (abrt) return 1;
|
||||
x87_pop();
|
||||
return 0;
|
||||
}
|
||||
@@ -145,7 +142,7 @@ static int FBSTP_a32(uint32_t fetchdat)
|
||||
int c;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FBSTP %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FBSTP %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempd = ST(0);
|
||||
if (tempd < 0.0)
|
||||
tempd = -tempd;
|
||||
@@ -157,11 +154,11 @@ static int FBSTP_a32(uint32_t fetchdat)
|
||||
tempc |= ((uint8_t)floor(fmod(tempd, 10.0))) << 4;
|
||||
tempd -= floor(fmod(tempd, 10.0));
|
||||
tempd /= 10.0;
|
||||
writememb(easeg, eaaddr + c, tempc);
|
||||
writememb(easeg, cpu_state.eaaddr + c, tempc);
|
||||
}
|
||||
tempc = (uint8_t)floor(fmod(tempd, 10.0));
|
||||
if (ST(0) < 0.0) tempc |= 0x80;
|
||||
writememb(easeg, eaaddr + 9, tempc); if (abrt) return 1;
|
||||
writememb(easeg, cpu_state.eaaddr + 9, tempc); if (abrt) return 1;
|
||||
x87_pop();
|
||||
return 0;
|
||||
}
|
||||
@@ -171,7 +168,7 @@ static int FISTPiq_a16(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
if (tag[TOP] & TAG_UINT64)
|
||||
temp64 = ST_i64[TOP];
|
||||
else
|
||||
@@ -186,7 +183,7 @@ static int FISTPiq_a32(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTPl %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
if (tag[TOP] & TAG_UINT64)
|
||||
temp64 = ST_i64[TOP];
|
||||
else
|
||||
@@ -202,7 +199,7 @@ static int opFILDil_a16(uint32_t fetchdat)
|
||||
int32_t templ;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FILDs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FILDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
templ = geteal(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %i\n", (double)templ, templ, templ);
|
||||
x87_push((double)templ);
|
||||
@@ -214,7 +211,7 @@ static int opFILDil_a32(uint32_t fetchdat)
|
||||
int32_t templ;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FILDs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FILDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
templ = geteal(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f %08X %i\n", (double)templ, templ, templ);
|
||||
x87_push((double)templ);
|
||||
@@ -227,7 +224,7 @@ static int opFISTil_a16(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
fatal("FISTl out of range! %i\n", temp64);*/
|
||||
@@ -240,7 +237,7 @@ static int opFISTil_a32(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
fatal("FISTl out of range! %i\n", temp64);*/
|
||||
@@ -254,7 +251,7 @@ static int opFISTPil_a16(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
fatal("FISTl out of range! %i\n", temp64);*/
|
||||
@@ -268,7 +265,7 @@ static int opFISTPil_a32(uint32_t fetchdat)
|
||||
int64_t temp64;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FISTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
temp64 = x87_fround(ST(0));
|
||||
/* if (temp64 > 2147483647 || temp64 < -2147483647)
|
||||
fatal("FISTl out of range! %i\n", temp64);*/
|
||||
@@ -283,7 +280,7 @@ static int opFLDe_a16(uint32_t fetchdat)
|
||||
double t;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FLDe %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FLDe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t=x87_ld80(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t);
|
||||
x87_push(t);
|
||||
@@ -295,7 +292,7 @@ static int opFLDe_a32(uint32_t fetchdat)
|
||||
double t;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FLDe %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FLDe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t=x87_ld80(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t);
|
||||
x87_push(t);
|
||||
@@ -307,7 +304,7 @@ static int opFSTPe_a16(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTPe %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTPe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
x87_st80(ST(0)); if (abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(6);
|
||||
@@ -317,7 +314,7 @@ static int opFSTPe_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTPe %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTPe %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
x87_st80(ST(0)); if (abrt) return 1;
|
||||
x87_pop();
|
||||
CLOCK_CYCLES(6);
|
||||
@@ -329,7 +326,7 @@ static int opFLDd_a16(uint32_t fetchdat)
|
||||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FLDd %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FLDd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.i = geteaq(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t.d);
|
||||
x87_push(t.d);
|
||||
@@ -341,7 +338,7 @@ static int opFLDd_a32(uint32_t fetchdat)
|
||||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FLDd %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FLDd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.i = geteaq(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", t.d);
|
||||
x87_push(t.d);
|
||||
@@ -354,7 +351,7 @@ static int opFSTd_a16(uint32_t fetchdat)
|
||||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
seteaq(t.i);
|
||||
CLOCK_CYCLES(8);
|
||||
@@ -365,7 +362,7 @@ static int opFSTd_a32(uint32_t fetchdat)
|
||||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
seteaq(t.i);
|
||||
CLOCK_CYCLES(8);
|
||||
@@ -377,8 +374,8 @@ static int opFSTPd_a16(uint32_t fetchdat)
|
||||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, eaaddr);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
seteaq(t.i); if (abrt) return 1;
|
||||
x87_pop();
|
||||
@@ -390,8 +387,8 @@ static int opFSTPd_a32(uint32_t fetchdat)
|
||||
x87_td t;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, eaaddr);
|
||||
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
|
||||
if (fplog) pclog("FSTd %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
t.d = ST(0);
|
||||
seteaq(t.i); if (abrt) return 1;
|
||||
x87_pop();
|
||||
@@ -404,7 +401,7 @@ static int opFLDs_a16(uint32_t fetchdat)
|
||||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FLDs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FLDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.i = geteal(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", ts.s);
|
||||
x87_push((double)ts.s);
|
||||
@@ -416,7 +413,7 @@ static int opFLDs_a32(uint32_t fetchdat)
|
||||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FLDs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FLDs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.i = geteal(); if (abrt) return 1;
|
||||
if (fplog) pclog(" %f\n", ts.s);
|
||||
x87_push((double)ts.s);
|
||||
@@ -429,7 +426,7 @@ static int opFSTs_a16(uint32_t fetchdat)
|
||||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i);
|
||||
CLOCK_CYCLES(7);
|
||||
@@ -440,7 +437,7 @@ static int opFSTs_a32(uint32_t fetchdat)
|
||||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i);
|
||||
CLOCK_CYCLES(7);
|
||||
@@ -452,7 +449,7 @@ static int opFSTPs_a16(uint32_t fetchdat)
|
||||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i); if (abrt) return 1;
|
||||
x87_pop();
|
||||
@@ -464,7 +461,7 @@ static int opFSTPs_a32(uint32_t fetchdat)
|
||||
x87_ts ts;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTs %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
ts.s = (float)ST(0);
|
||||
seteal(ts.i); if (abrt) return 1;
|
||||
x87_pop();
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
/* Copyright holders: Sarah Walker
|
||||
see COPYING for more details
|
||||
*/
|
||||
static int opFSTSW_AX(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
@@ -94,32 +91,32 @@ static int opFSTP(uint32_t fetchdat)
|
||||
static int FSTOR()
|
||||
{
|
||||
FP_ENTER();
|
||||
switch ((cr0 & 1) | (op32 & 0x100))
|
||||
switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
|
||||
{
|
||||
case 0x000: /*16-bit real mode*/
|
||||
case 0x001: /*16-bit protected mode*/
|
||||
npxc = readmemw(easeg, eaaddr);
|
||||
npxs = readmemw(easeg, eaaddr+2);
|
||||
x87_settag(readmemw(easeg, eaaddr+4));
|
||||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
npxs = readmemw(easeg, cpu_state.eaaddr+2);
|
||||
x87_settag(readmemw(easeg, cpu_state.eaaddr+4));
|
||||
TOP = (npxs >> 11) & 7;
|
||||
eaaddr += 14;
|
||||
cpu_state.eaaddr += 14;
|
||||
break;
|
||||
case 0x100: /*32-bit real mode*/
|
||||
case 0x101: /*32-bit protected mode*/
|
||||
npxc = readmemw(easeg, eaaddr);
|
||||
npxs = readmemw(easeg, eaaddr+4);
|
||||
x87_settag(readmemw(easeg, eaaddr+8));
|
||||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
npxs = readmemw(easeg, cpu_state.eaaddr+4);
|
||||
x87_settag(readmemw(easeg, cpu_state.eaaddr+8));
|
||||
TOP = (npxs >> 11) & 7;
|
||||
eaaddr += 28;
|
||||
cpu_state.eaaddr += 28;
|
||||
break;
|
||||
}
|
||||
x87_ldmmx(&MM[0]); x87_ld_frstor(0); eaaddr += 10;
|
||||
x87_ldmmx(&MM[1]); x87_ld_frstor(1); eaaddr += 10;
|
||||
x87_ldmmx(&MM[2]); x87_ld_frstor(2); eaaddr += 10;
|
||||
x87_ldmmx(&MM[3]); x87_ld_frstor(3); eaaddr += 10;
|
||||
x87_ldmmx(&MM[4]); x87_ld_frstor(4); eaaddr += 10;
|
||||
x87_ldmmx(&MM[5]); x87_ld_frstor(5); eaaddr += 10;
|
||||
x87_ldmmx(&MM[6]); x87_ld_frstor(6); eaaddr += 10;
|
||||
x87_ldmmx(&MM[0]); x87_ld_frstor(0); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[1]); x87_ld_frstor(1); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[2]); x87_ld_frstor(2); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[3]); x87_ld_frstor(3); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[4]); x87_ld_frstor(4); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[5]); x87_ld_frstor(5); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[6]); x87_ld_frstor(6); cpu_state.eaaddr += 10;
|
||||
x87_ldmmx(&MM[7]); x87_ld_frstor(7);
|
||||
|
||||
ismmx = 0;
|
||||
@@ -131,7 +128,7 @@ static int FSTOR()
|
||||
ismmx = 1;
|
||||
|
||||
CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
|
||||
if (fplog) pclog("FRSTOR %08X:%08X %i %i %04X\n", easeg, eaaddr, ismmx, TOP, x87_gettag());
|
||||
if (fplog) pclog("FRSTOR %08X:%08X %i %i %04X\n", easeg, cpu_state.eaaddr, ismmx, TOP, x87_gettag());
|
||||
return abrt;
|
||||
}
|
||||
static int opFSTOR_a16(uint32_t fetchdat)
|
||||
@@ -152,133 +149,133 @@ static int opFSTOR_a32(uint32_t fetchdat)
|
||||
static int FSAVE()
|
||||
{
|
||||
FP_ENTER();
|
||||
if (fplog) pclog("FSAVE %08X:%08X %i\n", easeg, eaaddr, ismmx);
|
||||
if (fplog) pclog("FSAVE %08X:%08X %i\n", easeg, cpu_state.eaaddr, ismmx);
|
||||
npxs = (npxs & ~(7 << 11)) | (TOP << 11);
|
||||
|
||||
switch ((cr0&1)|(op32&0x100))
|
||||
switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
|
||||
{
|
||||
case 0x000: /*16-bit real mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+2,npxs);
|
||||
writememw(easeg,eaaddr+4,x87_gettag());
|
||||
writememw(easeg,eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,eaaddr+10,x87_op_off);
|
||||
eaaddr+=14;
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+2,npxs);
|
||||
writememw(easeg,cpu_state.eaaddr+4,x87_gettag());
|
||||
writememw(easeg,cpu_state.eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
|
||||
cpu_state.eaaddr+=14;
|
||||
if (ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); eaaddr+=10;
|
||||
x87_stmmx(MM[1]); eaaddr+=10;
|
||||
x87_stmmx(MM[2]); eaaddr+=10;
|
||||
x87_stmmx(MM[3]); eaaddr+=10;
|
||||
x87_stmmx(MM[4]); eaaddr+=10;
|
||||
x87_stmmx(MM[5]); eaaddr+=10;
|
||||
x87_stmmx(MM[6]); eaaddr+=10;
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[7]);
|
||||
}
|
||||
else
|
||||
{
|
||||
x87_st_fsave(0); eaaddr+=10;
|
||||
x87_st_fsave(1); eaaddr+=10;
|
||||
x87_st_fsave(2); eaaddr+=10;
|
||||
x87_st_fsave(3); eaaddr+=10;
|
||||
x87_st_fsave(4); eaaddr+=10;
|
||||
x87_st_fsave(5); eaaddr+=10;
|
||||
x87_st_fsave(6); eaaddr+=10;
|
||||
x87_st_fsave(0); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(1); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(2); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(3); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(4); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(5); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(6); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(7);
|
||||
}
|
||||
break;
|
||||
case 0x001: /*16-bit protected mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+2,npxs);
|
||||
writememw(easeg,eaaddr+4,x87_gettag());
|
||||
writememw(easeg,eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,eaaddr+8,x87_pc_seg);
|
||||
writememw(easeg,eaaddr+10,x87_op_off);
|
||||
writememw(easeg,eaaddr+12,x87_op_seg);
|
||||
eaaddr+=14;
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+2,npxs);
|
||||
writememw(easeg,cpu_state.eaaddr+4,x87_gettag());
|
||||
writememw(easeg,cpu_state.eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,cpu_state.eaaddr+8,x87_pc_seg);
|
||||
writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
|
||||
writememw(easeg,cpu_state.eaaddr+12,x87_op_seg);
|
||||
cpu_state.eaaddr+=14;
|
||||
if (ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); eaaddr+=10;
|
||||
x87_stmmx(MM[1]); eaaddr+=10;
|
||||
x87_stmmx(MM[2]); eaaddr+=10;
|
||||
x87_stmmx(MM[3]); eaaddr+=10;
|
||||
x87_stmmx(MM[4]); eaaddr+=10;
|
||||
x87_stmmx(MM[5]); eaaddr+=10;
|
||||
x87_stmmx(MM[6]); eaaddr+=10;
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[7]);
|
||||
}
|
||||
else
|
||||
{
|
||||
x87_st_fsave(0); eaaddr+=10;
|
||||
x87_st_fsave(1); eaaddr+=10;
|
||||
x87_st_fsave(2); eaaddr+=10;
|
||||
x87_st_fsave(3); eaaddr+=10;
|
||||
x87_st_fsave(4); eaaddr+=10;
|
||||
x87_st_fsave(5); eaaddr+=10;
|
||||
x87_st_fsave(6); eaaddr+=10;
|
||||
x87_st_fsave(0); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(1); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(2); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(3); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(4); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(5); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(6); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(7);
|
||||
}
|
||||
break;
|
||||
case 0x100: /*32-bit real mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+4,npxs);
|
||||
writememw(easeg,eaaddr+8,x87_gettag());
|
||||
writememw(easeg,eaaddr+12,x87_pc_off);
|
||||
writememw(easeg,eaaddr+20,x87_op_off);
|
||||
writememl(easeg,eaaddr+24,(x87_op_off>>16)<<12);
|
||||
eaaddr+=28;
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+4,npxs);
|
||||
writememw(easeg,cpu_state.eaaddr+8,x87_gettag());
|
||||
writememw(easeg,cpu_state.eaaddr+12,x87_pc_off);
|
||||
writememw(easeg,cpu_state.eaaddr+20,x87_op_off);
|
||||
writememl(easeg,cpu_state.eaaddr+24,(x87_op_off>>16)<<12);
|
||||
cpu_state.eaaddr+=28;
|
||||
if (ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); eaaddr+=10;
|
||||
x87_stmmx(MM[1]); eaaddr+=10;
|
||||
x87_stmmx(MM[2]); eaaddr+=10;
|
||||
x87_stmmx(MM[3]); eaaddr+=10;
|
||||
x87_stmmx(MM[4]); eaaddr+=10;
|
||||
x87_stmmx(MM[5]); eaaddr+=10;
|
||||
x87_stmmx(MM[6]); eaaddr+=10;
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[7]);
|
||||
}
|
||||
else
|
||||
{
|
||||
x87_st_fsave(0); eaaddr+=10;
|
||||
x87_st_fsave(1); eaaddr+=10;
|
||||
x87_st_fsave(2); eaaddr+=10;
|
||||
x87_st_fsave(3); eaaddr+=10;
|
||||
x87_st_fsave(4); eaaddr+=10;
|
||||
x87_st_fsave(5); eaaddr+=10;
|
||||
x87_st_fsave(6); eaaddr+=10;
|
||||
x87_st_fsave(0); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(1); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(2); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(3); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(4); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(5); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(6); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(7);
|
||||
}
|
||||
break;
|
||||
case 0x101: /*32-bit protected mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+4,npxs);
|
||||
writememw(easeg,eaaddr+8,x87_gettag());
|
||||
writememl(easeg,eaaddr+12,x87_pc_off);
|
||||
writememl(easeg,eaaddr+16,x87_pc_seg);
|
||||
writememl(easeg,eaaddr+20,x87_op_off);
|
||||
writememl(easeg,eaaddr+24,x87_op_seg);
|
||||
eaaddr+=28;
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+4,npxs);
|
||||
writememw(easeg,cpu_state.eaaddr+8,x87_gettag());
|
||||
writememl(easeg,cpu_state.eaaddr+12,x87_pc_off);
|
||||
writememl(easeg,cpu_state.eaaddr+16,x87_pc_seg);
|
||||
writememl(easeg,cpu_state.eaaddr+20,x87_op_off);
|
||||
writememl(easeg,cpu_state.eaaddr+24,x87_op_seg);
|
||||
cpu_state.eaaddr+=28;
|
||||
if (ismmx)
|
||||
{
|
||||
x87_stmmx(MM[0]); eaaddr+=10;
|
||||
x87_stmmx(MM[1]); eaaddr+=10;
|
||||
x87_stmmx(MM[2]); eaaddr+=10;
|
||||
x87_stmmx(MM[3]); eaaddr+=10;
|
||||
x87_stmmx(MM[4]); eaaddr+=10;
|
||||
x87_stmmx(MM[5]); eaaddr+=10;
|
||||
x87_stmmx(MM[6]); eaaddr+=10;
|
||||
x87_stmmx(MM[0]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[1]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[2]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[3]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[4]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[5]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[6]); cpu_state.eaaddr+=10;
|
||||
x87_stmmx(MM[7]);
|
||||
}
|
||||
else
|
||||
{
|
||||
x87_st_fsave(0); eaaddr+=10;
|
||||
x87_st_fsave(1); eaaddr+=10;
|
||||
x87_st_fsave(2); eaaddr+=10;
|
||||
x87_st_fsave(3); eaaddr+=10;
|
||||
x87_st_fsave(4); eaaddr+=10;
|
||||
x87_st_fsave(5); eaaddr+=10;
|
||||
x87_st_fsave(6); eaaddr+=10;
|
||||
x87_st_fsave(0); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(1); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(2); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(3); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(4); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(5); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(6); cpu_state.eaaddr+=10;
|
||||
x87_st_fsave(7);
|
||||
}
|
||||
break;
|
||||
@@ -305,7 +302,7 @@ static int opFSTSW_a16(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTSW %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTSW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw((npxs & 0xC7FF) | (TOP << 11));
|
||||
CLOCK_CYCLES(3);
|
||||
return abrt;
|
||||
@@ -314,7 +311,7 @@ static int opFSTSW_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTSW %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTSW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw((npxs & 0xC7FF) | (TOP << 11));
|
||||
CLOCK_CYCLES(3);
|
||||
return abrt;
|
||||
@@ -673,21 +670,21 @@ static int opFCOS(uint32_t fetchdat)
|
||||
static int FLDENV()
|
||||
{
|
||||
FP_ENTER();
|
||||
if (fplog) pclog("FLDENV %08X:%08X\n", easeg, eaaddr);
|
||||
switch ((cr0 & 1) | (op32 & 0x100))
|
||||
if (fplog) pclog("FLDENV %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
|
||||
{
|
||||
case 0x000: /*16-bit real mode*/
|
||||
case 0x001: /*16-bit protected mode*/
|
||||
npxc = readmemw(easeg, eaaddr);
|
||||
npxs = readmemw(easeg, eaaddr+2);
|
||||
x87_settag(readmemw(easeg, eaaddr+4));
|
||||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
npxs = readmemw(easeg, cpu_state.eaaddr+2);
|
||||
x87_settag(readmemw(easeg, cpu_state.eaaddr+4));
|
||||
TOP = (npxs >> 11) & 7;
|
||||
break;
|
||||
case 0x100: /*32-bit real mode*/
|
||||
case 0x101: /*32-bit protected mode*/
|
||||
npxc = readmemw(easeg, eaaddr);
|
||||
npxs = readmemw(easeg, eaaddr+4);
|
||||
x87_settag(readmemw(easeg, eaaddr+8));
|
||||
npxc = readmemw(easeg, cpu_state.eaaddr);
|
||||
npxs = readmemw(easeg, cpu_state.eaaddr+4);
|
||||
x87_settag(readmemw(easeg, cpu_state.eaaddr+8));
|
||||
TOP = (npxs >> 11) & 7;
|
||||
break;
|
||||
}
|
||||
@@ -715,7 +712,7 @@ static int opFLDCW_a16(uint32_t fetchdat)
|
||||
uint16_t tempw;
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempw = geteaw();
|
||||
if (abrt) return 1;
|
||||
npxc = tempw;
|
||||
@@ -727,7 +724,7 @@ static int opFLDCW_a32(uint32_t fetchdat)
|
||||
uint16_t tempw;
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FLDCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
tempw = geteaw();
|
||||
if (abrt) return 1;
|
||||
npxc = tempw;
|
||||
@@ -738,41 +735,41 @@ static int opFLDCW_a32(uint32_t fetchdat)
|
||||
static int FSTENV()
|
||||
{
|
||||
FP_ENTER();
|
||||
if (fplog) pclog("FSTENV %08X:%08X\n", easeg, eaaddr);
|
||||
switch ((cr0 & 1) | (op32 & 0x100))
|
||||
if (fplog) pclog("FSTENV %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
|
||||
{
|
||||
case 0x000: /*16-bit real mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+2,npxs);
|
||||
writememw(easeg,eaaddr+4,x87_gettag());
|
||||
writememw(easeg,eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,eaaddr+10,x87_op_off);
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+2,npxs);
|
||||
writememw(easeg,cpu_state.eaaddr+4,x87_gettag());
|
||||
writememw(easeg,cpu_state.eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
|
||||
break;
|
||||
case 0x001: /*16-bit protected mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+2,npxs);
|
||||
writememw(easeg,eaaddr+4,x87_gettag());
|
||||
writememw(easeg,eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,eaaddr+8,x87_pc_seg);
|
||||
writememw(easeg,eaaddr+10,x87_op_off);
|
||||
writememw(easeg,eaaddr+12,x87_op_seg);
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+2,npxs);
|
||||
writememw(easeg,cpu_state.eaaddr+4,x87_gettag());
|
||||
writememw(easeg,cpu_state.eaaddr+6,x87_pc_off);
|
||||
writememw(easeg,cpu_state.eaaddr+8,x87_pc_seg);
|
||||
writememw(easeg,cpu_state.eaaddr+10,x87_op_off);
|
||||
writememw(easeg,cpu_state.eaaddr+12,x87_op_seg);
|
||||
break;
|
||||
case 0x100: /*32-bit real mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+4,npxs);
|
||||
writememw(easeg,eaaddr+8,x87_gettag());
|
||||
writememw(easeg,eaaddr+12,x87_pc_off);
|
||||
writememw(easeg,eaaddr+20,x87_op_off);
|
||||
writememl(easeg,eaaddr+24,(x87_op_off>>16)<<12);
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+4,npxs);
|
||||
writememw(easeg,cpu_state.eaaddr+8,x87_gettag());
|
||||
writememw(easeg,cpu_state.eaaddr+12,x87_pc_off);
|
||||
writememw(easeg,cpu_state.eaaddr+20,x87_op_off);
|
||||
writememl(easeg,cpu_state.eaaddr+24,(x87_op_off>>16)<<12);
|
||||
break;
|
||||
case 0x101: /*32-bit protected mode*/
|
||||
writememw(easeg,eaaddr,npxc);
|
||||
writememw(easeg,eaaddr+4,npxs);
|
||||
writememw(easeg,eaaddr+8,x87_gettag());
|
||||
writememl(easeg,eaaddr+12,x87_pc_off);
|
||||
writememl(easeg,eaaddr+16,x87_pc_seg);
|
||||
writememl(easeg,eaaddr+20,x87_op_off);
|
||||
writememl(easeg,eaaddr+24,x87_op_seg);
|
||||
writememw(easeg,cpu_state.eaaddr,npxc);
|
||||
writememw(easeg,cpu_state.eaaddr+4,npxs);
|
||||
writememw(easeg,cpu_state.eaaddr+8,x87_gettag());
|
||||
writememl(easeg,cpu_state.eaaddr+12,x87_pc_off);
|
||||
writememl(easeg,cpu_state.eaaddr+16,x87_pc_seg);
|
||||
writememl(easeg,cpu_state.eaaddr+20,x87_op_off);
|
||||
writememl(easeg,cpu_state.eaaddr+24,x87_op_seg);
|
||||
break;
|
||||
}
|
||||
CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
|
||||
@@ -798,7 +795,7 @@ static int opFSTCW_a16(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_16(fetchdat);
|
||||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw(npxc);
|
||||
CLOCK_CYCLES(3);
|
||||
return abrt;
|
||||
@@ -807,7 +804,7 @@ static int opFSTCW_a32(uint32_t fetchdat)
|
||||
{
|
||||
FP_ENTER();
|
||||
fetch_ea_32(fetchdat);
|
||||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, eaaddr);
|
||||
if (fplog) pclog("FSTCW %08X:%08X\n", easeg, cpu_state.eaaddr);
|
||||
seteaw(npxc);
|
||||
CLOCK_CYCLES(3);
|
||||
return abrt;
|
||||
|
||||
Reference in New Issue
Block a user