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Split up logs into two verbosity levels (one is just init/invalid regs/object submission/pci, everything else is verbose_only)

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starfrost013
2025-04-03 01:40:59 +01:00
parent 33c89abee1
commit 7c4e2c82d4
23 changed files with 219 additions and 211 deletions
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BIN
doc/nvidia_notes/status.xlsx
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Binary file not shown.

3
src/include/86box/nv/vid_nv.h
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@@ -38,6 +38,9 @@
void nv_log_set_device(void* device);
void nv_log(const char *fmt, ...);
// Verbose logging level.
void nv_log_verbose_only(const char *fmt, ...);
// Defines common to all NV chip architectural generations
// PCI IDs

6
src/include/86box/nv/vid_nv3.h
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@@ -14,7 +14,7 @@
* Also check the doc folder for some more notres
*
* vid_nv3.h: NV3 Architecture Hardware Reference (open-source)
* Last updated: 26 March 2025 (STILL WORKING ON IT!!!)
* Last updated: 2 April 2025 (STILL WORKING ON IT!!!)
*
* Authors: Connor Hyde <mario64crashed@gmail.com>
*
@@ -1605,7 +1605,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value);
void nv3_pfifo_interrupt(uint32_t id, bool fire_now);
// NV3 PFIFO - Caches
void nv3_pfifo_cache0_push();
//cache0_push not a thing
void nv3_pfifo_cache0_pull();
void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val);
void nv3_pfifo_cache1_pull();
@@ -1641,4 +1641,4 @@ void nv3_ptimer_tick(double real_time);
void nv3_pvideo_init();
// NV3 PME (Mediaport)
void nv3_pmedia_init();
void nv3_pme_init();

4
src/video/nv/nv3/classes/nv3_class_00d_m2mf.c
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@@ -64,8 +64,8 @@ void nv3_class_00d_method(uint32_t param, uint32_t method_id, nv3_ramin_context_
/* This is technically its own thing, but I don't know if it's ever a problem with how we've designed it */
if (nv3->pgraph.notify_pending)
{
nv_log("M2MF notification with notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n");
nv_log("IF THIS IS A DEBUG BUILD, YOU SHOULD SEE A CONTEXT BELOW");
nv_log("WARNING: M2MF notification with notify_pending already set. param=0x%08x, method=0x%04x, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n");
nv_log("IF THIS BUILD WAS COMPILED WITH NV_LOG_ENABLE_ULTRA, YOU SHOULD SEE A CONTEXT BELOW");
nv3_debug_ramin_print_context_info(param, context);
nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_DOUBLE_NOTIFY);

24
src/video/nv/nv3/classes/nv3_class_shared_methods.c
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@@ -112,33 +112,33 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t
// This code is temporary and will probably be moved somewhere else
// Print torns of debug info
#ifdef DEBUG
nv_log("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n");
nv_log_verbose_only("******* WARNING: IF THIS OPERATION FUCKS UP, RANDOM MEMORY WILL BE CORRUPTED, YOUR ENTIRE SYSTEM MAY BE HOSED *******\n");
nv_log("Notification Information:\n");
nv_log("Adjust Value: 0x%08x\n", info_adjust);
(info_pt_present) ? nv_log("Pagetable Present: True\n") : nv_log("Pagetable Present: False\n");
nv_log_verbose_only("Notification Information:\n");
nv_log_verbose_only("Adjust Value: 0x%08x\n", info_adjust);
(info_pt_present) ? nv_log_verbose_only("Pagetable Present: True\n") : nv_log_verbose_only("Pagetable Present: False\n");
switch (info_notification_target)
{
case NV3_NOTIFICATION_TARGET_NVM:
nv_log("Notification Target: VRAM\n");
nv_log_verbose_only("Notification Target: VRAM\n");
break;
case NV3_NOTIFICATION_TARGET_CART:
nv_log("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n");
nv_log_verbose_only("VERY BAD WARNING: Notification detected with Notification Target: Cartridge. THIS SHOULD NEVER HAPPEN!!!!!\n");
break;
case NV3_NOTIFICATION_TARGET_PCI:
(nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log("Notification Target: PCI Bus\n") : nv_log("Notification Target: PCI Bus (On AGP card?)\n");
(nv3->nvbase.bus_generation == nv_bus_pci) ? nv_log_verbose_only("Notification Target: PCI Bus\n") : nv_log_verbose_only("Notification Target: PCI Bus (On AGP card?)\n");
break;
case NV3_NOTIFICATION_TARGET_AGP:
(nv3->nvbase.bus_generation == nv_bus_agp_1x
|| nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log("Notification Target: AGP Bus\n") : nv_log("Notification Target: AGP Bus (On PCI card?)\n");
|| nv3->nvbase.bus_generation == nv_bus_agp_2x) ? nv_log_verbose_only("Notification Target: AGP Bus\n") : nv_log_verbose_only("Notification Target: AGP Bus (On PCI card?)\n");
break;
}
nv_log("Limit: 0x%08x\n", notify_obj_limit);
(page_is_present) ? nv_log("Page is present\n") : nv_log("Page is not present\n");
(page_is_readwrite) ? nv_log("Page is read-write\n") : nv_log("Page is read-only\n");
nv_log("Pageframe Address: 0x%08x\n", frame_base);
nv_log_verbose_only("Limit: 0x%08x\n", notify_obj_limit);
(page_is_present) ? nv_log_verbose_only("Page is present\n") : nv_log_verbose_only("Page is not present\n");
(page_is_readwrite) ? nv_log_verbose_only("Page is read-write\n") : nv_log_verbose_only("Page is read-only\n");
nv_log_verbose_only("Pageframe Address: 0x%08x\n", frame_base);
#endif
// set up the dma transfer. we need to translate to a physical address.

32
src/video/nv/nv3/nv3_core.c
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@@ -72,9 +72,7 @@ uint8_t nv3_mmio_read8(uint32_t addr, void* priv)
ret = nv3_svga_in(real_address, nv3);
#ifdef ENABLE_NV_LOG_ULTRA
nv_log("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret);
#endif
nv_log_verbose_only("Redirected MMIO read8 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret);
return ret;
}
@@ -100,9 +98,8 @@ uint16_t nv3_mmio_read16(uint32_t addr, void* priv)
ret = nv3_svga_in(real_address, nv3)
| (nv3_svga_in(real_address + 1, nv3) << 8);
//#ifdef ENABLE_NV_LOG_ULTRA
nv_log("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret);
//#endif
nv_log_verbose_only("Redirected MMIO read16 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret);
return ret;
}
@@ -128,9 +125,7 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv)
| (nv3_svga_in(real_address + 2, nv3) << 16)
| (nv3_svga_in(real_address + 3, nv3) << 24);
//#ifdef ENABLE_NV_LOG_ULTRA
nv_log("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret);
//#endif
nv_log_verbose_only("Redirected MMIO read32 to SVGA: addr=0x%04x returned 0x%04x\n", addr, ret);
return ret;
}
@@ -155,9 +150,7 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv)
// svga writes are not logged anyway rn
uint32_t real_address = addr & 0x3FF;
//#ifdef ENABLE_NV_LOG_ULTRA
nv_log("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
//#endif
nv_log_verbose_only("Redirected MMIO write8 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
nv3_svga_out(real_address, val & 0xFF, nv3);
@@ -184,9 +177,8 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv)
// svga writes are not logged anyway rn
uint32_t real_address = addr & 0x3FF;
//#ifdef ENABLE_NV_LOG_ULTRA
nv_log("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
//#endif
nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
nv3_svga_out(real_address, val & 0xFF, nv3);
nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3);
@@ -214,9 +206,7 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv)
// svga writes are not logged anyway rn
uint32_t real_address = addr & 0x3FF;
//#ifdef ENABLE_NV_LOG_ULTRA
nv_log("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
//#endif
nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
nv3_svga_out(real_address, val & 0xFF, nv3);
nv3_svga_out(real_address + 1, (val >> 8) & 0xFF, nv3);
@@ -1073,9 +1063,9 @@ void* nv3_init(const device_t *info)
#endif
nv_log("Initialising core\n");
#ifdef ENABLE_NV_LOG_ULTRA
nv_log("ULTRA LOGGING enabled");
#endif
// this will only be logged if ENABLE_NV_LOG_ULTRA is defined
nv_log_verbose_only("ULTRA LOGGING enabled");
// Figure out which vbios the user selected
const char* vbios_id = device_get_config_bios("vbios");

13
src/video/nv/nv3/render/nv3_render_core.c
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@@ -44,9 +44,8 @@ nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj)
// set the pixel format
color_final.pixel_format = format;
#ifdef ENABLE_NV_LOG
nv_log("Expanding Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d", color, format, alpha_enabled);
#endif
nv_log_verbose_only("Expanding Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled);
// default to fully opaque in case alpha is disabled
color_final.a = 0xFF;
@@ -112,9 +111,7 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co
uint8_t format = (grobj.grobj_0 & 0x07);
bool alpha_enabled = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_ALPHA) & 0x01;
#ifdef ENABLE_NV_LOG
nv_log("Downconverting Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled);
#endif
nv_log_verbose_only("Downconverting Colour 0x%08x using pgraph_pixel_format 0x%x alpha enabled=%d\n", color, format, alpha_enabled);
uint32_t packed_color = 0x00;
@@ -141,10 +138,10 @@ uint32_t nv3_render_downconvert_color(nv3_grobj_t grobj, nv3_color_expanded_t co
packed_color |= (color.b << 10);
break;
case nv3_pgraph_pixel_format_y8:
nv_log("nv3_render_downconvert: Y8 not implemented");
warning("nv3_render_downconvert: Y8 not implemented");
break;
case nv3_pgraph_pixel_format_y16:
nv_log("nv3_render_downconvert: Y16 not implemented");
warning("nv3_render_downconvert: Y16 not implemented");
break;
default:
warning("nv3_render_downconvert_color unknown format %d", format);

16
src/video/nv/nv3/subsystems/nv3_pbus.c
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@@ -54,7 +54,7 @@ uint32_t nv3_pbus_read(uint32_t address)
// todo: friendly logging
nv_log("PBUS Read from 0x%08x", address);
nv_log_verbose_only("PBUS Read from 0x%08x", address);
// if the register actually exists
if (reg)
@@ -79,9 +79,9 @@ uint32_t nv3_pbus_read(uint32_t address)
}
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else
{
@@ -95,15 +95,15 @@ void nv3_pbus_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pbus_registers, sizeof(pbus_registers)/sizeof(pbus_registers[0]));
nv_log("PBUS Write 0x%08x -> 0x%08x\n", value, address);
nv_log_verbose_only("PBUS Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
// on-read function
if (reg->on_write)
@@ -174,7 +174,7 @@ uint8_t nv3_pbus_rma_read(uint16_t addr)
}
// log current location for vbios RE
nv_log("MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n",
nv_log_verbose_only("MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n",
addr, real_final_address, ret);
break;
@@ -239,7 +239,7 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val)
nv3->pbus.rma.data &= ~0xff000000;
nv3->pbus.rma.data |= (val << 24);
nv_log("MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n",
nv_log_verbose_only("MMIO Real Mode Access write transaction complete, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n",
addr, nv3->pbus.rma.addr, nv3->pbus.rma.data);
if (nv3->pbus.rma.addr < NV3_MMIO_SIZE)

16
src/video/nv/nv3/subsystems/nv3_pextdev.c
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@@ -89,11 +89,11 @@ uint32_t nv3_pextdev_read(uint32_t address)
// special consideration for straps
if (address == NV3_PSTRAPS)
{
nv_log("Straps Read (current value=0x%08x)\n", nv3->pextdev.straps);
nv_log_verbose_only("Straps Read (current value=0x%08x)\n", nv3->pextdev.straps);
}
else
{
nv_log("PEXTDEV Read from 0x%08x", address);
nv_log_verbose_only("PEXTDEV Read from 0x%08x", address);
}
// if the register actually exists
@@ -113,9 +113,9 @@ uint32_t nv3_pextdev_read(uint32_t address)
}
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else
{
@@ -129,12 +129,12 @@ void nv3_pextdev_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pextdev_registers, sizeof(pextdev_registers)/sizeof(pextdev_registers[0]));
nv_log("PEXTDEV Write 0x%08x -> 0x%08x\n", value, address);
nv_log_verbose_only("PEXTDEV Write 0x%08x -> 0x%08x\n", value, address);
// special consideration for straps
if (address == NV3_PSTRAPS)
{
nv_log("Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps);
warning("Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps);
return;
}
@@ -142,9 +142,9 @@ void nv3_pextdev_write(uint32_t address, uint32_t value)
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
// on-read function
if (reg->on_write)

29
src/video/nv/nv3/subsystems/nv3_pfb.c
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@@ -75,7 +75,7 @@ uint32_t nv3_pfb_read(uint32_t address)
// todo: friendly logging
nv_log("PFB Read from 0x%08x", address);
nv_log_verbose_only("PFB Read from 0x%08x", address);
// if the register actually exists
if (reg)
@@ -111,9 +111,9 @@ uint32_t nv3_pfb_read(uint32_t address)
}
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else
{
@@ -127,15 +127,15 @@ void nv3_pfb_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pfb_registers, sizeof(pfb_registers)/sizeof(pfb_registers[0]));
nv_log("PFB Write 0x%08x -> 0x%08x", value, address);
nv_log_verbose_only("PFB Write 0x%08x -> 0x%08x", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
// on-read function
if (reg->on_write)
@@ -189,17 +189,16 @@ void nv3_pfb_config0_write(uint32_t val)
// This doesn't actually seem very useful
#ifdef ENABLE_NV_LOG_ULTRA
nv_log("Framebuffer Config Change\n");
nv_log("Horizontal Size=%d pixels\n", new_pfb_htotal);
nv_log("Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal);
nv_log_verbose_only("Framebuffer Config Change\n");
nv_log_verbose_only("Horizontal Size=%d pixels\n", new_pfb_htotal);
nv_log_verbose_only("Vertical Size @ 4:3=%d pixels\n", new_pfb_vtotal);
if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_8BPP)
nv_log("Bit Depth=8bpp\n");
nv_log_verbose_only("Bit Depth=8bpp\n");
else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_16BPP)
nv_log("Bit Depth=16bpp\n");
nv_log_verbose_only("Bit Depth=16bpp\n");
else if (new_bit_depth == NV3_PFB_CONFIG_0_DEPTH_32BPP)
nv_log("Bit Depth=32bpp\n");
#endif
nv_log_verbose_only("Bit Depth=32bpp\n");
}

73
src/video/nv/nv3/subsystems/nv3_pfifo.c
View File

@@ -101,7 +101,7 @@ uint32_t nv3_pfifo_read(uint32_t address)
// todo: friendly logging
nv_log("PFIFO Read from 0x%08x", address);
nv_log_verbose_only("PFIFO Read from 0x%08x", address);
// if the register actually exists
if (reg)
@@ -278,9 +278,9 @@ uint32_t nv3_pfifo_read(uint32_t address)
}
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
/* Handle some special memory areas */
else if (address >= NV3_PFIFO_CACHE1_CTX_START && address <= NV3_PFIFO_CACHE1_CTX_END)
@@ -288,24 +288,26 @@ uint32_t nv3_pfifo_read(uint32_t address)
uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8;
ret = nv3->pfifo.cache1_settings.context[ctx_entry_id];
nv_log("PFIFO Cache1 CTX Read Entry=%d Value=0x%04x\n", ctx_entry_id, ret);
nv_log_verbose_only("PFIFO Cache1 CTX Read Entry=%d Value=0x%04x\n", ctx_entry_id, ret);
}
/* Direct cache read stuff */
else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END)
{
nv_log("PFIFO Cache0 Read\n");
nv_log_verbose_only("PFIFO Cache0 Read\n");
// See if we want the object name or the channel/subchannel information.
if (address & 4)
{
nv_log("Data=0x%08x\n", nv3->pfifo.cache0_entry.data);
nv_log_verbose_only("Data=0x%08x\n", nv3->pfifo.cache0_entry.data);
return nv3->pfifo.cache0_entry.data;
}
else
{
uint32_t final = nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL);
nv_log("Param (subchannel=15:13, method=12:2)=0x%08x\n", final);
nv_log_verbose_only("Param (subchannel=15:13, method=12:2)=0x%08x\n", final);
return final;
}
@@ -320,19 +322,19 @@ uint32_t nv3_pfifo_read(uint32_t address)
slot = (address >> 3) & 0x3F;
else
slot = (address >> 3) & 0x1F;
nv_log("PFIFO Cache1 Read slot=%d", slot);
nv_log_verbose_only("PFIFO Cache1 Read slot=%d", slot);
// See if we want the object name or the channel/subchannel information.
if (address & 4)
{
nv_log("Data=0x%08x\n", nv3->pfifo.cache1_entries[slot].data);
nv_log_verbose_only("Data=0x%08x\n", nv3->pfifo.cache1_entries[slot].data);
return nv3->pfifo.cache1_entries[slot].data;
}
else
{
uint32_t final = nv3->pfifo.cache1_entries[slot].method | (nv3->pfifo.cache1_entries[slot].subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL);
nv_log("Param (subchannel=15:13, method=12:2)=0x%08x\n", final);
nv_log_verbose_only("Param (subchannel=15:13, method=12:2)=0x%08x\n", final);
return final;
}
@@ -392,7 +394,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val)
nv_register_t* reg = nv_get_register(address, pfifo_registers, sizeof(pfifo_registers)/sizeof(pfifo_registers[0]));
nv_log("PFIFO Write 0x%08x -> 0x%08x", val, address);
nv_log_verbose_only("PFIFO Write 0x%08x -> 0x%08x", val, address);
// if the register actually exists
if (reg)
@@ -571,18 +573,18 @@ void nv3_pfifo_write(uint32_t address, uint32_t val)
}
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END)
{
nv_log("PFIFO Cache0 Write\n");
nv_log_verbose_only("PFIFO Cache0 Write\n");
// 3104 always written after 3100
if (address & 4)
{
nv_log("Name = 0x%08x\n", val);
nv_log_verbose_only("Name = 0x%08x\n", val);
nv3->pfifo.cache0_entry.data = val;
nv3_pfifo_cache0_pull(); // immediately pull out
}
@@ -590,7 +592,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val)
{
nv3->pfifo.cache0_entry.method = (val & 0x1FFC);
nv3->pfifo.cache0_entry.subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07;
nv_log("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache0_entry.subchannel, nv3->pfifo.cache0_entry.method);
nv_log_verbose_only("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache0_entry.subchannel, nv3->pfifo.cache0_entry.method);
}
}
@@ -606,19 +608,19 @@ void nv3_pfifo_write(uint32_t address, uint32_t val)
uint32_t real_entry = nv3_pfifo_cache1_normal2gray(slot);
nv_log("Cache1 Write Slot %d (Gray code)", real_entry);
nv_log_verbose_only("Cache1 Write Slot %d (Gray code)", real_entry);
// See if we want the object name or the channel/subchannel information.
if (address & 4)
{
nv_log("Name = 0x%08x\n", val);
nv_log_verbose_only("Name = 0x%08x\n", val);
nv3->pfifo.cache1_entries[real_entry].data = val;
}
else
{
nv3->pfifo.cache1_entries[real_entry].method = (val & 0x1FFC);
nv3->pfifo.cache1_entries[real_entry].subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07;
nv_log("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache1_entries[real_entry].subchannel, nv3->pfifo.cache1_entries[real_entry].method);
nv_log_verbose_only("Subchannel = 0x%08x, method = 0x%04x\n", nv3->pfifo.cache1_entries[real_entry].subchannel, nv3->pfifo.cache1_entries[real_entry].method);
}
}
/* Handle some special memory areas */
@@ -627,7 +629,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t val)
uint32_t ctx_entry_id = ((address - NV3_PFIFO_CACHE1_CTX_START) / 16) % 8;
nv3->pfifo.cache1_settings.context[ctx_entry_id] = val;
nv_log("PFIFO Cache1 CTX Write Entry=%d value=0x%04x\n", ctx_entry_id, val);
nv_log_verbose_only("PFIFO Cache1 CTX Write Entry=%d value=0x%04x\n", ctx_entry_id, val);
}
else /* Completely unknown */
{
@@ -689,11 +691,10 @@ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val)
return nv3_pfifo_cache1_binary_code_table[val];
}
// Submits graphics objects INTO cache0
void nv3_pfifo_cache0_push()
{
}
/*
You can't push into cache0 on the real hardware, but it's not practically done because Cache0 is meant to be reserved for software objects,
NV_USER writes always go to CACHE1
*/
// Pulls graphics objects OUT of cache0
void nv3_pfifo_cache0_pull()
@@ -740,9 +741,9 @@ void nv3_pfifo_cache0_pull()
nv3->pfifo.cache0_settings.get_address ^= 0x04;
#ifndef RELEASE_BUILD
#ifdef ENABLE_NV_LOG_ULTRA
nv_log("***** DEBUG: CACHE0 PULLED ****** Contextual information below\n");
#endif
nv_log_verbose_only("***** DEBUG: CACHE0 PULLED ****** Contextual information below\n");
nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)&current_context;
@@ -757,7 +758,7 @@ void nv3_pfifo_context_switch(uint32_t new_channel)
{
/* Send our contexts to RAMFC. Load the new ones from RAMFC. */
if (new_channel >= NV3_DMA_CHANNELS)
fatal("Tried to switch to invalid dma channel");
fatal("nv3_pfifo_context_switch: Tried to switch to invalid dma channel");
uint16_t ramfc_base = nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS & 0xF;
@@ -832,7 +833,8 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param)
// Did we fuck up?
if (oh_shit)
{
nv_log("WE ARE FUCKED Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x IMPLEMENT THIS OR DIE!!!", oh_shit_reason, channel, subchannel, method_offset);
nv_log("OH CRAP: Runout Error=%d Channel=%d Subchannel=%d Method=0x%04x",
oh_shit_reason, channel, subchannel, method_offset);
nv3_ramro_write(nv3->pfifo.runout_put, new_address);
nv3_ramro_write(nv3->pfifo.runout_put + 4, param);
@@ -878,7 +880,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param)
nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address) << 2;
nv_log("Submitted object [PIO]: Channel %d.%d, Parameter 0x%08x, Method ID 0x%04x (Put Address is now %d)\n",
nv_log_verbose_only("Submitted object [PIO]: Channel %d.%d, Parameter 0x%08x, Method ID 0x%04x (Put Address is now %d)\n",
channel, subchannel, param, method_offset, nv3->pfifo.cache1_settings.put_address);
// Now we're done. Phew!
@@ -918,7 +920,7 @@ void nv3_pfifo_cache1_pull()
//bit23 set=hardware
if (!(current_context & 0x800000))
{
nv_log("The object in CACHE1 is a software object\n");
nv_log_verbose_only("The object in CACHE1 is a software object\n");
nv3->pfifo.cache1_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD;
nv3->pfifo.cache1_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED;
@@ -939,9 +941,8 @@ void nv3_pfifo_cache1_pull()
#ifndef RELEASE_BUILD
#ifdef ENABLE_NV_LOG_ULTRA
nv_log("***** DEBUG: CACHE1 PULLED ****** Contextual information below\n");
#endif
nv_log_verbose_only("***** DEBUG: CACHE1 PULLED ****** Contextual information below\n");
nv3_ramin_context_t context_structure = *(nv3_ramin_context_t*)&current_context;

24
src/video/nv/nv3/subsystems/nv3_pgraph.c
View File

@@ -108,7 +108,7 @@ uint32_t nv3_pgraph_read(uint32_t address)
// todo: friendly logging
nv_log("PGRAPH Read from 0x%08x", address);
nv_log_verbose_only("PGRAPH Read from 0x%08x", address);
// if the register actually exists
if (reg)
@@ -262,9 +262,9 @@ uint32_t nv3_pgraph_read(uint32_t address)
}
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else
{
@@ -275,7 +275,7 @@ uint32_t nv3_pgraph_read(uint32_t address)
// Addresses should be aligned to 4 bytes.
uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0));
nv_log("PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]);
nv_log_verbose_only("PGRAPH Context Cache Read (Entry=%04x Value=%04x)\n", entry, nv3->pgraph.context_cache[entry]);
}
else /* Completely unknown */
{
@@ -297,15 +297,11 @@ void nv3_pgraph_write(uint32_t address, uint32_t value)
nv_register_t* reg = nv_get_register(address, pgraph_registers, sizeof(pgraph_registers)/sizeof(pgraph_registers[0]));
nv_log("PGRAPH Write 0x%08x -> 0x%08x\n", value, address);
nv_log_verbose_only("PGRAPH Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
@@ -467,6 +463,12 @@ void nv3_pgraph_write(uint32_t address, uint32_t value)
}
}
if (reg->friendly_name)
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log_verbose_only("\n");
}
else
{
@@ -477,7 +479,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value)
// Addresses should be aligned to 4 bytes.
uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0));
nv_log("PGRAPH Context Cache Write (Entry=%04x Value=0x%08x)\n", entry, value);
nv_log_verbose_only("PGRAPH Context Cache Write (Entry=%04x Value=0x%08x)\n", entry, value);
nv3->pgraph.context_cache[entry] = value;
}
else /* Completely unknown */
@@ -524,7 +526,7 @@ void nv3_pgraph_arbitrate_method(uint32_t param, uint16_t method, uint8_t channe
grobj.grobj_2 = nv3_ramin_read32(real_ramin_base + 8, nv3);
grobj.grobj_3 = nv3_ramin_read32(real_ramin_base + 12, nv3);
nv_log("**** About to execute method **** method=0x%04x param=0x%08x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n",
nv_log_verbose_only("**** About to execute method **** method=0x%04x param=0x%08x, channel=%d.%d, class=%s, grobj=0x%08x 0x%08x 0x%08x 0x%08x\n",
method, param, channel, subchannel, nv3_class_names[class_id], grobj.grobj_0, grobj.grobj_1, grobj.grobj_2, grobj.grobj_3);
/* Methods below 0x104 are shared across all classids, so call generic_method for that*/

26
src/video/nv/nv3/subsystems/nv3_pmc.c
View File

@@ -60,7 +60,7 @@ nv_register_t pmc_registers[] = {
uint32_t nv3_pmc_clear_interrupts()
{
nv_log("Clearing IRQs\n");
nv_log_verbose_only("Clearing IRQs\n");
pci_clear_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state);
}
@@ -144,21 +144,21 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now)
{
if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_HARDWARE)
{
nv_log("Firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status);
nv_log_verbose_only("Firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status);
pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state);
}
else
nv_log("NOT firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE HARDWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status);
nv_log_verbose_only("NOT firing hardware-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE HARDWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status);
}
else
{
if (nv3->pmc.interrupt_enable & NV3_PMC_INTERRUPT_ENABLE_SOFTWARE)
{
nv_log("Firing software-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status);
nv_log_verbose_only("Firing software-originated interrupt NV3_PMC_INTR_0=0x%08x\n", nv3->pmc.interrupt_status);
pci_set_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state);
}
else
nv_log("NOT firing software-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE SOFTWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status);
nv_log_verbose_only("NOT firing software-originated interrupt NV3_PMC_INTR_0=0x%08x, BECAUSE SOFTWARE INTERRUPTS ARE DISABLED\n", nv3->pmc.interrupt_status);
}
}
@@ -178,7 +178,7 @@ uint32_t nv3_pmc_read(uint32_t address)
uint32_t ret = 0x00;
// todo: friendly logging
nv_log("PMC Read from 0x%08x", address);
nv_log_verbose_only("PMC Read from 0x%08x", address);
// if the register actually exists
if (reg)
@@ -194,7 +194,7 @@ uint32_t nv3_pmc_read(uint32_t address)
ret = nv3->pmc.boot;
break;
case NV3_PMC_INTERRUPT_STATUS:
nv_log("\n"); // clear_interrupts logs
nv_log_verbose_only("\n"); // clear_interrupts logs
nv3_pmc_clear_interrupts();
ret = nv3_pmc_handle_interrupts(false);
@@ -211,9 +211,9 @@ uint32_t nv3_pmc_read(uint32_t address)
}
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else
{
@@ -227,7 +227,7 @@ void nv3_pmc_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pmc_registers, sizeof(pmc_registers)/sizeof(pmc_registers[0]));
nv_log("PMC Write 0x%08x -> 0x%08x", value, address);
nv_log_verbose_only("PMC Write 0x%08x -> 0x%08x", value, address);
// if the register actually exists...
if (reg)
@@ -245,7 +245,7 @@ void nv3_pmc_write(uint32_t address, uint32_t value)
// This can only be done by software interrupts...
if (!(nv3->pmc.interrupt_status & 0x7FFFFFFF))
{
nv_log("Huh? This is a hardware interrupt...Please use the INTR_EN registers of the GPU subsystem you want to trigger "
warning("Huh? This is a hardware interrupt...Please use the INTR_EN registers of the GPU subsystem you want to trigger "
" an interrupt on, rather than writing to NV3_PMC_INTERRUPT_STATUS (Or this is a bug)...NV3_PMC_INTERRUPT_STATUS=0x%08x)\n", nv3->pmc.interrupt_enable);
return;
}
@@ -264,9 +264,9 @@ void nv3_pmc_write(uint32_t address, uint32_t value)
}
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else /* Completely unknown */

12
src/video/nv/nv3/subsystems/nv3_pme.c
View File

@@ -49,7 +49,7 @@ uint32_t nv3_pme_read(uint32_t address)
// todo: friendly logging
nv_log("PME Read from 0x%08x", address);
nv_log_verbose_only("PME Read from 0x%08x", address);
// if the register actually exists
if (reg)
@@ -77,9 +77,9 @@ uint32_t nv3_pme_read(uint32_t address)
}
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else
{
@@ -93,15 +93,15 @@ void nv3_pme_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pme_registers, sizeof(pme_registers)/sizeof(pme_registers[0]));
nv_log("PME Write 0x%08x -> 0x%08x\n", value, address);
nv_log_verbose_only("PME Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
// on-read function
if (reg->on_write)

18
src/video/nv/nv3/subsystems/nv3_pramdac.c
View File

@@ -223,7 +223,7 @@ uint32_t nv3_pramdac_read(uint32_t address)
// todo: friendly logging
nv_log("PRAMDAC Read from 0x%08x\n", address);
nv_log_verbose_only("PRAMDAC Read from 0x%08x\n", address);
// if the register actually exists
if (reg)
@@ -288,9 +288,9 @@ uint32_t nv3_pramdac_read(uint32_t address)
}
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else
{
@@ -304,15 +304,12 @@ void nv3_pramdac_write(uint32_t address, uint32_t value)
{
nv_register_t* reg = nv_get_register(address, pramdac_registers, sizeof(pramdac_registers)/sizeof(pramdac_registers[0]));
nv_log("PRAMDAC Write 0x%08x -> 0x%08x\n", value, address);
nv_log_verbose_only("PRAMDAC Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// on-read function
if (reg->on_write)
@@ -381,6 +378,11 @@ void nv3_pramdac_write(uint32_t address, uint32_t value)
break;
}
}
if (reg->friendly_name)
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log_verbose_only("\n");
}
else /* Completely unknown */
{

28
src/video/nv/nv3/subsystems/nv3_pramin.c
View File

@@ -61,7 +61,7 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv)
if (!nv3_ramin_arbitrate_read(addr, &val)) // Oh well
{
val = (uint8_t)nv3->nvbase.svga.vram[addr];
nv_log("Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr);
nv_log_verbose_only("Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr);
}
return (uint8_t)val;
@@ -87,7 +87,7 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv)
if (!nv3_ramin_arbitrate_read(addr, &val))
{
val = (uint16_t)vram_16bit[addr];
nv_log("Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr);
nv_log_verbose_only("Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr);
}
return val;
@@ -114,7 +114,7 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv)
{
val = vram_32bit[addr];
nv_log("Read dword from PRAMIN 0x%08x <- 0x%08x (raw address=0x%08x)\n", val, addr, raw_addr);
nv_log_verbose_only("Read dword from PRAMIN 0x%08x <- 0x%08x (raw address=0x%08x)\n", val, addr, raw_addr);
}
return val;
@@ -139,7 +139,7 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv)
if (!nv3_ramin_arbitrate_write(addr, val32))
{
nv3->nvbase.svga.vram[addr] = val;
nv_log("Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr);
nv_log_verbose_only("Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr);
}
@@ -165,7 +165,7 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv)
if (!nv3_ramin_arbitrate_write(addr, val32))
{
vram_16bit[addr] = val;
nv_log("Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr);
nv_log_verbose_only("Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr);
}
@@ -189,7 +189,7 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv)
if (!nv3_ramin_arbitrate_write(addr, val))
{
vram_32bit[addr] = val;
nv_log("Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr);
nv_log_verbose_only("Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr);
}
}
@@ -378,7 +378,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u
// Why does this work?
uint32_t ramht_cur_address = ramht_base + (nv3_ramht_hash(name, channel) * bucket_entries * 8);
nv_log("Beginning search for graphics object at RAMHT base=0x%04x, name=0x%08x, Cache%d, channel=%d.%d)\n",
nv_log_verbose_only("Beginning search for graphics object at RAMHT base=0x%04x, name=0x%08x, Cache%d, channel=%d.%d)\n",
ramht_cur_address, name, cache_num, channel, subchannel);
bool found_object = false;
@@ -503,13 +503,13 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u
void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t context)
{
#ifndef RELEASE_BUILD
nv_log("Found object:\n");
nv_log("Param: 0x%04x\n", name);
nv_log_verbose_only("Found object:\n");
nv_log_verbose_only("Param: 0x%04x\n", name);
nv_log("Context:\n");
nv_log("DMA Channel %d (0-7 valid)\n", context.channel);
nv_log("Class ID: =0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]);
nv_log("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering);
nv_log("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4);
nv_log_verbose_only("Context:\n");
nv_log_verbose_only("DMA Channel %d (0-7 valid)\n", context.channel);
nv_log_verbose_only("Class ID: =0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]);
nv_log_verbose_only("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering);
nv_log_verbose_only("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4);
#endif
}

4
src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c
View File

@@ -30,10 +30,10 @@
uint32_t nv3_ramfc_read(uint32_t address)
{
nv_log("RAMFC (Unused DMA channel context) Read (0x%04x)), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address);
nv_log_verbose_only("RAMFC (Unused DMA channel context) Read (0x%04x)\n", address);
}
void nv3_ramfc_write(uint32_t address, uint32_t value)
{
nv_log("RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x)), I DON'T BELIEVE THIS SHOULD EVER HAPPEN\n", value, address);
nv_log_verbose_only("RAMFC (Unused DMA channel context) Write (0x%04x -> 0x%04x)\n", value, address);
}

6
src/video/nv/nv3/subsystems/nv3_pramin_ramht.c
View File

@@ -39,17 +39,17 @@ uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel)
// is this the right endianness?
nv_log("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, (hash/8), name, channel);
nv_log_verbose_only("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, (hash/8), name, channel);
return hash;
}
uint32_t nv3_ramht_read(uint32_t address)
{
nv_log("RAMHT (Graphics object storage hashtable) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address);
nv_log_verbose_only("RAMHT (Graphics object storage hashtable) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address);
}
void nv3_ramht_write(uint32_t address, uint32_t value)
{
nv_log("RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - UNIMPLEMENTED\n", value, address);
nv_log_verbose_only("RAMHT (Graphics object storage hashtable) Write (0x%04x -> 0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - UNIMPLEMENTED\n", value, address);
}

9
src/video/nv/nv3/subsystems/nv3_pramin_ramro.c
View File

@@ -30,15 +30,10 @@
uint32_t nv3_ramro_read(uint32_t address)
{
nv_log("RAM Runout (invalid dma object submission) Read (0x%04x), Probably shouldn't happenn\n", address);
nv_log("BIG Problem: RAM Runout (invalid dma object submission) Read (0x%04x)\n", address);
}
void nv3_ramro_write(uint32_t address, uint32_t value)
{
nv_log("RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x), Probably shouldn't happenn", value, address);
}
void nv3_ramro_send()
{
nv_log("BIG Problem: RAM Runout WRITE, OH CRAP!!!! (0x%04x -> 0x%04x)", value, address);
}

14
src/video/nv/nv3/subsystems/nv3_ptimer.c
View File

@@ -82,7 +82,7 @@ void nv3_ptimer_tick(double real_time)
// Only log on ptimer alarm. Otherwise, it's too much spam.
if (nv3->ptimer.time >= nv3->ptimer.alarm)
{
nv_log("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv3->ptimer.alarm);
nv_log_verbose_only("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv3->ptimer.alarm);
nv3_ptimer_interrupt(NV3_PTIMER_INTR_ALARM);
}
}
@@ -97,7 +97,7 @@ uint32_t nv3_ptimer_read(uint32_t address)
if (address != NV3_PTIMER_TIME_0_NSEC
&& address != NV3_PTIMER_TIME_1_NSEC)
{
nv_log("PTIMER Read from 0x%08x", address);
nv_log_verbose_only("PTIMER Read from 0x%08x", address);
}
uint32_t ret = 0x00;
@@ -147,9 +147,9 @@ uint32_t nv3_ptimer_read(uint32_t address)
&& reg->address != NV3_PTIMER_TIME_1_NSEC)
{
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
}
else
@@ -165,15 +165,15 @@ void nv3_ptimer_write(uint32_t address, uint32_t value)
// before doing anything, check the subsystem enablement
nv_register_t* reg = nv_get_register(address, ptimer_registers, sizeof(ptimer_registers)/sizeof(ptimer_registers[0]));
nv_log("PTIMER Write 0x%08x -> 0x%08x", value, address);
nv_log_verbose_only("PTIMER Write 0x%08x -> 0x%08x", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
// on-read function
if (reg->on_write)

16
src/video/nv/nv3/subsystems/nv3_pvideo.c
View File

@@ -55,15 +55,15 @@ uint32_t nv3_pvideo_read(uint32_t address)
// todo: friendly logging
nv_log("PVIDEO Read from 0x%08x", address);
nv_log_verbose_only("PVIDEO Read from 0x%08x", address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
// on-read function
if (reg->on_read)
@@ -95,9 +95,9 @@ uint32_t nv3_pvideo_read(uint32_t address)
}
if (reg->friendly_name)
nv_log(": 0x%08x <- %s\n", ret, reg->friendly_name);
nv_log_verbose_only(": 0x%08x <- %s\n", ret, reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
}
else
{
@@ -112,15 +112,15 @@ void nv3_pvideo_write(uint32_t address, uint32_t value)
// before doing anything, check the subsystem enablement
nv_register_t* reg = nv_get_register(address, pvideo_registers, sizeof(pvideo_registers)/sizeof(pvideo_registers[0]));
nv_log("PVIDEO Write 0x%08x -> 0x%08x\n", value, address);
nv_log_verbose_only("PVIDEO Write 0x%08x -> 0x%08x\n", value, address);
// if the register actually exists
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
nv_log_verbose_only(": %s\n", reg->friendly_name);
else
nv_log("\n");
nv_log_verbose_only("\n");
// on-read function
if (reg->on_write)

6
src/video/nv/nv3/subsystems/nv3_user.c
View File

@@ -40,8 +40,7 @@ uint32_t nv3_user_read(uint32_t address)
uint8_t channel = (address - NV3_USER_START) / 0x10000;
uint8_t subchannel = ((address - NV3_USER_START)) / 0x2000 % NV3_DMA_SUBCHANNELS_PER_CHANNEL;
nv_log("User Submission Area PIO Channel %d.%d method_offset=0x%04x\n", channel, subchannel, method_offset);
nv_log_verbose_only("User Submission Area PIO Channel %d.%d method_offset=0x%04x\n", channel, subchannel, method_offset);
// 0x10 is free CACHE1 object
// TODO: THERE ARE OTHER STUFF!
@@ -54,8 +53,7 @@ uint32_t nv3_user_read(uint32_t address)
}
nv_log("IT'S NOT IMPLEMENTED!!!! offset=0x%04x\n", method_offset);
nv_log("NV_USER READ: Channel FIELD NOT IMPLEMENTED!!!! offset=0x%04x\n", method_offset);
return 0x00;
};

51
src/video/nv/nv_base.c
View File

@@ -50,31 +50,52 @@ void nv_log_set_device(void* device)
nv_log_device = device;
}
void nv_log(const char *fmt, ...)
void nv_log_internal(const char* fmt, va_list arg)
{
if (!nv_log_device)
return;
va_list ap;
if (nv_do_log) {
va_start(ap, fmt);
// If our debug config option is configured, full log. Otherwise log with cyclical detection.
#ifndef RELEASE_BUILD
if (nv_log_full)
log_out(nv_log_device, fmt, ap);
else
#endif
log_out_cyclic(nv_log_device, fmt, ap);
va_end(ap);
}
if (nv_log_full)
log_out(nv_log_device, fmt, arg);
else
log_out_cyclic(nv_log_device, fmt, arg);
}
void nv_log(const char *fmt, ...)
{
va_list arg;
if (!nv_do_log)
return;
va_start(arg, fmt);
nv_log_internal(fmt, arg);
va_end(arg);
}
void nv_log_verbose_only(const char *fmt, ...)
{
#ifdef ENABLE_NV_LOG_ULTRA
if (!nv_do_log)
return;
va_start(arg, fmt);
nv_log_internal(fmt, arg);
va_end(arg);
#endif
}
#else
void nv_log(const char *fmt, ...)
{
}
void nv_log_verbose_only(const char *fmt, ...)
{
}
void nv_log_set_device(void* device)