[realtek-ambz2] Make compiling base core possible
This commit is contained in:
12
boards/_base/realtek-ambz2-2mb-900k.json
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12
boards/_base/realtek-ambz2-2mb-900k.json
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@@ -0,0 +1,12 @@
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{
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"flash": {
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"ota1": "0x010000+0xE0000",
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"ota2": "0x0F0000+0xE0000",
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"kvs": "0x1D0000+0x8000",
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"userdata": "0x1D8000+0x28000"
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},
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"upload": {
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"flash_size": 2097152,
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"maximum_size": 917504
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}
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}
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96
boards/_base/realtek-ambz2-image.json
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96
boards/_base/realtek-ambz2-image.json
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@@ -0,0 +1,96 @@
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{
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"image": {
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"keys": {
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"decryption": "a0d6dae7e062ca94cbb294bf896b9f68cf8438774256ac7403ca4fd9a1c9564f",
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"keyblock": {
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"part_table": "882aa16c8c44a7760aa8c9ab22e3568c6fa16c2afa4f0cea29a10abcdf60e44f",
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"boot": "882aa16c8c44a7760aa8c9ab22e3568c6fa16c2afa4f0cea29a10abcdf60e44f"
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},
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"hash_keys": {
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"part_table": "47e5661335a4c5e0a94d69f3c737d54f2383791332939753ef24279608f6d72b",
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"boot": "ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff",
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"ota1": "000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e5f",
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"ota2": "000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e5f"
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},
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"user_keys": {
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"boot": "aa0102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f",
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"ota1": "bb0102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f",
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"ota2": "bb0102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f"
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},
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"xip_sce_key": "a0d6dae7e062ca94cbb294bf896b9f68",
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"xip_sce_iv": "94879487948794879487948794879487"
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},
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"ptable": {
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"boot": "BOOT",
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"ota1": "FW1",
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"ota2": "FW2"
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},
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"boot": {
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"name": "boot.sram",
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"type": "SRAM",
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"entry": "__ram_start_table_start__",
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"elf": [
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".ram.func.table",
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".data",
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".ram.code_text",
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".ram.code_rodata"
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],
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"is_boot": true
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},
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"fw": [
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{
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"type": "FWHS_S",
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"sections": [
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{
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"name": "fwhs.sram",
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"type": "SRAM",
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"entry": "__ram_start_table_start__",
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"elf": [
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".ram.img.signature",
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".ram.func.table",
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".data",
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".ram.code_text",
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".ram.code_rodata"
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]
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},
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{
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"name": "fwhs.psram",
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"type": "PSRAM",
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"entry": "__psram_start__",
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"elf": [
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".psram.data",
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".psram.code_text",
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".psram.code_rodata"
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]
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}
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]
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},
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{
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"type": "XIP",
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"sections": [
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{
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"name": "fwhs.xip_c",
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"entry": "XIP_RamImgSignature_s",
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"type": "XIP",
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"elf": [
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".xip.code_c"
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]
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}
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]
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},
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{
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"type": "XIP",
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"sections": [
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{
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"name": "fwhs.xip_p",
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"entry": "__xip_code_rodata_start__",
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"type": "XIP",
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"elf": [
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".xip.code_p"
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]
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}
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]
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}
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]
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}
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}
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@@ -16,7 +16,11 @@
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"protocols": []
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},
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"upload": {
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"maximum_ram_size": 262144
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"maximum_ram_size": 262144,
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"protocol": "uart",
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"protocols": [
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"uart"
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]
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},
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"doc": {
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"params": {
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26
boards/bw15.json
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26
boards/bw15.json
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@@ -0,0 +1,26 @@
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{
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"_base": [
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"realtek-ambz2",
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"realtek-ambz2-8720",
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"realtek-ambz2-image",
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"realtek-ambz2-2mb-992k",
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"ic/rtl8720cf",
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"pcb/bw15"
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],
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"build": {
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"mcu": "rtl8720cf",
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"variant": "bw15"
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},
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"name": "BW15",
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"url": "https://docs.ai-thinker.com/_media/rtl8710/docs/bw15_datasheet_en.pdf",
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"vendor": "Ai-Thinker Co., Ltd.",
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"pcb": {
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"symbol": "BW15"
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},
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"doc": {
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"fccid": "2AXVG-BW15",
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"links": {
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"Vendor datasheet": "https://docs.ai-thinker.com/_media/rtl8710/docs/bw15_datasheet_en.pdf"
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}
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}
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}
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102
boards/generic-rtl8720cf-2mb-992k.json
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102
boards/generic-rtl8720cf-2mb-992k.json
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@@ -0,0 +1,102 @@
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{
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"_base": [
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"generic",
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"realtek-ambz2",
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"realtek-ambz2-8720",
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"realtek-ambz2-image",
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"realtek-ambz2-2mb-992k",
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"ic/rtl8720cf"
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],
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"build": {
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"mcu": "rtl8720cf",
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"variant": "generic-rtl8720cf-2mb-992k"
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},
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"name": "Generic - RTL8720CF (2M/992k)",
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"symbol": "RTL8720CF (2M/992k)",
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"url": "https://docs.libretiny.eu/boards/generic-rtl8720cf-2mb-992k/",
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"vendor": "Generic",
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"pcb": {
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"pinout": {
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"1": {
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"IC": 15,
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"ARD": "D0"
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},
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"2": {
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"IC": 16,
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"ARD": "D1"
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},
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"3": {
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"IC": 18,
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"ARD": "D2"
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},
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"4": {
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"IC": 19,
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"ARD": "D3"
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},
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"5": {
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"IC": 20,
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"ARD": "D4"
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},
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"6": {
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"IC": 21,
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"ARD": "D5"
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},
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"7": {
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"IC": 22,
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"ARD": "D6"
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},
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"8": {
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"IC": 23,
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"ARD": "D7"
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},
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"9": {
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"IC": 24,
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"ARD": "D8"
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},
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"10": {
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"IC": 25,
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"ARD": "D9"
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},
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"11": {
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"IC": 26,
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"ARD": "D10"
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},
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"12": {
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"IC": 33,
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"ARD": "D11"
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},
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"13": {
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"IC": 34,
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"ARD": "D12"
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},
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"14": {
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"IC": 36,
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"ARD": "D13"
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},
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"15": {
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"IC": 37,
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"ARD": "D14"
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},
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"16": {
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"IC": 38,
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"ARD": "D15"
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},
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"17": {
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"IC": 39,
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"ARD": "D16"
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},
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"18": {
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"IC": 40,
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"ARD": "D17"
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},
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"19": {
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"IC": 1,
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"ARD": "D18"
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},
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"20": {
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"IC": 3,
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"ARD": "D19"
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}
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}
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}
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}
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@@ -1,6 +1,7 @@
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# Copyright (c) Kuba Szczodrzyński 2022-07-20.
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from os.path import join
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from os.path import isfile, join
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from shutil import copyfile
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from platformio.platform.base import PlatformBase
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from platformio.platform.board import PlatformBoardConfig
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@@ -436,10 +437,25 @@ env.Replace(
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SIZEPRINTCMD="$SIZETOOL -B -d $SOURCES",
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)
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# Bootloader - copy for linking
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# fmt: off
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bootloader_src = env.subst("${SDK_DIR}/component/soc/realtek/8710c/misc/bsp/image/bootloader.axf")
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bootloader_dst = env.subst("${BUILD_DIR}/bootloader.axf")
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# fmt: on
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if not isfile(bootloader_dst):
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copyfile(bootloader_src, bootloader_dst)
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# Build all libraries
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queue.BuildLibraries()
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# Main firmware outputs and actions
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image_firmware_is = "${BUILD_DIR}/image_firmware_is.${FLASH_OTA1_OFFSET}.bin"
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env.Replace(
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# TODO
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# linker command (dual .bin outputs)
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LINK="${LTCHIPTOOL} link2bin ${BOARD_JSON} '' ''",
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# UF2OTA input list
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UF2OTA=[
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# same OTA images for flasher and device
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f"{image_firmware_is},{image_firmware_is}=device:ota1,ota2;flasher:ota1,ota2",
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],
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)
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@@ -40,6 +40,8 @@ typedef enum {
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RTL8711BU = CPU_MODEL(F_RTL8710B, 0xFC), // CHIPID_8711BG / QFN68
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MX1290 = RTL8710BN,
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MX1290V2 = RTL8710BX,
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// Realtek AmebaZ2
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RTL8720CF = CPU_MODEL(F_RTL8720C, 0x00), // TODO
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// Beken 72XX
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BK7231T = CPU_MODEL(F_BK7231U, 0x1A), // *SCTRL_CHIP_ID = 0x7231a
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BK7231N = CPU_MODEL(F_BK7231N, 0x1C), // *SCTRL_CHIP_ID = 0x7231c
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@@ -20,6 +20,7 @@ extern "C" {
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#include <rtl8710b.h>
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#endif
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#if LT_RTL8720C
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#include <hal.h>
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#include <rtl8710c.h>
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#endif
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3
cores/realtek-ambz2/base/fixups/cmd_shell.c
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3
cores/realtek-ambz2/base/fixups/cmd_shell.c
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@@ -0,0 +1,3 @@
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/* Copyright (c) Kuba Szczodrzyński 2023-04-12. */
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void shell_cmd_init() {}
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38
cores/realtek-ambz2/base/port/printf.c
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38
cores/realtek-ambz2/base/port/printf.c
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@@ -0,0 +1,38 @@
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/* Copyright (c) Kuba Szczodrzyński 2023-04-12. */
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#include <libretiny.h>
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#include <sdk_private.h>
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#include <printf/printf.h>
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static UART0_Type *uart_dev[4] = {
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UART0,
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UART1,
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UART2,
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UART3,
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};
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uint8_t lt_uart_port = 2;
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void putchar_(char c) {
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putchar_p(c, lt_uart_port);
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}
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void putchar_p(char c, unsigned long port) {
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// while (UART_Writable(uart_dev[port]) == 0) {}
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uart_dev[port]->thr = c;
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}
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WRAP_PRINTF(rtl_printf);
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WRAP_SPRINTF(rtl_sprintf);
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WRAP_SNPRINTF(rtl_snprintf);
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WRAP_VSNPRINTF(rtl_vsnprintf);
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WRAP_VSNPRINTF(rtl_vsnprintf_r);
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WRAP_VPRINTF(rtl_vprintf);
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WRAP_PRINTF(DiagPrintf);
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WRAP_SPRINTF(DiagSPrintf);
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WRAP_SNPRINTF(DiagSnPrintf);
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WRAP_PRINTF(prvDiagPrintf);
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WRAP_SPRINTF(prvDiagSPrintf);
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WRAP_VSPRINTF(VSprintf);
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WRAP_PRINTF(LOG_PRINTF);
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18
cores/realtek-ambz2/base/port/printf_port.h
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18
cores/realtek-ambz2/base/port/printf_port.h
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@@ -0,0 +1,18 @@
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/* Copyright (c) Kuba Szczodrzyński 2022-06-20. */
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#pragma once
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#include <printf_config.h>
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#ifdef __cplusplus
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extern "C" {
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#endif // __cplusplus
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WRAP_DISABLE_DEF(rtl_printf);
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WRAP_DISABLE_DEF(DiagPrintf);
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WRAP_DISABLE_DEF(prvDiagPrintf);
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WRAP_DISABLE_DEF(LOG_PRINTF);
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#ifdef __cplusplus
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} // extern "C"
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#endif
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