A somewhat more robust explanation

_posts/2025-01-22-riva128-part-1.md

@@ -158,7 +158,7 @@ This is the primary area of memory mapping, and is set up as Base Address Regist
 
 _Note_: There is a wrinkle to this setup here. The VBIOS has to be able to communicate with the main GPU in real mode when PCI is not available. This is achieved by mapping I/O ports `0x3d0`-`0x3d3` in the Weitek core to the registers for a mechanism called RMA - Real Mode Access - that effectively serve as a mechanism for forming a 32-bit address; when a 32-bit address is formed by writing to all four RMA registers, (internally implemented using a mode register) the next SVGA x86 I/O port read/write will become a read/write from the main GPU PCI BAR0 MMIO space. This allows the VBIOS to POST the GPU during its initialisation process.
 
-*A zeta buffer is Nvidia parlance for a combined Z-buffer (sorting polygons based on their distance from the camera) and stencil buffer (a buffer allowing for part of an image to be discarded).
+*A zeta buffer is Nvidia parlance for a combined Z-buffer (a buffer that is a part of the framebuffer, allowing for orting polygons based on their distance from the camera) and stencil buffer (a buffer allowing for part of an image to be discarded). In this case, a 16-bit z-buffer and 8-bit stencil buffer are interleaved. (Later Nvidia GPUs have a "super zeta buffer"!)
 
 #### DFB
 DFB means "Dumb Framebuffer" (that's what Nvidia chose to call it) and is simply a linear framebuffer. It is mapped into PCI BAR1 and has a size of 0x400000 by default (depending on the VRAM size?). In the NV3, it is mapped into BAR1 (on later GPUs it was moved to BAR0 starting at `0x1000000`). It is presumably meant for manipulating the GPU without using its DMA facilities.