TC1995
c26ab74a8a
Merge branch 'master' into pc98x1
2025-05-29 20:25:51 +02:00
OBattler
25f0a26ea1
Vastly improve the ALi M1409 emulation (all of shadow RAM now work, as does bus speed and external cache setting), and fix the "Writing unimplemented Cyrix register FF" error as well.
2025-05-29 09:45:49 +02:00
OBattler
8aa15fa21f
The update value handler should be at Pentium Pro, not Cyrix Cx6x86.
2025-04-11 20:27:41 +02:00
RichardG867
4bd374a7df
Don't apply the Deschutes cacheability fix to Covington
2025-04-02 16:55:57 -03:00
RichardG867
f56f636248
Report 4 GB cacheable memory on Deschutes CPUs, fixes modern Linux limiting itself to 512 MB on some machines
2025-04-02 16:27:10 -03:00
TC1995
f5202f33a1
Merge branch 'master' into pc98x1
2025-03-26 19:24:31 +01:00
Cacodemon345
a9c97abfb6
Pre-calculate pow table for FXTRACT instruction
2025-03-20 21:52:48 +06:00
OBattler
395f23cf57
More Cyrix fixes.
2025-03-19 03:12:36 +01:00
OBattler
70dcdee72b
Some Cyrix MII table/ID fixes and added some Cyrix CPU blocking for the NuPRO 592 and the P5MMS98.
2025-03-18 19:21:00 +01:00
OBattler
1c5d432d3c
Disable special segment selector pushing behavior on Pentium onwards, fixes MSVC builds of ReactOS.
2025-03-16 18:37:32 +01:00
OBattler
aef06552fb
Some missing breaks in the Cyrix register writes.
2025-03-14 15:34:37 +01:00
TC1995
2e3eaf1a1e
Merge branch 'master' into pc98x1
2025-03-07 13:56:35 +01:00
OBattler
78f50c5b04
Move the Cyrix 6x86 out of the Dev branch.
2025-03-06 00:17:16 +01:00
Cacodemon345
5f3641ecbd
Implement Cyrix EMMI extensions and 4 FPU instructions
...
PADDSIW, PSUBSIW, PMULHRW (named PMULHRWC in the code as recognized by some assemblers), PMULHRIW, PDISTIB, PMACHRIW, PAVEB, PMAGW, PMVZB, PMVNZB, PMVLZB, PMVGEZB, FTSTP, FRINT2, FRINEAR, FRICHOP are implemented for Cyrix 6x86MX. Cyrix 6x86(L) only has the last 4 instructions.
2025-03-06 03:05:10 +06:00
OBattler
8c2db2892d
CPU: Fix Cyrix SMM instructions.
2025-03-05 21:52:17 +01:00
TC1995
d29189af42
Merge branch 'master' into pc98x1
2025-02-18 17:06:59 +01:00
pankozaC++
6362351987
bring back the Slot 1 to Socket 8 adapter
2025-02-13 19:14:36 +01:00
TC1995
910fcfa9e5
Merge branch 'master' into pc98x1
2025-02-08 19:11:55 +01:00
OBattler
34e3f6e849
No longer list Socket 8 CPU's for Slot 1 machines, closes #5196 .
2025-02-07 23:34:12 +01:00
TC1995
9599052055
Merge branch 'master' into pc98x1
2024-12-31 21:20:48 +01:00
Adrian Siekierka
eb25bccf1e
Add initial Mazovia 1016 emulation
2024-12-22 13:52:25 +01:00
OBattler
8f25851406
Pentium II: Change BIOS update signature to non-zero on CPUID with EAX = 1, fixes microcode update error messages on some BIOS'es.
2024-12-22 04:09:55 +01:00
TC1995
d195b3830d
Merge branch 'master' into pc98x1
2024-12-21 23:14:40 +01:00
Alexander Babikov
f1a60d8242
Add PSE-36 (36-bit page size extension) support
...
Code ported from PCBox
2024-12-21 20:44:31 +05:00
TC1995
606b0ddc11
Merge branch 'master' into pc98x1
2024-12-13 14:03:24 +01:00
OBattler
cc8cfb7b3f
The CPL checks introduced in build 6212 need to only be made in protected mode, fixes the Daewoo CB52X-SI.
2024-12-03 17:48:07 +01:00
TC1995
23a7e488f3
Merge branch 'master' into pc98x1
2024-10-16 00:02:49 +02:00
OBattler
0a3f1e3279
RDMSR, WRMSR, and WBINVD now correctly GPF when CPL > 0, fixes #4887 .
2024-10-15 23:54:57 +02:00
TC1995
a019c94996
Merge branch 'master' into pc98x1
2024-10-01 20:25:39 +02:00
OBattler
8899b1411b
AMD K6-2 onwards: EFER write GPF is now correctly on bits 5 onwards, not on bits 1 onwards.
2024-10-01 09:56:40 +02:00
OBattler
7e0c6e9b69
Enable the SYSENTER/SYSEXIT MSR's on Pentium Pro, fixes OpenBSD booting, fixes #4873 .
2024-09-30 18:08:05 +02:00
TC1995
1caefefe57
Merge branch 'master' into pc98x1
2024-08-29 20:51:41 +02:00
OBattler
fb3b46f648
Unbroke SCO Xenix on the 286/386 interpreter, this will do until the prefetch queue is finally implemented.
2024-08-29 01:57:22 +02:00
TC1995
6572d9f9d5
Merge branch 'master' into pc98x1
2024-08-29 00:49:26 +02:00
OBattler
7c7cc921ee
Non-808x interpreters: fetch the next instruction after a CR0 paging bit toggle with the old CR0 paging bit value, fixes SCO Unix.
2024-08-27 02:34:59 +02:00
Jasmine Iwanek
025798c832
PGE for K5
2024-08-25 20:20:21 -04:00
Jasmine Iwanek
97f861b0ba
Split off AMD K5 from K6
2024-08-25 19:08:30 -04:00
TC1995
7123443fef
Merge branch 'master' into pc98x1
2024-08-12 19:40:00 +02:00
Jasmine Iwanek
892f066ffa
Don't depend on DEV_BRANCH
...
Allows things to be compiled independently
2024-08-08 20:25:03 -04:00
TC1995
4dedfc897a
Small checks for PC-98x1 compatibility
...
See above.
2024-07-12 20:51:24 +02:00
Cacodemon345
2b3d3ad5bd
Make sure timers don't go completely out of sync upon altering TSC via WRMSR
2024-06-18 20:21:23 +06:00
OBattler
a369bc2d05
Reimplement S3 ViRGE reset and move PCI TRC CPU reset to outside the recompiled block, fixes #2903 .
2024-06-12 20:46:27 +02:00
OBattler
2273f563a5
Moved the offending SoftFloat-related stuff to x87_sf.h, fixes warnings.
2024-06-10 00:08:48 +02:00
Alexander Babikov
a07ffdecab
Restore the debug register operation on 486+
...
But put it behind a compile-time option due to performance hits
Also add the DE flag to CPUID on supported CPUs
2024-05-24 03:35:08 +05:00
Miran Grča
8928f5d771
Variable to override the 286/386 interpreter.
2024-04-25 19:10:40 +02:00
OBattler
15e3876e21
Prepare WD76C10 for 286/386 interpreter selection, exempt IBM 486BL and all Cyrix'es from the 286/386 interpreter.
2024-04-24 06:06:09 +02:00
Alexander Babikov
996769095b
Implement most missing P6 MSRs
...
Remove the 6 extraneous performance counter MSRs which
haven't existed on P6
2024-02-07 12:31:43 +05:00
Alexander Babikov
e54b57641c
Implement missing IBM, AMD and Cyrix MSRs
2024-02-07 12:31:42 +05:00
Alexander Babikov
65f40ca71d
Implement missing WinChip C6/2 and Cyrix III MSRs
2024-02-07 12:31:42 +05:00
Alexander Babikov
1b9bf568f2
Implement missing Pentium MSRs
...
Includes obscure behavior, like undocumented "high" MSRs
2024-02-07 12:31:41 +05:00
