TC1995
2e3eaf1a1e
Merge branch 'master' into pc98x1
2025-03-07 13:56:35 +01:00
OBattler
78f50c5b04
Move the Cyrix 6x86 out of the Dev branch.
2025-03-06 00:17:16 +01:00
Cacodemon345
5f3641ecbd
Implement Cyrix EMMI extensions and 4 FPU instructions
...
PADDSIW, PSUBSIW, PMULHRW (named PMULHRWC in the code as recognized by some assemblers), PMULHRIW, PDISTIB, PMACHRIW, PAVEB, PMAGW, PMVZB, PMVNZB, PMVLZB, PMVGEZB, FTSTP, FRINT2, FRINEAR, FRICHOP are implemented for Cyrix 6x86MX. Cyrix 6x86(L) only has the last 4 instructions.
2025-03-06 03:05:10 +06:00
OBattler
8c2db2892d
CPU: Fix Cyrix SMM instructions.
2025-03-05 21:52:17 +01:00
TC1995
d29189af42
Merge branch 'master' into pc98x1
2025-02-18 17:06:59 +01:00
pankozaC++
6362351987
bring back the Slot 1 to Socket 8 adapter
2025-02-13 19:14:36 +01:00
TC1995
910fcfa9e5
Merge branch 'master' into pc98x1
2025-02-08 19:11:55 +01:00
OBattler
34e3f6e849
No longer list Socket 8 CPU's for Slot 1 machines, closes #5196 .
2025-02-07 23:34:12 +01:00
TC1995
9599052055
Merge branch 'master' into pc98x1
2024-12-31 21:20:48 +01:00
Adrian Siekierka
eb25bccf1e
Add initial Mazovia 1016 emulation
2024-12-22 13:52:25 +01:00
OBattler
8f25851406
Pentium II: Change BIOS update signature to non-zero on CPUID with EAX = 1, fixes microcode update error messages on some BIOS'es.
2024-12-22 04:09:55 +01:00
TC1995
d195b3830d
Merge branch 'master' into pc98x1
2024-12-21 23:14:40 +01:00
Alexander Babikov
f1a60d8242
Add PSE-36 (36-bit page size extension) support
...
Code ported from PCBox
2024-12-21 20:44:31 +05:00
TC1995
606b0ddc11
Merge branch 'master' into pc98x1
2024-12-13 14:03:24 +01:00
OBattler
cc8cfb7b3f
The CPL checks introduced in build 6212 need to only be made in protected mode, fixes the Daewoo CB52X-SI.
2024-12-03 17:48:07 +01:00
TC1995
23a7e488f3
Merge branch 'master' into pc98x1
2024-10-16 00:02:49 +02:00
OBattler
0a3f1e3279
RDMSR, WRMSR, and WBINVD now correctly GPF when CPL > 0, fixes #4887 .
2024-10-15 23:54:57 +02:00
TC1995
a019c94996
Merge branch 'master' into pc98x1
2024-10-01 20:25:39 +02:00
OBattler
8899b1411b
AMD K6-2 onwards: EFER write GPF is now correctly on bits 5 onwards, not on bits 1 onwards.
2024-10-01 09:56:40 +02:00
OBattler
7e0c6e9b69
Enable the SYSENTER/SYSEXIT MSR's on Pentium Pro, fixes OpenBSD booting, fixes #4873 .
2024-09-30 18:08:05 +02:00
TC1995
1caefefe57
Merge branch 'master' into pc98x1
2024-08-29 20:51:41 +02:00
OBattler
fb3b46f648
Unbroke SCO Xenix on the 286/386 interpreter, this will do until the prefetch queue is finally implemented.
2024-08-29 01:57:22 +02:00
TC1995
6572d9f9d5
Merge branch 'master' into pc98x1
2024-08-29 00:49:26 +02:00
OBattler
7c7cc921ee
Non-808x interpreters: fetch the next instruction after a CR0 paging bit toggle with the old CR0 paging bit value, fixes SCO Unix.
2024-08-27 02:34:59 +02:00
Jasmine Iwanek
025798c832
PGE for K5
2024-08-25 20:20:21 -04:00
Jasmine Iwanek
97f861b0ba
Split off AMD K5 from K6
2024-08-25 19:08:30 -04:00
TC1995
7123443fef
Merge branch 'master' into pc98x1
2024-08-12 19:40:00 +02:00
Jasmine Iwanek
892f066ffa
Don't depend on DEV_BRANCH
...
Allows things to be compiled independently
2024-08-08 20:25:03 -04:00
TC1995
4dedfc897a
Small checks for PC-98x1 compatibility
...
See above.
2024-07-12 20:51:24 +02:00
Cacodemon345
2b3d3ad5bd
Make sure timers don't go completely out of sync upon altering TSC via WRMSR
2024-06-18 20:21:23 +06:00
OBattler
a369bc2d05
Reimplement S3 ViRGE reset and move PCI TRC CPU reset to outside the recompiled block, fixes #2903 .
2024-06-12 20:46:27 +02:00
OBattler
2273f563a5
Moved the offending SoftFloat-related stuff to x87_sf.h, fixes warnings.
2024-06-10 00:08:48 +02:00
Alexander Babikov
a07ffdecab
Restore the debug register operation on 486+
...
But put it behind a compile-time option due to performance hits
Also add the DE flag to CPUID on supported CPUs
2024-05-24 03:35:08 +05:00
Miran Grča
8928f5d771
Variable to override the 286/386 interpreter.
2024-04-25 19:10:40 +02:00
OBattler
15e3876e21
Prepare WD76C10 for 286/386 interpreter selection, exempt IBM 486BL and all Cyrix'es from the 286/386 interpreter.
2024-04-24 06:06:09 +02:00
Alexander Babikov
996769095b
Implement most missing P6 MSRs
...
Remove the 6 extraneous performance counter MSRs which
haven't existed on P6
2024-02-07 12:31:43 +05:00
Alexander Babikov
e54b57641c
Implement missing IBM, AMD and Cyrix MSRs
2024-02-07 12:31:42 +05:00
Alexander Babikov
65f40ca71d
Implement missing WinChip C6/2 and Cyrix III MSRs
2024-02-07 12:31:42 +05:00
Alexander Babikov
1b9bf568f2
Implement missing Pentium MSRs
...
Includes obscure behavior, like undocumented "high" MSRs
2024-02-07 12:31:41 +05:00
Alexander Babikov
2a3d13d306
Various consistency changes
2024-02-07 12:31:39 +05:00
Alexander Babikov
1e4455d98c
Add comments with MSR and CPUID flag names
...
Reorganize the MSR struct
2024-02-07 12:31:38 +05:00
Alexander Babikov
1bb31f3937
Remove the AP61 hack completely
...
It's no longer needed
2024-02-07 12:31:37 +05:00
Alexander Babikov
963525ff2e
Correct the CPUID SEP bit on AMD K6-2 and later
...
They use the standard bit 11, not he AMD-specific bit 10
2024-02-07 12:31:37 +05:00
Alexander Babikov
aef257378e
Add PGE to AMD K5 and K6-2C/III/2+/III+
2024-02-07 12:31:36 +05:00
Alexander Babikov
37cf0b6845
Separate Pentium and Cx6x86 MSR handling
2024-02-07 12:31:35 +05:00
Alexander Babikov
a1540eee92
Remove the machine check CPUID flag from the P24T
2024-02-07 12:31:35 +05:00
Alexander Babikov
032a161c4a
Implement IDT/VIA FCR2 CPUID family/model spoofing
2024-02-07 12:31:34 +05:00
Alexander Babikov
2da7b196ac
Rename unnamed MSR vars to real names where known
2024-02-07 12:31:34 +05:00
OBattler
0a5d25fdde
Memory: Disable _mem_exec in phys() accesses when not using the 486+ interpreter or dynamic recompiler, and write protect support in preparation for the WD76C10 rewrite.
2024-02-02 05:25:40 +01:00
OBattler
9107c2fa25
Added the AOpen AP61 and fixed floppies on the LG IBM 440 FX.
2024-01-24 04:56:31 +01:00
