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add various missing registers

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This commit is contained in:
starfrost013
2025-02-06 00:49:19 +00:00
parent d5393a0575
commit fea8cd649a
4 changed files with 89 additions and 6 deletions
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36
src/include/86box/nv/vid_nv3.h
View File

@@ -362,7 +362,15 @@ extern const device_config_t nv3_config[];
#define NV3_PFB_BOOT_RAM_EXTENSION 5
#define NV3_PFB_BOOT_RAM_EXTENSION_NONE 0x0
#define NV3_PFB_BOOT_RAM_EXTENSION_8MB 0x1
#define NV3_PFB_DELAY 0x100044
#define NV3_PFB_GREEN_0 0x1000C0
#define NV3_PFB_CONFIG_0 0x100200 // Framebuffer interface config register 0
// What is this lol
// ??? Part of the memory timings
#define NV3_PFB_RTL 0x100300
#define NV3_PFB_CONFIG_0_RESOLUTION 0
// 1=40 horiz. resolution
// i assume it can be divided by some kind of divisor to produce the vertical resolution (e.g. 3/2 or multiply by 2/3) to get the final
@@ -487,7 +495,12 @@ extern const device_config_t nv3_config[];
#define NV3_PGRAPH_TRAPPED_DATA 0x4006B8
#define NV3_PGRAPH_TRAPPED_INSTANCE 0x4006BC
#define NV3_PGRAPH_DMA_INTR_0 0x401000 // PGRAPH DMA Interrupt Status
#define NV3_PGRAPH_DMA_INTR_0 0x401100 // PGRAPH DMA Interrupt Status
#define NV3_PGRAPH_DMA_INTR_INSTANCE 0
#define NV3_PGRAPH_DMA_INTR_PRESENT 4
#define NV3_PGRAPH_DMA_INTR_PROTECTION 8
#define NV3_PGRAPH_DMA_INTR_LINEAR 12
#define NV3_PGRAPH_DMA_INTR_NOTIFY 16
#define NV3_PGRAPH_DMA_INTR_EN_0 0x401140 // PGRAPH DMA Interrupt Enable 0
// not sure about the class ids
@@ -559,6 +572,13 @@ extern const device_config_t nv3_config[];
#define NV3_PVIDEO_START 0x680000 // Video Generation / overlay configuration
#define NV3_PVIDEO_INTR 0x680100
#define NV3_PVIDEO_INTR_EN 0x680140
#define NV3_PVIDEO_FIFO_THRESHOLD 0x680238
#define NV3_PVIDEO_FIFO_BURST_LENGTH 0x68023C
#define NV3_PVIDEO_OVERLAY 0x680244
#define NV3_PVIDEO_OVERLAY_VIDEO_IS_ON 0
#define NV3_PVIDEO_OVERLAY_KEY_ENABLED 4
#define NV3_PVIDEO_OVERLAY_FORMAT 8 // 0 = CCIR, 1 = YUY2
#define NV3_PVIDEO_END 0x6802FF
#define NV3_PRAMDAC_START 0x680300
@@ -780,8 +800,11 @@ typedef struct nv3_straps_s
typedef struct nv3_pfb_s
{
uint32_t boot;
uint32_t config_0;
uint32_t config_0; // Framebuffer width, etc.
uint32_t config_1;
uint32_t green;
uint32_t delay;
uint32_t rtl; // Part of the memory timings
} nv3_pfb_t;
#define NV3_RMA_NUM_REGS 4
@@ -974,6 +997,8 @@ typedef struct nv3_pgraph_s
uint32_t interrupt_enable_0; // Interrupt enable 0
uint32_t interrupt_status_1; // Interrupt status 1
uint32_t interrupt_enable_1; // Interrupt enable 1
uint32_t interrupt_status_dma; // Interrupt status for DMA
uint32_t interrupt_enable_dma; // Interrupt enable for DMA
uint32_t context_switch; // TODO: Make this a struct, it's just going to be enormous lol.
nv3_pgraph_context_control_t context_control;
@@ -986,10 +1011,12 @@ typedef struct nv3_pgraph_s
uint32_t abs_uclip_xmax;
uint32_t abs_uclip_ymin;
uint32_t abs_uclip_ymax;
// Canvas stuff
nv3_position_16_bigy_t src_canvas_min;
nv3_position_16_bigy_t src_canvas_max;
nv3_position_16_bigy_t dst_canvas_min;
nv3_position_16_bigy_t dst_canvas_max;
// Pattern stuff
nv3_color_x3a10g10b10_t pattern_color_0_0;
uint32_t pattern_color_0_1; // only 7:0 relevant
nv3_color_x3a10g10b10_t pattern_color_1_0;
@@ -1012,8 +1039,6 @@ typedef struct nv3_pgraph_s
uint32_t trapped_address;
uint32_t trapped_data;
uint32_t trapped_instance;
uint32_t interrupt_status_dma;
uint32_t interrupt_enable_dma;
} nv3_pgraph_t;
// GPU Manufacturing Configuration (again)
@@ -1172,6 +1197,9 @@ typedef struct nv3_pvideo_s
{
uint32_t interrupt_status; // Interrupt status
uint32_t interrupt_enable; // Interrupt enable
uint32_t fifo_threshold; // FIFO threshold
uint32_t fifo_burst_size; // FIFO burst size
uint32_t overlay_settings; // Overlay settings
} nv3_pvideo_t;
typedef struct nv3_pme_s // Mediaport

27
src/video/nv/nv3/subsystems/nv3_pfb.c
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@@ -34,8 +34,11 @@ void nv3_pfb_config0_write(uint32_t val);
nv_register_t pfb_registers[] = {
{ NV3_PFB_BOOT, "PFB Boot Config", NULL, NULL},
{ NV3_PFB_DELAY, "PFB Delay", NULL, NULL},
{ NV3_PFB_GREEN_0, "PFB Green / Power Saving", NULL, NULL,},
{ NV3_PFB_CONFIG_0, "PFB Framebuffer Config 0", nv3_pfb_config0_read, nv3_pfb_config0_write },
{ NV3_PFB_CONFIG_1, "PFB Framebuffer Config 1", NULL, NULL },
{ NV3_PFB_RTL, "PFB RTL (Part of memory timings?)", NULL, NULL },
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
@@ -86,6 +89,16 @@ uint32_t nv3_pfb_read(uint32_t address)
case NV3_PFB_CONFIG_1:
ret = nv3->pfb.config_1;
break;
case NV3_PFB_GREEN_0:
ret = nv3->pfb.green;
break;
case NV3_PFB_DELAY:
ret = nv3->pfb.delay;
break;
case NV3_PFB_RTL:
ret = nv3->pfb.rtl;
break;
}
}
@@ -123,9 +136,19 @@ void nv3_pfb_write(uint32_t address, uint32_t value)
{
switch (reg->address)
{
// Config 0 has a read/write function
// Config 0 has a read/write function
case NV3_PFB_CONFIG_1: // Config Register 1
nv3->pfb.config_1 = value;
break;
case NV3_PFB_GREEN_0:
nv3->pfb.green = value;
break;
case NV3_PFB_DELAY:
nv3->pfb.delay = value;
break;
case NV3_PFB_RTL:
nv3->pfb.rtl = value;
break;
}
}
}
@@ -145,7 +168,7 @@ void nv3_pfb_config0_write(uint32_t val)
uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5;
// i don't think 16:9 is supported
uint32_t new_pfb_vtotal = new_pfb_htotal * (4/3);
uint32_t new_pfb_vtotal = new_pfb_htotal * (4.0/3.0);
uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03;
nv_log("Framebuffer Config Change\n");

9
src/video/nv/nv3/subsystems/nv3_pgraph.c
View File

@@ -332,6 +332,15 @@ void nv3_pgraph_write(uint32_t address, uint32_t value)
nv3->pgraph.interrupt_enable_1 = value & 0x00011111;
nv3_pmc_handle_interrupts(true);
break;
case NV3_PGRAPH_DMA_INTR_0:
nv3->pgraph.interrupt_status_dma &= ~value;
nv3_pmc_clear_interrupts();
break;
case NV3_PGRAPH_DMA_INTR_EN_0:
nv3->pgraph.interrupt_enable_dma = value & 0x000111111;
nv_log("Handling PGRAPH_DMA interrupts not implemented");
nv3_pmc_handle_interrupts(true);
break;
// A lot of this is currently a temporary implementation so that we can just debug what the current state looks like
// during the driver initialisation process

23
src/video/nv/nv3/subsystems/nv3_pvideo.c
View File

@@ -32,6 +32,9 @@
nv_register_t pvideo_registers[] = {
{ NV3_PVIDEO_INTR, "PVIDEO - Interrupt Status", NULL, NULL},
{ NV3_PVIDEO_INTR_EN, "PVIDEO - Interrupt Enable", NULL, NULL,},
{ NV3_PVIDEO_FIFO_THRESHOLD, "PVIDEO - FIFO Fill Threshold", NULL, NULL},
{ NV3_PVIDEO_FIFO_BURST_LENGTH, "PVIDEO - FIFO Burst Length (1=32, 2=64, 3=128)", NULL, NULL},
{ NV3_PVIDEO_OVERLAY, "PVIDEO - Overlay Info (Bit0 = Video On, Bit4 = Key On, Bit8 = Format, 0=CCIR, 1=YUV2)", NULL, NULL },
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
@@ -78,6 +81,16 @@ uint32_t nv3_pvideo_read(uint32_t address)
case NV3_PVIDEO_INTR_EN:
ret = nv3->pvideo.interrupt_enable;
break;
case NV3_PVIDEO_FIFO_THRESHOLD:
ret = nv3->pvideo.fifo_threshold;
break;
case NV3_PVIDEO_FIFO_BURST_LENGTH:
ret = nv3->pvideo.fifo_burst_size & 0x03;
break;
case NV3_PVIDEO_OVERLAY:
ret = nv3->pvideo.overlay_settings & 0xFF;
break;
}
}
@@ -126,6 +139,16 @@ void nv3_pvideo_write(uint32_t address, uint32_t value)
case NV3_PVIDEO_INTR_EN:
nv3->pvideo.interrupt_enable = value & 0x00000001;
break;
case NV3_PVIDEO_FIFO_THRESHOLD:
// only bits 6:3 matter
nv3->pvideo.fifo_threshold = ((value >> 3) & 0x0F) << 3;
break;
case NV3_PVIDEO_FIFO_BURST_LENGTH:
nv3->pvideo.fifo_burst_size = value & 0x03;
break;
case NV3_PVIDEO_OVERLAY:
nv3->pvideo.overlay_settings = value & 0xFF;
break;
}
}
}