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Revert "Merge branch 'feature/machine_and_kb' into master"

Browse Source 
This reverts commit 6604a29d7e, reversing
changes made to 1d7fca0abd.
This commit is contained in:
Daniel Gurney
2021-07-04 18:22:52 +03:00
parent 6604a29d7e
commit f2cd3756dd
77 changed files with 3483 additions and 11882 deletions
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4
src/CMakeLists.txt
View File

@@ -14,8 +14,8 @@
#
# WIN32 marks us as a GUI app on Windows
add_executable(86Box WIN32 86box.c config.c log.c random.c timer.c io.c acpi.c apm.c
dma.c ddma.c nmi.c pic.c pit.c port_6x.c port_92.c ppi.c pci.c mca.c usb.c
add_executable(86Box WIN32 86box.c config.c random.c timer.c io.c acpi.c apm.c
dma.c ddma.c nmi.c pic.c pit.c port_92.c ppi.c pci.c mca.c usb.c
device.c nvr.c nvr_at.c nvr_ps2.c)
if(NEW_DYNAREC)

184
src/acpi.c
View File

@@ -75,15 +75,11 @@ acpi_update_irq(void *priv)
if (sci_level) {
if (dev->irq_mode == 1)
pci_set_irq(dev->slot, dev->irq_pin);
else if (dev->irq_mode == 2)
pci_set_mirq(5, dev->mirq_is_level);
else
pci_set_mirq(0xf0 | dev->irq_line, 1);
} else {
if (dev->irq_mode == 1)
pci_clear_irq(dev->slot, dev->irq_pin);
else if (dev->irq_mode == 2)
pci_clear_mirq(5, dev->mirq_is_level);
else
pci_clear_mirq(0xf0 | dev->irq_line, 1);
}
@@ -91,29 +87,22 @@ acpi_update_irq(void *priv)
static void
acpi_raise_smi(void *priv, int do_smi)
acpi_raise_smi(void *priv)
{
acpi_t *dev = (acpi_t *) priv;
if (dev->regs.glbctl & 0x01) {
if ((dev->vendor == VEN_VIA) || (dev->vendor == VEN_VIA_596B)) {
if ((!dev->regs.smi_lock || !dev->regs.smi_active)) {
if (do_smi)
smi_line = 1;
if ((!dev->regs.smi_lock || !dev->regs.smi_active)) {
smi_line = 1;
dev->regs.smi_active = 1;
}
} else if ((dev->vendor == VEN_INTEL) || (dev->vendor == VEN_ALI)) {
if (do_smi)
smi_line = 1;
smi_line = 1;
/* Clear bit 16 of GLBCTL. */
if (dev->vendor == VEN_INTEL)
dev->regs.glbctl &= ~0x00010000;
else
dev->regs.ali_soft_smi = 1;
} else if (dev->vendor == VEN_SMC) {
if (do_smi)
smi_line = 1;
}
dev->regs.glbctl &= ~0x00010000;
} else if (dev->vendor == VEN_SMC)
smi_line = 1;
}
}
@@ -175,7 +164,8 @@ acpi_reg_read_ali(int size, uint16_t addr, void *p)
shift16 = (addr & 1) << 3;
shift32 = (addr & 3) << 3;
switch(addr) {
switch(addr)
{
case 0x10: case 0x11: case 0x12: case 0x13:
/* PCNTRL - Processor Control Register (IO) */
ret = (dev->regs.pcntrl >> shift16) & 0xff;
@@ -190,33 +180,39 @@ acpi_reg_read_ali(int size, uint16_t addr, void *p)
break;
case 0x18: case 0x19:
/* GPE0_STS - General Purpose Event0 Status Register */
ret = (dev->regs.gpsts >> shift16) & 0xff;
break;
ret = (dev->regs.gpsts >> shift16) & 0xff;
break;
case 0x1a: case 0x1b:
/* GPE0_EN - General Purpose Event0 Enable Register */
ret = (dev->regs.gpen >> shift16) & 0xff;
break;
ret = (dev->regs.gpen >> shift16) & 0xff;
break;
case 0x1d: case 0x1c:
/* GPE1_STS - General Purpose Event1 Status Register */
ret = (dev->regs.gpsts1 >> shift16) & 0xff;
break;
ret = (dev->regs.gpsts >> shift16) & 0xff;
break;
case 0x1f: case 0x1e:
/* GPE1_EN - General Purpose Event1 Enable Register */
ret = (dev->regs.gpen1 >> shift16) & 0xff;
break;
case 0x20 ... 0x27:
ret = (dev->regs.gpen1 >> shift16) & 0xff;
break;
case 0x20:
case 0x21:
case 0x22:
case 0x23:
case 0x24:
case 0x25:
case 0x26:
case 0x27:
/* GPE1_CTL - General Purpose Event1 Control Register */
ret = (dev->regs.gpcntrl >> shift32) & 0xff;
break;
ret = (dev->regs.gpcntrl >> shift32) & 0xff;
break;
case 0x30:
/* PM2_CNTRL - Power Management 2 Control Register( */
ret = dev->regs.pmcntrl;
break;
ret = dev->regs.pmcntrl;
break;
default:
ret = acpi_reg_read_common_regs(size, addr, p);
break;
}
}
#ifdef ENABLE_ACPI_LOG
if (size != 1)
acpi_log("(%i) ACPI Read (%i) %02X: %02X\n", in_smm, size, addr, ret);
@@ -300,7 +296,6 @@ acpi_reg_read_intel(int size, uint16_t addr, void *p)
return ret;
}
static uint32_t
acpi_reg_read_sis(int size, uint16_t addr, void *p)
{
@@ -708,37 +703,44 @@ acpi_reg_write_ali(int size, uint16_t addr, uint8_t val, void *p)
break;
case 0x18: case 0x19:
/* GPE0_STS - General Purpose Event0 Status Register */
dev->regs.gpsts &= ~((val << shift16) & 0x0d07);
break;
dev->regs.gpsts &= ~((val << shift16) & 0x0d07);
break;
case 0x1a: case 0x1b:
/* GPE0_EN - General Purpose Event0 Enable Register */
dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0d07;
break;
dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0d07;
break;
case 0x1d: case 0x1c:
/* GPE1_STS - General Purpose Event1 Status Register */
dev->regs.gpsts1 &= ~((val << shift16) & 0x0c01);
break;
dev->regs.gpsts &= ~((val << shift16) & 0x0c01);
break;
case 0x1f: case 0x1e:
/* GPE1_EN - General Purpose Event1 Enable Register */
dev->regs.gpen1 = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0c01;
break;
case 0x20 ... 0x27:
dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0c01;
break;
case 0x20:
case 0x21:
case 0x22:
case 0x23:
case 0x24:
case 0x25:
case 0x26:
case 0x27:
/* GPE1_CTL - General Purpose Event1 Control Register */
dev->regs.gpcntrl = ((dev->regs.gpcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00000001;
break;
dev->regs.gpcntrl = ((dev->regs.gpcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00000001;
break;
case 0x30:
/* PM2_CNTRL - Power Management 2 Control Register( */
dev->regs.pmcntrl = val & 1;
break;
dev->regs.pmcntrl = val & 1;
break;
default:
acpi_reg_write_common_regs(size, addr, val, p);
/* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
if ((addr == 0x00) && !(dev->regs.pmsts & 0x20))
dev->regs.gpcntrl &= ~0x0002;
dev->regs.glbctl &= ~0x0002;
else if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
dev->regs.gpsts1 |= 0x01;
if (dev->regs.gpen1 & 0x01)
acpi_raise_smi(dev, 1);
dev->regs.glbsts |= 0x01;
if (dev->regs.glben & 0x02)
acpi_raise_smi(dev);
}
}
}
@@ -814,7 +816,7 @@ acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *p)
else if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
dev->regs.glbsts |= 0x01;
if (dev->regs.glben & 0x02)
acpi_raise_smi(dev, 1);
acpi_raise_smi(dev);
}
break;
}
@@ -971,7 +973,7 @@ acpi_reg_write_via_common(int size, uint16_t addr, uint8_t val, void *p)
dev->regs.smicmd = val & 0xff;
dev->regs.glbsts |= 0x40;
if (dev->regs.glben & 0x40)
acpi_raise_smi(dev, 1);
acpi_raise_smi(dev);
}
break;
case 0x30: case 0x31: case 0x32: case 0x33:
@@ -994,7 +996,7 @@ acpi_reg_write_via_common(int size, uint16_t addr, uint8_t val, void *p)
else if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
dev->regs.glbsts |= 0x20;
if (dev->regs.glben & 0x20)
acpi_raise_smi(dev, 1);
acpi_raise_smi(dev);
}
break;
}
@@ -1082,7 +1084,7 @@ acpi_reg_write_smc(int size, uint16_t addr, uint8_t val, void *p)
else if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
dev->regs.glbsts |= 0x01;
if (dev->regs.glben & 0x01)
acpi_raise_smi(dev, 1);
acpi_raise_smi(dev);
}
}
@@ -1474,13 +1476,6 @@ acpi_set_irq_line(acpi_t *dev, int irq_line)
}
void
acpi_set_mirq_is_level(acpi_t *dev, int mirq_is_level)
{
dev->mirq_is_level = mirq_is_level;
}
void
acpi_set_gpireg2_default(acpi_t *dev, uint8_t gpireg2_default)
{
@@ -1496,20 +1491,6 @@ acpi_set_nvr(acpi_t *dev, nvr_t *nvr)
}
uint8_t
acpi_ali_soft_smi_status_read(acpi_t *dev)
{
return dev->regs.ali_soft_smi = 1;
}
void
acpi_ali_soft_smi_status_write(acpi_t *dev, uint8_t soft_smi)
{
dev->regs.ali_soft_smi = soft_smi;
}
static void
acpi_apm_out(uint16_t port, uint8_t val, void *p)
{
@@ -1519,25 +1500,15 @@ acpi_apm_out(uint16_t port, uint8_t val, void *p)
port &= 0x0001;
if (dev->vendor == VEN_ALI) {
if (port == 0x0001) {
acpi_log("ALi SOFT SMI# status set (%i)\n", dev->apm->do_smi);
dev->apm->cmd = val;
// acpi_raise_smi(dev, dev->apm->do_smi);
if (dev->apm->do_smi)
smi_line = 1;
dev->regs.ali_soft_smi = 1;
} else if (port == 0x0003)
dev->apm->stat = val;
} else {
if (port == 0x0000) {
dev->apm->cmd = val;
if (dev->vendor == VEN_INTEL)
if (port == 0x0000) {
dev->apm->cmd = val;
if (dev->apm->do_smi) {
if ((dev->vendor == VEN_INTEL) || (dev->vendor == VEN_ALI))
dev->regs.glbsts |= 0x20;
acpi_raise_smi(dev, dev->apm->do_smi);
} else
dev->apm->stat = val;
}
acpi_raise_smi(dev);
}
} else
dev->apm->stat = val;
}
@@ -1549,17 +1520,10 @@ acpi_apm_in(uint16_t port, void *p)
port &= 0x0001;
if (dev->vendor == VEN_ALI) {
if (port == 0x0001)
ret = dev->apm->cmd;
else if (port == 0x0003)
ret = dev->apm->stat;
} else {
if (port == 0x0000)
ret = dev->apm->cmd;
else
ret = dev->apm->stat;
}
if (port == 0x0000)
ret = dev->apm->cmd;
else
ret = dev->apm->stat;
acpi_log("[%04X:%08X] APM read: %04X = %02X\n", CS, cpu_state.pc, port, ret);
@@ -1652,14 +1616,8 @@ acpi_init(const device_t *info)
dev->irq_line = 9;
if ((dev->vendor == VEN_INTEL) || (dev->vendor == VEN_ALI)) {
if (dev->vendor == VEN_ALI)
dev->irq_mode = 2;
dev->apm = device_add(&apm_pci_acpi_device);
if (dev->vendor == VEN_ALI) {
acpi_log("Setting I/O handler at port B1\n");
io_sethandler(0x00b1, 0x0003, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev);
} else
io_sethandler(0x00b2, 0x0002, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev);
io_sethandler(0x00b2, 0x0002, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev);
} else if (dev->vendor == VEN_VIA) {
dev->i2c = i2c_gpio_init("smbus_vt82c586b");
i2c_smbus = i2c_gpio_get_bus(dev->i2c);

17
src/chipset/CMakeLists.txt
View File

@@ -13,18 +13,25 @@
# Copyright 2020,2021 David Hrdlička.
#
add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c ali1531.c ali1543.c
headland.c intel_82335.c cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c
../ioapic.c neat.c opti283.c opti291.c opti391.c opti495.c opti822.c opti895.c opti5x7.c
scamp.c scat.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c sis_5511.c sis_5571.c
add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c et6000.c headland.c
intel_82335.c cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c ../ioapic.c
neat.c opti283.c opti291.c opti495.c opti822.c opti895.c opti5x7.c scamp.c scat.c
sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c sis_5511.c sis_5571.c sis_5598.c
umc_8886.c umc_8890.c umc_hb4.c
via_vt82c49x.c via_vt82c505.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c
gc100.c stpc.c
via_apollo.c via_pipc.c vl82c480.c wd76c10.c)
via_apollo.c via_pipc.c wd76c10.c
vl82c480.c)
if(I450KX)
target_sources(chipset PRIVATE intel_i450kx.c)
endif()
if(M154X)
target_sources(chipset PRIVATE ali1531.c)
target_sources(chipset PRIVATE ali1543.c)
endif()
if(M6117)
target_sources(chipset PRIVATE ali6117.c)
endif()

369
src/chipset/ali1531.c
View File

@@ -34,7 +34,6 @@
#include <86box/chipset.h>
typedef struct ali1531_t
{
uint8_t pci_conf[256];
@@ -42,287 +41,201 @@ typedef struct ali1531_t
smram_t *smram;
} ali1531_t;
#ifdef ENABLE_ALI1531_LOG
int ali1531_do_log = ENABLE_ALI1531_LOG;
static void
ali1531_log(const char *fmt, ...)
void ali1531_shadow_recalc(int cur_reg, ali1531_t *dev)
{
va_list ap;
for (uint32_t i = 0; i < 8; i++)
mem_set_mem_state_both(0xc0000 + ((cur_reg & 1) << 17) + (i << 14), 0x4000, (((dev->pci_conf[0x4c + (cur_reg & 1)] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4e + (cur_reg & 1)] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
if (ali1531_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
flushmmucache_nopc();
}
#else
#define ali1531_log(fmt, ...)
#endif
static void
ali1531_smram_recalc(uint8_t val, ali1531_t *dev)
void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev)
{
smram_disable_all();
if (val & 1) {
switch (val & 0x0c) {
case 0x00:
ali1531_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02);
break;
case 0x04:
ali1531_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02);
break;
case 0x08:
ali1531_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
break;
}
if (dev->pci_conf[0x48] & 1)
{
switch (smm_state)
{
case 0:
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, 0, 1);
smram_map(1, 0xd0000, 0x10000, 1);
break;
case 1:
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, 1, 1);
smram_map(1, 0xd0000, 0x10000, 1);
break;
case 2:
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, 0, 1);
smram_map(1, 0xa0000, 0x20000, (dev->pci_conf[0x48] & 0x10) ? 2 : 1);
break;
case 3:
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, 1, 1);
smram_map(1, 0xa0000, 0x20000, (dev->pci_conf[0x48] & 0x10) ? 2 : 1);
break;
case 4:
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, 0, 1);
smram_map(1, 0x30000, 0x10000, 1);
break;
case 5:
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, 1, 1);
smram_map(1, 0x30000, 0x10000, 1);
break;
}
}
flushmmucache_nopc();
}
static void
ali1531_shadow_recalc(int cur_reg, ali1531_t *dev)
{
int i, bit, r_reg, w_reg;
uint32_t base, flags = 0;
shadowbios = shadowbios_write = 0;
for (i = 0; i < 16; i++) {
base = 0x000c0000 + (i << 14);
bit = i & 7;
r_reg = 0x4c + (i >> 3);
w_reg = 0x4e + (i >> 3);
flags = (dev->pci_conf[r_reg] & (1 << bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
flags |= ((dev->pci_conf[w_reg] & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY);
if (base >= 0x000e0000) {
if (dev->pci_conf[r_reg] & (1 << bit))
shadowbios |= 1;
if (dev->pci_conf[w_reg] & (1 << bit))
shadowbios_write |= 1;
}
ali1531_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff,
(dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E');
mem_set_mem_state_both(base, 0x00004000, flags);
}
flushmmucache_nopc();
}
static void
ali1531_write(int func, int addr, uint8_t val, void *priv)
{
ali1531_t *dev = (ali1531_t *)priv;
switch (addr) {
case 0x04:
dev->pci_conf[addr] = val;
break;
case 0x05:
dev->pci_conf[addr] = val & 0x01;
break;
switch (addr)
{
case 0x05:
dev->pci_conf[addr] = val & 1;
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0xf8);
break;
case 0x07:
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x0d:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x0d:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x2c: /* Subsystem Vendor ID */
case 0x2d:
case 0x2e:
case 0x2f:
if (dev->pci_conf[0x70] & 0x08)
dev->pci_conf[addr] = val;
break;
case 0x40:
dev->pci_conf[addr] = val & 0xf1;
break;
case 0x40:
dev->pci_conf[addr] = val & 0xf1;
break;
case 0x41:
dev->pci_conf[addr] = val & 0xdf;
break;
case 0x41:
dev->pci_conf[addr] = (val & 0xd6) | 0x08;
break;
case 0x42: /* L2 Cache */
dev->pci_conf[addr] = val & 0xf7;
cpu_cache_ext_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x42: /* L2 Cache */
dev->pci_conf[addr] = val & 0xf7;
cpu_cache_ext_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x43: /* L1 Cache */
dev->pci_conf[addr] = val;
cpu_cache_int_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x43: /* L1 Cache */
dev->pci_conf[addr] = val;
cpu_cache_int_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x47:
dev->pci_conf[addr] = val & 0xfc;
case 0x44:
dev->pci_conf[addr] = val;
break;
case 0x45:
dev->pci_conf[addr] = val;
break;
if (mem_size > 0xe00000)
mem_set_mem_state_both(0xe00000, 0x100000, !(val & 0x20) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
case 0x46:
dev->pci_conf[addr] = val;
break;
if (mem_size > 0xf00000)
mem_set_mem_state_both(0xf00000, 0x100000, !(val & 0x10) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
case 0x47:
dev->pci_conf[addr] = val & 0xfc;
mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
break;
if (mem_size > 0xe00000)
mem_set_mem_state_both(0xe00000, 0x100000, (val & 0x20) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
case 0x48: /* SMRAM */
dev->pci_conf[addr] = val;
ali1531_smm_recalc((val >> 1) & 7, dev);
break;
if (mem_size > 0xf00000)
mem_set_mem_state_both(0xf00000, 0x100000, (val & 0x10) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
case 0x49:
dev->pci_conf[addr] = val & 0x73;
break;
mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
case 0x4c: /* Shadow RAM */
case 0x4d:
case 0x4e:
case 0x4f:
dev->pci_conf[addr] = val;
ali1531_shadow_recalc(addr, dev);
break;
flushmmucache_nopc();
break;
case 0x57: /* H2PO */
dev->pci_conf[addr] = val & 0x60;
if (!(val & 0x20))
outb(0x92, 0x01);
break;
case 0x48: /* SMRAM */
dev->pci_conf[addr] = val;
ali1531_smram_recalc(val, dev);
break;
case 0x58:
dev->pci_conf[addr] = val & 0x83;
break;
case 0x49:
dev->pci_conf[addr] = val & 0x73;
break;
case 0x5b:
dev->pci_conf[addr] = val & 0x4f;
break;
case 0x4a:
dev->pci_conf[addr] = val;
break;
case 0x5d:
dev->pci_conf[addr] = val & 0x53;
break;
case 0x4c ... 0x4f: /* Shadow RAM */
dev->pci_conf[addr] = val;
ali1531_shadow_recalc(val, dev);
break;
case 0x5f:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x50: case 0x51: case 0x52: case 0x54:
case 0x55: case 0x56:
dev->pci_conf[addr] = val;
break;
case 0x57: /* H2PO */
dev->pci_conf[addr] = val & 0x60;
/* Find where the Shut-down Special cycle is initiated. */
// if (!(val & 0x20))
// outb(0x92, 0x01);
break;
case 0x58:
dev->pci_conf[addr] = val & 0x86;
break;
case 0x59: case 0x5a:
case 0x5c:
dev->pci_conf[addr] = val;
break;
case 0x5b:
dev->pci_conf[addr] = val & 0x4f;
break;
case 0x5d:
dev->pci_conf[addr] = val & 0x53;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x60: /* DRB's */
case 0x62:
case 0x64:
case 0x66:
case 0x68:
case 0x6a:
case 0x6c:
case 0x6e:
dev->pci_conf[addr] = val;
spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1);
break;
case 0x60: /* DRB's */
case 0x61:
case 0x62:
case 0x63:
case 0x64:
case 0x65:
case 0x66:
case 0x67:
case 0x68:
case 0x69:
case 0x6a:
case 0x6b:
case 0x6c:
case 0x6d:
case 0x6e:
case 0x6f:
dev->pci_conf[addr] = val;
break;
dev->pci_conf[addr] = val;
spd_write_drbs(dev->pci_conf, 0x60, 0x6f, 1);
break;
case 0x70: case 0x71:
dev->pci_conf[addr] = val;
break;
case 0x72:
dev->pci_conf[addr] = val & 0xf;
break;
case 0x72:
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x74:
dev->pci_conf[addr] = val & 0x2b;
break;
case 0x74:
dev->pci_conf[addr] = val & 0x2b;
break;
case 0x80:
dev->pci_conf[addr] = val & 0x84;
break;
case 0x76: case 0x77:
dev->pci_conf[addr] = val;
break;
case 0x81:
dev->pci_conf[addr] = val & 0x81;
break;
case 0x80:
dev->pci_conf[addr] = val & 0x84;
break;
case 0x83:
dev->pci_conf[addr] = val & 0x10;
break;
case 0x81:
dev->pci_conf[addr] = val & 0x81;
break;
case 0x83:
dev->pci_conf[addr] = val & 0x10;
break;
default:
dev->pci_conf[addr] = val;
break;
}
}
static uint8_t
ali1531_read(int func, int addr, void *priv)
{
ali1531_t *dev = (ali1531_t *)priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
return ret;
return dev->pci_conf[addr];
}
static void
ali1531_reset(void *priv)
{
ali1531_t *dev = (ali1531_t *)priv;
int i;
/* Default Registers */
dev->pci_conf[0x00] = 0xb9;
@@ -354,20 +267,11 @@ ali1531_reset(void *priv)
ali1531_write(0, 0x42, 0x00, dev);
ali1531_write(0, 0x43, 0x00, dev);
ali1531_write(0, 0x47, 0x00, dev);
ali1531_write(0, 0x48, 0x00, dev);
for (i = 0; i < 4; i++)
ali1531_write(0, 0x4c + i, 0x00, dev);
for (i = 0; i < 16; i += 2) {
ali1531_write(0, 0x60 + i, 0x08, dev);
ali1531_write(0, 0x61 + i, 0x40, dev);
}
ali1531_write(0, 0x60, 0x08, dev);
ali1531_write(0, 0x61, 0x40, dev);
}
static void
ali1531_close(void *priv)
{
@@ -377,7 +281,6 @@ ali1531_close(void *priv)
free(dev);
}
static void *
ali1531_init(const device_t *info)
{
@@ -393,7 +296,6 @@ ali1531_init(const device_t *info)
return dev;
}
const device_t ali1531_device = {
"ALi M1531 CPU-to-PCI Bridge",
DEVICE_PCI,
@@ -404,5 +306,4 @@ const device_t ali1531_device = {
{NULL},
NULL,
NULL,
NULL
};
NULL};

1936
src/chipset/ali1543.c
View File

File diff suppressed because it is too large Load Diff

226
src/chipset/opti391.c
View File

@@ -1,226 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C391/392 chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/chipset.h>
#ifdef ENABLE_OPTI391_LOG
int opti391_do_log = ENABLE_OPTI391_LOG;
static void
opti391_log(const char *fmt, ...)
{
va_list ap;
if (opti391_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define opti391_log(fmt, ...)
#endif
typedef struct
{
uint32_t phys, virt;
} mem_remapping_t;
typedef struct
{
uint8_t index, regs[256];
} opti391_t;
static void
opti391_shadow_recalc(opti391_t *dev)
{
uint32_t i, base;
uint8_t sh_enable, sh_master;
uint8_t sh_wp, sh_write_internal;
shadowbios = shadowbios_write = 0;
/* F0000-FFFFF */
sh_enable = !(dev->regs[0x22] & 0x80);
if (sh_enable)
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
sh_write_internal = (dev->regs[0x26] & 0x40);
/* D0000-EFFFF */
for (i = 0; i < 8; i++) {
base = 0xd0000 + (i << 14);
if (base >= 0xe0000) {
sh_master = (dev->regs[0x22] & 0x40);
sh_wp = (dev->regs[0x22] & 0x10);
} else {
sh_master = (dev->regs[0x22] & 0x20);
sh_wp = (dev->regs[0x22] & 0x08);
}
sh_enable = dev->regs[0x23] & (1 << i);
if (sh_master) {
if (sh_enable) {
if (sh_wp)
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
} else if (sh_write_internal)
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
} else if (sh_write_internal)
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
/* C0000-CFFFF */
sh_master = !(dev->regs[0x26] & 0x10);
sh_wp = (dev->regs[0x26] & 0x20);
for (i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
sh_enable = dev->regs[0x26] & (1 << i);
if (sh_master) {
if (sh_enable) {
if (sh_wp)
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
} else if (sh_write_internal)
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
} else if (sh_write_internal)
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
}
static void
opti391_write(uint16_t addr, uint8_t val, void *priv)
{
opti391_t *dev = (opti391_t *)priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x24:
opti391_log("OPTi 391: dev->regs[%02x] = %02x\n", dev->index, val);
switch (dev->index) {
case 0x20:
dev->regs[dev->index] = (dev->regs[dev->index] & 0xc0) | (val & 0x3f);
break;
case 0x21: case 0x24: case 0x25: case 0x27:
case 0x28: case 0x29: case 0x2a: case 0x2b:
dev->regs[dev->index] = val;
break;
case 0x22: case 0x23:
case 0x26:
dev->regs[dev->index] = val;
opti391_shadow_recalc(dev);
break;
}
break;
}
}
static uint8_t
opti391_read(uint16_t addr, void *priv)
{
opti391_t *dev = (opti391_t *)priv;
uint8_t ret = 0xff;
if (addr == 0x24)
ret = dev->regs[dev->index];
return ret;
}
static void
opti391_close(void *priv)
{
opti391_t *dev = (opti391_t *)priv;
free(dev);
}
static void *
opti391_init(const device_t *info)
{
opti391_t *dev = (opti391_t *)malloc(sizeof(opti391_t));
memset(dev, 0x00, sizeof(opti391_t));
io_sethandler(0x0022, 0x0001, opti391_read, NULL, NULL, opti391_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti391_read, NULL, NULL, opti391_write, NULL, NULL, dev);
dev->regs[0x21] = 0x84;
dev->regs[0x24] = 0x07;
dev->regs[0x25] = 0xf0;
dev->regs[0x26] = 0x30;
dev->regs[0x27] = 0x91;
dev->regs[0x28] = 0x80;
dev->regs[0x29] = 0x10;
dev->regs[0x2a] = 0x80;
dev->regs[0x2b] = 0x10;
opti391_shadow_recalc(dev);
return dev;
}
const device_t opti391_device = {
"OPTi 82C391",
0,
0,
opti391_init,
opti391_close,
NULL,
{ NULL },
NULL,
NULL,
NULL
};

32
src/chipset/opti895.c
View File

@@ -43,7 +43,6 @@ typedef struct
} opti895_t;
#define ENABLE_OPTI895_LOG 1
#ifdef ENABLE_OPTI895_LOG
int opti895_do_log = ENABLE_OPTI895_LOG;
@@ -92,15 +91,11 @@ opti895_recalc(opti895_t *dev)
shflags = MEM_READ_INTERNAL;
shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else {
shflags = (dev->regs[0x2d] & (1 << ((i >> 1) + 2))) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
if (dev->regs[0x26] & 0x40)
if (dev->regs[0x26] & 0x40) {
shflags = MEM_READ_EXTANY;
shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
else {
if (dev->regs[0x26] & 0x80)
shflags |= (dev->regs[0x2d] & (1 << ((i >> 1) + 2))) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
else
shflags |= MEM_WRITE_EXTERNAL;
}
} else
shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
}
mem_set_mem_state_both(base, 0x4000, shflags);
@@ -113,21 +108,17 @@ opti895_recalc(opti895_t *dev)
shflags = MEM_READ_INTERNAL;
shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else {
shflags = (dev->regs[0x2d] & (1 << (i >> 1))) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
if (dev->regs[0x26] & 0x40)
if (dev->regs[0x26] & 0x40) {
shflags = MEM_READ_EXTANY;
shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
else {
if (dev->regs[0x26] & 0x80)
shflags |= (dev->regs[0x2d] & (1 << (i >> 1))) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
else
shflags |= MEM_WRITE_EXTERNAL;
}
} else
shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
}
mem_set_mem_state_both(base, 0x4000, shflags);
}
flushmmucache_nopc();
flushmmucache();
}
@@ -147,7 +138,7 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
}
break;
case 0x24:
if (((dev->idx >= 0x20) && (dev->idx <= 0x2f)) ||
if (((dev->idx >= 0x20) && (dev->idx <= 0x2c)) ||
((dev->idx >= 0xe0) && (dev->idx <= 0xef))) {
dev->regs[dev->idx] = val;
opti895_log("dev->regs[%04x] = %08x\n", dev->idx, val);
@@ -161,7 +152,6 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
case 0x22:
case 0x23:
case 0x26:
case 0x2d:
opti895_recalc(dev);
break;
@@ -205,7 +195,7 @@ opti895_read(uint16_t addr, void *priv)
ret = dev->regs[dev->idx];
break;
case 0x24:
if (((dev->idx >= 0x20) && (dev->idx <= 0x2f)) ||
if (((dev->idx >= 0x20) && (dev->idx <= 0x2c)) ||
((dev->idx >= 0xe0) && (dev->idx <= 0xef))) {
ret = dev->regs[dev->idx];
if (dev->idx == 0xe0)

23
src/chipset/vl82c480.c
View File

@@ -98,18 +98,9 @@ vl82c480_write(uint16_t addr, uint8_t val, void *p)
default:
dev->regs[dev->idx] = val;
break;
case 0x04:
if (dev->regs[0x00] == 0x98)
dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x08) | (val & 0xf7);
else
dev->regs[dev->idx] = val;
break;
case 0x05:
dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x10) | (val & 0xef);
break;
case 0x07:
dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x40) | (val & 0xbf);
break;
case 0x0d: case 0x0e: case 0x0f: case 0x10:
case 0x11: case 0x12:
dev->regs[dev->idx] = val;
@@ -172,13 +163,11 @@ vl82c480_init(const device_t *info)
vl82c480_t *dev = (vl82c480_t *)malloc(sizeof(vl82c480_t));
memset(dev, 0, sizeof(vl82c480_t));
dev->regs[0x00] = info->local;
dev->regs[0x00] = 0x90;
dev->regs[0x01] = 0xff;
dev->regs[0x02] = 0x8a;
dev->regs[0x03] = 0x88;
dev->regs[0x06] = 0x1b;
if (info->local == 0x98)
dev->regs[0x07] = 0x21;
dev->regs[0x08] = 0x38;
io_sethandler(0x00ec, 0x0004, vl82c480_read, NULL, NULL, vl82c480_write, NULL, NULL, dev);
@@ -192,17 +181,7 @@ vl82c480_init(const device_t *info)
const device_t vl82c480_device = {
"VLSI VL82c480",
0,
0x90,
vl82c480_init, vl82c480_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t vl82c486_device = {
"VLSI VL82c486",
0,
0x98,
vl82c480_init, vl82c480_close, NULL,
{ NULL }, NULL, NULL,
NULL

20
src/config.c
View File

@@ -583,26 +583,20 @@ load_machine(void)
machine = machine_get_machine_from_internal_name("pc916sx");
else if (! strcmp(p, "cbm_sl386sx16"))
machine = machine_get_machine_from_internal_name("cmdsl386sx16");
else if (! strcmp(p, "olivetti_m300_08"))
machine = machine_get_machine_from_internal_name("m30008");
else if (! strcmp(p, "olivetti_m300_15"))
machine = machine_get_machine_from_internal_name("m30015");
else if (! strcmp(p, "cbm_sl386sx25"))
machine = machine_get_machine_from_internal_name("cmdsl386sx25");
else if (! strcmp(p, "award386dx")) /* ...merged machines... */
machine = machine_get_machine_from_internal_name("award495");
machine = machine_get_machine_from_internal_name("award486");
else if (! strcmp(p, "ami386dx"))
machine = machine_get_machine_from_internal_name("ami495");
machine = machine_get_machine_from_internal_name("ami486");
else if (! strcmp(p, "mr386dx"))
machine = machine_get_machine_from_internal_name("mr495");
else if (! strcmp(p, "award486"))
machine = machine_get_machine_from_internal_name("award495");
else if (! strcmp(p, "ami486"))
machine = machine_get_machine_from_internal_name("ami495");
else if (! strcmp(p, "mr486"))
machine = machine_get_machine_from_internal_name("mr495");
machine = machine_get_machine_from_internal_name("mr486");
else if (! strcmp(p, "fw6400gx_s1"))
machine = machine_get_machine_from_internal_name("fw6400gx");
else if (! strcmp(p, "p54vl"))
machine = machine_get_machine_from_internal_name("p5vl");
else if (! strcmp(p, "chariot"))
machine = machine_get_machine_from_internal_name("fmb");
else if (! strcmp(p, "president")) { /* ...and removed machines */
machine = machine_get_machine_from_internal_name("mb500n");
migrate_from = NULL;

8
src/cpu/386_ops.h
View File

@@ -641,7 +641,7 @@ const OpFn OP_TABLE(c486_0f)[1024] =
/*00*/ op0F00_a16, op0F01_w_a16, opLAR_w_a16, opLSL_w_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, opRDTSC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -663,7 +663,7 @@ const OpFn OP_TABLE(c486_0f)[1024] =
/*00*/ op0F00_a16, op0F01_l_a16, opLAR_l_a16, opLSL_l_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, opRDTSC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opSMINT, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opSMINT, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -685,7 +685,7 @@ const OpFn OP_TABLE(c486_0f)[1024] =
/*00*/ op0F00_a32, op0F01_w_a32, opLAR_w_a32, opLSL_w_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, opRDTSC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
@@ -707,7 +707,7 @@ const OpFn OP_TABLE(c486_0f)[1024] =
/*00*/ op0F00_a32, op0F01_l_a32, opLAR_l_a32, opLSL_l_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, opRDTSC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,

11
src/cpu/x86.c
View File

@@ -26,7 +26,6 @@
#include "cpu.h"
#include "x86.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
@@ -240,10 +239,8 @@ reset_common(int hard)
leave_smm();
/* Needed for the ALi M1533. */
if (soft_reset_pci && !hard) {
if (soft_reset_pci && !hard)
pci_reset();
device_reset_all_pci();
}
use32 = 0;
cpu_cur_status = 0;
@@ -267,7 +264,7 @@ reset_common(int hard)
} else {
loadcs(0xFFFF);
cpu_state.pc = 0;
rammask = is286 ? 0xffffff : 0xfffff;
rammask = 0xfffff;
}
}
idt.base = 0;
@@ -310,10 +307,8 @@ reset_common(int hard)
shadowbios = shadowbios_write = 0;
alt_access = cpu_end_block_after_ins = 0;
if (hard) {
if (hard)
reset_on_hlt = hlt_reset_pending = 0;
soft_reset_pci = 0;
}
if (!is286)
reset_808x(hard);

2
src/cpu/x86_ops_msr.h
View File

@@ -1,13 +1,11 @@
static int opRDTSC(uint32_t fetchdat)
{
#if 0
if (!cpu_has_feature(CPU_FEATURE_RDTSC))
{
cpu_state.pc = cpu_state.oldpc;
x86illegal();
return 1;
}
#endif
if ((cr4 & CR4_TSD) && CPL)
{
x86gpf("RDTSC when TSD set and CPL != 0", 0);

2324
src/device/kbc_at.c
View File

File diff suppressed because it is too large Load Diff

1162
src/device/kbd_at.c
View File

File diff suppressed because it is too large Load Diff

2786
src/device/keyboard_at.c
View File

File diff suppressed because it is too large Load Diff

236
src/device/keyboard_xt.c
View File

@@ -591,18 +591,20 @@ kbd_read(uint16_t port, void *priv)
case 0x62:
if (kbd->type == 0)
ret = 0x00;
else if (kbd->type == 1) {
else if (kbd->type == 1) {
if (kbd->pb & 0x04)
ret = ((mem_size - 64) / 32) & 0x0f;
ret = ((mem_size-64) / 32) & 0x0f;
else
ret = ((mem_size - 64) / 32) >> 4;
} else if (kbd->type == 8 || kbd->type == 9) {
/* Olivetti M19 or Zenith Data Systems Z-151 */
if (kbd->pb & 0x04)
ret = ((mem_size-64) / 32) >> 4;
}
else if (kbd->type == 8 || kbd->type == 9) {
/* Olivetti M19 or Zenith Data Systems Z-151 */
if (kbd->pb & 0x04)
ret = kbd->pd & 0xbf;
else
ret = kbd->pd >> 4;
} else {
else
ret = kbd->pd >> 4;
}
else {
if (kbd->pb & 0x08)
ret = kbd->pd >> 4;
else {
@@ -630,6 +632,7 @@ kbd_read(uint16_t port, void *priv)
case 0x63:
if ((kbd->type == 2) || (kbd->type == 3) || (kbd->type == 4) || (kbd->type == 6))
ret = kbd->pd;
break;
}
@@ -679,116 +682,119 @@ kbd_init(const device_t *info)
video_reset(gfxcard);
if ((kbd->type <= 3) || (kbd->type == 4) || (kbd->type == 6)) {
if (kbd->type <= 3 || kbd-> type == 8) {
/* DIP switch readout: bit set = OFF, clear = ON. */
if (kbd->type == 8)
/* Olivetti M19
* Jumpers J1, J2 - monitor type.
* 01 - mono (high-res)
* 10 - color (low-res, disables 640x400x2 mode)
* 00 - autoswitching
*/
kbd->pd |= 0x00;
else
/* Switches 7, 8 - floppy drives. */
kbd->pd = get_fdd_switch_settings();
if (kbd->type != 8)
/* Switches 7, 8 - floppy drives. */
kbd->pd = get_fdd_switch_settings();
else
/* Olivetti M19
* Jumpers J1, J2 - monitor type.
* 01 - mono (high-res)
* 10 - color (low-res, disables 640x400x2 mode)
* 00 - autoswitching
*/
kbd->pd |= 0x00;
kbd->pd |= get_videomode_switch_settings();
/* Switches 3, 4 - memory size. */
// Note to Compaq/Toshiba keyboard maintainers: type 4 and 6 will never be activated in this block
// Should the top if be closed right after setting floppy drive count?
if ((kbd->type == 3) || (kbd->type == 4) || (kbd->type == 6)) {
switch (mem_size) {
case 256:
kbd->pd |= 0x00;
break;
case 512:
kbd->pd |= 0x04;
break;
case 576:
kbd->pd |= 0x08;
break;
case 640:
default:
kbd->pd |= 0x0c;
break;
}
} else if (kbd->type >= 1) {
switch (mem_size) {
case 64:
kbd->pd |= 0x00;
break;
case 128:
kbd->pd |= 0x04;
break;
case 192:
kbd->pd |= 0x08;
break;
case 256:
default:
kbd->pd |= 0x0c;
break;
}
} else {
switch (mem_size) {
case 16:
kbd->pd |= 0x00;
break;
case 32:
kbd->pd |= 0x04;
break;
case 48:
kbd->pd |= 0x08;
break;
case 64:
default:
kbd->pd |= 0x0c;
break;
}
}
kbd->pd |= get_videomode_switch_settings();
/* Switch 2 - 8087 FPU. */
if (hasfpu)
kbd->pd |= 0x02;
/* Switches 3, 4 - memory size. */
if ((kbd->type == 3) || (kbd->type == 4) || (kbd->type == 6)) {
switch (mem_size) {
case 256:
kbd->pd |= 0x00;
break;
case 512:
kbd->pd |= 0x04;
break;
case 576:
kbd->pd |= 0x08;
break;
case 640:
default:
kbd->pd |= 0x0c;
break;
}
} else if (kbd->type >= 1) {
switch (mem_size) {
case 64:
kbd->pd |= 0x00;
break;
case 128:
kbd->pd |= 0x04;
break;
case 192:
kbd->pd |= 0x08;
break;
case 256:
default:
kbd->pd |= 0x0c;
break;
}
} else {
switch (mem_size) {
case 16:
kbd->pd |= 0x00;
break;
case 32:
kbd->pd |= 0x04;
break;
case 48:
kbd->pd |= 0x08;
break;
case 64:
default:
kbd->pd |= 0x0c;
break;
}
}
/* Switch 2 - 8087 FPU. */
if (hasfpu)
kbd->pd |= 0x02;
/* Switch 1 - always off. */
kbd->pd |= 0x01;
/* Switch 1 - always off. */
kbd->pd |= 0x01;
} else if (kbd-> type == 9) {
/* Zenith Data Systems Z-151
* SW2 switch settings:
* bit 7: monitor frequency
* bits 5-6: autoboot (00-11 resident monitor, 10 hdd, 01 fdd)
* bits 0-4: installed memory
*/
kbd->pd = 0x20;
switch (mem_size) {
case 128:
kbd->pd |= 0x02;
break;
case 192:
kbd->pd |= 0x04;
break;
case 256:
kbd->pd |= 0x06;
break;
case 320:
kbd->pd |= 0x08;
break;
case 384:
kbd->pd |= 0x0a;
break;
case 448:
kbd->pd |= 0x0c;
break;
case 512:
kbd->pd |= 0x0e;
break;
case 576:
kbd->pd |= 0x10;
break;
case 640:
default:
kbd->pd |= 0x12;
break;
/* Zenith Data Systems Z-151
* SW2 switch settings:
* bit 7: monitor frequency
* bits 5-6: autoboot (00-11 resident monitor, 10 hdd, 01 fdd)
* bits 0-4: installed memory
*/
kbd->pd = 0x20;
switch (mem_size) {
case 128:
kbd->pd |= 0x02;
break;
case 192:
kbd->pd |= 0x04;
break;
case 256:
kbd->pd |= 0x02|0x04;
break;
case 320:
kbd->pd |= 0x08;
break;
case 384:
kbd->pd |= 0x02|0x08;
break;
case 448:
kbd->pd |= 0x04|0x08;
break;
case 512:
kbd->pd |= 0x02|0x04|0x08;
break;
case 576:
kbd->pd |= 0x10;
break;
case 640:
default:
kbd->pd |= 0x02|0x10;
break;
}
}

61
src/device/mouse_ps2.c
View File

@@ -93,27 +93,22 @@ ps2_write(uint8_t val, void *priv)
mouse_t *dev = (mouse_t *)priv;
uint8_t temp;
pclog("ps2_write(%02X)\n", val);
if (dev->flags & FLAG_CTRLDAT) {
dev->flags &= ~FLAG_CTRLDAT;
if (val == 0xff)
goto mouse_reset;
switch (dev->command) {
case 0xe8: /* set mouse resolution */
dev->resolution = val;
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse(0xfa);
break;
case 0xf3: /* set sample rate */
dev->sample_rate = val;
keyboard_at_adddata_mouse_cmd(0xfa); /* Command response */
keyboard_at_adddata_mouse(0xfa); /* Command response */
break;
default:
keyboard_at_adddata_mouse_cmd(0xfc);
keyboard_at_adddata_mouse(0xfc);
}
} else {
dev->command = val;
@@ -121,21 +116,21 @@ ps2_write(uint8_t val, void *priv)
switch (dev->command) {
case 0xe6: /* set scaling to 1:1 */
dev->flags &= ~FLAG_SCALED;
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse(0xfa);
break;
case 0xe7: /* set scaling to 2:1 */
dev->flags |= FLAG_SCALED;
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse(0xfa);
break;
case 0xe8: /* set mouse resolution */
dev->flags |= FLAG_CTRLDAT;
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse(0xfa);
break;
case 0xe9: /* status request */
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse(0xfa);
temp = (dev->flags & 0x30);
if (mouse_buttons & 0x01)
temp |= 0x01;
@@ -143,13 +138,13 @@ ps2_write(uint8_t val, void *priv)
temp |= 0x02;
if (mouse_buttons & 0x04)
temp |= 0x03;
keyboard_at_adddata_mouse_cmd(temp);
keyboard_at_adddata_mouse_cmd(dev->resolution);
keyboard_at_adddata_mouse_cmd(dev->sample_rate);
keyboard_at_adddata_mouse(temp);
keyboard_at_adddata_mouse(dev->resolution);
keyboard_at_adddata_mouse(dev->sample_rate);
break;
case 0xeb: /* Get mouse data */
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse(0xfa);
temp = 0;
if (dev->x < 0)
@@ -162,51 +157,50 @@ ps2_write(uint8_t val, void *priv)
temp |= 2;
if ((mouse_buttons & 4) && (dev->flags & FLAG_INTELLI))
temp |= 4;
keyboard_at_adddata_mouse_cmd(temp);
keyboard_at_adddata_mouse_cmd(dev->x & 0xff);
keyboard_at_adddata_mouse_cmd(dev->y & 0xff);
keyboard_at_adddata_mouse(temp);
keyboard_at_adddata_mouse(dev->x & 0xff);
keyboard_at_adddata_mouse(dev->y & 0xff);
if (dev->flags & FLAG_INTMODE)
keyboard_at_adddata_mouse_cmd(dev->z);
keyboard_at_adddata_mouse(dev->z);
break;
case 0xf2: /* read ID */
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse(0xfa);
if (dev->flags & FLAG_INTMODE)
keyboard_at_adddata_mouse_cmd(0x03);
keyboard_at_adddata_mouse(0x03);
else
keyboard_at_adddata_mouse_cmd(0x00);
keyboard_at_adddata_mouse(0x00);
break;
case 0xf3: /* set command mode */
dev->flags |= FLAG_CTRLDAT;
keyboard_at_adddata_mouse_cmd(0xfa); /* ACK for command byte */
keyboard_at_adddata_mouse(0xfa); /* ACK for command byte */
break;
case 0xf4: /* enable */
dev->flags |= FLAG_ENABLED;
mouse_scan = 1;
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse(0xfa);
break;
case 0xf5: /* disable */
dev->flags &= ~FLAG_ENABLED;
mouse_scan = 0;
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse(0xfa);
break;
case 0xff: /* reset */
mouse_reset:
dev->mode = MODE_STREAM;
dev->flags &= 0x88;
mouse_scan = 1;
mouse_scan = 0;
keyboard_at_mouse_reset();
keyboard_at_adddata_mouse_cmd(0xfa);
keyboard_at_adddata_mouse_cmd(0xaa);
keyboard_at_adddata_mouse_cmd(0x00);
keyboard_at_adddata_mouse(0xfa);
keyboard_at_adddata_mouse(0xaa);
keyboard_at_adddata_mouse(0x00);
break;
default:
keyboard_at_adddata_mouse_cmd(0xfe);
keyboard_at_adddata_mouse(0xfe);
}
}
@@ -238,9 +232,6 @@ ps2_poll(int x, int y, int z, int b, void *priv)
return(0xff);
#endif
if ((keyboard_at_fixed_channel() & 0xf00) == 0x200)
return(0xff);
if (!mouse_scan)
return(0xff);

59
src/disk/hdc_ide.c
View File

@@ -916,14 +916,13 @@ ide_atapi_attach(ide_t *ide)
void
ide_set_callback(ide_t *ide, double callback)
{
ide_log("ide_set_callback(%i)\n", ide->channel);
if (!ide) {
ide_log("ide_set_callback(NULL): Set callback failed\n");
ide_log("Set callback failed\n");
return;
}
ide_log("ide_set_callback(%i)\n", ide->channel);
if (callback == 0.0)
timer_stop(&ide->timer);
else
@@ -2501,60 +2500,6 @@ id_not_found:
}
uint8_t
ide_read_ali_75(void)
{
ide_t *ide0, *ide1;
int ch0, ch1;
uint8_t ret = 0x00;
ch0 = ide_boards[0]->cur_dev;
ch1 = ide_boards[1]->cur_dev;
ide0 = ide_drives[ch0];
ide1 = ide_drives[ch1];
if (ch1)
ret |= 0x08;
if (ch0)
ret |= 0x04;
if (ide1->irqstat)
ret |= 0x02;
if (ide0->irqstat)
ret |= 0x01;
return ret;
}
uint8_t
ide_read_ali_76(void)
{
ide_t *ide0, *ide1;
int ch0, ch1;
uint8_t ret = 0x00;
ch0 = ide_boards[0]->cur_dev;
ch1 = ide_boards[1]->cur_dev;
ide0 = ide_drives[ch0];
ide1 = ide_drives[ch1];
if (ide1->atastat & BSY_STAT)
ret |= 0x40;
if (ide1->atastat & DRQ_STAT)
ret |= 0x20;
if (ide1->atastat & ERR_STAT)
ret |= 0x10;
if (ide0->atastat & BSY_STAT)
ret |= 0x04;
if (ide0->atastat & DRQ_STAT)
ret |= 0x02;
if (ide0->atastat & ERR_STAT)
ret |= 0x01;
return ret;
}
static void
ide_set_handlers(uint8_t board)
{

97
src/disk/hdc_ide_sff8038i.c
View File

@@ -370,49 +370,30 @@ void
sff_bus_master_set_irq(int channel, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
dev->status &= ~0x04;
dev->status &= ~4;
dev->status |= (channel >> 4);
channel &= 0x01;
switch (dev->irq_mode[channel]) {
case 0:
default:
/* Legacy IRQ mode. */
if (dev->status & 0x04)
picint(1 << (14 + channel));
else
picintc(1 << (14 + channel));
break;
case 1:
/* Native PCI IRQ mode with interrupt pin. */
if (dev->status & 0x04)
pci_set_irq(dev->slot, dev->irq_pin);
else
pci_clear_irq(dev->slot, dev->irq_pin);
break;
case 2:
case 5:
/* MIRQ 0 or 1. */
if (dev->status & 0x04)
pci_set_mirq(dev->irq_mode[channel] & 1, 0);
else
pci_clear_mirq(dev->irq_mode[channel] & 1, 0);
break;
case 3:
/* Native PCI IRQ mode with specified interrupt line. */
if (dev->status & 0x04)
picintlevel(1 << dev->irq_line);
else
picintc(1 << dev->irq_line);
break;
case 4:
/* ALi Aladdin Native PCI INTAJ mode. */
if (dev->status & 0x04)
pci_set_mirq(channel + 2, dev->irq_level[channel]);
else
pci_clear_mirq(channel + 2, dev->irq_level[channel]);
break;
if (dev->status & 0x04) {
sff_log("SFF8038i: Channel %i IRQ raise\n", channel);
if (dev->irq_mode[channel] == 3)
picintlevel(1 << dev->irq_line);
else if ((dev->irq_mode[channel] == 2) && channel && pci_use_mirq(0))
pci_set_mirq(0, 0);
else if (dev->irq_mode[channel] == 1)
pci_set_irq(dev->slot, dev->irq_pin);
else
picint(1 << (14 + channel));
} else {
sff_log("SFF8038i: Channel %i IRQ lower\n", channel);
if (dev->irq_mode[channel] == 3)
picintc(1 << dev->irq_line);
else if ((dev->irq_mode[channel] == 2) && channel && pci_use_mirq(0))
pci_clear_mirq(0, 0);
else if (dev->irq_mode[channel] == 1)
pci_clear_irq(dev->slot, dev->irq_pin);
else
picintc(1 << (14 + channel));
}
}
@@ -485,42 +466,10 @@ sff_set_irq_line(sff8038i_t *dev, int irq_line)
}
void
sff_set_irq_level(sff8038i_t *dev, int channel, int irq_level)
{
dev->irq_level[channel] = 0;
}
void
sff_set_irq_mode(sff8038i_t *dev, int channel, int irq_mode)
{
dev->irq_mode[channel] = irq_mode;
switch (dev->irq_mode[channel]) {
case 0:
default:
/* Legacy IRQ mode. */
sff_log("[%08X] Setting channel %i to legacy IRQ %i\n", dev, channel, 14 + channel);
break;
case 1:
/* Native PCI IRQ mode with interrupt pin. */
sff_log("[%08X] Setting channel %i to native PCI INT%c\n", dev, channel, '@' + dev->irq_pin);
break;
case 2:
case 5:
/* MIRQ 0 or 1. */
sff_log("[%08X] Setting channel %i to PCI MIRQ%i\n", dev, channel, irq_mode & 1);
break;
case 3:
/* Native PCI IRQ mode with specified interrupt line. */
sff_log("[%08X] Setting channel %i to native PCI IRQ %i\n", dev, channel, dev->irq_line);
break;
case 4:
/* ALi Aladdin Native PCI INTAJ mode. */
sff_log("[%08X] Setting channel %i to INT%cJ\n", dev, channel, 'A' + channel);
break;
}
}
@@ -557,11 +506,9 @@ static void
ide_set_bus_master(next_id, sff_bus_master_dma, sff_bus_master_set_irq, dev);
dev->slot = 7;
dev->irq_mode[0] = 0; /* Channel 0 goes to IRQ 14. */
dev->irq_mode[1] = 2; /* Channel 1 goes to MIRQ0. */
dev->irq_mode[0] = dev->irq_mode[1] = 2;
dev->irq_pin = PCI_INTA;
dev->irq_line = 14;
dev->irq_level[0] = dev->irq_level[1] = 0;
next_id++;

30
src/dma.c
View File

@@ -166,28 +166,6 @@ dma_block_transfer(int channel)
}
static void
dma_mem_to_mem_transfer(void)
{
int i;
if ((dma[0].mode & 0x0c) != 0x08)
fatal("DMA memory to memory transfer: channel 0 mode not read\n");
if ((dma[1].mode & 0x0c) != 0x04)
fatal("DMA memory to memory transfer: channel 1 mode not write\n");
dma_req_is_soft = 1;
for (i = 0; i <= dma[0].cb; i++)
dma_buffer[i] = dma_channel_read(0);
for (i = 0; i <= dma[1].cb; i++)
dma_channel_write(1, dma_buffer[i]);
dma_req_is_soft = 0;
}
static void
dma_sg_write(uint16_t port, uint8_t val, void *priv)
{
@@ -528,18 +506,14 @@ dma_write(uint16_t addr, uint8_t val, void *priv)
case 8: /*Control register*/
dma_command[0] = val;
if (val & 0x01)
pclog("[%08X:%04X] Memory-to-memory enable\n", CS, cpu_state.pc);
fatal("Memory-to-memory enable\n");
return;
case 9: /*Request register */
channel = (val & 3);
if (val & 4) {
dma_stat_rq_pc |= (1 << channel);
if ((channel == 0) && (dma_command[0] & 0x01)) {
pclog("Memory to memory transfer start\n");
dma_mem_to_mem_transfer();
} else
dma_block_transfer(channel);
dma_block_transfer(channel);
} else
dma_stat_rq_pc &= ~(1 << channel);
break;

8
src/include/86box/acpi.h
View File

@@ -54,7 +54,7 @@ typedef struct
{
uint8_t acpitst, auxen, auxsts, plvl2, plvl3,
smicmd, gpio_dir,
gpio_val, muxcntrl, ali_soft_smi,
gpio_val, muxcntrl, pad,
timer32, smireg,
gpireg[3], gporeg[4];
uint16_t pmsts, pmen,
@@ -83,8 +83,7 @@ typedef struct
uint16_t io_base, aux_io_base;
int vendor,
slot, irq_mode,
irq_pin, irq_line,
mirq_is_level;
irq_pin, irq_line;
pc_timer_t timer;
nvr_t *nvr;
apm_t *apm;
@@ -112,11 +111,8 @@ extern void acpi_set_slot(acpi_t *dev, int slot);
extern void acpi_set_irq_mode(acpi_t *dev, int irq_mode);
extern void acpi_set_irq_pin(acpi_t *dev, int irq_pin);
extern void acpi_set_irq_line(acpi_t *dev, int irq_line);
extern void acpi_set_mirq_is_level(acpi_t *dev, int mirq_is_level);
extern void acpi_set_gpireg2_default(acpi_t *dev, uint8_t gpireg2_default);
extern void acpi_set_nvr(acpi_t *dev, nvr_t *nvr);
extern uint8_t acpi_ali_soft_smi_status_read(acpi_t *dev);
extern void acpi_ali_soft_smi_status_write(acpi_t *dev, uint8_t soft_smi);
#ifdef __cplusplus
}

15
src/include/86box/chipset.h
View File

@@ -25,8 +25,10 @@ extern const device_t acc2168_device;
extern const device_t ali1217_device;
extern const device_t ali1429_device;
extern const device_t ali1489_device;
#if defined(DEV_BRANCH) && defined(USE_M154X)
extern const device_t ali1531_device;
extern const device_t ali1543_device;
#endif
#if defined(DEV_BRANCH) && defined(USE_M6117)
extern const device_t ali6117d_device;
#endif
@@ -42,6 +44,9 @@ extern const device_t scat_sx_device;
extern const device_t cs8230_device;
extern const device_t cs4031_device;
/* ETEQ */
extern const device_t et6000_device;
/* G2 */
extern const device_t gc100_device;
extern const device_t gc100a_device;
@@ -55,7 +60,6 @@ extern const device_t headland_ht18c_device;
/* Intel */
extern const device_t intel_82335_device;
extern const device_t i420ex_device;
extern const device_t i420ex_ide_device;
extern const device_t i420tx_device;
extern const device_t i420zx_device;
extern const device_t i430lx_device;
@@ -110,6 +114,7 @@ extern const device_t sis_85c496_ls486e_device;
extern const device_t sis_85c50x_device;
extern const device_t sis_5511_device;
extern const device_t sis_5571_device;
extern const device_t sis_5598_device;
/* ST */
extern const device_t stpc_client_device;
@@ -119,6 +124,13 @@ extern const device_t stpc_atlas_device;
extern const device_t stpc_serial_device;
extern const device_t stpc_lpt_device;
/* UMC */
extern const device_t umc_hb4_device;
extern const device_t umc_8890_device;
extern const device_t umc_8886f_device;
extern const device_t umc_8886af_device;
/* VIA */
extern const device_t via_vt82c49x_device;
extern const device_t via_vt82c49x_pci_device;
@@ -139,7 +151,6 @@ extern const device_t via_vt82c686b_device;
/* VLSI */
extern const device_t vl82c480_device;
extern const device_t vl82c486_device;
extern const device_t vlsi_scamp_device;
/* WD */

3
src/include/86box/hdc_ide.h
View File

@@ -150,8 +150,5 @@ extern int (*ide_bus_master_dma)(int channel, uint8_t *data, int transfer_length
extern void (*ide_bus_master_set_irq)(int channel, void *priv);
extern void *ide_bus_master_priv[2];
extern uint8_t ide_read_ali_75(void);
extern uint8_t ide_read_ali_76(void);
#endif /*EMU_IDE_H*/

6
src/include/86box/hdc_ide_sff8038i.h
View File

@@ -25,8 +25,8 @@ typedef struct
addr;
int count, eot,
slot,
irq_mode[2], irq_level[2],
irq_pin, irq_line;
irq_mode[2], irq_pin,
irq_line;
} sff8038i_t;
@@ -47,5 +47,3 @@ extern void sff_set_irq_line(sff8038i_t *dev, int irq_line);
extern void sff_set_irq_mode(sff8038i_t *dev, int channel, int irq_mode);
extern void sff_set_irq_pin(sff8038i_t *dev, int irq_pin);
extern void sff_set_irq_level(sff8038i_t *dev, int channel, int irq_level);

7
src/include/86box/keyboard.h
View File

@@ -72,12 +72,14 @@ extern const device_t keyboard_xt_olivetti_device;
extern const device_t keyboard_xt_zenith_device;
extern const device_t keyboard_at_device;
extern const device_t keyboard_at_ami_device;
extern const device_t keyboard_at_samsung_device;
extern const device_t keyboard_at_toshiba_device;
extern const device_t keyboard_at_olivetti_device;
extern const device_t keyboard_at_ncr_device;
extern const device_t keyboard_ps2_device;
extern const device_t keyboard_ps2_ps1_device;
extern const device_t keyboard_ps2_ps1_pci_device;
extern const device_t keyboard_ps2_ps2_device;
extern const device_t keyboard_ps2_xi8088_device;
extern const device_t keyboard_ps2_ami_device;
extern const device_t keyboard_ps2_olivetti_device;
@@ -106,15 +108,12 @@ extern int keyboard_isfsexit(void);
extern int keyboard_ismsexit(void);
extern void keyboard_set_is_amstrad(int ams);
extern void keyboard_at_adddata_keyboard_raw(uint8_t val);
extern void keyboard_at_adddata_mouse(uint8_t val);
extern void keyboard_at_adddata_mouse_direct(uint8_t val);
extern void keyboard_at_adddata_mouse_cmd(uint8_t val);
extern void keyboard_at_mouse_reset(void);
extern uint8_t keyboard_at_mouse_pos(void);
extern int keyboard_at_fixed_channel(void);
extern void keyboard_at_set_mouse(void (*mouse_write)(uint8_t val,void *), void *);
extern void keyboard_at_set_a20_key(int state);
extern void keyboard_at_set_mode(int ps2);
extern uint8_t keyboard_at_get_mouse_scan(void);
extern void keyboard_at_set_mouse_scan(uint8_t val);
extern void keyboard_at_reset(void);

151
src/include/86box/machine.h
View File

@@ -96,11 +96,9 @@ enum {
MACHINE_TYPE_8086,
MACHINE_TYPE_286,
MACHINE_TYPE_386SX,
MACHINE_TYPE_486SLC,
MACHINE_TYPE_386DX,
MACHINE_TYPE_386DX_486,
MACHINE_TYPE_486,
MACHINE_TYPE_486_S2,
MACHINE_TYPE_486_S3,
MACHINE_TYPE_486_MISC,
MACHINE_TYPE_SOCKET4,
@@ -252,8 +250,6 @@ extern int machine_at_mr286_init(const machine_t *);
extern int machine_at_neat_init(const machine_t *);
extern int machine_at_neat_ami_init(const machine_t *);
extern int machine_at_quadt386sx_init(const machine_t *);
extern int machine_at_award286_init(const machine_t *);
extern int machine_at_gdc212m_init(const machine_t *);
extern int machine_at_gw286ct_init(const machine_t *);
@@ -287,12 +283,16 @@ extern int machine_at_pja511m_init(const machine_t *);
extern int machine_at_pc916sx_init(const machine_t *);
extern int machine_at_m30008_init(const machine_t *);
extern int machine_at_m30015_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_ama932j_get_device(void);
extern const device_t *at_flytech386_get_device(void);
extern const device_t *at_cmdsl386sx25_get_device(void);
extern const device_t *at_spc4620p_get_device(void);
extern const device_t *at_spc6033p_get_device(void);
extern const device_t *at_m30008_get_device(void);
#endif
/* m_at_386dx_486.c */
@@ -310,8 +310,6 @@ extern int machine_at_cs4031_init(const machine_t *);
extern int machine_at_pb410a_init(const machine_t *);
extern int machine_at_acerv10_init(const machine_t *);
extern int machine_at_acera1g_init(const machine_t *);
extern int machine_at_ali1429_init(const machine_t *);
extern int machine_at_winbios1429_init(const machine_t *);
@@ -323,9 +321,9 @@ extern int machine_at_opti495_mr_init(const machine_t *);
extern int machine_at_vect486vl_init(const machine_t *);
extern int machine_at_d824_init(const machine_t *);
extern int machine_at_pcs46c_init(const machine_t *);
extern int machine_at_403tg_init(const machine_t *);
extern int machine_at_403tg_rev_d_init(const machine_t *);
extern int machine_at_403tg_rev_d_mr_init(const machine_t *);
extern int machine_at_pc330_6573_init(const machine_t *);
extern int machine_at_mvi486_init(const machine_t *);
@@ -347,16 +345,18 @@ extern int machine_at_4dps_init(const machine_t *);
extern int machine_at_4sa2_init(const machine_t *);
extern int machine_at_m4li_init(const machine_t *);
extern int machine_at_alfredo_init(const machine_t *);
extern int machine_at_ninja_init(const machine_t *);
extern int machine_at_486sp3_init(const machine_t *);
extern int machine_at_486sp3c_init(const machine_t *);
extern int machine_at_486sp3g_init(const machine_t *);
extern int machine_at_486ap4_init(const machine_t *);
extern int machine_at_g486vpa_init(const machine_t *);
extern int machine_at_486vipio2_init(const machine_t *);
extern int machine_at_abpb4_init(const machine_t *);
extern int machine_at_win486pci_init(const machine_t *);
extern int machine_at_atc1415_init(const machine_t *);
extern int machine_at_ecs486_init(const machine_t *);
extern int machine_at_hot433_init(const machine_t *);
extern int machine_at_itoxstar_init(const machine_t *);
extern int machine_at_arb1479_init(const machine_t *);
extern int machine_at_pcm9340_init(const machine_t *);
@@ -381,122 +381,113 @@ extern int machine_at_portableiii386_init(const machine_t *);
extern const device_t *at_cpqiii_get_device(void);
#endif
/* m_at_socket4.c */
extern void machine_at_premiere_common_init(const machine_t *, int);
extern void machine_at_award_common_init(const machine_t *);
extern void machine_at_sp4_common_init(const machine_t *model);
extern int machine_at_p5mp3_init(const machine_t *);
extern int machine_at_dellxp60_init(const machine_t *);
extern int machine_at_opti560l_init(const machine_t *);
extern int machine_at_ambradp60_init(const machine_t *);
extern int machine_at_valuepointp60_init(const machine_t *);
extern int machine_at_revenge_init(const machine_t *);
extern int machine_at_586mc1_init(const machine_t *);
extern int machine_at_pb520r_init(const machine_t *);
/* m_at_socket4_5.c */
extern int machine_at_excalibur_init(const machine_t *);
extern int machine_at_p5vl_init(const machine_t *);
extern int machine_at_pat54pv_init(const machine_t *);
extern int machine_at_p5sp4_init(const machine_t *);
extern int machine_at_hot543_init(const machine_t *);
extern int machine_at_p54vl_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_pb520r_get_device(void);
#endif
extern int machine_at_batman_init(const machine_t *);
extern int machine_at_ambradp60_init(const machine_t *);
extern int machine_at_dellxp60_init(const machine_t *);
extern int machine_at_opti560l_init(const machine_t *);
extern int machine_at_valuepointp60_init(const machine_t *);
extern int machine_at_p5mp3_init(const machine_t *);
extern int machine_at_pb520r_init(const machine_t *);
extern int machine_at_586mc1_init(const machine_t *);
/* m_at_socket5.c */
extern int machine_at_plato_init(const machine_t *);
extern int machine_at_ambradp90_init(const machine_t *);
extern int machine_at_430nx_init(const machine_t *);
extern int machine_at_acerv30_init(const machine_t *);
extern int machine_at_apollo_init(const machine_t *);
extern int machine_at_exp8551_init(const machine_t *);
extern int machine_at_vectra54_init(const machine_t *);
extern int machine_at_p54tp4xe_init(const machine_t *);
extern int machine_at_endeavor_init(const machine_t *);
extern int machine_at_zappa_init(const machine_t *);
extern int machine_at_powermatev_init(const machine_t *);
extern int machine_at_mb500n_init(const machine_t *);
extern int machine_at_hawk_init(const machine_t *);
extern int machine_at_pat54pv_init(const machine_t *);
extern int machine_at_hot543_init(const machine_t *);
extern int machine_at_apollo_init(const machine_t *);
extern int machine_at_vectra54_init(const machine_t *);
extern int machine_at_powermatev_init(const machine_t *);
extern int machine_at_acerv30_init(const machine_t *);
extern int machine_at_p5sp4_init(const machine_t *);
extern int machine_at_p54sp4_init(const machine_t *);
extern int machine_at_sq588_init(const machine_t *);
#ifdef EMU_DEVICE_H
#define at_vectra54_get_device at_endeavor_get_device
#endif
/* m_at_socket7_3v.c */
extern int machine_at_p54tp4xe_init(const machine_t *);
extern int machine_at_mr586_init(const machine_t *);
extern int machine_at_gw2katx_init(const machine_t *);
extern int machine_at_thor_init(const machine_t *);
extern int machine_at_mrthor_init(const machine_t *);
extern int machine_at_endeavor_init(const machine_t *);
extern int machine_at_ms5119_init(const machine_t *);
extern int machine_at_pb640_init(const machine_t *);
extern int machine_at_fmb_init(const machine_t *);
extern int machine_at_acerm3a_init(const machine_t *);
extern int machine_at_ap53_init(const machine_t *);
extern int machine_at_8500tuc_init(const machine_t *);
extern int machine_at_p55t2s_init(const machine_t *);
extern int machine_at_gw2kte_init(const machine_t *);
extern int machine_at_ap5s_init(const machine_t *);
extern int machine_at_hot539_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_endeavor_get_device(void);
#define at_vectra54_get_device at_endeavor_get_device
extern const device_t *at_pb520r_get_device(void);
extern const device_t *at_thor_get_device(void);
extern const device_t *at_pb640_get_device(void);
#endif
/* m_at_socket7.c */
/* m_at_socket7_s7.c */
extern int machine_at_ap5s_init(const machine_t *);
extern int machine_at_chariot_init(const machine_t *);
extern int machine_at_mr586_init(const machine_t *);
extern int machine_at_thor_init(const machine_t *);
extern int machine_at_gw2katx_init(const machine_t *);
extern int machine_at_mrthor_init(const machine_t *);
extern int machine_at_pb640_init(const machine_t *);
extern int machine_at_acerm3a_init(const machine_t *);
extern int machine_at_acerv35n_init(const machine_t *);
extern int machine_at_ap53_init(const machine_t *);
extern int machine_at_p55t2p4_init(const machine_t *);
extern int machine_at_p55t2s_init(const machine_t *);
extern int machine_at_8500tuc_init(const machine_t *);
extern int machine_at_m7shi_init(const machine_t *);
extern int machine_at_tc430hx_init(const machine_t *);
extern int machine_at_equium5200_init(const machine_t *);
extern int machine_at_pcv240_init(const machine_t *);
extern int machine_at_p65up5_cp55t2d_init(const machine_t *);
extern int machine_at_mb520n_init(const machine_t *);
extern int machine_at_p55tvp4_init(const machine_t *);
extern int machine_at_p55va_init(const machine_t *);
extern int machine_at_i430vx_init(const machine_t *);
extern int machine_at_5ivg_init(const machine_t *);
extern int machine_at_brio80xx_init(const machine_t *);
extern int machine_at_8500tvxa_init(const machine_t *);
extern int machine_at_presario2240_init(const machine_t *);
extern int machine_at_presario4500_init(const machine_t *);
extern int machine_at_p55va_init(const machine_t *);
extern int machine_at_brio80xx_init(const machine_t *);
extern int machine_at_gw2kte_init(const machine_t *);
extern int machine_at_pb680_init(const machine_t *);
extern int machine_at_mb520n_init(const machine_t *);
extern int machine_at_i430vx_init(const machine_t *);
extern int machine_at_nupro592_init(const machine_t *);
extern int machine_at_tx97_init(const machine_t *);
extern int machine_at_ym430tx_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern int machine_at_an430tx_init(const machine_t *);
#endif
extern int machine_at_ym430tx_init(const machine_t *);
extern int machine_at_mb540n_init(const machine_t *);
extern int machine_at_p5mms98_init(const machine_t *);
extern int machine_at_r534f_init(const machine_t *);
extern int machine_at_ms5146_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_M154X)
extern int machine_at_m560_init(const machine_t *);
extern int machine_at_ms5164_init(const machine_t *);
#endif
extern int machine_at_ficva502_init(const machine_t *);
extern int machine_at_ficpa2012_init(const machine_t *);
extern int machine_at_r534f_init(const machine_t *);
extern int machine_at_ms5146_init(const machine_t *);
extern int machine_at_sp97xv_init(const machine_t *);
extern int machine_at_m571_init(const machine_t *);
extern int machine_at_m560_init(const machine_t *);
extern int machine_at_ms5164_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_thor_get_device(void);
extern const device_t *at_pb640_get_device(void);
#endif
/* m_at_sockets7.c */
/* m_at_super7_ss7.c */
extern int machine_at_ax59pro_init(const machine_t *);
extern int machine_at_mvp3_init(const machine_t *);
extern int machine_at_ficva503a_init(const machine_t *);
@@ -535,6 +526,9 @@ extern int machine_at_atc6310bxii_init(const machine_t *);
extern int machine_at_686bx_init(const machine_t *);
extern int machine_at_tsunamiatx_init(const machine_t *);
extern int machine_at_p6sba_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern int machine_at_ergox365_init(const machine_t *);
#endif
extern int machine_at_ficka6130_init(const machine_t *);
extern int machine_at_p3v133_init(const machine_t *);
extern int machine_at_p3v4x_init(const machine_t *);
@@ -566,6 +560,7 @@ extern int machine_at_apas3_init(const machine_t *);
extern int machine_at_wcf681_init(const machine_t *);
extern int machine_at_cuv4xls_init(const machine_t *);
extern int machine_at_6via90ap_init(const machine_t *);
extern int machine_at_603tcf_init(const machine_t *);
extern int machine_at_trinity371_init(const machine_t *);
extern int machine_at_p6bap_init(const machine_t *);
@@ -654,6 +649,10 @@ extern int machine_xt_pc700_init(const machine_t *);
extern int machine_xt_iskra3104_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_HEDAKA)
extern int machine_xt_hed919_init(const machine_t *);
#endif
/* m_xt_compaq.c */
extern int machine_xt_compaq_deskpro_init(const machine_t *);
extern int machine_xt_compaq_portable_init(const machine_t *);

4
src/include/86box/pci.h
View File

@@ -45,10 +45,6 @@
#define PCI_MIRQ1 1
#define PCI_MIRQ2 2
#define PCI_MIRQ3 3
#define PCI_MIRQ4 4
#define PCI_MIRQ5 5
#define PCI_MIRQ6 6
#define PCI_MIRQ7 7
#define PCI_IRQ_DISABLED -1

5
src/include/86box/pic.h
View File

@@ -33,11 +33,6 @@ typedef struct pic {
extern pic_t pic, pic2;
extern void pic_reset_smi_irq_mask(void);
extern void pic_set_smi_irq_mask(int irq, int set);
extern uint16_t pic_get_smi_irq_status(void);
extern void pic_clear_smi_irq_status(int irq);
extern int pic_elcr_get_enabled(void);
extern void pic_elcr_set_enabled(int enabled);
extern void pic_elcr_io_handler(int set);

35
src/include/86box/pit.h
View File

@@ -18,34 +18,33 @@
# define EMU_PIT_H
typedef struct ctr_s {
typedef struct {
uint8_t m, ctrl,
read_status, latch,
s1_det, l_det,
bcd, flag_64k;
bcd, pad;
uint16_t l, rl;
union {
uint16_t count;
struct {
uint16_t units :4;
uint16_t tens :4;
uint16_t hundreds :4;
uint16_t thousands :4;
uint16_t myriads :4;
};
};
uint16_t rl;
int rm, wm, gate, out,
newcount, clock, using_timer, latched,
state, null_count, do_read_status, do_load;
state, null_count, do_read_status;
union {
int count;
struct {
int units :4;
int tens :4;
int hundreds :4;
int thousands :4;
int myriads :4;
};
};
uint32_t l;
void (*tick_func)(struct ctr_s *ctr);
void (*load_func)(uint8_t new_m, int new_count);
void (*out_func)(int new_out, int old_out);
struct PIT *pit;
} ctr_t;

38
src/include/86box/port_6x.h
View File

@@ -1,38 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Header for the implementation of Port 6x used by various
* machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.
*/
#ifndef EMU_PORT_6X_H
# define EMU_PORT_6X_H
#ifdef _TIMER_H_
typedef struct
{
uint8_t refresh, flags;
pc_timer_t refresh_timer;
} port_6x_t;
#endif
extern const device_t port_6x_device;
extern const device_t port_6x_xi8088_device;
extern const device_t port_6x_ps2_device;
extern const device_t port_6x_olivetti_device;
#endif /*EMU_PORT_6X_H*/

2
src/include/86box/sio.h
View File

@@ -27,7 +27,6 @@ extern const device_t fdc37c663_ide_device;
extern const device_t fdc37c665_device;
extern const device_t fdc37c665_ide_device;
extern const device_t fdc37c666_device;
extern const device_t fdc37c67x_device;
extern const device_t fdc37c669_device;
extern const device_t fdc37c669_370_device;
extern const device_t fdc37c931apm_device;
@@ -54,7 +53,6 @@ extern const device_t pc87311_ide_device;
extern const device_t pc87332_device;
extern const device_t pc87332_398_device;
extern const device_t pc87332_398_ide_device;
extern const device_t pc87332_398_ide_sec_device;
extern const device_t pc87332_398_ide_fdcon_device;
extern const device_t pc97307_device;
extern const device_t prime3b_device;

1
src/include/86box/spd.h
View File

@@ -106,7 +106,6 @@ typedef struct {
extern void spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size);
extern void spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit);
extern void spd_write_drbs_interleaved(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit);
#endif /*EMU_SPD_H*/

11
src/include/86box/vid_svga.h
View File

@@ -23,9 +23,8 @@
#define FLAG_EXT_WRITE 4
#define FLAG_LATCH8 8
#define FLAG_NOSKEW 16
#define FLAG_ADDR_BY16 32
#define FLAG_128K_MASK 64
typedef struct {
int ena,
@@ -50,8 +49,7 @@ typedef struct svga_t
lowres, interlace, linedbl, rowcount,
set_reset_disabled, bpp, ramdac_type, fb_only,
readmode, writemode, readplane,
hwcursor_oddeven, dac_hwcursor_oddeven, overlay_oddeven,
fcr, hblank_overscan;
hwcursor_oddeven, dac_hwcursor_oddeven, overlay_oddeven;
int dac_addr, dac_pos, dac_r, dac_g,
vtotal, dispend, vsyncstart, split, vblankstart,
@@ -61,9 +59,8 @@ typedef struct svga_t
con, cursoron, blink, scrollcache, char_width,
firstline, lastline, firstline_draw, lastline_draw,
displine, fullchange, x_add, y_add, pan,
vram_display_mask, vidclock, dots_per_clock, hblank_ext,
hwcursor_on, dac_hwcursor_on, overlay_on, set_override,
hblankstart, hblankend, hblank_sub, hblank_end_val, hblank_end_len;
vram_display_mask, vidclock,
hwcursor_on, dac_hwcursor_on, overlay_on, set_override;
/*The three variables below allow us to implement memory maps like that seen on a 1MB Trio64 :
0MB-1MB - VRAM

2
src/include/86box/vid_svga_render.h
View File

@@ -44,8 +44,6 @@ void svga_render_4bpp_lowres(svga_t *svga);
void svga_render_4bpp_highres(svga_t *svga);
void svga_render_8bpp_lowres(svga_t *svga);
void svga_render_8bpp_highres(svga_t *svga);
void svga_render_8bpp_tseng_lowres(svga_t *svga);
void svga_render_8bpp_tseng_highres(svga_t *svga);
void svga_render_8bpp_gs_lowres(svga_t *svga);
void svga_render_8bpp_gs_highres(svga_t *svga);
void svga_render_8bpp_rgb_lowres(svga_t *svga);

5
src/include/86box/video.h
View File

@@ -252,11 +252,7 @@ extern const device_t ogc_m24_device;
/* NCR NGA */
extern const device_t nga_device;
/* Tseng ET3000AX */
extern const device_t et3000_isa_device;
/* Tseng ET4000AX */
extern const device_t et4000_tc6058af_isa_device;
extern const device_t et4000_isa_device;
extern const device_t et4000k_isa_device;
extern const device_t et4000k_tg286_isa_device;
@@ -308,6 +304,7 @@ extern const device_t oti037c_device;
extern const device_t oti067_device;
extern const device_t oti067_acer386_device;
extern const device_t oti067_ama932j_device;
extern const device_t oti067_m300_device;
extern const device_t oti077_device;
/* Paradise/WD (S)VGA */

3
src/log.c
View File

@@ -43,9 +43,6 @@ typedef struct
} log_t;
extern FILE *stdlog; /* file to log output to */
void
log_set_suppr_seen(void *priv, int suppr_seen)
{

5
src/machine/CMakeLists.txt
View File

@@ -19,9 +19,8 @@ add_library(mch OBJECT machine.c machine_table.c m_xt.c m_xt_compaq.c
m_amstrad.c m_europc.c m_xt_olivetti.c m_tandy.c m_at.c m_at_commodore.c
m_at_t3100e.c m_at_t3100e_vid.c m_ps1.c m_ps1_hdc.c m_ps2_isa.c
m_ps2_mca.c m_at_compaq.c m_at_286_386sx.c m_at_386dx_486.c
m_at_socket4.c m_at_socket5.c m_at_socket7_3v.c m_at_socket7.c
m_at_sockets7.c m_at_socket8.c m_at_slot1.c m_at_slot2.c m_at_socket370.c
m_at_misc.c)
m_at_socket4_5.c m_at_socket7.c m_at_sockets7.c m_at_socket8.c
m_at_slot1.c m_at_slot2.c m_at_socket370.c m_at_misc.c)
if(HEDAKA)
target_compile_definitions(mch PRIVATE USE_HEDAKA)

5
src/machine/m_at.c
View File

@@ -56,7 +56,6 @@
#include <86box/lpt.h>
#include <86box/rom.h>
#include <86box/hdc.h>
#include <86box/port_6x.h>
#include <86box/machine.h>
@@ -70,10 +69,6 @@ machine_at_common_init_ex(const machine_t *model, int type)
pic2_init();
dma16_init();
if (!(type & 4))
device_add(&port_6x_device);
type &= 3;
if (type == 1)
device_add(&ibmat_nvr_device);
else if (type == 0)

91
src/machine/m_at_286_386sx.c
View File

@@ -37,7 +37,6 @@
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/port_6x.h>
#include <86box/sio.h>
#include <86box/serial.h>
#include <86box/video.h>
@@ -141,35 +140,11 @@ machine_at_quadt286_init(const machine_t *model)
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&keyboard_at_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&headland_gc10x_device);
return ret;
}
int
machine_at_quadt386sx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/quadt386sx/QTC-SXM-EVEN-U3-05-07.BIN",
"roms/machines/quadt386sx/QTC-SXM-ODD-U3-05-07.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&keyboard_at_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&fdc_at_device);
device_add(&headland_gc10x_device);
@@ -748,7 +723,6 @@ machine_at_pja511m_init(const machine_t *model)
return ret;
}
#endif
/*
@@ -776,7 +750,6 @@ machine_at_pc8_init(const machine_t *model)
return ret;
}
/*
* Current bugs:
* - ctrl-alt-del produces an 8042 error
@@ -810,7 +783,6 @@ machine_at_3302_init(const machine_t *model)
return ret;
}
/*
* Current bugs:
* - soft-reboot after saving CMOS settings/pressing ctrl-alt-del produces an 8042 error
@@ -838,7 +810,6 @@ machine_at_pc916sx_init(const machine_t *model)
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_OLIVETTI)
int
machine_at_m290_init(const machine_t *model)
@@ -851,10 +822,9 @@ machine_at_m290_init(const machine_t *model)
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 4);
machine_at_common_init(model);
device_add(&keyboard_at_olivetti_device);
device_add(&port_6x_olivetti_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
@@ -863,3 +833,58 @@ machine_at_m290_init(const machine_t *model)
return ret;
}
#endif
const device_t *
at_m30008_get_device(void)
{
return &oti067_m300_device;
}
int
machine_at_m30008_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m30008/BIOS.ROM",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti283_device);
device_add(&keyboard_ps2_olivetti_device);
device_add(&pc87310_ide_device);
if (gfxcard == VID_INTERNAL)
device_add(&oti067_m300_device);
return ret;
}
/* Almost identical to M300-08, save for CPU speed, VRAM, and BIOS identification string */
int
machine_at_m30015_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m30015/BIOS.ROM",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti283_device);
device_add(&keyboard_ps2_olivetti_device);
device_add(&pc87310_ide_device);
/* Stock VRAM is maxed out, so no need to expose video card config */
if (gfxcard == VID_INTERNAL)
device_add(&oti067_m300_device);
return ret;
}

288
src/machine/m_at_386dx_486.c
View File

@@ -32,17 +32,12 @@
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/dma.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/gameport.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/rom.h>
#include <86box/sio.h>
#include <86box/hdc.h>
#include <86box/port_6x.h>
#include <86box/video.h>
#include <86box/flash.h>
#include <86box/scsi_ncr53c8xx.h>
@@ -234,7 +229,7 @@ machine_at_spc6000a_init(const machine_t *model)
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&keyboard_at_ami_device);
device_add(&keyboard_at_samsung_device);
return ret;
}
@@ -302,7 +297,7 @@ machine_at_cs4031_init(const machine_t *model)
device_add(&keyboard_at_ami_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&fdc_at_device);
return ret;
}
@@ -364,7 +359,6 @@ at_vect486vl_get_device(void)
return &gd5428_onboard_device;
}
int
machine_at_d824_init(const machine_t *model)
{
@@ -388,13 +382,39 @@ machine_at_d824_init(const machine_t *model)
return ret;
}
const device_t *
at_d824_get_device(void)
{
return &gd5428_onboard_device;
}
int
machine_at_pcs46c_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pcs46c/OLIVETTI.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&et6000_device);
device_add(&keyboard_ps2_device);
if (gfxcard == VID_INTERNAL)
device_add(&gd5428_onboard_device);
return ret;
}
const device_t *
at_pcs46c_get_device(void)
{
return &gd5428_onboard_device;
}
int
machine_at_acera1g_init(const machine_t *model)
@@ -417,7 +437,7 @@ machine_at_acera1g_init(const machine_t *model)
device_add(&ide_isa_2ch_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&fdc_at_device);
return ret;
}
@@ -430,30 +450,6 @@ at_acera1g_get_device(void)
}
int
machine_at_acerv10_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acerv10/ALL.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&sis_85c461_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ide_isa_2ch_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
static void
machine_at_ali1429_common_init(const machine_t *model)
{
@@ -573,25 +569,6 @@ machine_at_opti495_mr_init(const machine_t *model)
return ret;
}
static void
machine_at_403tg_common_init(const machine_t *model, int nvr_hack)
{
if (nvr_hack) {
machine_at_common_init_ex(model, 2);
device_add(&ls486e_nvr_device);
} else
machine_at_common_init(model);
device_add(&opti895_device);
device_add(&keyboard_at_ami_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
}
int
machine_at_403tg_init(const machine_t *model)
{
@@ -603,41 +580,14 @@ machine_at_403tg_init(const machine_t *model)
if (bios_only || !ret)
return ret;
machine_at_403tg_common_init(model, 0);
machine_at_common_init(model);
return ret;
}
device_add(&opti895_device);
device_add(&keyboard_at_device);
int
machine_at_403tg_rev_d_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/403tg_rev_d/J403TGRevD.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_403tg_common_init(model, 1);
return ret;
}
int
machine_at_403tg_rev_d_mr_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/403tg_rev_d/MRBiosOPT895.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_403tg_common_init(model, 0);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
@@ -735,7 +685,7 @@ machine_at_vli486sv2g_init(const machine_t *model)
machine_at_sis_85c471_common_init(model);
device_add(&ide_vlb_2ch_device);
device_add(&keyboard_ps2_ami_device);
device_add(&keyboard_at_device);
return ret;
}
@@ -934,7 +884,7 @@ machine_at_4dps_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&w83787f_device);
device_add(&keyboard_at_ami_device);
device_add(&keyboard_ps2_pci_device);
device_add(&intel_flash_bxt_device);
@@ -990,13 +940,10 @@ machine_at_4sa2_init(const machine_t *model)
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
// device_add(&w83787f_device);
device_add(&prime3b_device);
// device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83787f_device);
device_add(&keyboard_ps2_pci_device);
// device_add(&intel_flash_bxt_device);
device_add(&sst_flash_29ee010_device);
device_add(&intel_flash_bxt_device);
return ret;
}
@@ -1023,7 +970,7 @@ machine_at_alfredo_init(const machine_t *model)
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sio_device);
device_add(&fdc37c663_device);
device_add(&intel_flash_bxt_ami_device);
@@ -1034,34 +981,6 @@ machine_at_alfredo_init(const machine_t *model)
}
int
machine_at_ninja_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/ninja/1008AY0_.BIO",
"roms/machines/ninja/1008AY0_.BI1", 0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x05, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 2, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 1, 2, 1);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&i420ex_device);
device_add(&i82091aa_device);
return ret;
}
int
machine_at_486sp3_init(const machine_t *model)
{
@@ -1152,7 +1071,7 @@ machine_at_486ap4_init(const machine_t *model)
device_add(&keyboard_ps2_ami_pci_device); /* Uses the AMIKEY KBC */
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&fdc_at_device);
device_add(&i420ex_device);
@@ -1160,36 +1079,6 @@ machine_at_486ap4_init(const machine_t *model)
}
int
machine_at_g486vpa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/g486vpa/3.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&via_vt82c49x_pci_ide_device);
device_add(&via_vt82c505_device);
device_add(&pc87332_398_ide_sec_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_486vipio2_init(const machine_t *model)
{
@@ -1276,6 +1165,99 @@ machine_at_win486pci_init(const machine_t *model)
}
int
machine_at_atc1415_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/atc1415/1415V330.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0c, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&umc_hb4_device);
device_add(&umc_8886af_device);
device_add(&keyboard_at_ami_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_ecs486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ecs486/8810AIO.32J",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0c, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0d, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0e, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0f, PCI_CARD_IDE, 0, 0, 0, 0);
device_add(&umc_hb4_device);
device_add(&umc_8886f_device);
device_add(&ide_cmd640_pci_legacy_only_device);
device_add(&fdc37c665_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_hot433_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/hot433/433AUS33.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0c, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0d, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0e, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0f, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&umc_hb4_device);
device_add(&umc_8886af_device);
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_itoxstar_init(const machine_t *model)
{

33
src/machine/m_at_slot1.c
View File

@@ -486,6 +486,37 @@ at_tsunamiatx_get_device(void)
return &es1371_onboard_device;
}
#if defined(DEV_BRANCH) && defined(NO_SIO)
int
machine_at_ergox365_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ergox365/M63v115.rom",
0x00080000, 524288, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x08, PCI_CARD_VIDEO, 3, 0, 0, 0);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device); /* Placeholder for the SM(S)C FDC37C675 */
device_add(&sst_flash_39sf040_device); /* Placeholder for the Intel 28F004 flash chip */
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
return ret;
}
#endif
int
machine_at_ficka6130_init(const machine_t *model)
@@ -617,10 +648,8 @@ machine_at_vei8_init(const machine_t *model)
device_add(&piix4e_device);
device_add(&fdc37m60x_370_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(ics9xxx_get(ICS9250_08));
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 512);
device_add(&as99127f_device); /* fans: Chassis, CPU, Power; temperatures: MB, JTPWR, CPU */
return ret;
}

38
src/machine/m_at_socket370.c
View File

@@ -100,7 +100,7 @@ machine_at_trinity371_init(const machine_t *model)
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977ef_370_device);
device_add(&w83977f_370_device);
device_add(&intel_flash_bxt_device);
return ret;
@@ -453,3 +453,39 @@ machine_at_6via90ap_init(const machine_t *model)
return ret;
}
int
machine_at_603tcf_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/603tcf/603tcfA4.BIN",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_vt8601_device);
device_add(&via_vt82c686b_device);
device_add(&via_vt82c686_sio_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 512);
device_add(&via_vt82c686_hwm_device); /* fans: 1, 2; temperatures: CPU, System, unused */
hwm_values.temperatures[0] += 2; /* CPU offset */
hwm_values.temperatures[1] += 2; /* System offset */
hwm_values.temperatures[2] = 0; /* unused */
return ret;
}

406
src/machine/m_at_socket4.c
View File

@@ -1,406 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 4 machines.
*
*
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2010-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/nvr.h>
#include <86box/scsi_ncr53c8xx.h>
#include <86box/sio.h>
#include <86box/video.h>
#include <86box/machine.h>
void
machine_at_premiere_common_init(const machine_t *model, int pci_switch)
{
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2 | pci_switch);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&sio_zb_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
}
void
machine_at_award_common_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 03 = Slot 1 */
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 04 = Slot 2 */
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 05 = Slot 3 */
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); /* 06 = Slot 4 */
pci_register_slot(0x07, PCI_CARD_SCSI, 1, 2, 3, 4); /* 07 = SCSI */
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
// device_add(&keyboard_ps2_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
}
void
machine_at_sp4_common_init(const machine_t *model)
{
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
/* Excluded: 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14 */
pci_register_slot(0x0D, PCI_CARD_IDE, 1, 2, 3, 4);
/* Excluded: 02, 03*, 04*, 05*, 06*, 07*, 08* */
/* Slots: 09 (04), 0A (03), 0B (02), 0C (07) */
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_85c50x_device);
device_add(&ide_cmd640_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
int
machine_at_p5mp3_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p5mp3/0205.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_device);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x05, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 05 = Slot 1 */
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 04 = Slot 2 */
pci_register_slot(0x03, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 03 = Slot 3 */
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&fdc_at_device);
device_add(&keyboard_ps2_pci_device);
device_add(&sio_zb_device);
device_add(&catalyst_flash_device);
device_add(&i430lx_device);
return ret;
}
int
machine_at_dellxp60_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/dellxp60/XP60-A08.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
/* Not: 00, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F. */
/* Yes: 01, 10, 11, 12, 13, 14. */
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x04, PCI_CARD_NORMAL, 4, 4, 3, 3);
pci_register_slot(0x05, PCI_CARD_NORMAL, 1, 4, 3, 2);
pci_register_slot(0x06, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430lx_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&sio_zb_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_opti560l_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/opti560l/560L_A06.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 4, 4, 3, 3);
pci_register_slot(0x07, PCI_CARD_NORMAL, 1, 4, 3, 2);
pci_register_slot(0x08, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430lx_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&sio_zb_device);
device_add(&i82091aa_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_ambradp60_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/ambradp60/1004AF1P.BIO",
"roms/machines/ambradp60/1004AF1P.BI1", 0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model, 0);
device_add(&i430lx_device);
return ret;
}
int
machine_at_valuepointp60_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/valuepointp60/1006AV0M.BIO",
"roms/machines/valuepointp60/1006AV0M.BI1", 0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ps1_pci_device);
device_add(&sio_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&i430lx_device);
return ret;
}
int
machine_at_revenge_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/revenge/1009af2_.bio",
"roms/machines/revenge/1009af2_.bi1", 0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model, 0);
device_add(&i430lx_device);
return ret;
}
int
machine_at_586mc1_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/586mc1/IS.34",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_award_common_init(model);
device_add(&sio_device);
device_add(&intel_flash_bxt_device);
device_add(&i430lx_device);
return ret;
}
int
machine_at_pb520r_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/pb520r/1009bc0r.bio",
"roms/machines/pb520r/1009bc0r.bi1", 0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_VIDEO, 3, 3, 3, 3);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430lx_device);
device_add(&ide_cmd640_pci_single_channel_device);
if (gfxcard == VID_INTERNAL)
device_add(&gd5434_onboard_pci_device);
device_add(&keyboard_ps2_pci_device);
device_add(&sio_zb_device);
device_add(&i82091aa_ide_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
const device_t *
at_pb520r_get_device(void)
{
return &gd5434_onboard_pci_device;
}
int
machine_at_excalibur_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/excalibur/S75P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti5x7_device);
device_add(&ide_opti611_vlb_device);
device_add(&fdc37c661_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
return ret;
}
int
machine_at_p5vl_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p5vl/SM507.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&opti5x7_device);
device_add(&opti822_device);
device_add(&sst_flash_29ee010_device);
device_add(&keyboard_at_ami_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_p5sp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p5sp4/0106.001",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_sp4_common_init(model);
return ret;
}

446
src/machine/m_at_socket5.c
View File

@@ -1,446 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 5 machines.
*
*
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2010-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/nvr.h>
#include <86box/scsi_ncr53c8xx.h>
#include <86box/sio.h>
#include <86box/video.h>
#include <86box/machine.h>
int
machine_at_plato_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/plato/1016ax1_.bio",
"roms/machines/plato/1016ax1_.bi1", 0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model, PCI_CAN_SWITCH_TYPE);
device_add(&i430nx_device);
return ret;
}
int
machine_at_ambradp90_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/ambradp90/1002AX1P.BIO",
"roms/machines/ambradp90/1002AX1P.BI1", 0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model, PCI_CAN_SWITCH_TYPE);
device_add(&i430nx_device);
return ret;
}
int
machine_at_430nx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/430nx/IP.20",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_award_common_init(model);
device_add(&sio_device);
device_add(&intel_flash_bxt_device);
device_add(&i430nx_device);
return ret;
}
int
machine_at_acerv30_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acerv30/V30R01N9.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_acer_pci_device);
device_add(&fdc37c665_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_apollo_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/apollo/S728P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ami_apollo_nvr_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87332_398_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_exp8551_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/exp8551/AMI20.BIO",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&w83787f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_vectra54_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/vectra54/GT0724.22",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_VIDEO, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x08, PCI_CARD_NORMAL, 3, 4, 1, 2);
if (gfxcard == VID_INTERNAL)
device_add(&s3_phoenix_trio64_onboard_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c931apm_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_zappa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/zappa/1006bs0_.bio",
"roms/machines/zappa/1006bs0_.bi1", 0x20000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_powermatev_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/powermatev/BIOS.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_mb500n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mb500n/031396s.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_hawk_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/hawk/HAWK.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_pat54pv_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pat54pv/pat54pv.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti5x7_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_hot543_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/hot543/543_R21.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&opti5x7_device);
device_add(&opti822_device);
device_add(&sst_flash_29ee010_device);
device_add(&keyboard_at_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_p54sp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p54sp4/SI5I0204.AWD",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_sp4_common_init(model);
return ret;
}
int
machine_at_sq588_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sq588/sq588b03.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
/* Correct: 0D (01), 0F (02), 11 (03), 13 (04) */
pci_register_slot(0x02, PCI_CARD_IDE, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_85c50x_device);
device_add(&ide_cmd640_pci_single_channel_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_ide_device);
device_add(&sst_flash_29ee010_device);
return ret;
}

865
src/machine/m_at_socket7.c
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514
src/machine/m_at_socket7_3v.c
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@@ -1,514 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 7 (Single Voltage) machines.
*
*
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Melissa Goad, <mszoopers@protonmail.com>
*
* Copyright 2010-2020 Sarah Walker.
* Copyright 2016-2020 Miran Grca.
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/sio.h>
#include <86box/hwm.h>
#include <86box/video.h>
#include <86box/spd.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/nvr.h>
static void
machine_at_thor_common_init(const machine_t *model, int mr)
{
machine_at_common_init_ex(model, mr);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 3, 2, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
// device_add(&keyboard_ps2_ami_pci_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
}
int
machine_at_p54tp4xe_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p54tp4xe/t15i0302.awd",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
/* Award BIOS, SMC FDC37C665. */
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_mr586_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mr586/TRITON.BIO",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_gw2katx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/gw2katx/1003cn0t.bio",
"roms/machines/gw2katx/1003cn0t.bi1", 0x20000, 128);
if (bios_only || !ret)
return ret;
machine_at_thor_common_init(model, 0);
return ret;
}
int
machine_at_thor_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/thor/1006cn0_.bio",
"roms/machines/thor/1006cn0_.bi1", 0x20000, 128);
if (bios_only || !ret)
return ret;
machine_at_thor_common_init(model, 0);
return ret;
}
int
machine_at_mrthor_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mrthor/mr_atx.bio",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_thor_common_init(model, 1);
return ret;
}
int
machine_at_endeavor_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/endeavor/1006cb0_.bio",
"roms/machines/endeavor/1006cb0_.bi1", 0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (gfxcard == VID_INTERNAL)
device_add(&s3_phoenix_trio64_onboard_pci_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
const device_t *
at_endeavor_get_device(void)
{
return &s3_phoenix_trio64_onboard_pci_device;
}
int
machine_at_ms5119_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms5119/A37E.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0d, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0e, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0f, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83787f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_pb640_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/pb640/1007CP0R.BIO",
"roms/machines/pb640/1007CP0R.BI1", 0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430fx_rev02_device);
device_add(&piix_rev02_device);
if (gfxcard == VID_INTERNAL)
device_add(&gd5440_onboard_pci_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
const device_t *
at_pb640_get_device(void)
{
return &gd5440_onboard_pci_device;
}
int
machine_at_fmb_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/fmb/P5IV183.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 3, 2, 1);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83787f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_acerm3a_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acerm3a/r01-b3.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x10, PCI_CARD_VIDEO, 4, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&fdc37c932fr_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_ap53_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ap53/ap53r2c0.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_VIDEO, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_8500tuc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/8500tuc/Tuc0221b.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_p55t2s_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p55t2s/s6y08t.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_gw2kte_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/gw2kte/1008CY1T.BIO",
"roms/machines/gw2kte/1008CY1T.BI1",
"roms/machines/gw2kte/1008CY1T.BI2",
"roms/machines/gw2kte/1008CY1T.BI3",
"roms/machines/gw2kte/1008CY1T.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c932fr_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_ap5s_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ap5s/AP5S150.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 3, 2, 1);
device_add(&sis_5511_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&sst_flash_29ee010_device);
return ret;
}

2
src/machine/m_at_socket8.c
View File

@@ -62,8 +62,6 @@ machine_at_p6rp4_init(const machine_t *model)
pci_register_slot(0x08, PCI_CARD_IDE, 0, 0, 0, 0);
device_add(&i450kx_device);
device_add(&sio_zb_device);
// device_add(&keyboard_ps2_ami_pci_device);
/* Input port bit 2 must be 1 or CMOS Setup is disabled. */
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&ide_cmd640_pci_device);

2
src/machine/m_ps1.c
View File

@@ -59,7 +59,6 @@
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/port_6x.h>
#include <86box/sound.h>
#include <86box/snd_sn76489.h>
#include <86box/video.h>
@@ -515,7 +514,6 @@ ps1_common_init(const machine_t *model)
pic2_init();
device_add(&keyboard_ps2_ps1_device);
device_add(&port_6x_device);
/* Audio uses ports 200h and 202-207h, so only initialize gameport on 201h. */
standalone_gameport_type = &gameport_201_device;

4
src/machine/m_ps2_isa.c
View File

@@ -15,7 +15,6 @@
#include <86box/nvr.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/port_6x.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/hdc.h>
@@ -187,8 +186,7 @@ machine_ps2_m30_286_init(const machine_t *model)
refresh_at_enable = 1;
pit_ctr_set_out_func(&pit->counters[1], pit_refresh_timer_at);
dma16_init();
device_add(&keyboard_ps2_device);
device_add(&port_6x_ps2_device);
device_add(&keyboard_ps2_ps2_device);
device_add(&ps_nvr_device);
pic2_init();
ps2board_init();

4
src/machine/m_ps2_mca.c
View File

@@ -63,7 +63,6 @@
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/mouse.h>
#include <86box/port_6x.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/video.h>
@@ -794,8 +793,7 @@ static void ps2_mca_board_common_init()
io_sethandler(0x0096, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
io_sethandler(0x0100, 0x0008, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
device_add(&port_6x_ps2_device);
device_add(&port_92_device);
device_add(&port_92_device);
ps2.setup = 0xff;

22
src/machine/m_xt.c
View File

@@ -290,6 +290,28 @@ machine_xt_pcxt_init(const machine_t *model)
}
#if defined(DEV_BRANCH) && defined(USE_HEDAKA)
int
machine_xt_hed919_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/hed919/Hedaka_HED-919_bios_version_3.28f.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model);
if (mem_size > 640)
mem_remap_top(mem_size - 640);
return ret;
}
#endif
int
machine_xt_pxxt_init(const machine_t *model)
{

5
src/machine/m_xt_olivetti.c
View File

@@ -44,7 +44,6 @@
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/gameport.h>
#include <86box/port_6x.h>
#include <86box/sound.h>
#include <86box/snd_speaker.h>
#include <86box/video.h>
@@ -766,9 +765,6 @@ machine_xt_m240_init(const machine_t *model)
pit_ctr_set_out_func(&pit->counters[1], pit_refresh_timer_xt);
/* Address 66-67 = mainboard dip-switch settings */
io_sethandler(0x0066, 2, m24_read, NULL, NULL, NULL, NULL, NULL, NULL);
/*
* port 60: should return jumper settings only under unknown conditions
* SWB on mainboard (off=1)
@@ -776,7 +772,6 @@ machine_xt_m240_init(const machine_t *model)
* bit 6 - use OCG/CGA display adapter (on) / other display adapter (off)
*/
device_add(&keyboard_at_olivetti_device);
device_add(&port_6x_olivetti_device);
/* FIXME: make sure this is correct?? */
device_add(&at_nvr_device);

2
src/machine/m_xt_xi8088.c
View File

@@ -19,7 +19,6 @@
#include <86box/lpt.h>
#include <86box/rom.h>
#include <86box/hdc.h>
#include <86box/port_6x.h>
#include <86box/video.h>
#include <86box/machine.h>
#include "cpu.h"
@@ -179,7 +178,6 @@ machine_xt_xi8088_init(const machine_t *model)
device_add(&fdc_at_device);
device_add(&keyboard_ps2_xi8088_device);
device_add(&port_6x_xi8088_device);
nmi_init();
device_add(&ibmat_nvr_device);
pic2_init();

500
src/machine/machine_table.c
View File

@@ -39,12 +39,10 @@ const machine_type_t machine_types[] = {
{ "8086", MACHINE_TYPE_8086 },
{ "80286", MACHINE_TYPE_286 },
{ "i386SX", MACHINE_TYPE_386SX },
{ "486SLC", MACHINE_TYPE_486SLC },
{ "i386DX", MACHINE_TYPE_386DX },
{ "i386DX/i486", MACHINE_TYPE_386DX_486 },
{ "i486 (Socket 168 and 1)", MACHINE_TYPE_486 },
{ "i486 (Socket 2)", MACHINE_TYPE_486_S2 },
{ "i486 (Socket 3)", MACHINE_TYPE_486_S3 },
{ "i486 (Socket 2 and 3)", MACHINE_TYPE_486_S3 },
{ "i486 (Miscellaneous)", MACHINE_TYPE_486_MISC },
{ "Socket 4", MACHINE_TYPE_SOCKET4 },
{ "Socket 5", MACHINE_TYPE_SOCKET5 },
@@ -60,49 +58,6 @@ const machine_type_t machine_types[] = {
};
/* Machines to add before machine freeze:
- Jetway J-403TG MR BIOS v2.02;
- Matsonic MS6260S (AMI Super Socket 7 with Aladdin V chipset);
- PCChips M773 (440BX + SMSC with AMI BIOS);
- Rise R418 (was removed on my end, has to be re-added);
- TMC Mycomp PCI54ST;
- Zeos Quadtel 486.
NOTE: The AMI MegaKey tests were done on a real Intel Advanced/ATX
(thanks, MrKsoft for running my AMIKEY.COM on it), but the
technical specifications of the other Intel machines confirm
that the other boards also have the MegaKey.
NOTE: The later (ie. not AMI Color) Intel AMI BIOS'es execute a
sequence of commands (B8, BA, BB) during one of the very first
phases of POST, in a way that is only valid on the AMIKey-3
KBC firmware, that includes the Classic PCI/ED (Ninja) BIOS
which otherwise does not execute any AMI KBC commands, which
indicates that the sequence is a leftover of whatever AMI
BIOS (likely a laptop one since the AMIKey-3 is a laptop KBC
firmware!) Intel forked.
NOTE: The VIA VT82C42N returns 0x46 ('F') in command 0xA1 (so it
emulates the AMI KF/AMIKey KBC firmware), and 0x42 ('B') in
command 0xAF.
The version on the VIA VT82C686B southbridge also returns
'F' in command 0xA1, but 0x45 ('E') in command 0xAF.
NOTE: The AMI MegaKey commands blanked in the technical reference
are CC and and C4, which are Set P14 High and Set P14 Low,
respectively. Also, AMI KBC command C1, mysteriously missing
from the technical references of AMI MegaKey and earlier, is
Write Input Port, same as on AMIKey-3.
Machines to remove:
- Hedaka HED-919;
- A-Trend ATC-1415;
- ECS Elite UM8810PAIO;
- Shuttle HOT-433A;
- Azza 5IVG (if a more interesting machine with Prime3C is found).
*/
const machine_t machines[] = {
/* 8088 Machines */
{ "[8088] IBM PC (1981)", "ibmpc", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 16, 64, 16, 0, machine_pc_init, NULL },
@@ -114,10 +69,10 @@ const machine_t machines[] = {
{ "[8088] AMI XT clone", "amixt", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_xt_amixt_init, NULL },
{ "[8088] Columbia Data Products MPC-1600", "mpc1600", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 512, 64, 0, machine_xt_mpc1600_init, NULL },
{ "[8088] Compaq Portable", "portable", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_compaq_portable_init, NULL },
{ "[8088] DTK PIM-TB10-Z", "dtk", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_xt_dtk_init, NULL },
{ "[8088] DTK XT clone", "dtk", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_xt_dtk_init, NULL },
{ "[8088] Eagle PC Spirit", "pcspirit", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 64, 0, machine_xt_pcspirit_init, NULL },
{ "[8088] Generic XT clone", "genxt", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_genxt_init, NULL },
{ "[8088] Juko ST", "jukopc", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_xt_jukopc_init, NULL },
{ "[8088] Juko XT clone", "jukopc", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 640, 64, 0, machine_xt_jukopc_init, NULL },
{ "[8088] Multitech PC-700", "pc700", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 64, 0, machine_xt_pc700_init, NULL },
{ "[8088] NCR PC4i", "pc4i", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 256, 640, 256, 0, machine_xt_pc4i_init, NULL },
{ "[8088] Olivetti M19", "m19", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO_FIXED, 256, 640, 256, 0, machine_xt_m19_init, NULL },
@@ -132,7 +87,6 @@ const machine_t machines[] = {
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8088] VTech Laser Turbo XT", "ltxt", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 256, 640, 256, 0, machine_xt_laserxt_init, NULL },
#endif
/* Has a standard PS/2 KBC (so, use IBM PS/2 Type 1). */
{ "[8088] Xi8088", "xi8088", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2, 64, 1024, 128, 127, machine_xt_xi8088_init, xi8088_get_device },
{ "[8088] Zenith Data Systems Z-151/152/161","zdsz151", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 64, 0, machine_xt_z151_init, NULL },
{ "[8088] Zenith Data Systems Z-159", "zdsz159", MACHINE_TYPE_8088, CPU_PKG_8088, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 64, 0, machine_xt_z159_init, NULL },
@@ -148,7 +102,6 @@ const machine_t machines[] = {
{ "[8086] Amstrad PPC512/640", "ppc512", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_ppc512_init, ppc512_get_device },
{ "[8086] Compaq Deskpro", "deskpro", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_compaq_deskpro_init, NULL },
{ "[8086] Olivetti M21/24/24SP", "m24", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_xt_m24_init, m24_get_device },
/* Has Olivetti KBC firmware. */
{ "[8086] Olivetti M240", "m240", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_m240_init, NULL },
{ "[8086] Schetmash Iskra-3104", "iskra3104", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_iskra3104_init, NULL },
{ "[8086] Tandy 1000 SL/2", "tandy1000sl2", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO_FIXED, 512, 768, 128, 0, machine_tandy1000sl2_init, tandy1k_sl_get_device },
@@ -158,693 +111,360 @@ const machine_t machines[] = {
{ "[8086] VTech Laser XT3", "lxt3", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 256, 640, 256, 0, machine_xt_lxt3_init, NULL },
#endif
/* 286 XT machines */
#if defined(DEV_BRANCH) && defined(USE_HEDAKA)
{ "[Citygate D30 XT] Hedaka HED-919", "hed919", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 64, 1024, 64, 0, machine_xt_hed919_init, NULL },
#endif
/* 286 AT machines */
/* Has IBM AT KBC firmware. */
{ "[ISA] IBM AT", "ibmat", MACHINE_TYPE_286, CPU_PKG_286, 0, 6000000, 8000000, 0, 0, 0, 0, MACHINE_AT, 256, 15872, 128, 63, machine_at_ibm_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[ISA] IBM PS/1 model 2011", "ibmps1es", MACHINE_TYPE_286, CPU_PKG_286, 0, 10000000, 10000000, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_XTA | MACHINE_VIDEO_FIXED, 512, 16384, 512, 63, machine_ps1_m2011_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[ISA] IBM PS/2 model 30-286", "ibmps2_m30_286", MACHINE_TYPE_286, CPU_PKG_286 | CPU_PKG_486SLC_IBM, 0, 10000000, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_XTA | MACHINE_VIDEO_FIXED, 1024, 16384,1024, 127, machine_ps2_m30_286_init, NULL },
/* Has IBM AT KBC firmware. */
{ "[ISA] IBM XT Model 286", "ibmxt286", MACHINE_TYPE_286, CPU_PKG_286, 0, 6000000, 6000000, 0, 0, 0, 0, MACHINE_AT, 256, 15872, 128, 127, machine_at_ibmxt286_init, NULL },
/* AMI BIOS for a chipset-less machine, most likely has AMI 'F' KBC firmware. */
{ "[ISA] AMI IBM AT", "ibmatami", MACHINE_TYPE_286, CPU_PKG_286, 0, 6000000, 8000000, 0, 0, 0, 0, MACHINE_AT, 256, 15872, 128, 63, machine_at_ibmatami_init, NULL },
/* Uses Commodore (CBM) KBC firmware, to be implemented as identical to the
IBM AT KBC firmware unless evidence emerges of any proprietary commands. */
{ "[ISA] Commodore PC 30 III", "cmdpc30", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 640, 16384, 128, 127, machine_at_cmdpc_init, NULL },
/* Uses Compaq KBC firmware. */
{ "[ISA] Compaq Portable II", "portableii", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 640, 16384, 128, 127, machine_at_portableii_init, NULL },
/* Uses Compaq KBC firmware. */
{ "[ISA] Compaq Portable III", "portableiii", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_VIDEO, 640, 16384, 128, 127, machine_at_portableiii_init, at_cpqiii_get_device },
/* Has IBM AT KBC firmware. */
{ "[ISA] MR 286 clone", "mr286", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 512, 16384, 128, 127, machine_at_mr286_init, NULL },
/* Has IBM AT KBC firmware. */
{ "[ISA] NCR PC8/810/710/3390/3392", "pc8", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 16384, 128, 127, machine_at_pc8_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_OLIVETTI)
/* Has Olivetti KBC firmware. */
{ "[ISA] Olivetti M290", "m290", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 640, 16384, 128, 127, machine_at_m290_init, NULL },
#endif
#if defined(DEV_BRANCH) && defined(USE_OPEN_AT)
/* Has IBM AT KBC firmware. */
#if defined(DEV_BRANCH) && defined(USE_OPEN_AT)
{ "[ISA] OpenAT", "openat", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 256, 15872, 128, 63, machine_at_openat_init, NULL },
#endif
/* Has IBM AT KBC firmware. */
{ "[ISA] Phoenix IBM AT", "ibmatpx", MACHINE_TYPE_286, CPU_PKG_286, 0, 6000000, 8000000, 0, 0, 0, 0, MACHINE_AT, 256, 15872, 128, 63, machine_at_ibmatpx_init, NULL },
/* Has Quadtel KBC firmware. */
{ "[ISA] Quadtel IBM AT", "ibmatquadtel", MACHINE_TYPE_286, CPU_PKG_286, 0, 6000000, 8000000, 0, 0, 0, 0, MACHINE_AT, 256, 15872, 128, 63, machine_at_ibmatquadtel_init, NULL },
/* This has a Siemens proprietary KBC which is completely undocumented. */
{ "[ISA] Siemens PCD-2L", "siemens", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 256, 15872, 128, 63, machine_at_siemens_init, NULL },
/* This has Toshiba's proprietary KBC, which is already implemented. */
{ "[ISA] Toshiba T3100e", "t3100e", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE | MACHINE_VIDEO_FIXED, 1024, 5120, 256, 63, machine_at_t3100e_init, NULL },
/* Has Quadtel KBC firmware. */
{ "[GC103] Quadtel 286 clone", "quadt286", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 16384, 128, 127, machine_at_quadt286_init, NULL },
/* Most likely has AMI 'F' KBC firmware. */
{ "[GC103] Trigem 286M", "tg286m", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 512, 8192, 128, 127, machine_at_tg286m_init, NULL },
/* This has "AMI KEYBOARD BIOS", most likely 'F'. */
{ "[NEAT] Dataexpert 286", "ami286", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_ami_init, NULL },
/* Has IBM AT KBC firmware. */
{ "[NEAT] AMI 286 clone", "ami286", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_ami_init, NULL },
{ "[NEAT] NCR 3302", "3302", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_VIDEO, 512, 16384, 128, 127, machine_at_3302_init, NULL },
/* Has IBM AT KBC firmware. */
{ "[NEAT] Phoenix 286 clone", "px286", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 16384, 128, 127, machine_at_px286_init, NULL },
/* Has Chips & Technologies KBC firmware. */
{ "[SCAT] Award 286 clone", "award286", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 16384, 128, 127, machine_at_award286_init, NULL },
{ "[SCAT] GW-286CT GEAR", "gw286ct", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 512, 16384, 128, 127, machine_at_gw286ct_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[SCAT] Goldstar GDC-212M", "gdc212m", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE | MACHINE_BUS_PS2, 512, 4096, 512, 127, machine_at_gdc212m_init, NULL },
/* Has a VIA VT82C42N KBC. */
{ "[SCAT] Hyundai Solomon 286KP", "award286", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 16384, 128, 127, machine_at_award286_init, NULL },
/* Has a VIA VT82C42N KBC. */
{ "[SCAT] Hyundai Super-286TR", "super286tr", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 16384, 128, 127, machine_at_super286tr_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[SCAT] Samsung SPC-4200P", "spc4200p", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2, 512, 2048, 128, 127, machine_at_spc4200p_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[SCAT] Samsung SPC-4216P", "spc4216p", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2, 1024, 5120,1024, 127, machine_at_spc4216p_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[SCAT] Samsung SPC-4620P", "spc4620p", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_VIDEO, 1024, 5120,1024, 127, machine_at_spc4620p_init, NULL },
/* Has IBM AT KBC firmware. */
{ "[SCAT] Samsung Deskmaster 286", "deskmaster286", MACHINE_TYPE_286, CPU_PKG_286, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 16384, 128, 127, machine_at_deskmaster286_init, NULL },
/* 286 machines that utilize the MCA bus */
/* Has IBM PS/2 Type 2 KBC firmware. */
{ "[MCA] IBM PS/2 model 50", "ibmps2_m50", MACHINE_TYPE_286, CPU_PKG_286 | CPU_PKG_486SLC_IBM, 0, 10000000, 0, 0, 0, 0, 0, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 1024, 10240,1024, 63, machine_ps2_model_50_init, NULL },
/* 386SX machines */
/* ISA slots available because an official IBM expansion for that existed. */
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[ISA] IBM PS/1 model 2121", "ibmps1_2121", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 2048, 6144,1024, 63, machine_ps1_m2121_init, NULL },
/* Has IBM AT KBC firmware. */
{ "[ISA] NCR PC916SX", "pc916sx", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 1024, 16384, 128, 127, machine_at_pc916sx_init, NULL },
/* Has Quadtel KBC firmware. */
{ "[ISA] QTC-SXM KT X20T02/HI", "quadt386sx", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 1024, 16384, 128, 127, machine_at_quadt386sx_init, NULL },
{ "[ISA] IBM PS/1 model 2121", "ibmps1_2121", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO_FIXED, 2048, 6144,1024, 63, machine_ps1_m2121_init, NULL },
{ "[ISA] IBM PS/1 m.2121+ISA", "ibmps1_2121_isa", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 2048, 6144,1024, 63, machine_ps1_m2121_init, NULL },
{ "[ISA] NCR PC916SX", "pc916sx", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 1024, 16384, 128, 127, machine_at_pc916sx_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_M6117)
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[ALi M6117] Acrosser AR-B1375", "arb1375", MACHINE_TYPE_386SX, CPU_PKG_M6117, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 32768,1024, 127, machine_at_arb1375_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[ALi M6117] Acrosser PJ-A511M", "pja511m", MACHINE_TYPE_386SX, CPU_PKG_M6117, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 32768,1024, 127, machine_at_pja511m_init, NULL },
#endif
/* Has an AMI KBC firmware, the only photo of this is too low resolution
for me to read what's on the KBC chip, so I'm going to assume AMI 'F'
based on the other known HT18 AMI BIOS strings. */
{ "[ALi M1217] Flytech 386", "flytech386", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 1024, 16384, 1024, 127, machine_at_flytech386_init, at_flytech386_get_device },
/* Has an AMI KBC firmware, the only photo of this is too low resolution
for me to read what's on the KBC chip, so I'm going to assume AMI 'F'
based on the other known HT18 AMI BIOS strings. */
{ "[ALi M1217] Flytech 386", "flytech386", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE | MACHINE_BUS_PS2 | MACHINE_VIDEO, 1024, 16384, 1024, 127, machine_at_flytech386_init, at_flytech386_get_device },
{ "[HT18] AMA-932J", "ama932j", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE | MACHINE_VIDEO, 512, 8192, 128, 127, machine_at_ama932j_init, at_ama932j_get_device },
/* Has an unknown KBC firmware with commands B8 and BB in the style of
Phoenix MultiKey and AMIKey-3(!), but also commands E1 and EA with
unknown functions. */
{ "[Intel 82335 ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL },
/* Has an AMI Keyboard BIOS PLUS KBC firmware ('8'). */
{ "[Intel 82335] ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL },
{ "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL },
/* Uses Commodore (CBM) KBC firmware, to be implemented as identical to
the IBM PS/2 Type 1 KBC firmware unless evidence emerges of any
proprietary commands. */
{ "[NEAT] Commodore SL386SX-16", "cmdsl386sx16", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 8192, 512, 127, machine_at_cmdsl386sx16_init, NULL },
/* Has IBM AT KBC firmware. */
{ "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 8192, 128, 127, machine_at_neat_init, NULL },
/* Has IBM AT KBC firmware. */
{ "[OPTi 283] Olivetti M300-08", "m30008", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 20000000, 20000000, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 2048, 16384, 2048, 127, machine_at_m30008_init, at_m30008_get_device },
{ "[OPTi 283] Olivetti M300-15", "m30015", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 25000000, 25000000, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 2048, 16384, 2048, 127, machine_at_m30015_init, NULL },
{ "[OPTi 291] DTK PPM-3333P", "awardsx", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 1024, 16384, 1024, 127, machine_at_awardsx_init, NULL },
/* Uses Commodore (CBM) KBC firmware, to be implemented as identical to
the IBM PS/2 Type 1 KBC firmware unless evidence emerges of any
proprietary commands. */
{ "[SCAMP] Commodore SL386SX-25", "cmdsl386sx25", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 1024, 8192, 512, 127, machine_at_cmdsl386sx25_init, at_cmdsl386sx25_get_device },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[SCAMP] Samsung SPC-6033P", "spc6033p", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 2048, 12288, 2048, 127, machine_at_spc6033p_init, at_spc6033p_get_device },
/* Has an unknown AMI KBC firmware, I'm going to assume 'F' until a
photo or real hardware BIOS string is found. */
{ "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 16384, 512, 127, machine_at_kmxc02_init, NULL },
/* Has Quadtel KBC firmware. */
{ "[WD76C10] Amstrad MegaPC", "megapc", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 1024, 32768, 1024, 127, machine_at_wd76c10_init, NULL },
/* 386SX machines which utilize the MCA bus */
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 1024, 8192, 1024, 63, machine_ps2_model_55sx_init, NULL },
/* 486SLC machines */
/* 486SLC machines with just the ISA slot */
/* Has AMIKey H KBC firmware. */
{ "[OPTi 283] RYC Leopard LX", "rycleopardlx", MACHINE_TYPE_486SLC, CPU_PKG_486SLC_IBM, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 16384, 1024, 127, machine_at_rycleopardlx_init, NULL },
/* 386DX machines */
{ "[ACC 2168] AMI 386DX clone", "acc386", MACHINE_TYPE_386DX, CPU_PKG_386DX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 1024, 16384, 1024, 127, machine_at_acc386_init, NULL },
/* Has an AMI Keyboard BIOS PLUS KBC firmware ('8'). */
{ "[C&T 386] ECS 386/32", "ecs386", MACHINE_TYPE_386DX, CPU_PKG_386DX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 1024, 16384, 1024, 127, machine_at_ecs386_init, NULL },
{ "[C&T 386] Samsung SPC-6000A", "spc6000a", MACHINE_TYPE_386DX, CPU_PKG_386DX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_spc6000a_init, NULL },
/* Uses Compaq KBC firmware. */
{ "[ISA] Compaq Portable III (386)", "portableiii386", MACHINE_TYPE_386DX, CPU_PKG_386DX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE | MACHINE_VIDEO, 1024, 14336, 1024, 127, machine_at_portableiii386_init, at_cpqiii_get_device },
/* Has IBM AT KBC firmware. */
{ "[ISA] Micronics 09-00021", "micronics386", MACHINE_TYPE_386DX, CPU_PKG_386DX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 8192, 128, 127, machine_at_micronics386_init, NULL },
/* Has AMIKey F KBC firmware. */
{ "[SiS 310] ASUS ISA-386C", "asus386", MACHINE_TYPE_386DX, CPU_PKG_386DX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 1024, 32768, 1024, 127, machine_at_asus386_init, NULL },
{ "[ISA] Micronics 386 clone", "micronics386", MACHINE_TYPE_386DX, CPU_PKG_386DX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 8192, 128, 127, machine_at_micronics386_init, NULL },
{ "[SiS 310] ASUS ISA-386C", "asus386", MACHINE_TYPE_386DX, CPU_PKG_386DX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 512, 16384, 128, 127, machine_at_asus386_init, NULL },
/* 386DX machines which utilize the MCA bus */
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[MCA] IBM PS/2 model 70 (type 3)", "ibmps2_m70_type3", MACHINE_TYPE_386DX, CPU_PKG_386DX | CPU_PKG_486BL, 0, 0, 0, 0, 0, 0, 0, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 2048, 16384, 2048, 63, machine_ps2_model_70_type3_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[MCA] IBM PS/2 model 80", "ibmps2_m80", MACHINE_TYPE_386DX, CPU_PKG_386DX | CPU_PKG_486BL, 0, 0, 0, 0, 0, 0, 0, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 1024, 12288, 1024, 63, machine_ps2_model_80_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[MCA] IBM PS/2 model 80 (type 3)", "ibmps2_m80_type3", MACHINE_TYPE_386DX, CPU_PKG_386DX | CPU_PKG_486BL, 0, 0, 0, 0, 0, 0, 0, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 2048, 12288, 2048, 63, machine_ps2_model_80_axx_init, NULL },
{ "[MCA] IBM PS/2 model 80 (type 3)", "ibmps2_m80_type3", MACHINE_TYPE_386DX, CPU_PKG_386DX | CPU_PKG_486BL, 0, 0, 0, 0, 0, 0, 0, MACHINE_MCA | MACHINE_BUS_PS2 | MACHINE_VIDEO, 2048, 12288, 2048, 63, machine_ps2_model_80_axx_init, NULL },
/* 386DX/486 machines */
/* The BIOS sends commands C9 without a parameter and D5, both of which are
Phoenix MultiKey commands. */
{ "[OPTi 495] Award 486 clone", "award495", MACHINE_TYPE_386DX_486, CPU_PKG_386DX | CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_opti495_init, NULL },
/* Has AMIKey F KBC firmware. */
{ "[OPTi 495] Dataexpert SX495", "ami495", MACHINE_TYPE_386DX_486, CPU_PKG_386DX | CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_opti495_ami_init, NULL },
/* Has AMIKey F KBC firmware (it's just the MR BIOS for the above machine). */
{ "[OPTi 495] Dataexpert SX495 (MR BIOS)", "mr495", MACHINE_TYPE_386DX_486, CPU_PKG_386DX | CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_opti495_mr_init, NULL },
{ "[OPTi 495] Award 486 clone", "award486", MACHINE_TYPE_386DX_486, CPU_PKG_386DX | CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_opti495_init, NULL },
{ "[OPTi 495] Dataexpert SX495 (486)", "ami486", MACHINE_TYPE_386DX_486, CPU_PKG_386DX | CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_opti495_ami_init, NULL },
{ "[OPTi 495] MR 486 clone", "mr486", MACHINE_TYPE_386DX_486, CPU_PKG_386DX | CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_opti495_mr_init, NULL },
/* 486 machines - Socket 1 */
/* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F.
It also has those Ex commands also seen on the VIA VT82C42N (the BIOS
supposedly sends command EF.
The board was also seen in 2003 with a -H string - perhaps someone swapped
the KBC? */
{ "[ALi M1429] Olystar LIL1429", "ali1429", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_ali1429_init, NULL },
/* Has JetKey 5 KBC Firmware - but the BIOS string ends in a hardcoded -F, and
the BIOS also explicitly expects command A1 to return a 'F', so it looks like
the JetKey 5 is a clone of AMIKey type F. */
{ "[CS4031] AMI 486 CS4031", "cs4031", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB, 1024, 65536, 1024, 127, machine_at_cs4031_init, NULL },
/* Uses some variant of Phoenix MultiKey/42 as the Intel 8242 chip has a Phoenix
copyright. */
{ "[ETEQ ET6000] Olivetti PCS-46C", "pcs46c", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE | MACHINE_VIDEO, 4096, 32768, 4096, 127, machine_at_pcs46c_init, at_pcs46c_get_device },
{ "[OPTi 895] Mylex MVI486", "mvi486", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE_DUAL, 1024, 65536, 1024, 127, machine_at_mvi486_init, NULL },
/* Has AMI KF KBC firmware. */
{ "[SiS 401] ASUS ISA-486", "isa486", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_isa486_init, NULL },
/* Has AMIKey H KBC firmware, per the screenshot in "How computers & MS-DOS work". */
{ "[SiS 401] Chaintech 433SC", "sis401", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_sis401_init, NULL },
/* Has AMIKey F KBC firmware, per a photo of a monitor with the BIOS screen on
eBay. */
{ "[SiS 460] ABIT AV4", "av4", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_av4_init, NULL },
/* Has a MR (!) KBC firmware, which is a clone of the standard IBM PS/2 KBC firmware. */
{ "[SiS 471] SiS VL-BUS 471 REV. A1", "px471", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024,131072, 1024, 127, machine_at_px471_init, NULL },
/* The chip is a Lance LT38C41, a clone of the Intel 8041, and the BIOS sends
commands BC, BD, and C9 which exist on both AMIKey and Phoenix MultiKey/42,
but it does not write a byte after C9, which is consistent with AMIKey, so
this must have some form of AMIKey. */
{ "[VIA VT82C495] FIC 486-VC-HD", "486vchd", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT, 1024, 64512, 1024, 127, machine_at_486vchd_init, NULL },
/* According to Deksor on the Win3x.org forum, the BIOS string ends in a -0,
indicating an unknown KBC firmware. But it does send the AMIKey get version
command, so it must expect an AMIKey. */
{ "[VLSI 82C480] HP Vectra 486VL", "vect486vl", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 2048, 32768, 2048, 127, machine_at_vect486vl_init, at_vect486vl_get_device },
/* Has a standard IBM PS/2 KBC firmware or a clone thereof. */
{ "[VLSI 82C481] Siemens Nixdorf D824", "d824", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 2048, 32768, 2048, 127, machine_at_d824_init, at_d824_get_device },
/* 486 machines - Socket 2 */
/* 486 machines with just the ISA slot */
/* Uses some variant of Phoenix MultiKey/42 as the BIOS sends keyboard controller
command C7 (OR input byte with received data byte). */
{ "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486_S2, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 4096, 36864, 1024, 127, machine_at_pb410a_init, NULL },
/* Uses an ACER/NEC 90M002A (UPD82C42C, 8042 clone) with unknown firmware (V4.01H). */
{ "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486_S2, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 4096, 36864, 1024, 127, machine_at_acera1g_init, at_acera1g_get_device },
/* There are two similar BIOS strings with -H, and one with -U, so I'm going to
give it an AMIKey H KBC firmware. */
{ "[ALi M1429G] AMI WinBIOS 486", "win486", MACHINE_TYPE_486_S2, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_winbios1429_init, NULL },
/* Uses an NEC 90M002A (UPD82C42C, 8042 clone) with unknown firmware. */
{ "[SiS 461] Acer V10", "acerv10", MACHINE_TYPE_486_S2, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 1024, 32768, 1024, 127, machine_at_acerv10_init, NULL },
/* The BIOS does not send any non-standard keyboard controller commands and wants
a PS/2 mouse, so it's an IBM PS/2 KBC (Type 1) firmware. */
{ "[SiS 461] IBM PS/ValuePoint 433DX/Si", "valuepoint433", MACHINE_TYPE_486_S2, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 1024, 65536, 1024, 127, machine_at_valuepoint433_init, NULL },
/* The BIOS string ends in -U, unless command 0xA1 (AMIKey get version) returns an
'F', in which case, it ends in -F, so it has an AMIKey F KBC firmware.
The photo of the board shows an AMIKey KBC which is indeed F. */
{ "[SiS 471] ABit AB-AH4", "win471", MACHINE_TYPE_486_S2, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_win471_init, NULL },
{ "[VLSI 82C481] Siemens Nixdorf D824", "d824", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 2048, 32768, 2048, 127, machine_at_d824_init, at_d824_get_device },
/* 486 machines - Socket 3 */
/* 486 machines with just the ISA slot */
/* Has a VIA VT82C42N KBC. */
{ "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 4096, 36864, 1024, 127, machine_at_pb410a_init, NULL },
{ "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 4096, 36864, 1024, 127, machine_at_acera1g_init, at_acera1g_get_device },
{ "[ALi M1429] AMI WinBIOS 486", "win486", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_winbios1429_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB, 1024, 65536, 1024, 127, machine_at_403tg_init, NULL },
/* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F. */
{ "[OPTi 895] Jetway J-403TG Rev D", "403tg_rev_d", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB, 1024, 65536, 1024, 127, machine_at_403tg_rev_d_init, NULL },
/* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F. */
{ "[OPTi 895] Jetway J-403TG Rev D (MR BIOS)","403tg_rev_d_mr", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB, 1024, 65536, 1024, 127, machine_at_403tg_rev_d_mr_init, NULL },
/* Has AMIKey H keyboard BIOS. */
{ "[SiS 401] AMI 486 Clone", "sis401", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_sis401_init, NULL },
{ "[SiS 401] ASUS ISA-486", "isa486", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_isa486_init, NULL },
{ "[SiS 460] ABIT AV4", "av4", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_av4_init, NULL },
{ "[SiS 461] IBM PS/ValuePoint 433DX/Si", "valuepoint433", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 1024, 65536, 1024, 127, machine_at_valuepoint433_init, NULL },
{ "[SiS 471] AMI 486 Clone", "ami471", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_ami471_init, NULL },
{ "[SiS 471] AMI WinBIOS 486 clone", "win471", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_win471_init, NULL },
{ "[SiS 471] AOpen Vi15G", "vi15g", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_vi15g_init, NULL },
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[SiS 471] ASUS VL/I-486SV2G (GX4)", "vli486sv2g", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 1024, 65536, 1024, 127, machine_at_vli486sv2g_init, NULL },
/* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F. */
{ "[SiS 471] ASUS VL/I-486SV2G (GX4)", "vli486sv2g", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE_DUAL, 1024, 65536, 1024, 127, machine_at_vli486sv2g_init, NULL },
{ "[SiS 471] DTK PKM-0038S E-2", "dtk486", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_dtk486_init, NULL },
/* Unknown Epox VLB Socket 3 board, has AMIKey F keyboard BIOS. */
{ "[SiS 471] Epox 486SX/DX Green", "ami471", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_ami471_init, NULL },
{ "[SiS 471] Phoenix SiS 471", "px471", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024,131072, 1024, 127, machine_at_px471_init, NULL },
/* 486 machines which utilize the PCI bus */
/* Has the ALi M1487/9's on-chip keyboard controller which clones a standard AT
KBC. */
{ "[ALi M1489] ABIT AB-PB4", "abpb4", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_abpb4_init, NULL },
/* Has the ALi M1487/9's on-chip keyboard controller which clones a standard AT
KBC.
The BIOS string always ends in -U, but the BIOS will send AMIKey commands 0xCA
and 0xCB if command 0xA1 returns a letter in the 0x5x or 0x7x ranges, so I'm
going to give it an AMI 'U' KBC. */
{ "[ALi M1489] AMI WinBIOS 486 PCI", "win486pci", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_win486pci_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[OPTi 802G] IBM PC 330 (type 6573)", "pc330_6573", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3_PC330, 0, 25000000, 33333333, 0, 0, 2.0, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_pc330_6573_init, NULL },
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[i420EX] ASUS PVI-486AP4", "486ap4", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCIV | MACHINE_IDE_DUAL, 1024, 131072, 1024, 127, machine_at_486ap4_init, NULL },
/* This has the Phoenix MultiKey KBC firmware. */
{ "[i420EX] Intel Classic/PCI ED", "ninja", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 1024, 131072, 1024, 127, machine_at_ninja_init, NULL },
/* This has an AMIKey-2, which is an updated version of type 'H'. Also has a
SST 29EE010 Flash chip. */
{ "[i420ZX] ASUS PCI/I-486SP3G", "486sp3g", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL | MACHINE_SCSI, 1024, 131072, 1024, 127, machine_at_486sp3g_init, NULL },
/* I'm going to assume this as an AMIKey-2 like the other two 486SP3's. */
{ "[i420TX] ASUS PCI/I-486SP3", "486sp3", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL | MACHINE_SCSI, 1024, 131072, 1024, 127, machine_at_486sp3_init, NULL },
/* This has the Phoenix MultiKey KBC firmware. */
{ "[i420TX] Intel Classic/PCI", "alfredo", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_alfredo_init, NULL },
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[SiS 496] ASUS PVI-486SP3C", "486sp3c", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCIV | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_486sp3c_init, NULL },
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[SiS 496] Lucky Star LS-486E", "ls486e", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_ls486e_init, NULL },
/* The BIOS does not send a single non-standard KBC command, so it has a standard PS/2 KBC. */
{ "[SiS 496] Micronics M4Li", "m4li", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 1024, 131072, 1024, 127, machine_at_m4li_init, NULL },
/* Has a BestKey KBC which clones AMI type 'H'. */
{ "[SiS 496] Rise Computer R418", "r418", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_r418_init, NULL },
/* This has a Holtek KBC and the BIOS does not send a single non-standard KBC command, so it
must be an ASIC that clones the standard IBM PS/2 KBC. */
{ "[SiS 496] Soyo 4SA2", "4sa2", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, CPU_BLOCK(CPU_i486SX, CPU_i486DX, CPU_Am486SX, CPU_Am486DX), 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_4sa2_init, NULL },
/* According to MrKsoft, his real 4DPS has an AMIKey-2, which is an updated version
of type 'H'. */
{ "[SiS 496] Zida Tomato 4DP", "4dps", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_4dps_init, NULL },
/* Has a VIA VT82C406 KBC+RTC that likely has identical commands to the VT82C42N. */
{ "[VIA VT82C496G] DFI G486VPA", "g486vpa", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCIV | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_g486vpa_init, NULL },
/* Has a VIA VT82C42N KBC. */
{ "[UMC 8881] A-Trend ATC-1415", "atc1415", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_atc1415_init, NULL },
{ "[UMC 8881] ECS Elite UM8810PAIO", "ecs486", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_ecs486_init, NULL },
{ "[UMC 8881] Shuttle HOT-433A", "hot433", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 262144, 1024, 255, machine_at_hot433_init, NULL },
{ "[VIA VT82C496G] FIC VIP-IO2", "486vipio2", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCIV | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_486vipio2_init, NULL },
/* 486 machines - Miscellaneous */
/* 486 machines with just the ISA slot */
{ "[OPTi 283] RYC Leopard LX", "rycleopardlx", MACHINE_TYPE_486_MISC, CPU_PKG_486SLC_IBM, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 16384, 1024, 127, machine_at_rycleopardlx_init, NULL },
/* 486 machines which utilize the PCI bus */
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[STPC Client] ITOX STAR", "itoxstar", MACHINE_TYPE_486_MISC, CPU_PKG_STPC, 0, 66666667, 75000000, 0, 0, 1.0, 1.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 255, machine_at_itoxstar_init, NULL },
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[STPC Consumer-II] Acrosser AR-B1479", "arb1479", MACHINE_TYPE_486_MISC, CPU_PKG_STPC, 0, 66666667, 66666667, 0, 0, 2.0, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 32768, 163840, 8192, 255, machine_at_arb1479_init, NULL },
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[STPC Elite] Advantech PCM-9340", "pcm9340", MACHINE_TYPE_486_MISC, CPU_PKG_STPC, 0, 66666667, 66666667, 0, 0, 2.0, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 32768, 98304, 8192, 255, machine_at_pcm9340_init, NULL },
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[STPC Atlas] AAEON PCM-5330", "pcm5330", MACHINE_TYPE_486_MISC, CPU_PKG_STPC, 0, 66666667, 66666667, 0, 0, 2.0, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 32768, 131072,32768, 255, machine_at_pcm5330_init, NULL },
/* Socket 4 machines */
/* 430LX */
/* Has AMIKey F KBC firmware (AMIKey). */
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 196608, 2048, 127, machine_at_p5mp3_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 131072, 2048, 127, machine_at_dellxp60_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[i430LX] Dell OptiPlex 560/L", "opti560l", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_opti560l_init, NULL },
/* This has the Phoenix MultiKey KBC firmware.
This is basically an Intel Batman (*NOT* Batman's Revenge) with a fancier
POST screen */
{ "[i430LX] AMBRA DP60 PCI", "ambradp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_ambradp60_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_valuepointp60_init, NULL },
/* This has the Phoenix MultiKey KBC firmware. */
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_revenge_init, NULL },
/* Has AMI MegaKey KBC firmware. */
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_batman_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_586mc1_init, NULL },
/* This has the Phoenix MultiKey KBC firmware. */
{ "[i430LX] Packard Bell PB520R", "pb520r", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 139264, 2048, 127, machine_at_pb520r_init, at_pb520r_get_device },
/* OPTi 596/597 */
/* This uses an AMI KBC firmware in PS/2 mode (it sends command A5 with the
PS/2 "Load Security" meaning), most likely MegaKey as it sends command AF
(Set Extended Controller RAM) just like the later Intel AMI BIOS'es. */
{ "[OPTi 597] AMI Excalibur VLB", "excalibur", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_VLB | MACHINE_IDE, 2048, 65536, 2048, 127, machine_at_excalibur_init, NULL },
/* OPTi 596/597/822 */
/* This has AMIKey 'F' KBC firmware. */
{ "[OPTi 597] Supermicro P5VL-PCI", "p5vl", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_VLB, 8192, 131072, 8192, 127, machine_at_p5vl_init, NULL },
/* SiS 85C50x */
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[SiS 85C50x] ASUS PCI/I-P5SP4", "p5sp4", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p5sp4_init, NULL },
/* Socket 5 machines */
/* 430NX */
/* This has the Phoenix MultiKey KBC firmware. */
{ "[i430NX] Intel Premiere/PCI II", "plato", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_plato_init, NULL },
/* This has the Phoenix MultiKey KBC firmware.
This is basically an Intel Premiere/PCI II with a fancier POST screen. */
{ "[i430NX] AMBRA DP90 PCI", "ambradp90", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_ambradp90_init, NULL },
/* Has AMI MegaKey KBC firmware. */
{ "[i430NX] Gigabyte GA-586IP", "430nx", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_430nx_init, NULL },
/* 430FX */
/* Uses an ACER/NEC 90M002A (UPD82C42C, 8042 clone) with unknown firmware (V5.0). */
{ "[i430FX] Acer V30", "acerv30", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_acerv30_init, NULL },
/* Has AMIKey F KBC firmware. */
{ "[i430FX] AMI Apollo", "apollo", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_apollo_init, NULL },
/* Has AMIKey H KBC firmware. */
{ "[i430FX] Dataexpert EXP8551", "exp8551", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_exp8551_init, NULL },
/* The BIOS does not send a single non-standard KBC command, but the board has a SMC Super I/O
chip with on-chip KBC and AMI MegaKey KBC firmware. */
{ "[i430FX] HP Vectra VL 5 Series 4", "vectra54", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 511, machine_at_vectra54_init, at_vectra54_get_device },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430FX] Intel Advanced/ZP", "zappa", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_zappa_init, NULL },
/* The BIOS sends KBC command B3 which indicates an AMI (or VIA VT82C42N) KBC. */
{ "[i430FX] NEC PowerMate V", "powermatev", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_powermatev_init, NULL },
/* Has a VIA VT82C42N KBC. */
{ "[i430FX] PC Partner MB500N", "mb500n", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mb500n_init, NULL },
/* Has AMIKey Z(!) KBC firmware. */
{ "[i430FX] Trigem Hawk", "hawk", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_hawk_init, NULL },
/* OPTi 596/597 */
/* This uses an AMI KBC firmware in PS/2 mode (it sends command A5 with the
PS/2 "Load Security" meaning), most likely MegaKey as it sends command AF
(Set Extended Controller RAM) just like the later Intel AMI BIOS'es. */
{ "[OPTi 597] TMC PAT54PV", "pat54pv", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_K5, CPU_5K86), 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_VLB, 2048, 65536, 2048, 127, machine_at_pat54pv_init, NULL },
/* OPTi 596/597/822 */
{ "[OPTi 597] Shuttle HOT-543", "hot543", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_VLB, 8192, 131072, 8192, 127, machine_at_hot543_init, NULL },
{ "[OPTi 597] Supermicro P54VL-PCI", "p54vl", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_VLB, 8192, 131072, 8192, 127, machine_at_p54vl_init, NULL },
/* SiS 85C50x */
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[SiS 85C50x] ASUS PCI/I-P54SP4", "p54sp4", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_K5, CPU_5K86), 40000000, 66666667, 3380, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54sp4_init, NULL },
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[SiS 85C50x] BCM SQ-588", "sq588", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_PENTIUMMMX), 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_sq588_init, NULL },
/* UMC 889x */
{ "[UMC 889x] Shuttle HOT-539", "hot539", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_K5, CPU_5K86), 40000000, 66666667, 3380, 3600, 1.5, 2.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 262144, 8192, 127, machine_at_hot539_init, NULL },
/* Socket 7 (Single Voltage) machines */
/* 430FX */
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[i430FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3600, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54tp4xe_init, NULL },
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[i430FX] ASUS P/I-P54TP4XE (MR BIOS)", "mr586", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3600, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mr586_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430FX] Gateway 2000 Thor", "gw2katx", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_gw2katx_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430FX] Intel Advanced/ATX", "thor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_thor_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430FX] Intel Advanced/ATX (MR BIOS)", "mrthor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_mrthor_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430FX] Intel Advanced/EV", "endeavor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_endeavor_init, at_endeavor_get_device },
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[i430FX] MSI MS-5119", "ms5119", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_ms5119_init, NULL },
/* This most likely uses AMI MegaKey KBC firmware as well due to having the same
Super I/O chip (that has the KBC firmware on it) as eg. the Advanced/EV. */
{ "[i430FX] Packard Bell PB640", "pb640", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_pb640_init, at_pb640_get_device },
/* Has an AMI 'H' KBC firmware (1992). */
{ "[i430FX] QDI FMB", "fmb", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_WINCHIP, CPU_WINCHIP2, CPU_Cx6x86, CPU_Cx6x86L, CPU_Cx6x86MX), 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_fmb_init, NULL },
{ "[i430FX] QDI Chariot", "chariot", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_WINCHIP, CPU_WINCHIP2, CPU_Cx6x86, CPU_Cx6x86L, CPU_Cx6x86MX), 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_chariot_init, NULL },
/* 430HX */
/* I can't determine what KBC firmware this has, but given that the Acer V35N and
V60 have Phoenix MultiKey KBC firmware on the chip, I'm going to assume so
does the M3A. */
{ "[i430HX] Acer M3A", "acerm3a", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3300, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_acerm3a_init, NULL },
/* Has AMIKey F KBC firmware. */
{ "[i430HX] AOpen AP53", "ap53", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3450, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_ap53_init, NULL },
/* [TEST] Has a VIA 82C42N KBC, with AMIKey F KBC firmware. */
{ "[i430HX] Biostar MB-8500TUC", "8500tuc", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_8500tuc_init, NULL },
/* [TEST] Unable to determine what KBC this has. A list on a Danish site shows
the BIOS as having a -0 string, indicating non-AMI KBC firmware. */
{ "[i430HX] SuperMicro Super P55T2S", "p55t2s", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3300, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 127, machine_at_p55t2s_init, NULL },
/* 430VX */
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430VX] Gateway 2000 Tigereye", "gw2kte", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_gw2kte_init, NULL },
/* SiS 5511 */
/* Has AMIKey H KBC firmware (AMIKey-2). */
{ "[SiS 5511] AOpen AP5S", "ap5s", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_ap5s_init, NULL },
{ "[SiS 5511] AOpen AP5S", "ap5s", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_ap5s_init, NULL },
/* Socket 7 (Dual Voltage) machines */
/* 430HX */
/* Has SST flash and the SMC FDC73C935's on-chip KBC with Phoenix MultiKey firmware. */
{ "[i430HX] Acer V35N", "acerv35n", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_Cx6x86MX), 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_acerv35n_init, NULL },
/* Has AMIKey H KBC firmware (AMIKey-2). */
{ "[i430HX] ASUS P/I-P55T2P4", "p55t2p4", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 83333333, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 127, machine_at_p55t2p4_init, NULL },
/* Has the SMC FDC73C935's on-chip KBC with Phoenix MultiKey firmware. */
{ "[i430HX] Micronics M7S-Hi", "m7shi", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 511, machine_at_m7shi_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430HX] Intel TC430HX", "tc430hx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 255, machine_at_tc430hx_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430HX] Toshiba Equium 5200D", "equium5200", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_equium5200_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI .
Yes, this is an Intel AMI BIOS with a fancy splash screen. */
{ "[i430HX] Sony Vaio PCV-240", "pcv240", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_pcv240_init, NULL },
/* The base board has AMIKey-2 (updated 'H') KBC firmware. */
{ "[i430HX] ASUS P/I-P65UP5 (C-P55T2D)", "p65up5_cp55t2d", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_p65up5_cp55t2d_init, NULL },
/* 430VX */
/* Has AMIKey H KBC firmware (AMIKey-2). */
{ "[i430VX] ASUS P/I-P55TVP4", "p55tvp4", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p55tvp4_init, NULL },
/* The BIOS does not send a single non-standard KBC command, so it must have a standard IBM
PS/2 KBC firmware or a clone thereof. */
{ "[i430VX] Azza 5IVG", "5ivg", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_5ivg_init, NULL },
/* [TEST] Has AMIKey 'F' KBC firmware. */
{ "[i430VX] Biostar MB-8500TVX-A", "8500tvxa", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2600, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_8500tvxa_init, NULL },
/* The BIOS does not send a single non-standard KBC command, but the board has a SMC Super I/O
chip with on-chip KBC and AMI MegaKey KBC firmware. */
{ "[i430VX] Compaq Presario 2240", "presario2240", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_presario2240_init, NULL },
/* This most likely has AMI MegaKey as above. */
{ "[i430VX] Compaq Presario 4500", "presario4500", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_presario4500_init, NULL },
/* The BIOS sends KBC command CB which is an AMI KBC command, so it has an AMI KBC firmware. */
{ "[i430VX] Epox P55-VA", "p55va", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p55va_init, NULL },
/* The BIOS does not send a single non-standard KBC command. */
{ "[i430VX] HP Brio 80xx", "brio80xx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 66666667, 66666667, 2200, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_brio80xx_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430VX] Packard Bell PB680", "pb680", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_pb680_init, NULL },
/* This has the AMIKey 'H' firmware, possibly AMIKey-2. Photos show it with a BestKey, so it
likely clones the behavior of AMIKey 'H'. */
{ "[i430VX] PC Partner MB520N", "mb520n", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2600, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mb520n_init, NULL },
/* This has a Holtek KBC and the BIOS does not send a single non-standard KBC command, so it
must be an ASIC that clones the standard IBM PS/2 KBC. */
{ "[i430VX] Shuttle HOT-557", "430vx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_GAMEPORT, 8192, 131072, 8192, 127, machine_at_i430vx_init, NULL },
/* 430TX */
/* The BIOS sends KBC command B8, CA, and CB, so it has an AMI KBC firmware. */
{ "[i430TX] ADLink NuPRO-592", "nupro592", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 66666667, 66666667, 1900, 2800, 1.5, 5.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_nupro592_init, NULL },
/* This has the AMIKey KBC firmware, which is an updated 'F' type (YM430TX is based on the TX97). */
{ "[i430TX] ASUS TX97", "tx97", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 75000000, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_tx97_init, NULL },
#if defined(DEV_BRANCH) && defined(NO_SIO)
/* This has the Phoenix MultiKey KBC firmware. */
{ "[i430TX] Intel AN430TX", "an430tx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_an430tx_init, NULL },
#endif
/* This has the AMIKey KBC firmware, which is an updated 'F' type. */
{ "[i430TX] Intel YM430TX", "ym430tx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_ym430tx_init, NULL },
/* The BIOS sends KBC command BB and expects it to output a byte, which is AMI KBC behavior. */
{ "[i430TX] PC Partner MB540N", "mb540n", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 2700, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_mb540n_init, NULL },
/* [TEST] Has AMIKey 'H' KBC firmware. */
{ "[i430TX] SuperMicro Super P5MMS98", "p5mms98", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2100, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_p5mms98_init, NULL },
/* Apollo VPX */
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA VPX] FIC VA-502", "ficva502", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 75000000, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_ficva502_init, NULL },
/* Apollo VP3 */
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA VP3] FIC PA-2012", "ficpa2012", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 55000000, 75000000, 2100, 3520, 1.5, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 127, machine_at_ficpa2012_init, NULL },
/* SiS 5571 */
/* Has the SiS 5571 chipset with on-chip KBC. */
{ "[SiS 5571] Rise R534F", "r534f", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 393216, 8192, 127, machine_at_r534f_init, NULL },
/* Has the SiS 5571 chipset with on-chip KBC. */
{ "[SiS 5571] MSI MS-5146", "ms5146", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 127, machine_at_ms5146_init, NULL },
/* SiS 5598 */
{ "[SiS 5598] ASUS SP97-XV", "sp97xv", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 2100, 3200, 1.5, 2.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_sp97xv_init, NULL },
{ "[SiS 5598] PC Chips M571", "m571", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 75000000, 2500, 3500, 1.5, 3.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_m571_init, NULL },
/* ALi ALADDiN IV */
/* Has the ALi M1543 southbridge with on-chip KBC. */
#if defined(DEV_BRANCH) && defined(USE_M154X)
{ "[ALi ALADDiN IV] PC Chips M560", "m560", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 83333333, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_m560_init, NULL },
/* Has the ALi M1543 southbridge with on-chip KBC. */
{ "[ALi ALADDiN IV] MSI MS-5164", "ms5164", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 2100, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_ms5164_init, NULL },
#endif
/* Super Socket 7 machines */
/* Apollo MVP3 */
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA MVP3] AOpen AX59 Pro", "ax59pro", MACHINE_TYPE_SOCKETS7, CPU_PKG_SOCKET5_7, 0, 66666667, 124242424, 1300, 3520, 1.5, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_ax59pro_init, NULL },
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA MVP3] FIC VA-503+", "ficva503p", MACHINE_TYPE_SOCKETS7, CPU_PKG_SOCKET5_7, 0, 66666667, 124242424, 2000, 3200, 1.5, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_mvp3_init, NULL },
/* Has the VIA VT82C686A southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA MVP3] FIC VA-503A", "ficva503a", MACHINE_TYPE_SOCKETS7, CPU_PKG_SOCKET5_7, 0, 66666667, 124242424, 1800, 3100, 1.5, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_ficva503a_init, NULL },
/* Socket 8 machines */
/* 450KX */
#if defined(DEV_BRANCH) && defined(USE_I450KX)
/* This has an AMIKey, which is an updated version of type 'F'. */
{ "[i450KX] ASUS P/I-P6RP4", "p6rp4", MACHINE_TYPE_SOCKET8, CPU_PKG_SOCKET8, 0, 60000000, 66666667, 2100, 3500, 1.5, 8.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_p6rp4_init, NULL },
#endif
/* 440FX */
/* Has the SMC FDC73C935's on-chip KBC with Phoenix MultiKey firmware. */
{ "[i440FX] Acer V60N", "v60n", MACHINE_TYPE_SOCKET8, CPU_PKG_SOCKET8, 0, 60000000, 66666667, 2500, 3500, 1.5, 8.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_v60n_init, NULL },
/* The base board has AMIKey-2 (updated 'H') KBC firmware. */
{ "[i440FX] ASUS P/I-P65UP5 (C-P6ND)", "p65up5_cp6nd", MACHINE_TYPE_SOCKET8, CPU_PKG_SOCKET8, 0, 60000000, 66666667, 2100, 3500, 1.5, 8.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 127, machine_at_p65up5_cp6nd_init, NULL },
/* The MB-8600TTX has an AMIKey 'F' KBC firmware, so I'm going to assume so does
the MB-8600TTC until someone can actually identify it. */
{ "[i440FX] Biostar MB-8600TTC", "8600ttc", MACHINE_TYPE_SOCKET8, CPU_PKG_SOCKET8, 0, 50000000, 66666667, 2900, 3300, 2.0, 5.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 127, machine_at_8500ttc_init, NULL },
{ "[i440FX] Gigabyte GA-686NX", "686nx", MACHINE_TYPE_SOCKET8, CPU_PKG_SOCKET8, 0, 60000000, 66666667, 2100, 3500, 2.0, 5.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_686nx_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i440FX] Intel AP440FX", "ap440fx", MACHINE_TYPE_SOCKET8, CPU_PKG_SOCKET8, 0, 60000000, 66666667, 2100, 3500, 2.0, 3.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_ap440fx_init, NULL },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i440FX] Intel VS440FX", "vs440fx", MACHINE_TYPE_SOCKET8, CPU_PKG_SOCKET8, 0, 60000000, 66666667, 2100, 3500, 2.0, 3.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_vs440fx_init, NULL },
/* Has the SMC FDC73C935's on-chip KBC with Phoenix MultiKey firmware. */
{ "[i440FX] Micronics M6Mi", "m6mi", MACHINE_TYPE_SOCKET8, CPU_PKG_SOCKET8, 0, 60000000, 66666667, 2900, 3300, 1.5, 8.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 127, machine_at_m6mi_init, NULL },
/* I found a BIOS string of it that ends in -S, but it could be a typo for -5
(there's quite a few AMI BIOS strings around with typo'd KBC codes), so I'm
going to give it an AMI MegaKey. */
{ "[i440FX] PC Partner MB600N", "mb600n", MACHINE_TYPE_SOCKET8, CPU_PKG_SOCKET8, 0, 60000000, 66666667, 2100, 3500, 1.5, 8.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_mb600n_init, NULL },
/* Slot 1 machines */
/* 440FX */
/* The base board has AMIKey-2 (updated 'H') KBC firmware. */
{ "[i440FX] ASUS P/I-P65UP5 (C-PKND)", "p65up5_cpknd", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 50000000, 66666667, 1800, 3500, 1.5, 8.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 127, machine_at_p65up5_cpknd_init, NULL },
/* This has a Holtek KBC and the BIOS does not send a single non-standard KBC command, so it
must be an ASIC that clones the standard IBM PS/2 KBC. */
{ "[i440FX] ASUS KN97", "kn97", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 60000000, 83333333, 1800, 3500, 1.5, 8.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 127, machine_at_kn97_init, NULL },
/* 440LX */
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440LX] ABIT LX6", "lx6", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 60000000, 100000000, 1500, 3500, 2.0, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_lx6_init, NULL },
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey KBC firmware. */
{ "[i440LX] Micronics Spitfire", "spitfire", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 66666667, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_spitfire_init, NULL },
/* 440EX */
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440EX] QDI EXCELLENT II", "p6i440e2", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 83333333, 1800, 3500, 3.0, 8.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 255, machine_at_p6i440e2_init, NULL },
/* 440BX */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] ASUS P2B-LS", "p2bls", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 50000000, 112121212, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_p2bls_init, NULL },
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] ASUS P3B-F", "p3bf", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 150000000, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_p3bf_init, NULL },
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] ABIT BF6", "bf6", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 133333333, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_bf6_init, NULL },
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] AOpen AX6BC", "ax6bc", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 112121212, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_ax6bc_init, NULL },
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] Gigabyte GA-686BX", "686bx", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_686bx_init, NULL },
/* Has a SM(S)C FDC37M60x Super I/O chip with on-chip KBC with most likely
AMIKey-2 KBC firmware. */
{ "[i440BX] HP Vectra VEi 8", "vei8", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_vei8_init, NULL },
/* Has a National Semiconductors PC87309 Super I/O chip with on-chip KBC
with most likely AMIKey-2 KBC firmware. */
{ "[i440BX] Tyan Tsunami ATX", "tsunamiatx", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 112121212, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_SOUND, 8192,1048576, 8192, 255, machine_at_tsunamiatx_init, at_tsunamiatx_get_device },
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] SuperMicro Super P6SBA", "p6sba", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_p6sba_init, NULL },
#if defined(DEV_BRANCH) && defined(NO_SIO)
{ "[i440BX] Fujitsu ErgoPro x365", "ergox365", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 393216, 8192, 511, machine_at_ergox365_init, NULL },
#endif
/* 440ZX */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440ZX] MSI MS-6168", "ms6168", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_SOUND,8192, 524288, 8192, 255, machine_at_ms6168_init, NULL },
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440ZX] Packard Bell Bora Pro", "borapro", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 66666667, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_SOUND,8192, 524288, 8192, 255, machine_at_borapro_init, NULL },
/* SMSC VictoryBX-66 */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[SMSC VictoryBX-66] A-Trend ATC6310BXII","atc6310bxii", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 133333333, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_atc6310bxii_init, NULL },
/* VIA Apollo Pro */
/* Has the VIA VT82C596B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA Apollo Pro] FIC KA-6130", "ficka6130", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 255, machine_at_ficka6130_init, NULL },
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[VIA Apollo Pro133] ASUS P3V133", "p3v133", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 150000000, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1572864, 8192, 255, machine_at_p3v133_init, NULL },
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[VIA Apollo Pro133A] ASUS P3V4X", "p3v4x", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 150000000, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,2097152, 8192, 255, machine_at_p3v4x_init, NULL },
/* Slot 1/2 machines */
/* 440GX */
/* Has a National Semiconductors PC87309 Super I/O chip with on-chip KBC
with most likely AMIKey-2 KBC firmware. */
{ "[i440GX] Freeway FW-6400GX", "fw6400gx", MACHINE_TYPE_SLOT1_2, CPU_PKG_SLOT1 | CPU_PKG_SLOT2, 0, 100000000, 150000000, 1800, 3500, 3.0, 8.0, (MACHINE_AGP & ~MACHINE_AT) | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 16384,2080768,16384, 511, machine_at_fw6400gx_init, NULL },
/* Slot 2 machines */
/* 440GX */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440GX] Gigabyte GA-6GXU", "6gxu", MACHINE_TYPE_SLOT2, CPU_PKG_SLOT2, 0, 100000000, 133333333, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 16384,2097152,16384, 511, machine_at_6gxu_init, NULL },
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440GX] SuperMicro Super S2DGE", "s2dge", MACHINE_TYPE_SLOT2, CPU_PKG_SLOT2, 0, 66666667, 100000000, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 16384,2097152,16384, 511, machine_at_s2dge_init, NULL },
/* PGA370 machines */
/* 440LX */
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440LX] SuperMicro Super 370SLM", "s370slm", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 100000000, 1800, 3500, MACHINE_MULTIPLIER_FIXED, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_s370slm_init, NULL },
/* 440BX */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] AEWIN AW-O671R", "awo671r", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 133333333, 1300, 3500, 1.5, 8.0, /* limits assumed */ MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 255, machine_at_awo671r_init, NULL },
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] ASUS CUBX", "cubx", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_cubx_init, NULL },
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] AmazePC AM-BX133", "ambx133", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 133333333, 1300, 3500, 1.5, 8.0, /* limits assumed */ MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_ambx133_init, NULL },
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] Tyan Trinity 371", "trinity371", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 133333333, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_trinity371_init, NULL },
/* 440ZX */
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440ZX] Soltek SL-63A1", "63a", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 100000000, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 255, machine_at_63a_init, NULL },
/* SMSC VictoryBX-66 */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[SMSC VictoryBX-66] A-Trend ATC7020BXII","atc7020bxii", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 133333333, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_atc7020bxii_init, NULL },
/* VIA Apollo Pro */
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA Apollo Pro] PC Partner APAS3", "apas3", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 100000000, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_apas3_init, NULL },
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[VIA Apollo Pro133] ECS P6BAP", "p6bap", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1572864, 8192, 255, machine_at_p6bap_init, NULL },
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[VIA Apollo Pro133A] AEWIN WCF-681", "wcf681", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 133333333, 1300, 3500, 1.5, 8.0, /* limits assumed */ MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_wcf681_init, NULL },
/* Has the VIA VT82C686B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA Apollo Pro133A] ASUS CUV4X-LS", "cuv4xls", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, 1.5, 8.0, (MACHINE_AGP & ~MACHINE_AT) | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 16384,1572864, 8192, 255, machine_at_cuv4xls_init, NULL },
/* Has the VIA VT82C686B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA Apollo Pro133A] Acorp 6VIA90AP", "6via90ap", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, MACHINE_MULTIPLIER_FIXED, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1572864, 8192, 255, machine_at_6via90ap_init, NULL },
{ "[VIA Apollo ProMedia] Jetway 603TCF", "603tcf", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_603tcf_init, NULL },
/* Miscellaneous/Fake/Hypervisor machines */
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{ "[i440BX] Microsoft Virtual PC 2007", "vpc2007", MACHINE_TYPE_MISC, CPU_PKG_SLOT1, CPU_BLOCK(CPU_PENTIUM2, CPU_CYRIX3S), 0, 0, 0, 0, 0, 0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_vpc2007_init, NULL },
{ NULL, NULL, MACHINE_TYPE_NONE, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL }

41
src/mem/mem.c
View File

@@ -1794,7 +1794,7 @@ mem_read_ram(uint32_t addr, void *priv)
mem_log("Read B %02X from %08X\n", ram[addr], addr);
#endif
if (is286 || AT)
if (AT)
addreadlookup(mem_logical_addr, addr);
return ram[addr];
@@ -1809,7 +1809,7 @@ mem_read_ramw(uint32_t addr, void *priv)
mem_log("Read W %04X from %08X\n", *(uint16_t *)&ram[addr], addr);
#endif
if (is286 || AT)
if (AT)
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *)&ram[addr];
@@ -1824,7 +1824,7 @@ mem_read_raml(uint32_t addr, void *priv)
mem_log("Read L %08X from %08X\n", *(uint32_t *)&ram[addr], addr);
#endif
if (is286 || AT)
if (AT)
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *)&ram[addr];
@@ -2068,7 +2068,7 @@ mem_write_ram(uint32_t addr, uint8_t val, void *priv)
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Write B %02X to %08X\n", val, addr);
#endif
if (is286 || AT) {
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[addr >> 12]);
} else
@@ -2083,7 +2083,7 @@ mem_write_ramw(uint32_t addr, uint16_t val, void *priv)
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Write W %04X to %08X\n", val, addr);
#endif
if (is286 || AT) {
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[addr >> 12]);
} else
@@ -2098,7 +2098,7 @@ mem_write_raml(uint32_t addr, uint32_t val, void *priv)
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Write L %08X to %08X\n", val, addr);
#endif
if (is286 || AT) {
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[addr >> 12]);
} else
@@ -2110,7 +2110,7 @@ static uint8_t
mem_read_remapped(uint32_t addr, void *priv)
{
addr = 0xA0000 + (addr - remap_start_addr);
if (is286 || AT)
if (AT)
addreadlookup(mem_logical_addr, addr);
return ram[addr];
}
@@ -2120,7 +2120,7 @@ static uint16_t
mem_read_remappedw(uint32_t addr, void *priv)
{
addr = 0xA0000 + (addr - remap_start_addr);
if (is286 || AT)
if (AT)
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *)&ram[addr];
}
@@ -2130,7 +2130,7 @@ static uint32_t
mem_read_remappedl(uint32_t addr, void *priv)
{
addr = 0xA0000 + (addr - remap_start_addr);
if (is286 || AT)
if (AT)
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *)&ram[addr];
}
@@ -2141,7 +2141,7 @@ mem_write_remapped(uint32_t addr, uint8_t val, void *priv)
{
uint32_t oldaddr = addr;
addr = 0xA0000 + (addr - remap_start_addr);
if (is286 || AT) {
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[oldaddr >> 12]);
} else
@@ -2154,7 +2154,7 @@ mem_write_remappedw(uint32_t addr, uint16_t val, void *priv)
{
uint32_t oldaddr = addr;
addr = 0xA0000 + (addr - remap_start_addr);
if (is286 || AT) {
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[oldaddr >> 12]);
} else
@@ -2167,7 +2167,7 @@ mem_write_remappedl(uint32_t addr, uint32_t val, void *priv)
{
uint32_t oldaddr = addr;
addr = 0xA0000 + (addr - remap_start_addr);
if (is286 || AT) {
if (AT) {
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[oldaddr >> 12]);
} else
@@ -2536,7 +2536,7 @@ mem_a20_init(void)
flushmmucache();
mem_a20_state = mem_a20_key | mem_a20_alt;
} else {
rammask = is286 ? 0xffffff : 0xfffff;
rammask = 0xfffff;
flushmmucache();
mem_a20_key = mem_a20_alt = mem_a20_state = 0;
}
@@ -2662,20 +2662,15 @@ mem_reset(void)
*/
if (AT) {
if (cpu_16bitbus) {
/* 80286/386SX; maximum address space is 16MB. */
/* 80186/286; maximum address space is 16MB. */
m = 4096;
} else {
/* 80386DX+; maximum address space is 4GB. */
/* 80386+; maximum address space is 4GB. */
m = 1048576;
}
} else {
if (is286) {
/* 80286; maximum address space is 16MB. */
m = 4096;
} else {
/* 8088/86; maximum address space is 1MB. */
m = 256;
}
/* 8088/86; maximum address space is 1MB. */
m = 256;
}
/*
@@ -2869,7 +2864,7 @@ mem_a20_recalc(void)
int state;
if (! AT) {
rammask = is286 ? 0xffffff : 0xfffff;
rammask = 0xfffff;
flushmmucache();
mem_a20_key = mem_a20_alt = mem_a20_state = 0;

6
src/mem/rom.c
View File

@@ -392,12 +392,10 @@ static void
bios_add(void)
{
int temp_cpu_type, temp_cpu_16bitbus = 1;
int temp_is286 = 0;
if (/*AT && */cpu_s) {
if (AT && cpu_s) {
temp_cpu_type = cpu_s->cpu_type;
temp_cpu_16bitbus = (temp_cpu_type == CPU_286 || temp_cpu_type == CPU_386SX || temp_cpu_type == CPU_486SLC || temp_cpu_type == CPU_IBM386SLC || temp_cpu_type == CPU_IBM486SLC );
temp_is286 = (temp_cpu_type == CPU_286);
}
if (biosmask > 0x1ffff) {
@@ -419,7 +417,7 @@ bios_add(void)
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
if (temp_is286 || AT) {
if (AT) {
mem_mapping_add(&bios_high_mapping, biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
bios_read,bios_readw,bios_readl,
NULL,NULL,NULL,

56
src/mem/spd.c
View File

@@ -384,62 +384,6 @@ spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit
}
void
spd_write_drbs_interleaved(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
{
uint8_t row, dimm, drb, apollo = 0;
uint16_t size, rows[SPD_MAX_SLOTS];
/* Special case for VIA Apollo Pro family, which jumps from 5F to 56. */
if (reg_max < reg_min) {
apollo = reg_max;
reg_max = reg_min + 7;
}
/* No SPD: split SIMMs into pairs as if they were "DIMM"s. */
if (!spd_present) {
dimm = ((reg_max - reg_min) + 1) >> 2; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */
spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].max_ram >> 10) / dimm)), 0);
}
/* Write DRBs for each row. */
spd_log("SPD: Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit);
for (row = 0; row <= (reg_max - reg_min); row += 2) {
dimm = (row >> 2);
size = 0;
if (spd_present) {
/* SPD enabled: use SPD info for this slot, if present. */
if (spd_modules[dimm]) {
if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */
size = ((row >> 1) & 1) ? 0 : drb_unit;
else
size = ((row >> 1) & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1;
}
} else {
/* No SPD: use the values calculated above. */
size = (rows[dimm] >> 1);
}
/* Determine the DRB register to write. */
drb = reg_min + row;
if (apollo && ((drb & 0xf) < 0xa))
drb = apollo + (drb & 0xf);
/* Write DRB register, adding the previous DRB's value. */
if (row == 0)
regs[drb] = 0;
else if ((apollo) && (drb == apollo))
regs[drb] = regs[drb | 0xf]; /* 5F comes before 56 */
else
regs[drb] = regs[drb - 1];
if (size)
regs[drb] += size / drb_unit; /* this will intentionally overflow on 440GX with 2 GB */
spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row >> 1, size, regs[drb]);
}
}
static const device_t spd_device = {
"Serial Presence Detect ROMs",
DEVICE_ISA,

3
src/pci.c
View File

@@ -59,7 +59,7 @@ static uint8_t pci_pmc = 0, last_pci_card = 0, last_normal_pci_card = 0, last_p
static uint8_t pci_card_to_slot_mapping[256][32], pci_bus_number_to_index_mapping[256];
static uint8_t pci_irqs[16], pci_irq_level[16];
static uint64_t pci_irq_hold[16];
static pci_mirq_t pci_mirqs[8];
static pci_mirq_t pci_mirqs[4];
static int pci_type,
pci_switch,
pci_index,
@@ -74,7 +74,6 @@ static int trc_reg = 0;
static void pci_reset_regs(void);
// #define ENABLE_PCI_LOG 1
#ifdef ENABLE_PCI_LOG
int pci_do_log = ENABLE_PCI_LOG;

44
src/pic.c
View File

@@ -54,8 +54,6 @@ static pc_timer_t pic_timer;
static int shadow = 0, elcr_enabled = 0,
tmr_inited = 0, latched = 0;
static uint16_t smi_irq_mask = 0x0000,
smi_irq_status = 0x0000;
static void (*update_pending)(void);
@@ -81,39 +79,6 @@ pic_log(const char *fmt, ...)
#endif
void
pic_reset_smi_irq_mask(void)
{
smi_irq_mask = 0x0000;
}
void
pic_set_smi_irq_mask(int irq, int set)
{
if ((irq >= 0) && (irq <= 15)) {
if (set)
smi_irq_mask |= (1 << irq);
else
smi_irq_mask &= ~(1 << irq);
}
}
uint16_t
pic_get_smi_irq_status(void)
{
return smi_irq_status;
}
void
pic_clear_smi_irq_status(int irq)
{
if ((irq >= 0) && (irq <= 15))
smi_irq_status &= ~(1 << irq);
}
void
pic_elcr_write(uint16_t port, uint8_t val, void *priv)
{
@@ -290,8 +255,6 @@ pic_reset()
update_pending = is_at ? pic_update_pending_at : pic_update_pending_xt;
pic.at = pic2.at = is_at;
smi_irq_mask = smi_irq_status = 0x0000;
}
@@ -578,11 +541,6 @@ picint_common(uint16_t num, int level, int set)
acpi_rtc_status = !!set;
if (set) {
if (smi_irq_mask & num) {
smi_line = 1;
smi_irq_status |= num;
}
if (num & 0xff00) {
if (level)
pic2.lines |= (num >> 8);
@@ -597,8 +555,6 @@ picint_common(uint16_t num, int level, int set)
pic.irr |= num;
}
} else {
smi_irq_status &= ~num;
if (num & 0xff00) {
pic2.lines &= ~(num >> 8);
pic2.irr &= ~(num >> 8);

469
src/pit.c
View File

@@ -64,7 +64,6 @@ int64_t firsttime = 1;
#define PIT_EXT_IO 32 /* The PIT has externally specified port I/O. */
#define PIT_CUSTOM_CLOCK 64 /* The PIT uses custom clock inputs provided by another provider. */
#define PIT_SECONDARY 128 /* The PIT is secondary (ports 0048-004B). */
#define PIT_OLIVETTI 256 /* The PIT is that of the Olivetti 486 (has slight timing differences). */
enum {
@@ -93,214 +92,67 @@ pit_log(const char *fmt, ...)
#endif
#define NEW_PIT_CODE 1
#ifdef NEW_PIT_CODE
typedef void (*tf_t)(ctr_t *ctr);
static void ctr_tick_mode_0(ctr_t *ctr);
static void ctr_tick_mode_1(ctr_t *ctr);
static void ctr_tick_mode_2_and_6(ctr_t *ctr);
static void ctr_tick_mode_3_and_7(ctr_t *ctr);
static void ctr_tick_mode_4_and_5(ctr_t *ctr);
static tf_t ctr_tick_funcs[8] = { ctr_tick_mode_0, ctr_tick_mode_1, ctr_tick_mode_2_and_6,
ctr_tick_mode_3_and_7, ctr_tick_mode_4_and_5, ctr_tick_mode_4_and_5,
ctr_tick_mode_2_and_6, ctr_tick_mode_3_and_7 };
/* MODE 0: Interrupt on Terminal Count. */
static void
ctr_tick_mode_0(ctr_t *ctr)
ctr_set_out(ctr_t *ctr, int out)
{
uint8_t state = ctr->state;
if (ctr == NULL)
return;
switch (state) {
case 1:
/* Load count. */
ctr->count = ctr->l;
ctr->null_count = 0;
/* Switch to next state. */
ctr->state++;
case 2: case 3:
if (ctr->gate) {
/* Decrease counter. */
if ((state == 3) || ctr->gate)
ctr->count--;
if ((state == 2) && ctr->gate && (ctr->count == 0)) {
/* Terminal count reached, switch to next state. */
ctr->state++;
/* Set output high. */
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
}
}
break;
}
}
/* MODE 1: Programmale One-Shoft. */
static void
ctr_tick_mode_1(ctr_t *ctr)
{
uint8_t state = ctr->state;
switch (state) {
case 1:
/* Load count. */
ctr->count = ctr->l;
ctr->null_count = 0;
/* Switch to next state. */
ctr->state++;
/* Set output low. */
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
break;
case 2: case 3:
/* Decrease counter. */
ctr->count--;
if ((state == 2) && (ctr->count == 0)) {
/* Terminal count reached, switch to next state. */
ctr->state++;
/* Set output high. */
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
}
break;
}
if (ctr->out_func != NULL)
ctr->out_func(out, ctr->out);
ctr->out = out;
}
static void
ctr_tick_mode_2_and_6(ctr_t *ctr)
ctr_decrease_count(ctr_t *ctr)
{
uint8_t state = ctr->state;
switch (state) {
case 1: case 3:
/* Load count. */
ctr->count = ctr->l;
ctr->null_count = 0;
if (ctr->state == 3) {
/* Set output high. */
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
}
/* Switch to next state. */
ctr->state = 2;
break;
case 2:
/* Decrease counter. */
if (ctr->gate) {
ctr->count--;
if (ctr->count == 1) {
/* Terminal count reached, switch to previous state. */
ctr->state = 3;
/* Set output low. */
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
if (ctr->bcd) {
ctr->units--;
if (ctr->units == 0xff) {
ctr->units = 9;
ctr->tens--;
if (ctr->tens == 0xff) {
ctr->tens = 9;
ctr->hundreds--;
if (ctr->hundreds == 0xff) {
ctr->hundreds = 9;
ctr->thousands--;
if (ctr->thousands == 0xff) {
ctr->thousands = 9;
ctr->myriads--;
if (ctr->myriads == 0xff)
ctr->myriads = 0; /* 0 - 1 should wrap around to 9999. */
}
}
}
break;
}
}
static void
ctr_tick_mode_3_and_7(ctr_t *ctr)
{
uint8_t state = ctr->state;
uint16_t old_count = ctr->count;
switch (state) {
case 1:
/* Load count. */
ctr->count = ctr->l;
ctr->flag_64k = !ctr->count;
ctr->null_count = 0;
ctr->newcount = ctr->count & 1;
/* Switch to next state. */
ctr->state = 2;
case 2: case 3:
if (ctr->gate) {
ctr->count -= (ctr->newcount ? ((ctr->state == 3) ? 3 : 1) : 2);
if (!ctr->flag_64k && (ctr->count > old_count)) {
/* Load count. */
ctr->count = ctr->l;
ctr->flag_64k = !ctr->count;
ctr->null_count = 0;
ctr->newcount = ctr->count & 1;
/* Switch to next state. */
ctr->state ^= 1;
/* Set output low. */
if (ctr->out_func != NULL)
ctr->out_func(state & 1, ctr->out);
ctr->out = state & 1;
} else {
if (ctr->newcount)
ctr->newcount = 0;
ctr->flag_64k = 0;
}
}
break;
}
}
static void
ctr_tick_mode_4_and_5(ctr_t *ctr)
{
uint8_t state = ctr->state;
/* Software triggered strobe */
/* Hardware triggered strobe */
if (ctr->gate || (ctr->m != 4)) {
switch(state) {
case 0: case 2:
ctr->count--;
if ((state == 2) && (ctr->count < 1)) {
ctr->state++;
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
}
break;
case 3:
ctr->state = 0;
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
break;
}
}
} else
ctr->count = (ctr->count - 1) & 0xffff;
}
#else
static void
ctr_load_count(ctr_t *ctr)
{
int l = ctr->l ? ctr->l : 0x10000;
ctr->count = l;
pit_log("ctr->count = %i\n", l);
ctr->null_count = 0;
ctr->newcount = !!(l & 1);
}
static void
ctr_tick(ctr_t *ctr)
{
uint8_t state = ctr->state;
uint16_t old_count = ctr->count;
if (state == 1) {
/* This is true for all modes */
ctr->count = ctr->l;
ctr->null_count = 0;
ctr->newcount = !!(ctr->count & 1);
ctr->state++;
if ((ctr->m & 0x07) == 1) {
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
}
ctr_load_count(ctr);
ctr->state = 2;
return;
}
@@ -309,35 +161,38 @@ ctr_tick(ctr_t *ctr)
/* Interrupt on terminal count */
switch (state) {
case 2:
if (ctr->gate) {
ctr->count--;
if (ctr->gate && (ctr->count >= 1)) {
ctr_decrease_count(ctr);
if (ctr->count < 1) {
ctr->state++;
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
ctr->state = 3;
ctr_set_out(ctr, 1);
}
}
break;
case 3:
ctr->count--;
ctr_decrease_count(ctr);
break;
}
break;
case 1:
/* Hardware retriggerable one-shot */
switch (state) {
case 1:
ctr_load_count(ctr);
ctr->state = 2;
ctr_set_out(ctr, 0);
break;
case 2:
ctr->count--;
if (ctr->count < 1) {
ctr->state++;
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
if (ctr->count >= 1) {
ctr_decrease_count(ctr);
if (ctr->count < 1) {
ctr->state = 3;
ctr_set_out(ctr, 1);
}
}
break;
case 3:
ctr->count--;
ctr_decrease_count(ctr);
break;
}
break;
@@ -345,40 +200,59 @@ ctr_tick(ctr_t *ctr)
/* Rate generator */
switch (state) {
case 3:
ctr->count = ctr->l;
ctr->null_count = 0;
ctr->state ^= 1;
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
ctr_load_count(ctr);
ctr->state = 2;
ctr_set_out(ctr, 1);
break;
case 2:
// if (ctr->gate) {
ctr->count--;
if (ctr->gate == 0)
break;
else if (ctr->count >= 2) {
ctr_decrease_count(ctr);
if (ctr->count < 2) {
ctr->state ^= 1;
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
ctr->state = 3;
ctr_set_out(ctr, 0);
}
// }
}
break;
}
break;
case 3: case 7:
/* Square wave mode */
switch (state) {
case 2: case 3:
if (ctr->gate != 0) {
ctr->count -= (ctr->newcount ? ((state & 1) ? 3 : 1) : 2);
if (ctr->count > old_count) {
ctr->count = ctr->l;
ctr->null_count = 0;
ctr->newcount = !!(ctr->count & 1);
ctr->state ^= 1;
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
case 2:
if (ctr->gate == 0)
break;
else if (ctr->count >= 0) {
if (ctr->bcd) {
ctr_decrease_count(ctr);
if (!ctr->newcount)
ctr_decrease_count(ctr);
} else
ctr->count -= (ctr->newcount ? 1 : 2);
if (ctr->count < 0) {
ctr_load_count(ctr);
ctr->state = 3;
ctr_set_out(ctr, 0);
} else if (ctr->newcount)
ctr->newcount = 0;
}
break;
case 3:
if (ctr->gate == 0)
break;
else if (ctr->count >= 0) {
if (ctr->bcd) {
ctr_decrease_count(ctr);
ctr_decrease_count(ctr);
if (ctr->newcount)
ctr_decrease_count(ctr);
} else
ctr->count -= (ctr->newcount ? 3 : 2);
if (ctr->count < 0) {
ctr_load_count(ctr);
ctr->state = 2;
ctr_set_out(ctr, 1);
} else if (ctr->newcount)
ctr->newcount = 0;
}
@@ -390,20 +264,21 @@ ctr_tick(ctr_t *ctr)
/* Hardware triggered strobe */
if ((ctr->gate != 0) || (ctr->m != 4)) {
switch(state) {
case 0: case 2:
ctr->count--;
if ((state == 2) && (ctr->count < 1)) {
ctr->state++;
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
case 0:
ctr_decrease_count(ctr);
break;
case 2:
if (ctr->count >= 1) {
ctr_decrease_count(ctr);
if (ctr->count < 1) {
ctr->state = 3;
ctr_set_out(ctr, 0);
}
}
break;
case 3:
ctr->state = 0;
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
ctr_set_out(ctr, 1);
break;
}
}
@@ -412,24 +287,19 @@ ctr_tick(ctr_t *ctr)
break;
}
}
#endif
static void
ctr_clock(ctr_t *ctr)
{
/* FIXME: Is this even needed? */
/* FIXME: Is this even needed? */
if ((ctr->state == 3) && (ctr->m != 2) && (ctr->m != 3))
return;
if (ctr->using_timer)
return;
#ifdef NEW_PIT_CODE
ctr->tick_func(ctr);
#else
ctr_tick(ctr);
#endif
}
@@ -480,11 +350,6 @@ ctr_latch_count(ctr_t *ctr)
{
int count = (ctr->latch || (ctr->state == 1)) ? ctr->l : ctr->count;
// if ((ctr->pit->flags & PIT_OLIVETTI) && (ctr->state == 0))
// count--;
pit_log("PIT latch count with state %i (%i)\n", ctr->state, ctr->latch);
switch (ctr->rm & 0x03) {
case 0x00:
/* This should never happen. */
@@ -550,21 +415,15 @@ pit_ctr_set_gate(ctr_t *ctr, int gate)
if (!old && gate) {
/* Here we handle the rising edges. */
if (mode & 1) {
if (mode != 1) {
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
}
if (mode != 1)
ctr_set_out(ctr, 1);
ctr->state = 1;
} else if (mode == 2)
ctr->state = 3;
} else if (old && !gate) {
/* Here we handle the lowering edges. */
if (mode & 2) {
if (ctr->out_func != NULL)
ctr->out_func(1, ctr->out);
ctr->out = 1;
}
if (mode & 2)
ctr_set_out(ctr, 1);
}
break;
}
@@ -578,27 +437,12 @@ pit_ctr_set_clock_common(ctr_t *ctr, int clock)
ctr->clock = clock;
if (!ctr->using_timer)
return;
#if 0
if ((ctr->pit->flags & PIT_OLIVETTI) && !old && ctr->clock) {
if (ctr->do_load) {
if (ctr->do_load == 3)
ctr_load(ctr);
ctr->do_load++;
if (ctr->do_load == 4)
ctr->do_load = 0;
}
}
#endif
if (ctr->latch) {
if (ctr->using_timer && ctr->latch) {
if (old && !ctr->clock) {
ctr_set_state_1(ctr);
ctr->latch = 0;
}
} else if (!ctr->latch) {
} else if (ctr->using_timer && !ctr->latch) {
if (ctr->state == 1) {
if (!old && ctr->clock)
ctr->s1_det = 1; /* Rising edge. */
@@ -606,19 +450,11 @@ pit_ctr_set_clock_common(ctr_t *ctr, int clock)
ctr->s1_det++; /* Falling edge. */
if (ctr->s1_det >= 2) {
ctr->s1_det = 0;
#ifdef NEW_PIT_CODE
ctr->tick_func(ctr);
#else
ctr_tick(ctr);
#endif
}
}
} else if (old && !ctr->clock)
#ifdef NEW_PIT_CODE
ctr->tick_func(ctr);
#else
ctr_tick(ctr);
#endif
}
}
@@ -702,14 +538,9 @@ pit_write(uint16_t addr, uint8_t val, void *priv)
ctr->m = (val >> 1) & 7;
if (ctr->m > 5)
ctr->m &= 3;
#ifdef NEW_PIT_CODE
ctr->tick_func = ctr_tick_funcs[ctr->m];
#endif
ctr->null_count = 1;
ctr->bcd = (ctr->ctrl & 0x01);
if (ctr->out_func != NULL)
ctr->out_func(!!ctr->m, ctr->out);
ctr->out = !!ctr->m;
ctr_set_out(ctr, !!ctr->m);
ctr->state = 0;
if (ctr->latched) {
pit_log("PIT %i: Reload while counter is latched\n", t);
@@ -732,44 +563,27 @@ pit_write(uint16_t addr, uint8_t val, void *priv)
break;
case 1:
ctr->l = val;
if (ctr->m == 0) {
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
}
if (dev->flags & PIT_OLIVETTI)
ctr->do_load = 1;
else
ctr_load(ctr);
if (ctr->m == 0)
ctr_set_out(ctr, 0);
ctr_load(ctr);
break;
case 2:
ctr->l = (val << 8);
if (ctr->m == 0) {
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
}
if (dev->flags & PIT_OLIVETTI)
ctr->do_load = 1;
else
ctr_load(ctr);
if (ctr->m == 0)
ctr_set_out(ctr, 0);
ctr_load(ctr);
break;
case 3: case 0x83:
if (ctr->wm & 0x80) {
ctr->l = (ctr->l & 0x00ff) | (val << 8);
pit_log("PIT %i: Written high byte %02X, latch now %04X\n", t, val, ctr->l);
if (dev->flags & PIT_OLIVETTI)
ctr->do_load = 1;
else
ctr_load(ctr);
ctr_load(ctr);
} else {
ctr->l = (ctr->l & 0xff00) | val;
pit_log("PIT %i: Written low byte %02X, latch now %04X\n", t, val, ctr->l);
if (ctr->m == 0) {
ctr->state = 0;
if (ctr->out_func != NULL)
ctr->out_func(0, ctr->out);
ctr->out = 0;
ctr_set_out(ctr, 0);
}
}
@@ -943,7 +757,7 @@ pit_nmi_timer_ps2(int new_out, int old_out)
static void
ctr_reset(pit_t *dev, ctr_t *ctr)
ctr_reset(ctr_t *ctr)
{
ctr->ctrl = 0;
ctr->m = 0;
@@ -957,8 +771,6 @@ ctr_reset(pit_t *dev, ctr_t *ctr)
ctr->s1_det = 0;
ctr->l_det = 0;
ctr->pit = dev;
}
@@ -972,15 +784,10 @@ pit_reset(pit_t *dev)
dev->clock = 0;
for (i = 0; i < 3; i++)
ctr_reset(dev, &dev->counters[i]);
ctr_reset(&dev->counters[i]);
/* Disable speaker gate. */
dev->counters[2].gate = 0;
#ifdef NEW_PIT_CODE
dev->counters[0].tick_func = dev->counters[1].tick_func =
dev->counters[2].tick_func = ctr_tick_funcs[0];
#endif
}
@@ -1051,17 +858,6 @@ const device_t i8254_device =
};
const device_t i8254_olivetti_device =
{
"Intel 8254 Programmable Interval Timer (Olivetti)",
DEVICE_ISA,
PIT_8254 | PIT_OLIVETTI,
pit_init, pit_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t i8254_sec_device =
{
"Intel 8254 Programmable Interval Timer (Secondary)",
@@ -1108,9 +904,6 @@ pit_common_init(int type, void (*out0)(int new_out, int old_out), void (*out1)(i
case PIT_8254:
pit = device_add(&i8254_device);
break;
case (PIT_8254 | PIT_OLIVETTI):
pit = device_add(&i8254_olivetti_device);
break;
}
for (i = 0; i < 3; i++) {

214
src/port_6x.c
View File

@@ -1,214 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Ports 61, 62, and 63 used by various
* machines.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/m_xt_xi8088.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sound.h>
#include <86box/snd_speaker.h>
#include <86box/pit.h>
#include <86box/ppi.h>
#include <86box/video.h>
#include <86box/port_6x.h>
#define PS2_REFRESH_TIME (16 * TIMER_USEC)
#define PORT_6X_TURBO 1
#define PORT_6X_EXT_REF 2
#define PORT_6X_MIRROR 4
#define PORT_6X_SWA 8
static void
port_6x_write(uint16_t port, uint8_t val, void *priv)
{
port_6x_t *dev = (port_6x_t *) priv;
port &= 3;
if ((port == 3) && (dev->flags & PORT_6X_MIRROR))
port = 1;
switch (port) {
case 1:
ppi.pb = (ppi.pb & 0x10) | (val & 0x0f);
speaker_update();
speaker_gated = val & 1;
speaker_enable = val & 2;
if (speaker_enable)
was_speaker_enable = 1;
pit_ctr_set_gate(&pit->counters[2], val & 1);
if (dev->flags & PORT_6X_TURBO)
xi8088_turbo_set(!!(val & 0x04));
break;
}
}
static uint8_t
port_6x_read(uint16_t port, void *priv)
{
port_6x_t *dev = (port_6x_t *) priv;
uint8_t ret = 0xff;
port &= 3;
if ((port == 3) && (dev->flags & PORT_6X_MIRROR))
port = 1;
switch (port) {
case 1:
if (dev->flags & PORT_6X_EXT_REF) {
ret = ppi.pb & 0x0f;
if (dev->refresh)
ret |= 0x10;
} else
ret = ppi.pb & 0x1f;
if (ppispeakon)
ret |= 0x20;
if (dev->flags & PORT_6X_TURBO)
ret = (ret & 0xfb) | (xi8088_turbo_get() ? 0x04 : 0x00);
break;
case 2:
if (dev->flags & PORT_6X_SWA) {
/* SWA on Olivetti M240 mainboard (off=1) */
ret = 0x00;
if (ppi.pb & 0x8) {
/* Switches 4, 5 - floppy drives (number) */
int i, fdd_count = 0;
for (i = 0; i < FDD_NUM; i++) {
if (fdd_get_flags(i))
fdd_count++;
}
if (!fdd_count)
ret |= 0x00;
else
ret |= ((fdd_count - 1) << 2);
/* Switches 6, 7 - monitor type */
if (video_is_mda())
ret |= 0x3;
else if (video_is_cga())
ret |= 0x2; /* 0x10 would be 40x25 */
else
ret |= 0x0;
} else {
/* bit 2 always on */
ret |= 0x4;
/* Switch 8 - 8087 FPU. */
if (hasfpu)
ret |= 0x02;
}
}
break;
}
return(ret);
}
static void
port_6x_refresh(void *priv)
{
port_6x_t *dev = (port_6x_t *) priv;
dev->refresh = !dev->refresh;
timer_advance_u64(&dev->refresh_timer, PS2_REFRESH_TIME);
}
static void
port_6x_close(void *priv)
{
port_6x_t *dev = (port_6x_t *) priv;
timer_disable(&dev->refresh_timer);
free(dev);
}
void *
port_6x_init(const device_t *info)
{
port_6x_t *dev = (port_6x_t *) malloc(sizeof(port_6x_t));
memset(dev, 0, sizeof(port_6x_t));
dev->flags = info->local & 0xff;
io_sethandler(0x0061, 3, port_6x_read, NULL, NULL, port_6x_write, NULL, NULL, dev);
if (dev->flags & PORT_6X_EXT_REF)
timer_add(&dev->refresh_timer, port_6x_refresh, dev, 1);
return dev;
}
const device_t port_6x_device = {
"Port 6x Registers",
0,
0,
port_6x_init, port_6x_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t port_6x_xi8088_device = {
"Port 6x Registers (Xi8088)",
0,
PORT_6X_TURBO | PORT_6X_EXT_REF | PORT_6X_MIRROR,
port_6x_init, port_6x_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t port_6x_ps2_device = {
"Port 6x Registers (IBM PS/2)",
0,
PORT_6X_EXT_REF,
port_6x_init, port_6x_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t port_6x_olivetti_device = {
"Port 6x Registers (Olivetti)",
0,
PORT_6X_SWA,
port_6x_init, port_6x_close, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/sio/CMakeLists.txt
View File

@@ -14,7 +14,7 @@
#
add_library(sio OBJECT sio_acc3221.c sio_f82c710.c sio_82091aa.c sio_fdc37c651.c sio_fdc37c661.c
sio_fdc37c66x.c sio_fdc37c67x.c sio_fdc37c669.c sio_fdc37c93x.c sio_fdc37m60x.c
sio_fdc37c66x.c sio_fdc37c669.c sio_fdc37c93x.c sio_fdc37m60x.c
sio_it8661f.c
sio_pc87306.c sio_pc87307.c sio_pc87309.c sio_pc87310.c sio_pc87311.c sio_pc87332.c
sio_prime3b.c sio_prime3c.c

613
src/sio/sio_fdc37c67x.c
View File

@@ -1,613 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C67X Super I/O Chip.
*
*
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include "cpu.h"
#include <86box/sio.h>
#define AB_RST 0x80
typedef struct {
uint8_t chip_id, is_apm,
tries,
gpio_regs[2], auxio_reg,
regs[48],
ld_regs[11][256];
uint16_t gpio_base, /* Set to EA */
auxio_base, sio_base;
int locked,
cur_reg;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c67x_t;
static void fdc37c67x_write(uint16_t port, uint8_t val, void *priv);
static uint8_t fdc37c67x_read(uint16_t port, void *priv);
static uint16_t
make_port(fdc37c67x_t *dev, uint8_t ld)
{
uint16_t r0 = dev->ld_regs[ld][0x60];
uint16_t r1 = dev->ld_regs[ld][0x61];
uint16_t p = (r0 << 8) + r1;
return p;
}
static uint8_t
fdc37c67x_auxio_read(uint16_t port, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
return dev->auxio_reg;
}
static void
fdc37c67x_auxio_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
dev->auxio_reg = val;
}
static uint8_t
fdc37c67x_gpio_read(uint16_t port, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
uint8_t ret = 0xff;
ret = dev->gpio_regs[port & 1];
return ret;
}
static void
fdc37c67x_gpio_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
if (!(port & 1))
dev->gpio_regs[0] = (dev->gpio_regs[0] & 0xfc) | (val & 0x03);
}
static void
fdc37c67x_fdc_handler(fdc37c67x_t *dev)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << 0));
uint8_t local_enable = !!dev->ld_regs[0][0x30];
fdc_remove(dev->fdc);
if (global_enable && local_enable) {
ld_port = make_port(dev, 0) & 0xFFF8;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
fdc_set_base(dev->fdc, ld_port);
}
}
static void
fdc37c67x_lpt_handler(fdc37c67x_t *dev)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << 3));
uint8_t local_enable = !!dev->ld_regs[3][0x30];
uint8_t lpt_irq = dev->ld_regs[3][0x70];
if (lpt_irq > 15)
lpt_irq = 0xff;
lpt1_remove();
if (global_enable && local_enable) {
ld_port = make_port(dev, 3) & 0xFFFC;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
lpt1_init(ld_port);
}
lpt1_irq(lpt_irq);
}
static void
fdc37c67x_serial_handler(fdc37c67x_t *dev, int uart)
{
uint16_t ld_port = 0;
uint8_t uart_no = 4 + uart;
uint8_t global_enable = !!(dev->regs[0x22] & (1 << uart_no));
uint8_t local_enable = !!dev->ld_regs[uart_no][0x30];
serial_remove(dev->uart[uart]);
if (global_enable && local_enable) {
ld_port = make_port(dev, uart_no) & 0xFFF8;
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
serial_setup(dev->uart[uart], ld_port, dev->ld_regs[uart_no][0x70]);
}
}
static void
fdc37c67x_auxio_handler(fdc37c67x_t *dev)
{
uint16_t ld_port = 0;
uint8_t local_enable = !!dev->ld_regs[8][0x30];
io_removehandler(dev->auxio_base, 0x0001,
fdc37c67x_auxio_read, NULL, NULL, fdc37c67x_auxio_write, NULL, NULL, dev);
if (local_enable) {
dev->auxio_base = ld_port = make_port(dev, 8);
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFF))
io_sethandler(dev->auxio_base, 0x0001,
fdc37c67x_auxio_read, NULL, NULL, fdc37c67x_auxio_write, NULL, NULL, dev);
}
}
static void
fdc37c67x_sio_handler(fdc37c67x_t *dev)
{
#if 0
if (dev->sio_base) {
io_removehandler(dev->sio_base, 0x0002,
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
}
dev->sio_base = (((uint16_t) dev->regs[0x27]) << 8) | dev->regs[0x26];
if (dev->sio_base) {
io_sethandler(dev->sio_base, 0x0002,
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
}
#endif
}
static void
fdc37c67x_gpio_handler(fdc37c67x_t *dev)
{
uint16_t ld_port = 0;
uint8_t local_enable;
local_enable = !!(dev->regs[0x03] & 0x80);
io_removehandler(dev->gpio_base, 0x0002,
fdc37c67x_gpio_read, NULL, NULL, fdc37c67x_gpio_write, NULL, NULL, dev);
if (local_enable) {
switch (dev->regs[0x03] & 0x03) {
case 0:
ld_port = 0xe0;
break;
case 1:
ld_port = 0xe2;
break;
case 2:
ld_port = 0xe4;
break;
case 3:
ld_port = 0xea; /* Default */
break;
}
dev->gpio_base = ld_port;
if (ld_port > 0x0000)
io_sethandler(dev->gpio_base, 0x0002,
fdc37c67x_gpio_read, NULL, NULL, fdc37c67x_gpio_write, NULL, NULL, dev);
}
}
static void
fdc37c67x_smi_handler(fdc37c67x_t *dev)
{
/* TODO: 8042 P1.2 SMI#. */
pic_reset_smi_irq_mask();
pic_set_smi_irq_mask(dev->ld_regs[3][0x70], dev->ld_regs[8][0xb4] & 0x02);
pic_set_smi_irq_mask(dev->ld_regs[5][0x70], dev->ld_regs[8][0xb4] & 0x04);
pic_set_smi_irq_mask(dev->ld_regs[4][0x70], dev->ld_regs[8][0xb4] & 0x08);
pic_set_smi_irq_mask(dev->ld_regs[0][0x70], dev->ld_regs[8][0xb4] & 0x10);
pic_set_smi_irq_mask(12, dev->ld_regs[8][0xb5] & 0x01);
pic_set_smi_irq_mask(1, dev->ld_regs[8][0xb5] & 0x02);
pic_set_smi_irq_mask(10, dev->ld_regs[8][0xb5] & 0x80);
}
static void
fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor = 0x00, keep = 0x00;
if (index) {
if ((val == 0x55) && !dev->locked) {
if (dev->tries) {
dev->locked = 1;
fdc_3f1_enable(dev->fdc, 0);
dev->tries = 0;
} else
dev->tries++;
} else {
if (dev->locked) {
if (val == 0xaa) {
dev->locked = 0;
fdc_3f1_enable(dev->fdc, 1);
return;
}
dev->cur_reg = val;
} else {
if (dev->tries)
dev->tries = 0;
}
}
return;
} else {
if (dev->locked) {
if (dev->cur_reg < 48) {
valxor = val ^ dev->regs[dev->cur_reg];
if ((val == 0x20) || (val == 0x21))
return;
dev->regs[dev->cur_reg] = val;
} else {
valxor = val ^ dev->ld_regs[dev->regs[7]][dev->cur_reg];
if (((dev->cur_reg & 0xF0) == 0x70) && (dev->regs[7] < 4))
return;
/* Block writes to some logical devices. */
if (dev->regs[7] > 0x0a)
return;
else switch (dev->regs[7]) {
case 0x01:
case 0x02:
case 0x07:
return;
}
dev->ld_regs[dev->regs[7]][dev->cur_reg] = val | keep;
}
} else
return;
}
if (dev->cur_reg < 48) {
switch(dev->cur_reg) {
case 0x03:
if (valxor & 0x83)
fdc37c67x_gpio_handler(dev);
dev->regs[0x03] &= 0x83;
break;
case 0x22:
if (valxor & 0x01)
fdc37c67x_fdc_handler(dev);
if (valxor & 0x08)
fdc37c67x_lpt_handler(dev);
if (valxor & 0x10)
fdc37c67x_serial_handler(dev, 0);
if (valxor & 0x20)
fdc37c67x_serial_handler(dev, 1);
break;
case 0x26: case 0x27:
fdc37c67x_sio_handler(dev);
}
return;
}
switch(dev->regs[7]) {
case 0:
/* FDD */
switch(dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x01;
if (valxor)
fdc37c67x_fdc_handler(dev);
break;
case 0xF0:
if (valxor & 0x01)
fdc_update_enh_mode(dev->fdc, val & 0x01);
if (valxor & 0x10)
fdc_set_swap(dev->fdc, (val & 0x10) >> 4);
break;
case 0xF1:
if (valxor & 0xC)
fdc_update_densel_force(dev->fdc, (val & 0xc) >> 2);
break;
case 0xF2:
if (valxor & 0xC0)
fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6);
if (valxor & 0x30)
fdc_update_rwc(dev->fdc, 2, (val & 0x30) >> 4);
if (valxor & 0x0C)
fdc_update_rwc(dev->fdc, 1, (val & 0x0c) >> 2);
if (valxor & 0x03)
fdc_update_rwc(dev->fdc, 0, (val & 0x03));
break;
case 0xF4:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 0, (val & 0x18) >> 3);
break;
case 0xF5:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 1, (val & 0x18) >> 3);
break;
case 0xF6:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 2, (val & 0x18) >> 3);
break;
case 0xF7:
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 3, (val & 0x18) >> 3);
break;
}
break;
case 3:
/* Parallel port */
switch(dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x08;
if (valxor)
fdc37c67x_lpt_handler(dev);
if (dev->cur_reg == 0x70)
fdc37c67x_smi_handler(dev);
break;
}
break;
case 4:
/* Serial port 1 */
switch(dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x10;
if (valxor)
fdc37c67x_serial_handler(dev, 0);
if (dev->cur_reg == 0x70)
fdc37c67x_smi_handler(dev);
break;
}
break;
case 5:
/* Serial port 2 */
switch(dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if ((dev->cur_reg == 0x30) && (val & 0x01))
dev->regs[0x22] |= 0x20;
if (valxor)
fdc37c67x_serial_handler(dev, 1);
if (dev->cur_reg == 0x70)
fdc37c67x_smi_handler(dev);
break;
}
break;
case 8:
/* Auxiliary I/O */
switch(dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if (valxor)
fdc37c67x_auxio_handler(dev);
break;
case 0xb4:
case 0xb5:
fdc37c67x_smi_handler(dev);
break;
}
break;
}
}
static uint8_t
fdc37c67x_read(uint16_t port, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ret = 0xff;
uint16_t smi_stat = pic_get_smi_irq_status();
int f_irq = dev->ld_regs[0][0x70];
int p_irq = dev->ld_regs[3][0x70];
int s1_irq = dev->ld_regs[4][0x70];
int s2_irq = dev->ld_regs[5][0x70];
if (dev->locked) {
if (index)
ret = dev->cur_reg;
else {
if (dev->cur_reg < 0x30) {
if (dev->cur_reg == 0x20)
ret = dev->chip_id;
else
ret = dev->regs[dev->cur_reg];
} else {
if ((dev->regs[7] == 0) && (dev->cur_reg == 0xF2)) {
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) |
(fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
} else
ret = dev->ld_regs[dev->regs[7]][dev->cur_reg];
/* TODO: 8042 P1.2 SMI#. */
if ((dev->regs[7] == 8) && (dev->cur_reg == 0xb6)) {
ret = dev->regs[dev->cur_reg] & 0xe1;
ret |= ((!!(smi_stat & (1 << p_irq))) << 1);
ret |= ((!!(smi_stat & (1 << s2_irq))) << 2);
ret |= ((!!(smi_stat & (1 << s1_irq))) << 3);
ret |= ((!!(smi_stat & (1 << f_irq))) << 4);
} else if ((dev->regs[7] == 8) && (dev->cur_reg == 0xb7)) {
ret = dev->regs[dev->cur_reg] & 0xec;
ret |= ((!!(smi_stat & (1 << 12))) << 0);
ret |= ((!!(smi_stat & (1 << 1))) << 1);
ret |= ((!!(smi_stat & (1 << 10))) << 4);
}
}
}
}
return ret;
}
static void
fdc37c67x_reset(fdc37c67x_t *dev)
{
int i = 0;
memset(dev->regs, 0, 48);
dev->regs[0x03] = 0x03;
dev->regs[0x20] = dev->chip_id;
dev->regs[0x22] = 0x39;
dev->regs[0x24] = 0x04;
dev->regs[0x26] = 0xf0;
dev->regs[0x27] = 0x03;
for (i = 0; i < 11; i++)
memset(dev->ld_regs[i], 0, 256);
/* Logical device 0: FDD */
dev->ld_regs[0][0x30] = 1;
dev->ld_regs[0][0x60] = 3;
dev->ld_regs[0][0x61] = 0xf0;
dev->ld_regs[0][0x70] = 6;
dev->ld_regs[0][0x74] = 2;
dev->ld_regs[0][0xf0] = 0x0e;
dev->ld_regs[0][0xf2] = 0xff;
/* Logical device 3: Parallel Port */
dev->ld_regs[3][0x30] = 1;
dev->ld_regs[3][0x60] = 3;
dev->ld_regs[3][0x61] = 0x78;
dev->ld_regs[3][0x70] = 7;
dev->ld_regs[3][0x74] = 4;
dev->ld_regs[3][0xf0] = 0x3c;
/* Logical device 4: Serial Port 1 */
dev->ld_regs[4][0x30] = 1;
dev->ld_regs[4][0x60] = 3;
dev->ld_regs[4][0x61] = 0xf8;
dev->ld_regs[4][0x70] = 4;
dev->ld_regs[4][0xf0] = 3;
serial_setup(dev->uart[0], 0x3f8, dev->ld_regs[4][0x70]);
/* Logical device 5: Serial Port 2 */
dev->ld_regs[5][0x30] = 1;
dev->ld_regs[5][0x60] = 2;
dev->ld_regs[5][0x61] = 0xf8;
dev->ld_regs[5][0x70] = 3;
dev->ld_regs[5][0x74] = 4;
dev->ld_regs[5][0xf1] = 2;
dev->ld_regs[5][0xf2] = 3;
serial_setup(dev->uart[1], 0x2f8, dev->ld_regs[5][0x70]);
/* Logical device 7: Keyboard */
dev->ld_regs[7][0x30] = 1;
dev->ld_regs[7][0x61] = 0x60;
dev->ld_regs[7][0x70] = 1;
dev->ld_regs[7][0x72] = 12;
/* Logical device 8: Auxiliary I/O */
dev->ld_regs[8][0xc0] = 6;
dev->ld_regs[8][0xc1] = 3;
fdc37c67x_gpio_handler(dev);
fdc37c67x_lpt_handler(dev);
fdc37c67x_serial_handler(dev, 0);
fdc37c67x_serial_handler(dev, 1);
fdc37c67x_auxio_handler(dev);
fdc37c67x_sio_handler(dev);
fdc_reset(dev->fdc);
fdc37c67x_fdc_handler(dev);
dev->locked = 0;
}
static void
fdc37c67x_close(void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
free(dev);
}
static void *
fdc37c67x_init(const device_t *info)
{
fdc37c67x_t *dev = (fdc37c67x_t *) malloc(sizeof(fdc37c67x_t));
memset(dev, 0, sizeof(fdc37c67x_t));
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->chip_id = info->local & 0xff;
dev->gpio_regs[0] = 0xff;
// dev->gpio_regs[1] = (info->local == 0x0030) ? 0xff : 0xfd;
dev->gpio_regs[1] = (dev->chip_id == 0x30) ? 0xff : 0xfd;
fdc37c67x_reset(dev);
io_sethandler(0x370, 0x0002,
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
io_sethandler(0x3f0, 0x0002,
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
return dev;
}
const device_t fdc37c67x_device = {
"SMC FDC37C67X Super I/O",
0,
0x40,
fdc37c67x_init, fdc37c67x_close, NULL,
{ NULL }, NULL, NULL,
NULL
};

10
src/sio/sio_pc87332.c
View File

@@ -366,16 +366,6 @@ const device_t pc87332_398_ide_device = {
};
const device_t pc87332_398_ide_sec_device = {
"National Semiconductor PC87332 Super I/O (Port 398h) (With Secondary IDE)",
0,
0x201,
pc87332_init, pc87332_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t pc87332_398_ide_fdcon_device = {
"National Semiconductor PC87332 Super I/O (Port 398h) (With IDE and FDC on)",
0,

3
src/sound/snd_sb.c
View File

@@ -1026,9 +1026,8 @@ sb_ct1745_mixer_read(uint16_t addr, void *p)
/* 0 = none, 1 = digital 8bit or SBMIDI, 2 = digital 16bit, 4 = MPU-401 */
/* 0x02000 DSP v4.04, 0x4000 DSP v4.05, 0x8000 DSP v4.12.
I haven't seen this making any difference, but I'm keeping it for now. */
/* If QEMU is any indication, then the values are actually 0x20, 0x40, and 0x80. */
temp = ((sb->dsp.sb_irq8) ? 1 : 0) | ((sb->dsp.sb_irq16) ? 2 : 0) |
((sb->dsp.sb_irq401) ? 4 : 0) | 0x40;
((sb->dsp.sb_irq401) ? 4 : 0) | 0x4000;
ret = temp;
break;

3
src/usb.c
View File

@@ -146,9 +146,6 @@ ohci_mmio_read(uint32_t addr, void *p)
ret = dev->ohci_mmio[addr];
if (addr == 0x101)
ret = (ret & 0xfe) | (!!mem_a20_key);
return ret;
}

4
src/video/CMakeLists.txt
View File

@@ -20,8 +20,8 @@ add_library(vid OBJECT video.c vid_table.c vid_cga.c vid_cga_comp.c
vid_svga_render.c vid_ddc.c vid_vga.c vid_ati_eeprom.c vid_ati18800.c
vid_ati28800.c vid_ati_mach64.c vid_ati68860_ramdac.c vid_bt48x_ramdac.c
vid_av9194.c vid_icd2061.c vid_ics2494.c vid_ics2595.c vid_cl54xx.c
vid_et3000.c vid_et4000.c vid_sc1148x_ramdac.c vid_sc1502x_ramdac.c
vid_et4000w32.c vid_stg_ramdac.c vid_ht216.c vid_oak_oti.c vid_paradise.c vid_rtg310x.c
vid_et4000.c vid_sc1148x_ramdac.c vid_sc1502x_ramdac.c vid_et4000w32.c
vid_stg_ramdac.c vid_ht216.c vid_oak_oti.c vid_paradise.c vid_rtg310x.c
vid_ti_cf62011.c vid_tvga.c vid_tgui9440.c vid_tkd8001_ramdac.c
vid_att20c49x_ramdac.c vid_s3.c vid_s3_virge.c vid_ibm_rgb528_ramdac.c
vid_sdac_ramdac.c vid_ogc.c vid_nga.c)

24
src/video/vid_cl54xx.c
View File

@@ -1597,7 +1597,7 @@ gd54xx_recalctimings(svga_t *svga)
uint8_t clocksel, rdmask;
uint8_t linedbl = svga->dispend * 9 / 10 >= svga->hdisp;
svga->rowoffset = (svga->crtc[0x13]) | (((int) (uint32_t) (svga->crtc[0x1b] & 0x10)) << 4);
svga->rowoffset = (svga->crtc[0x13]) | ((svga->crtc[0x1b] & 0x10) << 4);
svga->interlace = (svga->crtc[0x1a] & 0x01);
@@ -1774,28 +1774,6 @@ gd54xx_recalctimings(svga_t *svga)
}
svga->vram_display_mask = (svga->crtc[0x1b] & 2) ? gd54xx->vram_mask : 0x3ffff;
pclog("svga->crtc[0x1a] = %02X\n", svga->crtc[0x1a]);
pclog("svga->crtc[0x1b] = %02X\n", svga->crtc[0x1b]);
pclog("svga->crtc[0x1c] = %02X\n", svga->crtc[0x1c]);
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5430)
svga->htotal += ((svga->crtc[0x1c] >> 3) & 0x07);
if (svga->crtc[0x1b] & ((svga->crtc[0x27] >= CIRRUS_ID_CLGD5424) ? 0xa0 : 0x20)) {
/* Special blanking mode: the blank start and end become components of the window generator,
and the actual blanking comes from the display enable signal. */
/* Start blanking at the first character clock after the last active one. */
svga->hblankstart = svga->crtc[1] + 1;
svga->hblank_end_val = (svga->htotal + 6) & 0x3f;
/* In this mode, the dots per clock are always 8 or 16, never 9 or 18. */
if (!svga->scrblank && svga->attr_palette_enable)
svga->dots_per_clock = (svga->seqregs[1] & 8) ? 16 : 8;
/* No overscan in this mode. */
svga->hblank_overscan = 0;
/* Also make sure vertical blanking starts on display end. */
svga->vblankstart = svga->dispend;
}
}

308
src/video/vid_et3000.c
View File

@@ -1,308 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Tseng Labs ET3000.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mca.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#define BIOS_ROM_PATH "roms/video/et3000/Tseng ET3000AX ISA VGA-VGA ULTRA.bin"
typedef struct {
const char *name;
int type;
svga_t svga;
rom_t bios_rom;
uint8_t banking;
} et3000_t;
static video_timings_t timing_et3000_isa = {VIDEO_ISA, 3, 3, 6, 5, 5, 10};
static uint8_t et3000_in(uint16_t addr, void *priv);
static void et3000_out(uint16_t addr, uint8_t val, void *priv);
static uint8_t
et3000_in(uint16_t addr, void *priv)
{
et3000_t *dev = (et3000_t *)priv;
svga_t *svga = &dev->svga;
if (((addr & 0xfff0) == 0x3d0 ||
(addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1)) addr ^= 0x60;
switch (addr) {
case 0x3cd: /*Banking*/
return dev->banking;
case 0x3d4:
return svga->crtcreg;
case 0x3d5:
return svga->crtc[svga->crtcreg];
}
return svga_in(addr, svga);
}
static void
et3000_out(uint16_t addr, uint8_t val, void *priv)
{
et3000_t *dev = (et3000_t *)priv;
svga_t *svga = &dev->svga;
uint8_t old;
if (((addr & 0xfff0) == 0x3d0 ||
(addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1)) addr ^= 0x60;
switch (addr) {
case 0x3c0:
case 0x3c1:
if (svga->attrff && (svga->attraddr == 0x16)) {
svga->attrregs[0x16] = val;
svga->chain4 &= ~0x10;
if (svga->gdcreg[5] & 0x40)
svga->chain4 |= (svga->attrregs[0x16] & 0x10);
svga_recalctimings(svga);
}
break;
case 0x3c5:
if (svga->seqaddr == 4) {
svga->seqregs[4] = val;
svga->chain2_write = !(val & 4);
svga->chain4 = (svga->chain4 & ~8) | (val & 8);
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) &&
!svga->gdcreg[1]) && svga->chain4 && !(svga->adv_flags & FLAG_ADDR_BY8);
return;
}
break;
case 0x3cf:
if ((svga->gdcaddr & 15) == 5) {
svga->chain4 &= ~0x10;
if (val & 0x40)
svga->chain4 |= (svga->attrregs[0x16] & 0x10);
}
break;
case 0x3cd: /*Banking*/
dev->banking = val;
if (!(svga->crtc[0x23] & 0x80) && !(svga->gdcreg[6] & 0x08)) {
switch ((val >> 6) & 3) {
case 0: /*128K segments*/
svga->write_bank = (val & 7) << 17;
svga->read_bank = ((val >> 3) & 7) << 17;
break;
case 1: /*64K segments*/
svga->write_bank = (val & 7) << 16;
svga->read_bank = ((val >> 3) & 7) << 16;
break;
}
}
return;
case 0x3d4:
svga->crtcreg = val & 0x3f;
return;
case 0x3d5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0x0e || svga->crtcreg > 0x10) {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
break;
}
svga_out(addr, val, svga);
}
static void
et3000_recalctimings(svga_t *svga)
{
svga->ma_latch |= (svga->crtc[0x23] & 2) << 15;
if (svga->crtc[0x25] & 1) svga->vblankstart |= 0x400;
if (svga->crtc[0x25] & 2) svga->vtotal |= 0x400;
if (svga->crtc[0x25] & 4) svga->dispend |= 0x400;
if (svga->crtc[0x25] & 8) svga->vsyncstart |= 0x400;
if (svga->crtc[0x25] & 0x10) svga->split |= 0x400;
svga->interlace = !!(svga->crtc[0x25] & 0x80);
if (svga->attrregs[0x16] & 0x10) {
svga->ma_latch <<= (1 << 0);
svga->rowoffset <<= (1 << 0);
switch (svga->gdcreg[5] & 0x60) {
case 0x00:
svga->render = svga_render_4bpp_highres;
svga->hdisp *= 2;
break;
case 0x20:
svga->render = svga_render_2bpp_highres;
break;
case 0x40: case 0x60:
svga->render = svga_render_8bpp_highres;
break;
}
}
/* pclog("HDISP = %i, HTOTAL = %i, ROWOFFSET = %i, INTERLACE = %i\n",
svga->hdisp, svga->htotal, svga->rowoffset, svga->interlace); */
switch (((svga->miscout >> 2) & 3) | ((svga->crtc[0x24] << 1) & 4)) {
case 0:
case 1:
break;
case 3:
svga->clock = (cpuclock * (double)(1ull << 32)) / 40000000.0;
break;
case 5:
svga->clock = (cpuclock * (double)(1ull << 32)) / 65000000.0;
break;
default:
svga->clock = (cpuclock * (double)(1ull << 32)) / 36000000.0;
break;
}
}
static void *
et3000_init(const device_t *info)
{
const char *fn;
et3000_t *dev;
dev = (et3000_t *)malloc(sizeof(et3000_t));
memset(dev, 0x00, sizeof(et3000_t));
dev->name = info->name;
dev->type = info->local;
fn = BIOS_ROM_PATH;
switch(dev->type) {
case 0: /* ISA ET3000AX */
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et3000_isa);
svga_init(info, &dev->svga, dev, device_get_config_int("memory") << 10,
et3000_recalctimings, et3000_in, et3000_out,
NULL, NULL);
io_sethandler(0x03c0, 32,
et3000_in,NULL,NULL, et3000_out,NULL,NULL, dev);
break;
}
rom_init(&dev->bios_rom, (char *) fn,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
dev->svga.bpp = 8;
dev->svga.miscout = 1;
return(dev);
}
static void
et3000_close(void *priv)
{
et3000_t *dev = (et3000_t *)priv;
svga_close(&dev->svga);
free(dev);
}
static void
et3000_speed_changed(void *priv)
{
et3000_t *dev = (et3000_t *)priv;
svga_recalctimings(&dev->svga);
}
static void
et3000_force_redraw(void *priv)
{
et3000_t *dev = (et3000_t *)priv;
dev->svga.fullchange = changeframecount;
}
static int
et3000_available(void)
{
return rom_present(BIOS_ROM_PATH);
}
static const device_config_t et3000_config[] =
{
{
"memory", "Memory size", CONFIG_SELECTION, "", 512, "", { 0 },
{
{
"256 KB", 256
},
{
"512 KB", 512
},
{
"1 MB", 1024
},
{
""
}
}
},
{
"", "", -1
}
};
const device_t et3000_isa_device = {
"Tseng Labs ET3000AX (ISA)",
DEVICE_ISA,
0,
et3000_init, et3000_close, NULL,
{ et3000_available },
et3000_speed_changed,
et3000_force_redraw,
et3000_config
};

153
src/video/vid_et4000.c
View File

@@ -55,7 +55,6 @@
#define BIOS_ROM_PATH "roms/video/et4000/et4000.bin"
#define TC6058AF_BIOS_ROM_PATH "roms/video/et4000/Tseng_Labs_VGA-4000_BIOS_V1.1.bin"
#define KOREAN_BIOS_ROM_PATH "roms/video/et4000/tgkorvga.bin"
#define KOREAN_FONT_ROM_PATH "roms/video/et4000/tg_ksc5601.rom"
#define KASAN_BIOS_ROM_PATH "roms/video/et4000/et4000_kasan16.bin"
@@ -110,14 +109,13 @@ et4000_in(uint16_t addr, void *priv)
{
et4000_t *dev = (et4000_t *)priv;
svga_t *svga = &dev->svga;
uint8_t ret;
if (((addr & 0xfff0) == 0x3d0 ||
(addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1)) addr ^= 0x60;
switch (addr) {
case 0x3c2:
if (dev->type == 2) {
if (dev->type == 1) {
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x4e)
return 0;
else
@@ -134,9 +132,7 @@ et4000_in(uint16_t addr, void *priv)
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (dev->type >= 1)
return sc1502x_ramdac_in(addr, svga->ramdac, svga);
break;
return sc1502x_ramdac_in(addr, svga->ramdac, svga);
case 0x3cd: /*Banking*/
return dev->banking;
@@ -146,26 +142,6 @@ et4000_in(uint16_t addr, void *priv)
case 0x3d5:
return svga->crtc[svga->crtcreg];
case 0x3da:
svga->attrff = 0;
if (svga->cgastat & 0x01)
svga->cgastat &= ~0x30;
else
svga->cgastat ^= 0x30;
ret = svga->cgastat;
if ((svga->fcr & 0x08) && svga->dispon)
ret |= 0x08;
if (ret & 0x08)
ret &= 0x7f;
else
ret |= 0x80;
return ret;
}
return svga_in(addr, svga);
@@ -247,34 +223,12 @@ et4000_out(uint16_t addr, uint8_t val, void *priv)
(addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1)) addr ^= 0x60;
switch (addr) {
case 0x3c5:
if (svga->seqaddr == 4) {
svga->seqregs[4] = val;
svga->chain2_write = !(val & 4);
svga->chain4 = (svga->chain4 & ~8) | (val & 8);
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) &&
!svga->gdcreg[1]) && svga->chain4 && !(svga->adv_flags & FLAG_ADDR_BY8);
return;
} else if (svga->seqaddr == 0x0e) {
svga->seqregs[0x0e] = val;
svga->chain4 &= ~0x02;
if (svga->gdcreg[5] & 0x40)
svga->chain4 |= (svga->seqregs[0x0e] & 0x02);
svga_recalctimings(svga);
return;
}
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (dev->type >= 1) {
sc1502x_ramdac_out(addr, val, svga->ramdac, svga);
return;
}
break;
sc1502x_ramdac_out(addr, val, svga->ramdac, svga);
return;
case 0x3cd: /*Banking*/
if (!(svga->crtc[0x36] & 0x10) && !(svga->gdcreg[6] & 0x08)) {
@@ -285,11 +239,7 @@ et4000_out(uint16_t addr, uint8_t val, void *priv)
return;
case 0x3cf:
if ((svga->gdcaddr & 15) == 5) {
svga->chain4 &= ~0x02;
if (val & 0x40)
svga->chain4 |= (svga->seqregs[0x0e] & 0x02);
} else if ((svga->gdcaddr & 15) == 6) {
if ((svga->gdcaddr & 15) == 6) {
if (!(svga->crtc[0x36] & 0x10) && !(val & 0x08)) {
svga->write_bank = (dev->banking & 0x0f) * 0x10000;
svga->read_bank = ((dev->banking >> 4) & 0x0f) * 0x10000;
@@ -592,13 +542,13 @@ et4000_recalctimings(svga_t *svga)
et4000_t *dev = (et4000_t *)svga->p;
svga->ma_latch |= (svga->crtc[0x33] & 3) << 16;
if (svga->crtc[0x35] & 1) svga->vblankstart |= 0x400;
if (svga->crtc[0x35] & 2) svga->vtotal |= 0x400;
if (svga->crtc[0x35] & 4) svga->dispend |= 0x400;
if (svga->crtc[0x35] & 8) svga->vsyncstart |= 0x400;
if (svga->crtc[0x35] & 0x10) svga->split |= 0x400;
if (svga->crtc[0x35] & 1) svga->vblankstart += 0x400;
if (svga->crtc[0x35] & 2) svga->vtotal += 0x400;
if (svga->crtc[0x35] & 4) svga->dispend += 0x400;
if (svga->crtc[0x35] & 8) svga->vsyncstart += 0x400;
if (svga->crtc[0x35] & 0x10) svga->split += 0x400;
if (!svga->rowoffset) svga->rowoffset = 0x100;
if (svga->crtc[0x3f] & 1) svga->htotal |= 0x100;
if (svga->crtc[0x3f] & 1) svga->htotal += 256;
if (svga->attrregs[0x16] & 0x20) svga->hdisp <<= 1;
switch (((svga->miscout >> 2) & 3) | ((svga->crtc[0x34] << 1) & 4)) {
@@ -627,7 +577,7 @@ et4000_recalctimings(svga_t *svga)
break;
}
if (dev->type == 3 || dev->type == 4 || dev->type == 5) {
if (dev->type == 2 || dev->type == 3 || dev->type == 4) {
if ((svga->render == svga_render_text_80) && ((svga->crtc[0x37] & 0x0A) == 0x0A)) {
if (dev->port_32cb_val & 0x80) {
svga->ma_latch -= 2;
@@ -638,19 +588,6 @@ et4000_recalctimings(svga_t *svga)
}
}
}
if ((svga->seqregs[0x0e] & 0x02) && ((svga->gdcreg[5] & 0x60) >= 0x40)) {
svga->ma_latch <<= (1 << 0);
svga->rowoffset <<= (1 << 0);
svga->render = svga_render_8bpp_highres;
}
if (dev->type == 0) {
if (svga->render == svga_render_8bpp_lowres)
svga->render = svga_render_8bpp_tseng_lowres;
else if (svga->render == svga_render_8bpp_highres)
svga->render = svga_render_8bpp_tseng_highres;
}
}
static void
@@ -664,7 +601,6 @@ et4000_kasan_recalctimings(svga_t *svga)
svga->ma_latch -= 3;
svga->ca_adj = (et4000->kasan_cfg_regs[0] >> 6) - 3;
svga->ksc5601_sbyte_mask = (et4000->kasan_cfg_regs[0] & 4) << 5;
/* TODO: Are we sure this doesn't use Attribute register 16h bit 6 (two-byte character code enable)? */
if((et4000->kasan_cfg_regs[0] & 0x23) == 0x20 && (et4000->kasan_cfg_regs[4] & 0x80) && ((svga->crtc[0x37] & 0x0B) == 0x0A))
svga->render = svga_render_text_80_ksc5601;
}
@@ -713,8 +649,7 @@ et4000_init(const device_t *info)
fn = BIOS_ROM_PATH;
switch(dev->type) {
case 0: /* ISA ET4000AX (TC6058AF) */
case 1: /* ISA ET4000AX */
case 0: /* ISA ET4000AX */
dev->vram_size = device_get_config_int("memory") << 10;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000_isa);
svga_init(info, &dev->svga, dev, dev->vram_size,
@@ -722,11 +657,9 @@ et4000_init(const device_t *info)
NULL, NULL);
io_sethandler(0x03c0, 32,
et4000_in,NULL,NULL, et4000_out,NULL,NULL, dev);
if (dev->type == 0)
fn = TC6058AF_BIOS_ROM_PATH;
break;
case 2: /* MCA ET4000AX */
case 1: /* MCA ET4000AX */
dev->vram_size = 1024 << 10;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000_mca);
svga_init(info, &dev->svga, dev, dev->vram_size,
@@ -739,8 +672,8 @@ et4000_init(const device_t *info)
mca_add(et4000_mca_read, et4000_mca_write, et4000_mca_feedb, NULL, dev);
break;
case 3: /* Korean ET4000 */
case 4: /* Trigem 286M ET4000 */
case 2: /* Korean ET4000 */
case 3: /* Trigem 286M ET4000 */
dev->vram_size = device_get_config_int("memory") << 10;
dev->port_22cb_val = 0x60;
dev->port_32cb_val = 0;
@@ -764,7 +697,7 @@ et4000_init(const device_t *info)
loadfont(KOREAN_FONT_ROM_PATH, 6);
fn = KOREAN_BIOS_ROM_PATH;
break;
case 5: /* Kasan ET4000 */
case 4: /* Kasan ET4000 */
dev->vram_size = device_get_config_int("memory") << 10;
dev->svga.ksc5601_sbyte_mask = 0;
dev->svga.ksc5601_udc_area_msb[0] = 0xC9;
@@ -800,8 +733,7 @@ et4000_init(const device_t *info)
}
if (dev->type >= 1)
dev->svga.ramdac = device_add(&sc1502x_ramdac_device);
dev->svga.ramdac = device_add(&sc1502x_ramdac_device);
dev->vram_mask = dev->vram_size - 1;
@@ -845,13 +777,6 @@ et4000_force_redraw(void *priv)
}
static int
et4000_tc6058af_available(void)
{
return rom_present(TC6058AF_BIOS_ROM_PATH);
}
static int
et4000_available(void)
{
@@ -873,27 +798,6 @@ et4000_kasan_available(void)
rom_present(KASAN_FONT_ROM_PATH);
}
static const device_config_t et4000_tc6058af_config[] =
{
{
"memory", "Memory size", CONFIG_SELECTION, "", 1024, "", { 0 },
{
{
"256 KB", 256
},
{
"512 KB", 512
},
{
""
}
}
},
{
"", "", -1
}
};
static const device_config_t et4000_config[] =
{
{
@@ -918,21 +822,10 @@ static const device_config_t et4000_config[] =
}
};
const device_t et4000_tc6058af_isa_device = {
"Tseng Labs ET4000AX (TC6058AF) (ISA)",
DEVICE_ISA,
0,
et4000_init, et4000_close, NULL,
{ et4000_tc6058af_available },
et4000_speed_changed,
et4000_force_redraw,
et4000_tc6058af_config
};
const device_t et4000_isa_device = {
"Tseng Labs ET4000AX (ISA)",
DEVICE_ISA,
1,
0,
et4000_init, et4000_close, NULL,
{ et4000_available },
et4000_speed_changed,
@@ -943,7 +836,7 @@ const device_t et4000_isa_device = {
const device_t et4000_mca_device = {
"Tseng Labs ET4000AX (MCA)",
DEVICE_MCA,
2,
1,
et4000_init, et4000_close, NULL,
{ et4000_available },
et4000_speed_changed,
@@ -954,7 +847,7 @@ const device_t et4000_mca_device = {
const device_t et4000k_isa_device = {
"Trigem Korean VGA (Tseng Labs ET4000AX Korean)",
DEVICE_ISA,
3,
2,
et4000_init, et4000_close, NULL,
{ et4000k_available },
et4000_speed_changed,
@@ -965,7 +858,7 @@ const device_t et4000k_isa_device = {
const device_t et4000k_tg286_isa_device = {
"Trigem Korean VGA (Trigem 286M)",
DEVICE_ISA,
4,
3,
et4000_init, et4000_close, NULL,
{ et4000k_available },
et4000_speed_changed,
@@ -976,7 +869,7 @@ const device_t et4000k_tg286_isa_device = {
const device_t et4000_kasan_isa_device = {
"Kasan Hangulmadang-16 VGA (Tseng Labs ET4000AX Korean)",
DEVICE_ISA,
5,
4,
et4000_init, et4000_close, NULL,
{ et4000_kasan_available },
et4000_speed_changed,

7
src/video/vid_et4000w32.c
View File

@@ -363,7 +363,6 @@ et4000w32p_recalctimings(svga_t *svga)
svga->clock = (cpuclock * (double)(1ull << 32)) / svga->getclock((svga->miscout >> 2) & 3, svga->clock_gen);
#if 0
if (svga->adv_flags & FLAG_NOSKEW) {
/* On the Cardex ET4000/W32p-based cards, adjust text mode clocks by 1. */
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /* Text mode */
@@ -380,10 +379,10 @@ et4000w32p_recalctimings(svga_t *svga)
svga->hdisp += (svga->seqregs[1] & 1) ? 16 : 18;
else
svga->hdisp += (svga->seqregs[1] & 1) ? 8 : 9;
}
} else if ((svga->gdcreg[5] & 0x40) == 0)
svga->hdisp += (svga->seqregs[1] & 1) ? 8 : 9;
}
}
#endif
if (et4000->type == ET4000W32) {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
@@ -422,10 +421,8 @@ et4000w32p_recalctimings(svga_t *svga)
else
svga->render = svga_render_text_80;
} else {
#if 0
if (svga->adv_flags & FLAG_NOSKEW)
svga->ma_latch--;
#endif
switch (svga->gdcreg[5] & 0x60) {
case 0x00:

38
src/video/vid_oak_oti.c
View File

@@ -30,7 +30,9 @@
#include <86box/vid_svga.h>
#define BIOS_037C_PATH "roms/video/oti/bios.bin"
#define BIOS_067_AMA932J_PATH "roms/machines/ama932j/oti067.bin"
#define BIOS_067_AMA932J_PATH "roms/machines/ama932j/oti067.bin"
#define BIOS_067_M300_08_PATH "roms/machines/olivetti_m300_08/EVC_BIOS.ROM"
#define BIOS_067_M300_15_PATH "roms/machines/olivetti_m300_15/EVC_BIOS.ROM"
#define BIOS_077_PATH "roms/video/oti/oti077.vbi"
@@ -38,6 +40,7 @@ enum {
OTI_037C,
OTI_067 = 2,
OTI_067_AMA932J,
OTI_067_M300 = 4,
OTI_077 = 5
};
@@ -367,6 +370,16 @@ oti_init(const device_t *info)
io_sethandler(0x46e8, 1, oti_pos_in, NULL, NULL, oti_pos_out, NULL, NULL, oti);
break;
case OTI_067_M300:
if (rom_present(BIOS_067_M300_15_PATH))
romfn = BIOS_067_M300_15_PATH;
else
romfn = BIOS_067_M300_08_PATH;
oti->vram_size = device_get_config_int("memory");
oti->pos = 0x08; /* Tell the BIOS the I/O ports are already enabled to avoid a double I/O handler mess. */
io_sethandler(0x46e8, 1, oti_pos_in, NULL, NULL, oti_pos_out, NULL, NULL, oti);
break;
case OTI_067:
case OTI_077:
romfn = BIOS_077_PATH;
@@ -433,20 +446,27 @@ oti037c_available(void)
return(rom_present(BIOS_037C_PATH));
}
static int
oti067_ama932j_available(void)
{
return(rom_present(BIOS_067_AMA932J_PATH));
}
static int
oti067_077_available(void)
{
return(rom_present(BIOS_077_PATH));
}
static int
oti067_m300_available(void)
{
if (rom_present(BIOS_067_M300_15_PATH))
return(rom_present(BIOS_067_M300_15_PATH));
else
return(rom_present(BIOS_067_M300_08_PATH));
}
static const device_config_t oti067_config[] =
{
@@ -539,6 +559,18 @@ const device_t oti067_device =
oti067_config
};
const device_t oti067_m300_device =
{
"Oak OTI-067 (Olivetti M300-08/15)",
DEVICE_ISA,
4,
oti_init, oti_close, NULL,
{ oti067_m300_available },
oti_speed_changed,
oti_force_redraw,
oti067_config
};
const device_t oti067_ama932j_device =
{
"Oak OTI-067 (AMA-932J)",

30
src/video/vid_s3.c
View File

@@ -2531,14 +2531,14 @@ static void s3_recalctimings(svga_t *svga)
s3_t *s3 = (s3_t *)svga->p;
int clk_sel = (svga->miscout >> 2) & 3;
svga->hdisp = svga->hdisp_old;
svga->ma_latch |= (s3->ma_ext << 16);
if (s3->chip >= S3_86C928) {
svga->hdisp = svga->hdisp_old;
if (svga->crtc[0x5d] & 0x01) svga->htotal |= 0x100;
if (svga->crtc[0x5d] & 0x02) {
svga->hdisp_time |= 0x100;
svga->hdisp |= 0x100 * svga->dots_per_clock;
svga->hdisp |= 0x100 * ((svga->seqregs[1] & 8) ? 16 : 8);
}
if (svga->crtc[0x5e] & 0x01) svga->vtotal |= 0x400;
if (svga->crtc[0x5e] & 0x02) svga->dispend |= 0x400;
@@ -2547,7 +2547,7 @@ static void s3_recalctimings(svga_t *svga)
if (svga->crtc[0x5e] & 0x40) svga->split |= 0x400;
if (svga->crtc[0x51] & 0x30) svga->rowoffset |= (svga->crtc[0x51] & 0x30) << 4;
else if (svga->crtc[0x43] & 0x04) svga->rowoffset |= 0x100;
} else if (svga->crtc[0x43] & 0x04) svga->rowoffset |= 0x100;
}
if (!svga->rowoffset) svga->rowoffset = 256;
if ((s3->chip == S3_VISION964) || (s3->chip == S3_86C928)) {
@@ -2649,28 +2649,6 @@ static void s3_recalctimings(svga_t *svga)
svga->rowoffset <<= 1;
}
}
if (s3->chip >= S3_86C801) {
if (!svga->scrblank && svga->attr_palette_enable && (svga->crtc[0x43] & 0x80)) {
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 16 : 18);
}
if (svga->crtc[0x5d] & 0x04)
svga->hblankstart += 0x100;
if (s3->chip >= S3_VISION964) {
/* NOTE: The S3 Trio64V+ datasheet says this is bit 7, but then where is bit 6?
The datasheets for the pre-Trio64V+ cards say +64, which implies bit 6,
and, contrary to VGADOC, it also exists on Trio32, Trio64, Vision868,
and Vision968. */
// pclog("svga->crtc[0x5d] = %02X\n", svga->crtc[0x5d]);
if (svga->crtc[0x5d] & 0x08)
svga->hblank_ext = 0x40;
svga->hblank_end_len = 0x00000040;
}
}
svga->hblank_overscan = !(svga->crtc[0x33] & 0x20);
}
static void s3_trio64v_recalctimings(svga_t *svga)

152
src/video/vid_svga.c
View File

@@ -20,13 +20,11 @@
* Copyright 2016-2019 Miran Grca.
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/device.h>
@@ -55,27 +53,6 @@ uint8_t svga_rotate[8][256];
static svga_t *svga_pri;
// #define ENABLE_SVGA_LOG 1
#ifdef ENABLE_SVGA_LOG
int svga_do_log = ENABLE_SVGA_LOG;
static void
svga_log(const char *fmt, ...)
{
va_list ap;
if (svga_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define svga_log(fmt, ...)
#endif
svga_t
*svga_get_pri()
{
@@ -199,7 +176,7 @@ svga_out(uint16_t addr, uint8_t val, void *p)
break;
case 4:
svga->chain2_write = !(val & 4);
svga->chain4 = (svga->chain4 & ~8) | (val & 8);
svga->chain4 = val & 8;
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) &&
!svga->gdcreg[1]) && ((svga->chain4 && svga->packed_chain4) || svga->fb_only) && !(svga->adv_flags & FLAG_ADDR_BY8);
break;
@@ -258,7 +235,7 @@ svga_out(uint16_t addr, uint8_t val, void *p)
break;
case 6:
if ((svga->gdcreg[6] & 0xc) != (val & 0xc)) {
switch (val & 0xc) {
switch (val&0xC) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
@@ -289,9 +266,6 @@ svga_out(uint16_t addr, uint8_t val, void *p)
((svga->gdcaddr & 15) == 6 && (val ^ o) & 1))
svga_recalctimings(svga);
break;
case 0x3da:
svga->fcr = val;
break;
}
}
@@ -357,9 +331,6 @@ svga_in(uint16_t addr, void *p)
break;
}
break;
case 0x3ca:
ret = svga->fcr;
break;
case 0x3cc:
ret = svga->miscout;
break;
@@ -393,11 +364,7 @@ svga_in(uint16_t addr, void *p)
svga->cgastat &= ~0x30;
else
svga->cgastat ^= 0x30;
ret = svga->cgastat;
if ((svga->fcr & 0x08) && svga->dispon)
ret |= 0x08;
break;
}
@@ -429,10 +396,6 @@ void
svga_recalctimings(svga_t *svga)
{
double crtcconst, _dispontime, _dispofftime, disptime;
#ifdef ENABLE_SVGA_LOG
int vsyncend, vblankend;
int hdispstart, hdispend, hsyncstart, hsyncend;
#endif
svga->vtotal = svga->crtc[6];
svga->dispend = svga->crtc[0x12];
@@ -470,9 +433,12 @@ svga_recalctimings(svga_t *svga)
svga->vblankstart |= 0x200;
svga->vblankstart++;
svga->hdisp = svga->crtc[1] - ((svga->crtc[3] & 0x60) >> 5);
svga->hdisp = svga->crtc[1] - ((svga->crtc[5] & 0x60) >> 5);
svga->hdisp++;
svga->htotal = svga->crtc[0];
svga->htotal += 6; /*+6 is required for Tyrian*/
svga->rowoffset = svga->crtc[0x13];
svga->clock = (svga->vidclock) ? VGACONST2 : VGACONST1;
@@ -489,19 +455,20 @@ svga_recalctimings(svga_t *svga)
svga->hdisp_time = svga->hdisp;
svga->render = svga_render_blank;
if (!svga->scrblank && svga->attr_palette_enable) {
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
if (svga->seqregs[1] & 8)
svga->hdisp *= (svga->seqregs[1] & 1) ? 16 : 18;
else
svga->hdisp *= (svga->seqregs[1] & 1) ? 8 : 9;
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
if (svga->seqregs[1] & 8) /*40 column*/
if (svga->seqregs[1] & 8) /*40 column*/ {
svga->render = svga_render_text_40;
else
svga->hdisp *= (svga->seqregs[1] & 1) ? 16 : 18;
/* Character clock is off by 1 now in 40-line modes, on all cards. */
svga->ma_latch--;
svga->hdisp += (svga->seqregs[1] & 1) ? 16 : 18;
} else {
svga->render = svga_render_text_80;
svga->hdisp *= (svga->seqregs[1] & 1) ? 8 : 9;
}
svga->hdisp_old = svga->hdisp;
} else {
svga->hdisp *= (svga->seqregs[1] & 8) ? 16 : 8;
svga->hdisp_old = svga->hdisp;
switch (svga->gdcreg[5] & 0x60) {
@@ -563,7 +530,7 @@ svga_recalctimings(svga_t *svga)
}
svga->linedbl = svga->crtc[9] & 0x80;
svga->char_width = (svga->seqregs[1] & 1) ? 8 : 9;
svga->char_width = (svga->seqregs[1] & 1) ? 8 : 9;
if (enable_overscan) {
overscan_y = (svga->rowcount + 1) << 1;
@@ -580,41 +547,9 @@ svga_recalctimings(svga_t *svga)
} else
overscan_x = 16;
svga->htotal = svga->crtc[0];
svga->hblankstart = svga->crtc[4] + 1;
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | ((svga->crtc[5] & 0x80) ? 0x20 : 0x00);
// pclog("htotal = %i, hblankstart = %i, hblank_end_val = %02X\n", svga->htotal, svga->hblankstart, svga->hblank_end_val);
svga->hblank_end_len = 0x00000040;
svga->hblank_overscan = 1;
if (!svga->scrblank && svga->attr_palette_enable) {
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
if (svga->seqregs[1] & 8)
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 16 : 18);
else
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 8 : 9);
} else
svga->dots_per_clock = 1;
/* Do svga->recalctimings_ex() here so that the above five variables can be
updated by said function. */
if (svga->recalctimings_ex)
svga->recalctimings_ex(svga);
svga->htotal += 6; /*+6 is required for Tyrian*/
svga->hblankend = (svga->hblankstart & ~(svga->hblank_end_len - 1)) | svga->hblank_end_val;
if (svga->hblankend <= svga->hblankstart)
svga->hblankend += svga->hblank_end_len;
svga->hblankend += svga->hblank_ext;
svga->hblank_sub = 0;
if (svga->hblankend > svga->htotal) {
svga->hblankend &= (svga->hblank_end_len - 1);
svga->hblank_sub = svga->hblankend + svga->hblank_overscan;
svga->hdisp -= (svga->hblank_sub * svga->dots_per_clock);
}
svga->y_add = (overscan_y >> 1) - (svga->crtc[8] & 0x1f);
svga->x_add = (overscan_x >> 1);
@@ -623,44 +558,6 @@ svga_recalctimings(svga_t *svga)
crtcconst = svga->clock * svga->char_width;
#ifdef ENABLE_SVGA_LOG
vsyncend = (svga->vsyncstart & 0xfffffff0) | (svga->crtc[0x11] & 0x0f);
if (vsyncend <= svga->vsyncstart)
vsyncend += 0x00000010;
vblankend = (svga->vblankstart & 0xffffff80) | (svga->crtc[0x16] & 0x7f);
if (vblankend <= svga->vblankstart)
vblankend += 0x00000080;
hdispstart = ((svga->crtc[3] >> 5) & 3);
hdispend = svga->crtc[1] + 1;
hsyncstart = svga->crtc[4] + ((svga->crtc[5] >> 5) & 3) + 1;
hsyncend = (hsyncstart & 0xffffffe0) | (svga->crtc[5] & 0x1f);
if (hsyncend <= hsyncstart)
hsyncend += 0x00000020;
#endif
svga_log("Last scanline in the vertical period: %i\n"
"First scanline after the last of active display: %i\n"
"First scanline with vertical retrace asserted: %i\n"
"First scanline after the last with vertical retrace asserted: %i\n"
"First scanline of blanking: %i\n"
"First scanline after the last of blanking: %i\n"
"\n"
"Last character in the horizontal period: %i\n"
"First character of active display: %i\n"
"First character after the last of active display: %i\n"
"First character with horizontal retrace asserted: %i\n"
"First character after the last with horizontal retrace asserted: %i\n"
"First character of blanking: %i\n"
"First character after the last of blanking: %i\n"
"\n"
"\n",
svga->vtotal, svga->dispend, svga->vsyncstart, vsyncend,
svga->vblankstart, vblankend,
svga->htotal, hdispstart, hdispend, hsyncstart, hsyncend,
svga->hblankstart, svga->hblankend
);
disptime = svga->htotal;
_dispontime = svga->hdisp_time;
@@ -746,8 +643,6 @@ svga_poll(void *p)
uint32_t x, blink_delay;
int wx, wy;
int ret, old_ma;
// int lines_num = (svga->vtotal > svga->vsyncstart) ? svga->vtotal : svga->vsyncstart;
// int lines_num = svga->vsyncstart + 3 + 19;
if (!svga->linepos) {
if (svga->displine == svga->hwcursor_latch.y && svga->hwcursor_latch.ena) {
@@ -826,7 +721,7 @@ svga_poll(void *p)
svga->displine++;
if (svga->interlace)
svga->displine++;
if ((svga->cgastat & 8) && ((svga->displine & 15) == (svga->crtc[0x11] & 15)))
if ((svga->cgastat & 8) && ((svga->displine & 15) == (svga->crtc[0x11] & 15)) && svga->vslines)
svga->cgastat &= ~8;
svga->vslines++;
if (svga->displine > 1500)
@@ -878,12 +773,11 @@ svga_poll(void *p)
if (ret) {
if (svga->interlace && svga->oddeven)
svga->ma = svga->maback = (svga->rowoffset << 1) + ((svga->crtc[3] & 0x60) >> 5) + svga->hblank_sub;
svga->ma = svga->maback = (svga->rowoffset << 1) + ((svga->crtc[5] & 0x60) >> 5);
else
svga->ma = svga->maback = ((svga->crtc[3] & 0x60) >> 5) + svga->hblank_sub;
svga->ma = svga->maback = ((svga->crtc[5] & 0x60) >> 5);
svga->ma = (svga->ma << 2);
svga->maback = (svga->maback << 2);
svga->sc = 0;
if (svga->attrregs[0x10] & 0x20) {
svga->scrollcache = 0;
@@ -948,9 +842,9 @@ svga_poll(void *p)
svga->vslines = 0;
if (svga->interlace && svga->oddeven)
svga->ma = svga->maback = svga->ma_latch + (svga->rowoffset << 1) + ((svga->crtc[3] & 0x60) >> 5) + svga->hblank_sub;
svga->ma = svga->maback = svga->ma_latch + (svga->rowoffset << 1) + ((svga->crtc[5] & 0x60) >> 5);
else
svga->ma = svga->maback = svga->ma_latch + ((svga->crtc[3] & 0x60) >> 5) + svga->hblank_sub;
svga->ma = svga->maback = svga->ma_latch + ((svga->crtc[5] & 0x60) >> 5);
svga->ca = ((svga->crtc[0xe] << 8) | svga->crtc[0xf]) + ((svga->crtc[0xb] & 0x60) >> 5) + svga->ca_adj;
svga->ma = (svga->ma << 2);
@@ -960,7 +854,6 @@ svga_poll(void *p)
if (svga->vsync_callback)
svga->vsync_callback(svga);
}
// if (svga->vc == lines_num) {
if (svga->vc == svga->vtotal) {
svga->vc = 0;
svga->sc = 0;
@@ -1080,7 +973,6 @@ svga_init(const device_t *info, svga_t *svga, void *p, int memsize,
svga->ramdac_type = RAMDAC_6BIT;
svga->map8 = svga->pallook;
svga->hblank_overscan = 1; /* Do at least 1 character of overscan after horizontal blanking. */
return 0;
}

2
src/video/vid_table.c
View File

@@ -111,8 +111,6 @@ video_cards[] = {
{ "tvga9000b", &tvga9000b_device },
{ "tgkorvga", &et4000k_isa_device },
{ "et2000", &et2000_device },
{ "et3000ax", &et3000_isa_device },
{ "et4000ax_tc6058af", &et4000_tc6058af_isa_device },
{ "et4000ax", &et4000_isa_device },
{ "et4000w32", &et4000w32_device },
{ "et4000w32i", &et4000w32i_isa_device },

65
src/win/Makefile.mingw
View File

@@ -46,7 +46,10 @@ ifeq ($(DEV_BUILD), y)
HEDAKA := y
endif
ifndef I450KX
I450KX := y
I450KX := y
endif
ifndef M154X
M154X := y
endif
ifndef LASERXT
LASERXT := y
@@ -75,6 +78,9 @@ ifeq ($(DEV_BUILD), y)
ifndef SIO_DETECT
SIO_DETECT := y
endif
ifndef M154X
M154X := y
endif
ifndef M6117
M6117 := y
endif
@@ -93,9 +99,6 @@ ifeq ($(DEV_BUILD), y)
ifndef OLIVETTI
OLIVETTI := y
endif
ifndef NEW_KBC
NEW_KBC := n
endif
else
ifndef DEBUG
DEBUG := n
@@ -121,6 +124,9 @@ else
ifndef LASERXT
LASERXT := n
endif
ifndef M154X
M154X := n
endif
ifndef MGA
MGA := n
endif
@@ -145,6 +151,9 @@ else
ifndef SIO_DETECT
SIO_DETECT := n
endif
ifndef M154X
M154X := n
endif
ifndef M6117
M6117 := n
endif
@@ -163,9 +172,6 @@ else
ifndef OLIVETTI
OLIVETTI := n
endif
ifndef NEW_KBC
NEW_KBC := n
endif
endif
# Defaults for several build options (possibly defined in a chained file.)
@@ -551,6 +557,11 @@ OPTS += -DUSE_SIO_DETECT
DEVBROBJ += sio_detect.o
endif
ifeq ($(M154X), y)
OPTS += -DUSE_M154X
DEVBROBJ += ali1531.o ali1543.o
endif
ifeq ($(M6117), y)
OPTS += -DUSE_M6117
DEVBROBJ += ali6117.o
@@ -587,8 +598,8 @@ CXXFLAGS := $(CFLAGS)
#########################################################################
# Create the (final) list of objects to build. #
#########################################################################
MAINOBJ := 86box.o config.o log.o random.o timer.o io.o acpi.o apm.o dma.o ddma.o \
nmi.o pic.o pit.o port_6x.o port_92.o ppi.o pci.o mca.o \
MAINOBJ := 86box.o config.o random.o timer.o io.o acpi.o apm.o dma.o ddma.o \
nmi.o pic.o pit.o port_92.o ppi.o pci.o mca.o \
usb.o device.o nvr.o nvr_at.o nvr_ps2.o \
$(VNCOBJ)
@@ -599,18 +610,13 @@ CPUOBJ := cpu.o cpu_table.o fpu.o x86.o \
x86seg.o x87.o x87_timings.o \
$(DYNARECOBJ)
CHIPSETOBJ := acc2168.o \
cs4031.o cs8230.o \
ali1217.o ali1429.o ali1489.o ali1531.o ali1543.o \
gc100.o headland.o \
intel_82335.o intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o \
opti283.o opti291.o opti391.o opti495.o opti822.o opti895.o opti5x7.o \
scamp.o scat.o \
stpc.o \
wd76c10.o vl82c480.o \
via_vt82c49x.o via_vt82c505.o via_apollo.o via_pipc.o \
sis_85c310.o sis_85c4xx.o sis_85c496.o sis_85c50x.o sis_5511.o sis_5571.o
CHIPSETOBJ := acc2168.o cs8230.o ali1217.o ali1429.o ali1489.o et6000.o headland.o intel_82335.o cs4031.o \
intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o opti495.o opti822.o opti895.o opti5x7.o scamp.o scat.o via_vt82c49x.o via_vt82c505.o \
gc100.o \
sis_85c310.o sis_85c4xx.o sis_85c496.o sis_85c50x.o sis_5511.o sis_5571.o sis_5598.o stpc.o opti283.o opti291.o \
umc_8886.o umc_8890.o umc_hb4.o \
via_apollo.o via_pipc.o wd76c10.o vl82c480.o
MCHOBJ := machine.o machine_table.o \
m_xt.o m_xt_compaq.o \
@@ -626,21 +632,10 @@ MCHOBJ := machine.o machine_table.o \
m_ps2_isa.o m_ps2_mca.o \
m_at_compaq.o \
m_at_286_386sx.o m_at_386dx_486.o \
m_at_socket4.o m_at_socket5.o m_at_socket7_3v.o m_at_socket7.o m_at_sockets7.o \
m_at_socket4_5.o m_at_socket7.o m_at_sockets7.o \
m_at_socket8.o m_at_slot1.o m_at_slot2.o m_at_socket370.o \
m_at_misc.o
ifeq ($(NEW_KBC), y)
DEVOBJ := bugger.o hwm.o hwm_lm75.o hwm_lm78.o hwm_gl518sm.o hwm_vt82c686.o ibm_5161.o isamem.o isartc.o \
lpt.o pci_bridge.o postcard.o serial.o vpc2007.o clock_ics9xxx.o isapnp.o \
i2c.o i2c_gpio.o smbus_piix4.o \
keyboard.o \
keyboard_xt.o kbc_at.o kbd_at.o \
mouse.o \
mouse_bus.o \
mouse_serial.o mouse_ps2.o \
phoenix_486_jumper.o
else
DEVOBJ := bugger.o hwm.o hwm_lm75.o hwm_lm78.o hwm_gl518sm.o hwm_vt82c686.o ibm_5161.o isamem.o isartc.o \
lpt.o pci_bridge.o postcard.o serial.o vpc2007.o clock_ics9xxx.o isapnp.o \
i2c.o i2c_gpio.o smbus_piix4.o \
@@ -650,11 +645,10 @@ DEVOBJ := bugger.o hwm.o hwm_lm75.o hwm_lm78.o hwm_gl518sm.o hwm_vt82c686.o ibm
mouse_bus.o \
mouse_serial.o mouse_ps2.o \
phoenix_486_jumper.o
endif
SIOOBJ := sio_acc3221.o \
sio_f82c710.o sio_82091aa.o sio_fdc37c651.o \
sio_fdc37c661.o sio_fdc37c66x.o sio_fdc37c67x.o sio_fdc37c669.o sio_fdc37c93x.o sio_fdc37m60x.o \
sio_fdc37c661.o sio_fdc37c66x.o sio_fdc37c669.o sio_fdc37c93x.o sio_fdc37m60x.o \
sio_it8661f.o \
sio_pc87306.o sio_pc87307.o sio_pc87309.o sio_pc87310.o sio_pc87311.o sio_pc87332.o \
sio_prime3b.o sio_prime3c.o \
@@ -759,7 +753,6 @@ VIDOBJ := video.o \
vid_bt48x_ramdac.o \
vid_av9194.o vid_icd2061.o vid_ics2494.o vid_ics2595.o \
vid_cl54xx.o \
vid_et3000.o \
vid_et4000.o vid_sc1148x_ramdac.o \
vid_sc1502x_ramdac.o \
vid_et4000w32.o vid_stg_ramdac.o \

3
src/win/win.c
View File

@@ -508,8 +508,7 @@ main_thread(void *param)
frames = 0;
}
} else /* Just so we dont overload the host OS. */
Sleep((drawits < -1) ? 1 : 0);
// Sleep(1);
Sleep(1);
/* If needed, handle a screen resize. */
if (doresize && !video_fullscreen) {