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fix logging for ramin writes.

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This commit is contained in:
starfrost013
2025-01-22 14:52:46 +00:00
parent bc77c95c4d
commit e4f446c6d0
4 changed files with 52 additions and 6 deletions
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2
doc/nvidia_notes/nv3_object_classes.txt
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@@ -26,7 +26,7 @@ Object classes as understood by the GPU.
0x15 = Stretched image from CPU
0x16 = INVALID
0x17 = Direct3D 5.0 accelerated textured triangle w/zeta buffer
0x18 = INVALID
0x18 = Point w/zeta buffer
0x19 = INVALID
0x1A = INVALID
0x1B = INVALID

27
src/include/86box/nv/vid_nv3.h
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@@ -242,6 +242,10 @@ extern const device_config_t nv3_config[];
#define NV3_PFIFO_CACHE0_ACCESS 0x3000
#define NV3_PFIFO_CACHE0_DMA_CHANNEL_ID 0x3004
#define NV3_PFIFO_CACHE0_PUT 0x3010
#define NV3_PFIFO_CACHE0_STATUS 0x3014
#define NV3_PFIFO_CACHE0_STATUS_RANOUT 0 // 1 if we fucked up
#define NV3_PFIFO_CACHE0_STATUS_LOW_MARK 4 // 1 if ramro is empty
#define NV3_PFIFO_CACHE0_STATUS_HIGH_MARK 8
#define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit
#define NV3_PFIFO_CACHE0_PULLER 0x3040
#define NV3_PFIFO_CACHE0_GET 0x3070
@@ -250,6 +254,10 @@ extern const device_config_t nv3_config[];
#define NV3_PFIFO_CACHE1_DMA_CHANNEL_ID 0x3204
#define NV3_PFIFO_CACHE1_PUT 0x3210
#define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2
#define NV3_PFIFO_CACHE1_STATUS 0x3214
#define NV3_PFIFO_CACHE1_STATUS_RANOUT 0 // 1 if we fucked up
#define NV3_PFIFO_CACHE1_STATUS_LOW_MARK 4 // 1 if ramro is empty
#define NV3_PFIFO_CACHE1_STATUS_HIGH_MARK 8
#define NV3_PFIFO_CACHE1_DMA_STATUS 0x3218
#define NV3_PFIFO_CACHE1_DMA_CONFIG_0 0x3220
#define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224
@@ -740,6 +748,20 @@ typedef struct nv3_pbus_s
nv3_pbus_rma_t rma;
} nv3_pbus_t;
typedef struct nv3_pfifo_cache_s
{
uint8_t put_address; // Trigger a DMA into the value you put here.
uint8_t get_address; // Trigger a DMA from the value you put here into where you were going.
/* TODO */
} nv3_pfifo_cache_t;
typedef struct nv3_pfifo_cache_entry_s
{
uint8_t subchannel_id : 3;
uint16_t method : 11; // method id depending on class (offset from entry channel start in ramin)
uint32_t data; // is this the context
} nv3_pfifo_cache_entry_t;
// Command submission to PGRAPH
typedef struct nv3_pfifo_s
{
@@ -749,7 +771,10 @@ typedef struct nv3_pfifo_s
uint32_t ramfc_config; // RAMFC config
uint32_t ramro_config; // RAMRO config
uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0?
nv3_pfifo_cache_t cache0_settings;
nv3_pfifo_cache_t cache1_settings;
uint32_t cache0_status; // status of cache0
uint32_t cache1_status; // status of cache1
} nv3_pfifo_t;
// create_object(uint32_t type) here

13
src/video/nv/nv3/subsystems/nv3_pfifo.c
View File

@@ -29,7 +29,7 @@
#include <86Box/nv/vid_nv3.h>
//
// ****** pfifo register list START ******
// ****** PFIFO register list START ******
//
nv_register_t pfifo_registers[] = {
@@ -38,6 +38,12 @@ nv_register_t pfifo_registers[] = {
{ NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL },
{ NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL },
{ NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL },
{ NV3_PFIFO_CACHE0_STATUS, "PFIFO - Cache0 Status", NULL, NULL},
{ NV3_PFIFO_CACHE1_STATUS, "PFIFO - Cache1 Status", NULL, NULL},
{ NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL },
{ NV3_PFIFO_CACHE1_GET, "PFIFO - Cache1 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL },
{ NV3_PFIFO_CACHE0_PUT, "PFIFO - Cache0 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL },
{ NV3_PFIFO_CACHE1_PUT, "PFIFO - Cache1 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL },
{ NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value
};
@@ -101,6 +107,9 @@ uint32_t nv3_pfifo_read(uint32_t address)
case NV3_PFIFO_CONFIG_RAMRO:
ret = nv3->pfifo.ramro_config;
break;
case NV3_PFIFO_CACHE0_GET:
//wa
break;
}
}
@@ -220,7 +229,7 @@ uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val)
/*
Back to sanity
*/
uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val)
uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val)
{
uint32_t mask = val >> 1;

16
src/video/nv/nv3/subsystems/nv3_pramin.c
View File

@@ -43,6 +43,8 @@
// Read 8-bit ramin
uint8_t nv3_ramin_read8(uint32_t addr, void* priv)
{
if (!nv3) return;
addr &= (nv3->nvbase.svga.vram_max - 1);
uint32_t raw_addr = addr; // saved after and
@@ -62,6 +64,8 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv)
// Read 16-bit ramin
uint16_t nv3_ramin_read16(uint32_t addr, void* priv)
{
if (!nv3) return;
addr &= (nv3->nvbase.svga.vram_max - 1);
// why does this not work in one line
@@ -86,6 +90,8 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv)
// Read 32-bit ramin
uint32_t nv3_ramin_read32(uint32_t addr, void* priv)
{
if (!nv3) return;
addr &= (nv3->nvbase.svga.vram_max - 1);
// why does this not work in one line
@@ -111,6 +117,8 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv)
// Write 8-bit ramin
void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv)
{
if (!nv3) return;
addr &= (nv3->nvbase.svga.vram_max - 1);
uint32_t raw_addr = addr; // saved after and
@@ -134,6 +142,8 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv)
// Write 16-bit ramin
void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv)
{
if (!nv3) return;
addr &= (nv3->nvbase.svga.vram_max - 1);
// why does this not work in one line
@@ -149,7 +159,7 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv)
if (!nv3_pramin_arbitrate_write(addr, val32))
{
vram_16bit[addr] = val;
nv_log("NV3: Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, raw_addr);
nv_log("NV3: Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr);
}
@@ -158,6 +168,8 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv)
// Write 32-bit ramin
void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv)
{
if (!nv3) return;
addr &= (nv3->nvbase.svga.vram_max - 1);
// why does this not work in one line
@@ -173,7 +185,7 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv)
if (!nv3_pramin_arbitrate_write(addr, val32))
{
vram_32bit[addr] = val;
nv_log("NV3: Write dnv3_pramin_arbitrate_readword to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, raw_addr);
nv_log("NV3: Write dword to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr);
}
}