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sonarlint related changes

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This commit is contained in:
Jasmine Iwanek
2023-06-24 08:55:42 -04:00
parent 552554de2f
commit db3f1cce7c
24 changed files with 1187 additions and 875 deletions
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17
src/chipset/intel_815ep.c
View File

@@ -13,8 +13,8 @@
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Jasmine Iwanek.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#include <stdarg.h>
@@ -30,6 +30,7 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/plat.h> // Replace with plat_unused.h when upstreamed
#include <86box/mem.h>
#include <86box/pci.h>
@@ -57,9 +58,10 @@ intel_815ep_log(const char *fmt, ...)
typedef struct intel_815ep_t {
uint8_t pci_conf[256];
smram_t *lsmm_segment, *h_segment, *usmm_segment;
smram_t *lsmm_segment;
smram_t *h_segment;
smram_t *usmm_segment;
agpgart_t *agpgart;
} intel_815ep_t;
static void
@@ -126,6 +128,8 @@ intel_lsmm_segment_recalc(intel_815ep_t *dev, uint8_t val)
case 3:
smram_enable(dev->lsmm_segment, 0x000a0000, 0x000a0000, 0x20000, 0, 1);
break;
default:
break;
}
flushmmucache();
@@ -305,6 +309,9 @@ intel_815ep_write(int func, int addr, uint8_t val, void *priv)
case 0xcb:
dev->pci_conf[addr] = val & 0x3f;
break;
default:
break;
}
}
@@ -414,7 +421,7 @@ intel_815ep_close(void *priv)
}
static void *
intel_815ep_init(const device_t *info)
intel_815ep_init(UNUSED(const device_t *info))
{
intel_815ep_t *dev = (intel_815ep_t *) malloc(sizeof(intel_815ep_t));
memset(dev, 0, sizeof(intel_815ep_t));

38
src/chipset/intel_ich2.c
View File

@@ -13,8 +13,8 @@
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Jasmine Iwanek.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#include <stdarg.h>
@@ -30,6 +30,7 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/plat.h> // Replace with plat_unused.h when upstreamed
#include <86box/apm.h>
#include <86box/nvr.h>
@@ -81,7 +82,6 @@ typedef struct intel_ich2_t {
smbus_piix4_t *smbus;
tco_t *tco;
usb_t *usb_hub[2];
} intel_ich2_t;
/* LPC Bridge functions */
@@ -208,6 +208,9 @@ intel_ich2_trap_update(void *priv)
case 7:
temp_addr = 0x3e8;
break;
default:
break;
}
intel_ich2_device_trap_setup(0x48, 0x10, temp_addr, 8, dev->trap_device[2]);
@@ -244,6 +247,9 @@ intel_ich2_trap_update(void *priv)
case 7:
temp_addr = 0x3e8;
break;
default:
break;
}
intel_ich2_device_trap_setup(0x48, 0x10, temp_addr, 8, dev->trap_device[3]);
@@ -260,6 +266,9 @@ intel_ich2_trap_update(void *priv)
case 2:
temp_addr = 0x3bc;
break;
default:
break;
}
intel_ich2_device_trap_setup(0x48, 0x10, temp_addr, 8, dev->trap_device[4]);
@@ -284,6 +293,9 @@ intel_ich2_trap_update(void *priv)
case 3:
temp_addr = 0xf40;
break;
default:
break;
}
intel_ich2_device_trap_setup(0x49, 0x04, temp_addr, 8, dev->trap_device[6]);
@@ -566,6 +578,9 @@ intel_ich2_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[func][addr] = val & ((addr & 1) ? 0x01 : 0xfe);
intel_ich2_function_disable(dev);
break;
default:
break;
}
} else if ((func == 1) && !(dev->pci_conf[0][0xf2] & 2)) {
intel_ich2_log("Intel ICH2 IDE: dev->regs[%02x] = %02x\n", addr, val);
@@ -607,6 +622,9 @@ intel_ich2_write(int func, int addr, uint8_t val, void *priv)
case 0x4a ... 0x4b:
dev->pci_conf[func][addr] = val & 0x33;
break;
default:
break;
}
} else if (((func == 2) && !(dev->pci_conf[0][0xf2] & 4)) || ((func == 4) && !(dev->pci_conf[0][0xf2] & 0x10))) {
intel_ich2_log("Intel ICH2 USB Hub %d: dev->regs[%02x] = %02x\n", (func == 4), addr, val);
@@ -636,6 +654,9 @@ intel_ich2_write(int func, int addr, uint8_t val, void *priv)
case 0xc4:
dev->pci_conf[func][addr] = val & 3;
break;
default:
break;
}
} else if ((func == 3) && !(dev->pci_conf[0][0xf2] & 8)) {
intel_ich2_log("Intel ICH2 SMBus: dev->regs[%02x] = %02x\n", addr, val);
@@ -665,6 +686,9 @@ intel_ich2_write(int func, int addr, uint8_t val, void *priv)
intel_ich2_smbus_setup(dev);
smbus_piix4_smi_en(!!(val & 2), dev->smbus);
break;
default:
break;
}
}
@@ -699,6 +723,9 @@ intel_ich2_write(int func, int addr, uint8_t val, void *priv)
if (sound_card_current[0] == SOUND_INTERNAL) /* can't use pointers as whatever recieved from there is temporary. */
intel_ac97_set_irq(pci_get_int(0x1f, 2), dev->ac97);
break;
default:
break;
}
} else if ((func == 6) && !(dev->pci_conf[0][0xf2] & 0x40)) {
intel_ich2_log("Intel ICH2 AC'97 Modem: dev->regs[%02x] = %02x\n", addr, val);
@@ -723,6 +750,9 @@ intel_ich2_write(int func, int addr, uint8_t val, void *priv)
case 0x3c:
dev->pci_conf[func][addr] = val;
break;
default:
break;
}
}
}
@@ -977,7 +1007,7 @@ intel_ich2_close(void *priv)
}
static void *
intel_ich2_init(const device_t *info)
intel_ich2_init(UNUSED(const device_t *info))
{
intel_ich2_t *dev = (intel_ich2_t *) malloc(sizeof(intel_ich2_t));
memset(dev, 0, sizeof(intel_ich2_t));

2
src/cpu/386_dynarec.c
View File

@@ -431,7 +431,7 @@ exec386_dynarec_dyn(void)
uint64_t mask = (uint64_t) 1 << ((phys_addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
# ifdef USE_NEW_DYNAREC
int byte_offset = (phys_addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
uint64_t byte_mask = 1ull << (PAGE_BYTE_MASK_MASK & 0x3f);
uint64_t byte_mask = 1ULL << (PAGE_BYTE_MASK_MASK & 0x3f);
if ((page->code_present_mask & mask) || (page->byte_code_present_mask[byte_offset] & byte_mask))
# else

148
src/cpu/cpu.c
View File

@@ -80,66 +80,105 @@ fpu_state_t fpu_state;
uint32_t abrt_error;
#ifdef USE_DYNAREC
const OpFn *x86_dynarec_opcodes, *x86_dynarec_opcodes_0f,
*x86_dynarec_opcodes_d8_a16, *x86_dynarec_opcodes_d8_a32,
*x86_dynarec_opcodes_d9_a16, *x86_dynarec_opcodes_d9_a32,
*x86_dynarec_opcodes_da_a16, *x86_dynarec_opcodes_da_a32,
*x86_dynarec_opcodes_db_a16, *x86_dynarec_opcodes_db_a32,
*x86_dynarec_opcodes_dc_a16, *x86_dynarec_opcodes_dc_a32,
*x86_dynarec_opcodes_dd_a16, *x86_dynarec_opcodes_dd_a32,
*x86_dynarec_opcodes_de_a16, *x86_dynarec_opcodes_de_a32,
*x86_dynarec_opcodes_df_a16, *x86_dynarec_opcodes_df_a32,
*x86_dynarec_opcodes_REPE, *x86_dynarec_opcodes_REPNE,
*x86_dynarec_opcodes_3DNOW;
const OpFn *x86_dynarec_opcodes, *x86_dynarec_opcodes_0f;
const OpFn *x86_dynarec_opcodes_d8_a16, *x86_dynarec_opcodes_d8_a32;
const OpFn *x86_dynarec_opcodes_d9_a16, *x86_dynarec_opcodes_d9_a32;
const OpFn *x86_dynarec_opcodes_da_a16, *x86_dynarec_opcodes_da_a32;
const OpFn *x86_dynarec_opcodes_db_a16, *x86_dynarec_opcodes_db_a32;
const OpFn *x86_dynarec_opcodes_dc_a16, *x86_dynarec_opcodes_dc_a32;
const OpFn *x86_dynarec_opcodes_dd_a16, *x86_dynarec_opcodes_dd_a32;
const OpFn *x86_dynarec_opcodes_de_a16, *x86_dynarec_opcodes_de_a32;
const OpFn *x86_dynarec_opcodes_df_a16, *x86_dynarec_opcodes_df_a32;
const OpFn *x86_dynarec_opcodes_REPE, *x86_dynarec_opcodes_REPNE;
const OpFn *x86_dynarec_opcodes_3DNOW;
#endif
const OpFn *x86_opcodes, *x86_opcodes_0f,
*x86_opcodes_d8_a16, *x86_opcodes_d8_a32,
*x86_opcodes_d9_a16, *x86_opcodes_d9_a32,
*x86_opcodes_da_a16, *x86_opcodes_da_a32,
*x86_opcodes_db_a16, *x86_opcodes_db_a32,
*x86_opcodes_dc_a16, *x86_opcodes_dc_a32,
*x86_opcodes_dd_a16, *x86_opcodes_dd_a32,
*x86_opcodes_de_a16, *x86_opcodes_de_a32,
*x86_opcodes_df_a16, *x86_opcodes_df_a32,
*x86_opcodes_REPE, *x86_opcodes_REPNE,
*x86_opcodes_3DNOW;
const OpFn *x86_opcodes, *x86_opcodes_0f;
const OpFn *x86_opcodes_d8_a16, *x86_opcodes_d8_a32;
const OpFn *x86_opcodes_d9_a16, *x86_opcodes_d9_a32;
const OpFn *x86_opcodes_da_a16, *x86_opcodes_da_a32;
const OpFn *x86_opcodes_db_a16, *x86_opcodes_db_a32;
const OpFn *x86_opcodes_dc_a16, *x86_opcodes_dc_a32;
const OpFn *x86_opcodes_dd_a16, *x86_opcodes_dd_a32;
const OpFn *x86_opcodes_de_a16, *x86_opcodes_de_a32;
const OpFn *x86_opcodes_df_a16, *x86_opcodes_df_a32;
const OpFn *x86_opcodes_REPE, *x86_opcodes_REPNE;
const OpFn *x86_opcodes_3DNOW;
uint16_t cpu_fast_off_count, cpu_fast_off_val;
uint16_t cpu_fast_off_count;
uint16_t cpu_fast_off_val;
uint16_t temp_seg_data[4] = { 0, 0, 0, 0 };
int isa_cycles, cpu_inited,
int isa_cycles;
int cpu_inited;
cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l,
cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles,
cpu_waitstates, cpu_cache_int_enabled, cpu_cache_ext_enabled,
cpu_isa_speed, cpu_pci_speed, cpu_isa_pci_div, cpu_agp_speed, cpu_alt_reset,
int cpu_cycles_read;
int cpu_cycles_read_l;
int cpu_cycles_write;
int cpu_cycles_write_l;
int cpu_prefetch_cycles;
int cpu_prefetch_width;
int cpu_mem_prefetch_cycles;
int cpu_rom_prefetch_cycles;
int cpu_waitstates;
int cpu_cache_int_enabled;
int cpu_cache_ext_enabled;
int cpu_isa_speed;
int cpu_pci_speed;
int cpu_isa_pci_div;
int cpu_agp_speed;
int cpu_alt_reset;
cpu_override, cpu_effective, cpu_multi, cpu_16bitbus, cpu_64bitbus,
cpu_cyrix_alignment, CPUID,
int cpu_override;
int cpu_effective;
int cpu_multi;
int cpu_16bitbus;
int cpu_64bitbus;
int cpu_cyrix_alignment;
int CPUID;
is186, is_nec,
is286, is386, is6117, is486 = 1,
cpu_isintel, cpu_iscyrix, hascache, isibm486, israpidcad, is_vpc,
is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
int is186;
int is_nec;
int is286;
int is386;
int is6117;
int is486 = 1;
int cpu_isintel;
int cpu_iscyrix;
int hascache;
int isibm486;
int israpidcad;
int is_vpc;
int is_am486;
int is_am486dxl;
int is_pentium;
int is_k5;
int is_k6;
int is_p6;
int is_cxsmm;
int hasfpu;
timing_rr, timing_mr, timing_mrl, timing_rm, timing_rml,
timing_mm, timing_mml, timing_bt, timing_bnt,
timing_int, timing_int_rm, timing_int_v86, timing_int_pm,
timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm,
timing_iret_pm_outer, timing_call_rm, timing_call_pm, timing_call_pm_gate,
timing_call_pm_gate_inner, timing_retf_rm, timing_retf_pm, timing_retf_pm_outer,
timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate, timing_misaligned;
uint32_t cpu_features, cpu_fast_off_flags;
int timing_rr, timing_mr, timing_mrl, timing_rm, timing_rml;
int timing_mm, timing_mml, timing_bt, timing_bnt;
int timing_int, timing_int_rm, timing_int_v86, timing_int_pm;
int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm;
int timing_iret_pm_outer, timing_call_rm, timing_call_pm, timing_call_pm_gate;
int timing_call_pm_gate_inner, timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate, timing_misaligned;
uint32_t cpu_features;
uint32_t cpu_fast_off_flags;
uint32_t _tr[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
uint32_t cache_index = 0;
uint8_t _cache[2048];
uint64_t cpu_CR4_mask, tsc = 0;
uint64_t cpu_CR4_mask;
uint64_t tsc = 0;
uint64_t pmc[2] = { 0, 0 };
double cpu_dmulti, cpu_busspeed;
double cpu_dmulti;
double cpu_busspeed;
msr_t msr;
@@ -148,11 +187,18 @@ cyrix_t cyrix;
cpu_family_t *cpu_f;
CPU *cpu_s;
uint8_t do_translate = 0, do_translate2 = 0;
uint8_t do_translate = 0;
uint8_t do_translate2 = 0;
void (*cpu_exec)(int cycs);
static uint8_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6;
static uint8_t ccr0;
static uint8_t ccr1;
static uint8_t ccr2;
static uint8_t ccr3;
static uint8_t ccr4;
static uint8_t ccr5;
static uint8_t ccr6;
static int cyrix_addr;
@@ -225,7 +271,8 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
{
const machine_t *machine_s = &machines[machine];
const CPU *cpu_s = &cpu_family->cpus[cpu];
uint32_t packages, bus_speed;
uint32_t packages;
uint32_t bus_speed;
uint8_t i;
double multi;
@@ -1647,7 +1694,7 @@ cpu_current_pc(char *bufp)
sprintf(bufp, "%04X:%04X", CS, cpu_state.pc);
return (bufp);
return bufp;
}
void
@@ -3253,7 +3300,7 @@ cpu_write(uint16_t addr, uint8_t val, void *priv)
if (!(ccr3 & CCR3_SMI_LOCK) || in_smm) {
cyrix.arr[3].base = (cyrix.arr[3].base & ~0x0000f000) | ((val & 0xf0) << 8);
if ((val & 0xf) == 0xf)
cyrix.arr[3].size = 1ull << 32; /* 4 GB */
cyrix.arr[3].size = 1ULL << 32; /* 4 GB */
else if (val & 0xf)
cyrix.arr[3].size = 2048 << (val & 0xf);
else
@@ -3315,6 +3362,9 @@ cpu_read(uint16_t addr, void *priv)
return cpu_s->cyrix_id & 0xff;
case 0xff:
return cpu_s->cyrix_id >> 8;
default:
break;
}
if ((cyrix_addr & 0xf0) == 0xc0)

224
src/cpu/cpu.h
View File

@@ -150,8 +150,10 @@ typedef struct {
uint32_t cpuid_model;
uint16_t cyrix_id;
uint8_t cpu_flags;
int8_t mem_read_cycles, mem_write_cycles;
int8_t cache_read_cycles, cache_write_cycles;
int8_t mem_read_cycles;
int8_t mem_write_cycles;
int8_t cache_read_cycles;
int8_t cache_write_cycles;
int8_t atclk_div;
} CPU;
@@ -215,17 +217,19 @@ typedef union {
uint32_t l;
uint16_t w;
struct {
uint8_t l,
h;
uint8_t l;
uint8_t h;
} b;
} x86reg;
typedef struct {
uint32_t base;
uint32_t limit;
uint8_t access, ar_high;
uint8_t access;
uint8_t ar_high;
uint16_t seg;
uint32_t limit_low, limit_high;
uint32_t limit_low;
uint32_t limit_high;
int checked; /*Non-zero if selector is known to be valid*/
} x86seg;
@@ -243,8 +247,9 @@ typedef union {
typedef struct {
/* IDT WinChip and WinChip 2 MSR's */
uint32_t tr1, tr12; /* 0x00000002, 0x0000000e */
uint32_t cesr; /* 0x00000011 */
uint32_t tr1; /* 0x00000002, 0x0000000e */
uint32_t tr12; /* 0x00000002, 0x0000000e */
uint32_t cesr; /* 0x00000011 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */
@@ -259,8 +264,9 @@ typedef struct {
uint64_t mtrr_cap; /* 0x000000fe */
/* IDT WinChip and WinChip 2 MSR's that are also on the VIA Cyrix III */
uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
uint64_t fcr2, fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
uint64_t fcr2; /* 0x00000108 (IDT), 0x00001108 (VIA) */
uint64_t fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx116; /* 0x00000116 */
@@ -276,8 +282,9 @@ typedef struct {
uint64_t mcg_ctl; /* 0x0000017b - Machine Check Architecture */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx186, ecx187; /* 0x00000186, 0x00000187 */
uint64_t ecx1e0; /* 0x000001e0 */
uint64_t ecx186; /* 0x00000186, 0x00000187 */
uint64_t ecx187; /* 0x00000186, 0x00000187 */
uint64_t ecx1e0; /* 0x000001e0 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
on the VIA Cyrix III */
@@ -331,7 +338,8 @@ typedef struct {
uint64_t amd_epmr; /* 0xc0000086 */
/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
uint64_t amd_psor, amd_pfir; /* 0xc0000087, 0xc0000088 */
uint64_t amd_psor; /* 0xc0000087, 0xc0000088 */
uint64_t amd_pfir; /* 0xc0000087, 0xc0000088 */
/* K6-3, K6-2P, and K6-3P MSR's */
uint64_t amd_l2aar; /* 0xc0000089 */
@@ -351,33 +359,38 @@ typedef struct {
uint32_t eaaddr;
int flags_op;
uint32_t flags_res,
flags_op1, flags_op2;
uint32_t flags_res;
uint32_t flags_op1;
uint32_t flags_op2;
uint32_t pc,
oldpc, op32;
uint32_t pc;
uint32_t oldpc;
uint32_t op32;
int TOP;
union {
struct {
int8_t rm,
mod,
reg;
int8_t rm;
int8_t mod;
int8_t reg;
} rm_mod_reg;
int32_t rm_mod_reg_data;
} rm_data;
uint8_t ssegs, ismmx,
abrt, _smi_line;
uint8_t ssegs;
uint8_t ismmx;
uint8_t abrt;
uint8_t _smi_line;
int _cycles;
#ifdef FPU_CYCLES
int _cycles, _fpu_cycles, _in_smm;
#else
int _cycles, _in_smm;
int _fpu_cycles;
#endif
int _in_smm;
uint16_t npxs, npxc;
uint16_t npxs;
uint16_t npxc;
double ST[8];
@@ -386,26 +399,34 @@ typedef struct {
MMX_REG MM[8];
#ifdef USE_NEW_DYNAREC
uint32_t old_fp_control, new_fp_control;
uint32_t old_fp_control;
uint32_t new_fp_control;
# if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
uint16_t old_fp_control2, new_fp_control2;
uint16_t old_fp_control2;
uint16_t new_fp_control2;
# endif
# if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64
uint32_t trunc_fp_control;
uint32_t trunc_fp_control;
# endif
#else
uint16_t old_npxc, new_npxc;
uint16_t old_npxc;
uint16_t new_npxc;
#endif
x86seg seg_cs, seg_ds, seg_es, seg_ss,
seg_fs, seg_gs;
x86seg seg_cs;
x86seg seg_ds;
x86seg seg_es;
x86seg seg_ss;
x86seg seg_fs;
x86seg seg_gs;
union {
uint32_t l;
uint16_t w;
} CR0;
uint16_t flags, eflags;
uint16_t flags;
uint16_t eflags;
uint32_t _smbase;
} cpu_state_t;
@@ -421,7 +442,9 @@ typedef struct {
uint16_t fds;
floatx80 st_space[8];
unsigned char tos;
unsigned char align1, align2, align3;
unsigned char align1;
unsigned char align2;
unsigned char align3;
} fpu_state_t;
#define in_smm cpu_state._in_smm
@@ -514,7 +537,8 @@ extern int cpu_override;
extern int cpu_isintel;
extern int cpu_iscyrix;
extern int cpu_16bitbus, cpu_64bitbus;
extern int cpu_16bitbus;
extern int cpu_64bitbus;
extern int cpu_pci_speed;
extern int cpu_multi;
extern double cpu_dmulti;
@@ -523,8 +547,19 @@ extern double cpu_busspeed;
extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
penalties when crossing 8-byte boundaries*/
extern int is8086, is186, is286, is386, is6117, is486;
extern int is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
extern int is8086;
extern int is186;
extern int is286;
extern int is386;
extern int is6117;
extern int is486;
extern int is_am486;
extern int is_am486dxl;
extern int is_pentium;
extern int is_k5;
extern int is_k6;
extern int is_p6;
extern int is_cxsmm;
extern int hascache;
extern int isibm486;
extern int is_nec;
@@ -542,7 +577,8 @@ extern int hasfpu;
extern uint32_t cpu_features;
extern int smi_latched, smm_in_hlt;
extern int smi_latched;
extern int smm_in_hlt;
extern int smi_block;
#ifdef USE_NEW_DYNAREC
@@ -558,12 +594,21 @@ extern int cgate16;
extern int cpl_override;
extern int CPUID;
extern uint64_t xt_cpu_multi;
extern int isa_cycles, cpu_inited;
extern uint32_t oldds, oldss, olddslimit, oldsslimit, olddslimitw, oldsslimitw;
extern int isa_cycles;
extern int cpu_inited;
extern uint32_t oldds;
extern uint32_t oldss;
extern uint32_t olddslimit;
extern uint32_t oldsslimit;
extern uint32_t olddslimitw;
extern uint32_t oldsslimitw;
extern uint32_t pccache;
extern uint8_t *pccache2;
extern double bus_timing, isa_timing, pci_timing, agp_timing;
extern double bus_timing;
extern double isa_timing;
extern double pci_timing;
extern double agp_timing;
extern uint64_t pmc[2];
extern uint16_t temp_seg_data[4];
extern uint16_t cs_msr;
@@ -571,13 +616,16 @@ extern uint32_t esp_msr;
extern uint32_t eip_msr;
/* For the AMD K6. */
extern uint64_t amd_efer, star;
extern uint64_t amd_efer;
extern uint64_t star;
#define FPU_CW_Reserved_Bits (0xe0c0)
#define cr0 cpu_state.CR0.l
#define msw cpu_state.CR0.w
extern uint32_t cr2, cr3, cr4;
#define cr0 cpu_state.CR0.l
#define msw cpu_state.CR0.w
extern uint32_t cr2;
extern uint32_t cr3;
extern uint32_t cr4;
extern uint32_t dr[8];
extern uint32_t _tr[8];
extern uint32_t cache_index;
@@ -587,7 +635,10 @@ extern uint8_t _cache[2048];
_cs,_ds,_es,_ss are the segment structures
CS,DS,ES,SS is the 16-bit data
cs,ds,es,ss are defines to the bases*/
extern x86seg gdt, ldt, idt, tr;
extern x86seg gdt;
extern x86seg ldt;
extern x86seg idt;
extern x86seg tr;
extern x86seg _oldds;
#define CS cpu_state.seg_cs.seg
#define DS cpu_state.seg_ds.seg
@@ -604,37 +655,67 @@ extern x86seg _oldds;
#define ISA_CYCLES(x) (x * isa_cycles)
extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
extern int cpu_cycles_read;
extern int cpu_cycles_read_l;
extern int cpu_cycles_write;
extern int cpu_cycles_write_l;
extern int cpu_prefetch_cycles;
extern int cpu_prefetch_width;
extern int cpu_mem_prefetch_cycles;
extern int cpu_rom_prefetch_cycles;
extern int cpu_waitstates;
extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
extern int cpu_isa_speed, cpu_pci_speed, cpu_agp_speed;
extern int cpu_cache_int_enabled;
extern int cpu_cache_ext_enabled;
extern int cpu_isa_speed;
extern int cpu_pci_speed;
extern int cpu_agp_speed;
extern int timing_rr;
extern int timing_mr, timing_mrl;
extern int timing_rm, timing_rml;
extern int timing_mm, timing_mml;
extern int timing_bt, timing_bnt;
extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm;
extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm;
extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm;
extern int timing_call_pm_gate, timing_call_pm_gate_inner;
extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
extern int timing_mr;
extern int timing_mrl;
extern int timing_rm;
extern int timing_rml;
extern int timing_mm;
extern int timing_mml;
extern int timing_bt;
extern int timing_bnt;
extern int timing_int;
extern int timing_int_rm;
extern int timing_int_v86;
extern int timing_int_pm;
extern int timing_int_pm_outer;
extern int timing_iret_rm;
extern int timing_iret_v86;
extern int timing_iret_pm;
extern int timing_iret_pm_outer;
extern int timing_call_rm;
extern int timing_call_pm;
extern int timing_call_pm_gate;
extern int timing_call_pm_gate_inner;
extern int timing_retf_rm;
extern int timing_retf_pm;
extern int timing_retf_pm_outer;
extern int timing_jmp_rm;
extern int timing_jmp_pm;
extern int timing_jmp_pm_gate;
extern int timing_misaligned;
extern int in_sys, unmask_a20_in_smm;
extern int in_sys;
extern int unmask_a20_in_smm;
extern int cycles_main;
extern uint32_t old_rammask;
#ifdef USE_ACYCS
extern int acycs;
#endif
extern int pic_pending, is_vpc;
extern int soft_reset_mask, alt_access;
extern int pic_pending;
extern int is_vpc;
extern int soft_reset_mask;
extern int alt_access;
extern int cpu_end_block_after_ins;
extern uint16_t cpu_fast_off_count, cpu_fast_off_val;
extern uint16_t cpu_fast_off_count;
extern uint16_t cpu_fast_off_val;
extern uint32_t cpu_fast_off_flags;
/* Functions. */
@@ -709,7 +790,8 @@ extern void x87_dumpregs(void);
extern void x87_reset(void);
#endif
extern int cpu_effective, cpu_alt_reset;
extern int cpu_effective;
extern int cpu_alt_reset;
extern void cpu_dynamic_switch(int new_cpu);
extern void cpu_ven_reset(void);
@@ -744,12 +826,15 @@ typedef struct
uint32_t smhr;
} cyrix_t;
extern uint32_t addr64, addr64_2;
extern uint32_t addr64a[8], addr64a_2[8];
extern uint32_t addr64;
extern uint32_t addr64_2;
extern uint32_t addr64a[8];
extern uint32_t addr64a_2[8];
extern int soft_reset_pci;
extern int reset_on_hlt, hlt_reset_pending;
extern int reset_on_hlt;
extern int hlt_reset_pending;
extern cyrix_t cyrix;
@@ -757,7 +842,8 @@ extern uint8_t use_custom_nmi_vector;
extern uint32_t custom_nmi_vector;
extern void (*cpu_exec)(int cycs);
extern uint8_t do_translate, do_translate2;
extern uint8_t do_translate;
extern uint8_t do_translate2;
extern void SF_FPU_reset(void);

16
src/device/hwm_nsc366.c
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
/* The conversion algorithms were taken by the pc87360.c driver of the Linux kernel.
@@ -29,6 +31,7 @@
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h> // Replace with plat_unused.h when upstreamed
#include <86box/hwm.h>
#include <86box/nsc366.h>
@@ -103,6 +106,9 @@ nsc366_fscm_write(uint16_t addr, uint8_t val, void *priv)
case 0x0d:
dev->fscm_config[addr] = (val & 0x78) | 1;
break;
default:
break;
}
}
@@ -192,6 +198,9 @@ nsc366_vlm_write(uint16_t addr, uint8_t val, void *priv)
if (VLM_BANK < 13)
dev->vlm_config_bank[VLM_BANK][addr - 0x0a] = val;
break;
default:
break;
}
}
@@ -279,6 +288,9 @@ nsc366_tms_write(uint16_t addr, uint8_t val, void *priv)
if (TMS_BANK < 3)
dev->tms_config_bank[TMS_BANK][addr - 0x0a] = val;
break;
default:
break;
}
}
@@ -370,7 +382,7 @@ nsc366_hwm_close(void *priv)
}
static void *
nsc366_hwm_init(const device_t *info)
nsc366_hwm_init(UNUSED(const device_t *info))
{
nsc366_hwm_t *dev = (nsc366_hwm_t *) malloc(sizeof(nsc366_hwm_t));
memset(dev, 0, sizeof(nsc366_hwm_t));

10
src/device/intel_ich2_gpio.c
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#include <stdarg.h>
@@ -28,6 +30,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/intel_ich2_gpio.h>
#include <86box/plat.h> // Replace with plat_unused.h when upstreamed
#ifdef ENABLE_INTEL_ICH2_GPIO_LOG
int intel_ich2_gpio_do_log = ENABLE_INTEL_ICH2_GPIO_LOG;
@@ -97,6 +100,9 @@ intel_ich2_gpio_write(uint16_t addr, uint8_t val, void *priv)
case 0x2d:
dev->gpio_regs[addr] = val & 0x39;
break;
default:
break;
}
}
@@ -158,7 +164,7 @@ intel_ich2_gpio_close(void *priv)
}
static void *
intel_ich2_gpio_init(const device_t *info)
intel_ich2_gpio_init(UNUSED(const device_t *info))
{
intel_ich2_gpio_t *dev = (intel_ich2_gpio_t *) malloc(sizeof(intel_ich2_gpio_t));
memset(dev, 0, sizeof(intel_ich2_gpio_t));

9
src/device/intel_ich2_trap.c
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#include <stdarg.h>
@@ -27,6 +29,7 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/plat.h> // Replace with plat_unused.h when upstreamed
#include <86box/apm.h>
#include <86box/nvr.h>
@@ -58,7 +61,7 @@ intel_ich2_trap_set_acpi(intel_ich2_trap_t *dev, acpi_t *acpi)
}
static void
intel_ich2_trap_kick(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
intel_ich2_trap_kick(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
{
intel_ich2_trap_t *dev = (intel_ich2_trap_t *) priv;
intel_ich2_trap_log("Intel ICH2 Trap: Entered an I/O Trap. Provoking an SMI.\n");
@@ -87,7 +90,7 @@ intel_ich2_trap_close(void *priv)
}
static void *
intel_ich2_trap_init(const device_t *info)
intel_ich2_trap_init(UNUSED(const device_t *info))
{
intel_ich2_trap_t *dev = (intel_ich2_trap_t *) malloc(sizeof(intel_ich2_trap_t));
memset(dev, 0, sizeof(intel_ich2_trap_t));

9
src/device/smbus_piix4.c
View File

@@ -115,6 +115,9 @@ smbus_piix4_read(uint16_t addr, void *priv)
if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE)
dev->index = 0;
break;
default:
break;
}
smbus_piix4_log("SMBus PIIX4: read(%02X) = %02x\n", addr, ret);
@@ -377,6 +380,9 @@ unknown_protocol:
dev->index = 0;
}
break;
default:
break;
}
if (dev->next_stat) { /* schedule dispatch of any pending status register update */
@@ -439,6 +445,9 @@ smbus_piix4_init(const device_t *info)
case SMBUS_VIA:
i2c_smbus = dev->i2c = i2c_addbus("smbus_vt82c686b");
break;
default:
break;
}
timer_add(&dev->response_timer, smbus_piix4_response, dev, 0);

16
src/device/tco.c
View File

@@ -12,8 +12,10 @@
* not implemented
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
/* Note: There's a TCO Timer too but for now it's of no use thus not implemented */
@@ -34,6 +36,7 @@
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/tco.h>
#include <86box/plat.h> // Replace with plat_unused.h when upstreamed
#ifdef ENABLE_TCO_LOG
int tco_do_log = ENABLE_TCO_LOG;
@@ -54,10 +57,12 @@ tco_log(const char *fmt, ...)
#endif
void
tco_timer_handler(void *priv)
tco_timer_handler(UNUSED(void *priv))
{
/* TODO: Implement the TCO timer. */
// tco_t *dev = (tco_t *) priv;
#if 0
tco_t *dev = (tco_t *) priv;
#endif
}
void
@@ -128,6 +133,9 @@ tco_write(uint16_t addr, uint8_t val, tco_t *dev)
case 0x10:
dev->regs[addr] = val & 0x03;
break;
default:
break;
}
}
@@ -164,7 +172,7 @@ tco_close(void *priv)
}
static void *
tco_init(const device_t *info)
tco_init(UNUSED(const device_t *info))
{
tco_t *dev = (tco_t *) malloc(sizeof(tco_t));
memset(dev, 0, sizeof(tco_t));

3
src/include/86box/ddma.h
View File

@@ -24,7 +24,8 @@ extern "C" {
typedef struct
{
uint16_t io_base;
int channel, enable;
int channel;
int enable;
} ddma_channel_t;
typedef struct

4
src/include/86box/intel_ich2_gpio.h
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#ifndef EMU_INTEL_ICH2_GPIO_H

4
src/include/86box/intel_ich2_trap.h
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#ifndef EMU_INTEL_ICH2_TRAP_H

7
src/include/86box/nsc366.h
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#ifndef EMU_NSC_366_H
@@ -22,8 +24,7 @@
extern "C" {
#endif
typedef struct
{
typedef struct {
hwm_values_t *values;
uint8_t fscm_enable;

4
src/include/86box/snd_ac97_intel.h
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*
*/

4
src/include/86box/tco.h
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#ifndef EMU_TCO_H

1392
src/machine/m_at_socket370.c
View File

File diff suppressed because it is too large Load Diff

4
src/mem/815ep_spd_hack.c
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
/* This is a hack because the 86Box SPD calculation algorithm is not made for the 815EP banking.

3
src/mem/spd.c
View File

@@ -651,6 +651,9 @@ spd_write_drbs_intel_815ep(uint8_t *regs)
case 2:
regs[0x54] |= reg_apply;
break;
default:
break;
}
}
}

30
src/sio/sio_it8702.c
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*
*/
@@ -41,16 +43,18 @@
#include <86box/sio.h>
typedef struct
{
int ldn, unlock;
typedef struct {
int ldn;
int unlock;
uint8_t index, regs[15], sw_lock,
enable[11],
b_addr[4][11],
irq[11],
dma[11],
d_spec[15][11];
uint8_t index;
uint8_t regs[15];
uint8_t sw_lock;
uint8_t enable[11];
uint8_t b_addr[4][11];
uint8_t irq[11];
uint8_t dma[11];
uint8_t d_spec[15][11];
fdc_t *fdc;
serial_t *uart[2];
@@ -160,6 +164,9 @@ it8702_ldn(it8702_t *dev)
case 2 ... 3:
it8702_uart((dev->ldn == 3), dev);
break;
default:
break;
}
}
@@ -261,6 +268,9 @@ it8702_write(uint16_t addr, uint8_t val, void *priv)
it8702_ldn(dev);
break;
default:
break;
}
}
}

40
src/sio/sio_nsc366.c
View File

@@ -12,8 +12,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#include <stdarg.h>
@@ -39,21 +41,22 @@
#include <86box/port_92.h>
#include <86box/sio.h>
typedef struct
{
typedef struct {
fdc_t *fdc;
serial_t *uart[2];
nsc366_hwm_t *hwm;
uint8_t index, ldn, sio_config[14],
ld_activate[15],
io_base0[2][15],
io_base1[2][15],
int_num_irq[15],
irq[15],
dma_select0[15],
dma_select1[15],
dev_specific_config[3][15];
uint8_t index;
uint8_t ldn;
uint8_t sio_config[14];
uint8_t ld_activate[15];
uint8_t io_base0[2][15];
uint8_t io_base1[2][15];
uint8_t int_num_irq[15];
uint8_t irq[15];
uint8_t dma_select0[15];
uint8_t dma_select1[15];
uint8_t dev_specific_config[3][15];
int siofc_lock;
} nsc366_t;
@@ -113,8 +116,8 @@ static void
nsc366_uart(int uart, nsc366_t *dev)
{
serial_remove(dev->uart[uart]);
int base = ((dev->io_base0[0][2 + uart] & 7) << 8) | (dev->io_base0[1][2 + uart] & 0xf8);
int irq = (dev->int_num_irq[2 + uart] & 0x0f);
uint16_t base = ((dev->io_base0[0][2 + uart] & 7) << 8) | (dev->io_base0[1][2 + uart] & 0xf8);
uint8_t irq = (dev->int_num_irq[2 + uart] & 0x0f);
if (dev->ld_activate[2 + uart]) {
nsc366_log("NSC 366 UART Serial %d: Reconfigured with Base 0x%04x IRQ: %d\n", uart, base, irq);
@@ -196,6 +199,9 @@ nsc366_ldn_redirect(nsc366_t *dev)
case 14:
nsc366_tms(dev);
break;
default:
break;
}
}
@@ -263,6 +269,9 @@ nsc366_write(uint16_t addr, uint8_t val, void *priv)
case 0x0c ... 0x0d:
dev->sio_config[dev->index - 0x20] = val & 0xf3;
break;
default:
break;
}
break;
@@ -306,6 +315,9 @@ nsc366_write(uint16_t addr, uint8_t val, void *priv)
dev->dev_specific_config[dev->index - 0xf0][dev->ldn] = val;
nsc366_ldn_redirect(dev);
break;
default:
break;
}
else
dev->index = val;

65
src/sio/sio_w83627hf.c
View File

@@ -11,9 +11,11 @@
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2020-2022 Tiseno100.
* Copyright 2021-2022 Miran Grca.
* Copyright 2022-2023 Jasmine Iwanek.
*/
/*
@@ -92,6 +94,7 @@ Notes : ISAPnP is missing and the Hardware Monitor I2C is not implemented.
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/plat.h> // Replace with plat_unused.h when upstreamed
#include <86box/fdd.h>
#include <86box/fdc.h>
@@ -122,12 +125,14 @@ w83627hf_log(const char *fmt, ...)
# define w83627hf_log(fmt, ...)
#endif
typedef struct
{
uint8_t hwm_index, hwm_regs[256];
typedef struct {
uint8_t hwm_index;
uint8_t hwm_regs[256];
uint8_t index, cfg_unlocked,
regs[48], dev_regs[12][256];
uint8_t index;
uint8_t cfg_unlocked;
uint8_t regs[48];
uint8_t dev_regs[12][256];
int has_hwm;
fdc_t *fdc_controller;
@@ -238,8 +243,14 @@ w83627hf_hwm_write(uint16_t addr, uint8_t val, void *priv)
case 0x5c:
dev->hwm_regs[dev->hwm_index] = val & 0x77;
break;
default:
break;
}
break;
default:
break;
}
}
@@ -289,6 +300,9 @@ w83627hf_hwm_read(uint16_t addr, void *priv)
case 0x0b ... 0x1f:
return dev->hwm_regs[dev->hwm_index & 0x1f];
default:
break;
}
case 0x4f:
@@ -356,6 +370,9 @@ w83627hf_fdc_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
dev->dev_regs[0][cur_reg] = val & 0x5b;
fdc_update_drvrate(dev->fdc_controller, cur_reg & 1, (val & 0x18) >> 3);
break;
default:
break;
}
if (dev->dev_regs[0][0x30] & 1) {
@@ -388,6 +405,9 @@ w83627hf_lpt_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
case 0xf0:
dev->dev_regs[1][cur_reg] = val & 0x7f;
break;
default:
break;
}
if (dev->dev_regs[1][0x30] & 1) {
@@ -435,6 +455,9 @@ w83627hf_uart_write(int uart, uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
case 3:
uart_clock = 24000000.0;
break;
default:
break;
}
break;
@@ -442,6 +465,9 @@ w83627hf_uart_write(int uart, uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
if (uart)
dev->dev_regs[2 + uart][cur_reg] = val & 0x7f;
break;
default:
break;
}
if (dev->dev_regs[2 + uart][0x30] & 1) {
@@ -478,6 +504,9 @@ w83627hf_kbc_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
case 0xf0:
dev->dev_regs[5][cur_reg] = val & 0xc7;
break;
default:
break;
}
if (dev->dev_regs[5][0x30] & 1) {
@@ -503,6 +532,9 @@ w83627hf_cir_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
case 0x70:
dev->dev_regs[6][cur_reg] = val & 0x0f;
break;
default:
break;
}
}
@@ -525,6 +557,9 @@ w83627hf_gameport_midi_gpio1_write(uint16_t cur_reg, uint8_t val, w83627hf_t *de
case 0xf0 ... 0xf2:
dev->dev_regs[7][cur_reg] = val;
break;
default:
break;
}
}
@@ -547,6 +582,9 @@ w83627hf_watchdog_timer_gpio2_write(uint16_t cur_reg, uint8_t val, w83627hf_t *d
case 0xf6 ... 0xf7:
dev->dev_regs[8][cur_reg] = val;
break;
default:
break;
}
}
@@ -565,6 +603,9 @@ w83627hf_gpio3_vsb_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
case 0xf3:
dev->dev_regs[9][cur_reg] = val & 0xc0;
break;
default:
break;
}
}
@@ -620,6 +661,9 @@ w83627hf_acpi_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
case 0xf7:
dev->dev_regs[0x0a][cur_reg] = val & 0x3f;
break;
default:
break;
}
}
@@ -638,6 +682,9 @@ w83627hf_hwm_lpc_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
case 0xf0:
dev->dev_regs[0x0b][cur_reg] = val & 1;
break;
default:
break;
}
}
@@ -848,13 +895,19 @@ w83627hf_write(uint16_t addr, uint8_t val, void *priv)
break;
}
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
w83627hf_read(uint16_t addr, void *priv)
w83627hf_read(UNUSED(uint16_t addr), void *priv)
{
w83627hf_t *dev = (w83627hf_t *) priv;

3
src/sound/snd_ac97_codec.c
View File

@@ -445,6 +445,9 @@ rate: /* Writable only if VRA/VRM is set. */
case 0x7c: /* Vendor ID1 */
case 0x7e: /* Vendor ID2 */
return;
default:
break;
}
dev->regs[reg >> 1] = val;

10
src/sound/snd_ac97_intel.c
View File

@@ -11,8 +11,10 @@
*
*
* Authors: Tiseno100,
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2022 Tiseno100.
* Copyright 2022 Tiseno100.
* Copyright 2022-2023 Jasmine Iwanek.
*
*/
@@ -33,6 +35,7 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/plat.h> // Replace with plat_unused.h when upstreamed
#include <86box/snd_ac97.h>
#include <86box/snd_ac97_intel.h>
@@ -131,6 +134,9 @@ intel_ac97_write(uint16_t addr, uint8_t val, void *priv)
case 0x34: /* Codec Access Semaphore */
dev->regs[addr] = val & 1;
break;
default:
break;
}
}
@@ -178,7 +184,7 @@ intel_ac97_close(void *priv)
}
static void *
intel_ac97_init(const device_t *info)
intel_ac97_init(UNUSED(const device_t *info))
{
intel_ac97_t *dev = (intel_ac97_t *) malloc(sizeof(intel_ac97_t));
memset(dev, 0, sizeof(intel_ac97_t));