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Merge branch 'master' of https://github.com/86Box/86Box

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RichardG867
2020-12-18 15:57:10 -03:00
parent 134254630a 76d38b2665
commit d5e9ee763d
54 changed files with 736 additions and 522 deletions
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643
src/chipset/sis_85c50x.c
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@@ -6,405 +6,365 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 85c501/85c503 chip.
* Implementation of the SiS 85C50x Chipset.
*
*
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Authors: Tiseno100,
*
* Copyright 2019 Miran Grca.
* Copyright 2020 Tiseno100.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/apm.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct sis_85c501_t
#ifdef ENABLE_SIS_85C50X_LOG
int sis_85c50x_do_log = ENABLE_SIS_85C50X_LOG;
static void
sis_85c50x_log(const char *fmt, ...)
{
/* 85c501 */
uint8_t turbo_reg;
va_list ap;
/* 85c503 */
if (sis_85c50x_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define sis_85c50x_log(fmt, ...)
#endif
/* Registers */
uint8_t pci_conf[2][256];
/* 85c50x ISA */
uint8_t cur_reg,
regs[39];
typedef struct sis_85c50x_t
{
uint8_t index,
pci_conf[256], pci_conf_sb[256],
regs[256];
smram_t * smram;
port_92_t * port_92;
} sis_85c50x_t;
static void
sis_85c501_recalcmapping(sis_85c50x_t *dev)
sis_85c50x_shadow_recalc(sis_85c50x_t *dev)
{
int c, d;
uint32_t base;
uint32_t base, i, can_read, can_write;
for (c = 0; c < 1; c++) {
for (d = 0; d < 4; d++) {
base = 0xe0000 + (d << 14);
if (dev->pci_conf[0][0x54 + c] & (1 << (d + 4))) {
switch (dev->pci_conf[0][0x53] & 0x60) {
case 0x00:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x40:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x60:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
}
} else
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
can_read = (dev->pci_conf[0x53] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
can_write = (dev->pci_conf[0x53] & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
if (!can_read)
can_write = MEM_WRITE_EXTANY;
mem_set_mem_state_both(0xf0000, 0x10000, can_read | can_write);
shadowbios = 1;
shadowbios_write = 1;
for (i = 0; i < 4; i++) {
base = 0xe0000 + (i << 14);
mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x54] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
base = 0xd0000 + (i << 14);
mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x55] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
base = 0xc0000 + (i << 14);
mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x56] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
}
flushmmucache();
shadowbios = 1;
}
static void
sis_85c501_write(int func, int addr, uint8_t val, void *priv)
sis_85c50x_smm_recalc(sis_85c50x_t *dev)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
/* NOTE: Naming mismatch - what the datasheet calls "host address" is what we call ram_base. */
uint32_t ram_base = (dev->pci_conf[0x64] << 20) |
((dev->pci_conf[0x65] & 0x07) << 28);
if (func)
smram_disable(dev->smram);
if ((((dev->pci_conf[0x65] & 0xe0) >> 5) != 0x00) && (ram_base == 0x00000000))
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch ((dev->pci_conf[0x65] & 0xe0) >> 5) {
case 0x00:
if (!(dev->pci_conf[0x54] & 0xc0))
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x01:
smram_enable(dev->smram, 0xb0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x02:
smram_enable(dev->smram, 0xa0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x04:
smram_enable(dev->smram, 0xa0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x06:
smram_enable(dev->smram, 0xb0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
}
}
static void
sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
uint8_t valxor = (val ^ dev->pci_conf[addr]);
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x42;
val |= 0x04;
case 0x04: /* Command - low byte */
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xb4) | (val & 0x4b);
break;
case 0x05:
val &= 0x01;
case 0x07: /* Status - high byte */
dev->pci_conf[addr] = ((dev->pci_conf[addr] & 0xf9) & ~(val & 0xf8)) | (val & 0x06);
break;
case 0x50:
dev->pci_conf[addr] = val;
break;
case 0x51: /* Cache */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = (val & 0x40);
cpu_update_waitstates();
break;
case 0x52:
dev->pci_conf[addr] = val;
break;
case 0x53: /* Shadow RAM */
case 0x54:
case 0x55:
case 0x56:
dev->pci_conf[addr] = val;
sis_85c50x_shadow_recalc(dev);
if (addr == 0x54)
sis_85c50x_smm_recalc(dev);
break;
case 0x57: case 0x58: case 0x59: case 0x5a:
case 0x5c: case 0x5d: case 0x5e: case 0x61:
case 0x62: case 0x63: case 0x67: case 0x68:
case 0x6a: case 0x6b: case 0x6c: case 0x6d:
case 0x6e: case 0x6f:
dev->pci_conf[addr] = val;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x5b:
dev->pci_conf[addr] = val;
if (valxor & 0xc0)
port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80));
break;
case 0x60: /* SMI */
if ((dev->pci_conf[0x68] & 0x01) && !(dev->pci_conf[addr] & 0x02) && (val & 0x02)) {
dev->pci_conf[0x69] |= 0x01;
smi_line = 1;
}
dev->pci_conf[addr] = val & 0x3e;
break;
case 0x64: /* SMRAM */
case 0x65:
dev->pci_conf[addr] = val;
sis_85c50x_smm_recalc(dev);
break;
case 0x66:
dev->pci_conf[addr] = (val & 0x7f);
break;
case 0x69:
dev->pci_conf[addr] &= ~(val);
break;
}
sis_85c50x_log("85C501: dev->pci_conf[%02x] = %02x\n", addr, val);
}
static uint8_t
sis_85c50x_read(int func, int addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
sis_85c50x_log("85C501: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]);
return dev->pci_conf[addr];
}
static void
sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
switch (addr) {
case 0x04: /* Command */
dev->pci_conf_sb[addr] = val & 0x0f;
break;
case 0x07: /* Status */
dev->pci_conf_sb[addr] &= ~(val & 0x30);
break;
case 0x40: /* BIOS Control Register */
dev->pci_conf_sb[addr] = val & 0x3f;
break;
case 0x41: case 0x42: case 0x43: case 0x44:
/* INTA/B/C/D# Remapping Control Register */
dev->pci_conf_sb[addr] = val & 0x8f;
if (val & 0x80)
pci_set_irq_routing(PCI_INTA + (addr - 0x41), PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA + (addr - 0x41), val & 0xf);
break;
case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */
case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */
case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */
case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
dev->pci_conf_sb[addr] = val;
break;
}
sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] = %02x\n", addr, val);
}
static uint8_t
sis_85c50x_sb_read(int func, int addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] (%02x)\n", addr, dev->pci_conf_sb[addr]);
return dev->pci_conf_sb[addr];
}
static void
sis_85c50x_isa_write(uint16_t addr, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x54: /*Shadow configure*/
if ((dev->pci_conf[0][0x54] & val) ^ 0xf0) {
dev->pci_conf[0][0x54] = val;
sis_85c501_recalcmapping(dev);
case 0x23:
switch (dev->index) {
case 0x80:
dev->regs[dev->index] = val & 0xe7;
break;
case 0x81:
dev->regs[dev->index] = val & 0xf4;
break;
case 0x84: case 0x88: case 0x9: case 0x8a:
case 0x8b:
dev->regs[dev->index] = val;
break;
case 0x85:
outb(0x70, val);
break;
}
break;
}
dev->pci_conf[0][addr] = val;
sis_85c50x_log("85C501-ISA: dev->regs[%02x] = %02x\n", addr, val);
}
static void
sis_85c503_write(int func, int addr, uint8_t val, void *priv)
static uint8_t
sis_85c50x_isa_read(uint16_t addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
uint8_t ret = 0xff;
if (func > 0)
return;
if (addr >= 0x0f && addr < 0x41)
return;
switch(addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x08;
val |= 0x07;
break;
case 0x05:
val = 0;
switch (addr) {
case 0x22:
ret = dev->index;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x41:
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
case 0x23:
if (dev->index == 0x85)
ret = inb(0x70);
else
pci_set_irq_routing(PCI_INTA, val & 0xf);
break;
case 0x42:
if (val & 0x80)
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTC, val & 0xf);
break;
case 0x43:
if (val & 0x80)
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTB, val & 0xf);
break;
case 0x44:
if (val & 0x80)
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTD, val & 0xf);
ret = dev->regs[dev->index];
break;
}
sis_85c50x_log("85C501-ISA: dev->regs[%02x] (%02x)\n", dev->index, ret);
dev->pci_conf[1][addr] = val;
}
static void
sis_85c50x_isa_write(uint16_t port, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
if (port & 1) {
if (dev->cur_reg <= 0x1a)
dev->regs[dev->cur_reg] = val;
} else
dev->cur_reg = val;
}
static uint8_t
sis_85c501_read(int func, int addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
if (func)
return 0xff;
return dev->pci_conf[0][addr];
}
static uint8_t
sis_85c503_read(int func, int addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
if (func > 0)
return 0xff;
return dev->pci_conf[1][addr];
}
static uint8_t
sis_85c50x_isa_read(uint16_t port, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
if (port & 1) {
if (dev->cur_reg <= 0x1a)
return dev->regs[dev->cur_reg];
else
return 0xff;
} else
return dev->cur_reg;
}
static void
sis_85c50x_isa_reset(sis_85c50x_t *dev)
{
int mem_size_mb, i = 0;
memset(dev->regs, 0, sizeof(dev->regs));
dev->cur_reg = 0;
for (i = 0; i < 0x27; i++)
dev->regs[i] = 0x00;
dev->regs[9] = 0x40;
mem_size_mb = mem_size >> 10;
switch (mem_size_mb) {
case 0: case 1:
dev->regs[9] |= 0;
break;
case 2: case 3:
dev->regs[9] |= 1;
break;
case 4:
dev->regs[9] |= 2;
break;
case 5:
dev->regs[9] |= 0x20;
break;
case 6: case 7:
dev->regs[9] |= 9;
break;
case 8: case 9:
dev->regs[9] |= 4;
break;
case 10: case 11:
dev->regs[9] |= 5;
break;
case 12: case 13: case 14: case 15:
dev->regs[9] |= 0xB;
break;
case 16:
dev->regs[9] |= 0x13;
break;
case 17:
dev->regs[9] |= 0x21;
break;
case 18: case 19:
dev->regs[9] |= 6;
break;
case 20: case 21: case 22: case 23:
dev->regs[9] |= 0xD;
break;
case 24: case 25: case 26: case 27:
case 28: case 29: case 30: case 31:
dev->regs[9] |= 0xE;
break;
case 32: case 33: case 34: case 35:
dev->regs[9] |= 0x1B;
break;
case 36: case 37: case 38: case 39:
dev->regs[9] |= 0xF;
break;
case 40: case 41: case 42: case 43:
case 44: case 45: case 46: case 47:
dev->regs[9] |= 0x17;
break;
case 48:
dev->regs[9] |= 0x1E;
break;
default:
if (mem_size_mb < 64)
dev->regs[9] |= 0x1E;
else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[9] |= 0x22;
else
dev->regs[9] |= 0x24;
break;
}
dev->regs[0x11] = 9;
dev->regs[0x12] = 0xFF;
dev->regs[0x23] = 0xF0;
dev->regs[0x26] = 1;
io_removehandler(0x22, 0x0002,
sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
io_sethandler(0x22, 0x0002,
sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
return ret;
}
static void
sis_85c50x_reset(void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
uint8_t val = 0;
/* North Bridge (SiS 85C501/502) */
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x06;
dev->pci_conf[0x03] = 0x04;
dev->pci_conf[0x04] = 0x04;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
val = sis_85c501_read(0, 0x54, priv); /* Read current value of 0x44. */
sis_85c501_write(0, 0x54, val & 0xf, priv); /* Turn off shadow BIOS but keep the lower 4 bits. */
sis_85c50x_write(0, 0x51, 0x00, dev);
sis_85c50x_write(0, 0x53, 0x00, dev);
sis_85c50x_write(0, 0x54, 0x00, dev);
sis_85c50x_write(0, 0x55, 0x00, dev);
sis_85c50x_write(0, 0x56, 0x00, dev);
sis_85c50x_write(0, 0x5b, 0x00, dev);
sis_85c50x_write(0, 0x60, 0x00, dev);
sis_85c50x_write(0, 0x64, 0x00, dev);
sis_85c50x_write(0, 0x65, 0x00, dev);
sis_85c50x_write(0, 0x68, 0x00, dev);
sis_85c50x_write(0, 0x69, 0xff, dev);
sis_85c50x_isa_reset(dev);
}
static void
sis_85c50x_setup(sis_85c50x_t *dev)
{
memset(dev, 0, sizeof(sis_85c50x_t));
/* 85c501 */
dev->pci_conf[0][0x00] = 0x39; /*SiS*/
dev->pci_conf[0][0x01] = 0x10;
dev->pci_conf[0][0x02] = 0x06; /*501/502*/
dev->pci_conf[0][0x03] = 0x04;
dev->pci_conf[0][0x04] = 7;
dev->pci_conf[0][0x05] = 0;
dev->pci_conf[0][0x06] = 0x80;
dev->pci_conf[0][0x07] = 0x02;
dev->pci_conf[0][0x08] = 0; /*Device revision*/
dev->pci_conf[0][0x09] = 0x00; /*Device class (PCI bridge)*/
dev->pci_conf[0][0x0a] = 0x00;
dev->pci_conf[0][0x0b] = 0x06;
dev->pci_conf[0][0x0e] = 0x00; /*Single function device*/
dev->pci_conf[0][0x50] = 0xbc;
dev->pci_conf[0][0x51] = 0xfb;
dev->pci_conf[0][0x52] = 0xad;
dev->pci_conf[0][0x53] = 0xfe;
shadowbios = 1;
/* 85c503 */
dev->pci_conf[1][0x00] = 0x39; /*SiS*/
dev->pci_conf[1][0x01] = 0x10;
dev->pci_conf[1][0x02] = 0x08; /*503*/
dev->pci_conf[1][0x03] = 0x00;
dev->pci_conf[1][0x04] = 7;
dev->pci_conf[1][0x05] = 0;
dev->pci_conf[1][0x06] = 0x80;
dev->pci_conf[1][0x07] = 0x02;
dev->pci_conf[1][0x08] = 0; /*Device revision*/
dev->pci_conf[1][0x09] = 0x00; /*Device class (PCI bridge)*/
dev->pci_conf[1][0x0a] = 0x01;
dev->pci_conf[1][0x0b] = 0x06;
dev->pci_conf[1][0x0e] = 0x00; /*Single function device*/
dev->pci_conf[1][0x41] = dev->pci_conf[1][0x42] =
dev->pci_conf[1][0x43] = dev->pci_conf[1][0x44] = 0x80;
/* South Bridge (SiS 85C503) */
dev->pci_conf_sb[0x00] = 0x39;
dev->pci_conf_sb[0x01] = 0x10;
dev->pci_conf_sb[0x02] = 0x08;
dev->pci_conf_sb[0x03] = 0x00;
dev->pci_conf_sb[0x04] = 0x07;
dev->pci_conf_sb[0x05] = 0x00;
dev->pci_conf_sb[0x06] = 0x00;
dev->pci_conf_sb[0x07] = 0x02;
dev->pci_conf_sb[0x08] = 0x00;
dev->pci_conf_sb[0x09] = 0x00;
dev->pci_conf_sb[0x0a] = 0x01;
dev->pci_conf_sb[0x0b] = 0x06;
sis_85c50x_write(0, 0x41, 0x80, dev);
sis_85c50x_write(0, 0x42, 0x80, dev);
sis_85c50x_write(0, 0x43, 0x80, dev);
sis_85c50x_write(0, 0x44, 0x80, dev);
}
static void
sis_85c50x_close(void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
smram_del(dev->smram);
free(dev);
}
@@ -412,30 +372,31 @@ sis_85c50x_close(void *priv)
static void *
sis_85c50x_init(const device_t *info)
{
sis_85c50x_t *dev = (sis_85c50x_t *) malloc(sizeof(sis_85c50x_t));
sis_85c50x_t *dev = (sis_85c50x_t *)malloc(sizeof(sis_85c50x_t));
memset(dev, 0x00, sizeof(sis_85c50x_t));
pci_add_card(0, sis_85c501_read, sis_85c501_write, dev);
pci_add_card(5, sis_85c503_read, sis_85c503_write, dev);
/* 501/502 (Northbridge) */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c50x_read, sis_85c50x_write, dev);
sis_85c50x_setup(dev);
sis_85c50x_isa_reset(dev);
/* 503 (Southbridge) */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_85c50x_sb_read, sis_85c50x_sb_write, dev);
io_sethandler(0x0022, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
device_add(&port_92_pci_device);
dev->smram = smram_add();
dev->port_92 = device_add(&port_92_device);
sis_85c50x_reset(dev);
return dev;
}
const device_t sis_85c50x_device =
{
"SiS 85c501/85c503",
const device_t sis_85c50x_device = {
"SiS 85C50x",
DEVICE_PCI,
0,
sis_85c50x_init,
sis_85c50x_close,
sis_85c50x_reset,
{ NULL },
NULL,
NULL,
sis_85c50x_init, sis_85c50x_close,
sis_85c50x_reset, { NULL },
NULL, NULL,
NULL
};

4
src/codegen/codegen_ops.c
View File

@@ -15,9 +15,9 @@
#include "codegen.h"
#include "codegen_ops.h"
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include "codegen_ops_x86-64.h"
#elif defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64
#elif defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
#include "codegen_ops_x86.h"
#endif

24
src/codegen/codegen_ops_x86-64.h
View File

@@ -57,7 +57,7 @@ static inline void call_long(uintptr_t func)
static inline void load_param_1_32(codeblock_t *block, uint32_t param)
{
#if WIN64
#if _WIN64
addbyte(0xb9); /*MOVL $fetchdat,%ecx*/
#else
addbyte(0xbf); /*MOVL $fetchdat,%edi*/
@@ -66,7 +66,7 @@ static inline void load_param_1_32(codeblock_t *block, uint32_t param)
}
static inline void load_param_1_reg_32(int reg)
{
#if WIN64
#if _WIN64
if (reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOV ECX, EAX*/
@@ -82,7 +82,7 @@ static inline void load_param_1_reg_32(int reg)
static inline void load_param_1_64(codeblock_t *block, uint64_t param)
{
addbyte(0x48);
#if WIN64
#if _WIN64
addbyte(0xb9); /*MOVL $fetchdat,%ecx*/
#else
addbyte(0xbf); /*MOVL $fetchdat,%edi*/
@@ -93,7 +93,7 @@ static inline void load_param_1_64(codeblock_t *block, uint64_t param)
static inline void load_param_2_32(codeblock_t *block, uint32_t param)
{
#if WIN64
#if _WIN64
addbyte(0xba); /*MOVL $fetchdat,%edx*/
#else
addbyte(0xbe); /*MOVL $fetchdat,%esi*/
@@ -102,7 +102,7 @@ static inline void load_param_2_32(codeblock_t *block, uint32_t param)
}
static inline void load_param_2_reg_32(int reg)
{
#if WIN64
#if _WIN64
if (reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOV EDX, EAX*/
@@ -117,7 +117,7 @@ static inline void load_param_2_reg_32(int reg)
static inline void load_param_2_64(codeblock_t *block, uint64_t param)
{
addbyte(0x48);
#if WIN64
#if _WIN64
addbyte(0xba); /*MOVL $fetchdat,%edx*/
#else
addbyte(0xbe); /*MOVL $fetchdat,%esi*/
@@ -128,7 +128,7 @@ static inline void load_param_2_reg_64(int reg)
{
if (reg & 8)
{
#if WIN64
#if _WIN64
addbyte(0x4c); /*MOVL EDX,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | ((reg & 7) << 3));
@@ -140,7 +140,7 @@ static inline void load_param_2_reg_64(int reg)
}
else
{
#if WIN64
#if _WIN64
addbyte(0x48); /*MOVL EDX,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | ((reg & 7) << 3));
@@ -156,7 +156,7 @@ static inline void load_param_3_reg_32(int reg)
{
if (reg & 8)
{
#if WIN64
#if _WIN64
addbyte(0x45); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
@@ -168,7 +168,7 @@ static inline void load_param_3_reg_32(int reg)
}
else
{
#if WIN64
#if _WIN64
addbyte(0x41); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
@@ -183,7 +183,7 @@ static inline void load_param_3_reg_64(int reg)
{
if (reg & 8)
{
#if WIN64
#if _WIN64
addbyte(0x4d); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
@@ -195,7 +195,7 @@ static inline void load_param_3_reg_64(int reg)
}
else
{
#if WIN64
#if _WIN64
addbyte(0x49); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));

8
src/codegen/codegen_x86-64.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdarg.h>
#include <stdio.h>
@@ -24,7 +24,7 @@
#include <sys/mman.h>
#include <unistd.h>
#endif
#if WIN64
#if _WIN64
#include <windows.h>
#endif
@@ -70,7 +70,7 @@ void codegen_init()
long pagemask = ~(pagesize - 1);
#endif
#if WIN64
#if _WIN64
codeblock = VirtualAlloc(NULL, BLOCK_SIZE * sizeof(codeblock_t), MEM_COMMIT, PAGE_EXECUTE_READWRITE);
#else
codeblock = malloc(BLOCK_SIZE * sizeof(codeblock_t));
@@ -295,7 +295,7 @@ void codegen_block_start_recompile(codeblock_t *block)
block_pos = BLOCK_GPF_OFFSET;
#ifdef OLD_GPF
#if WIN64
#if _WIN64
addbyte(0x48); /*XOR RCX, RCX*/
addbyte(0x31);
addbyte(0xc9);

2
src/codegen/codegen_x86.c
View File

@@ -36,7 +36,7 @@
* Boston, MA 02111-1307
* USA.
*/
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
#include <stdio.h>
#include <stdint.h>

6
src/codegen_new/codegen_allocator.c
View File

@@ -112,10 +112,14 @@ uint8_t *codeblock_allocator_get_ptr(mem_block_t *block)
void codegen_allocator_clean_blocks(struct mem_block_t *block)
{
#if defined __ARM_EABI__ || defined _ARM_ || defined __aarch64__
#if defined __ARM_EABI__ || defined _ARM_ || defined __aarch64__ || defined _M_ARM || defined _M_ARM64
while (1)
{
#ifndef _MSC_VER
__clear_cache(&mem_block_alloc[block->offset], &mem_block_alloc[block->offset + MEM_BLOCK_SIZE]);
#else
FlushInstructionCache(GetCurrentProcess(), &mem_block_alloc[block->offset], MEM_BLOCK_SIZE);
#endif
if (block->next)
block = &mem_blocks[block->next - 1];
else

2
src/codegen_new/codegen_allocator.h
View File

@@ -13,7 +13,7 @@
Due to the chaining, the total memory size is limited by the range of a jump
instruction. ARMv7 is restricted to +/- 32 MB, ARMv8 to +/- 128 MB, x86 to
+/- 2GB. As a result, total memory size is limited to 32 MB on ARMv7*/
#if defined __ARM_EABI__ || _ARM_
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#define MEM_BLOCK_NR 32768
#else
#define MEM_BLOCK_NR 131072

6
src/codegen_new/codegen_backend.h
View File

@@ -1,13 +1,13 @@
#ifndef _CODEGEN_BACKEND_H_
#define _CODEGEN_BACKEND_H_
#if defined __amd64__
#if defined __amd64__ || defined _M_X64
#include "codegen_backend_x86-64.h"
#elif defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
#include "codegen_backend_x86.h"
#elif defined __ARM_EABI__ || defined _ARM_
#elif defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#include "codegen_backend_arm.h"
#elif defined __aarch64__
#elif defined __aarch64__ || defined _M_ARM64
#include "codegen_backend_arm64.h"
#else
#error Dynamic recompiler not implemented on your platform

6
src/codegen_new/codegen_backend_arm.c
View File

@@ -1,4 +1,4 @@
#if defined __ARM_EABI__ || defined _ARM_
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#include <stdint.h>
#include <stdlib.h>
@@ -327,9 +327,13 @@ printf("block_pos=%i\n", block_pos);
block_write_data = NULL;
//fatal("block_pos=%i\n", block_pos);
#if !defined _MSC_VER || defined __clang__
asm("vmrs %0, fpscr\n"
: "=r" (cpu_state.old_fp_control)
);
#else
cpu_state.old_fp_control = _controlfp();
#endif
if ((cpu_state.old_fp_control >> 22) & 3)
fatal("VFP not in nearest rounding mode\n");
}

6
src/codegen_new/codegen_backend_arm64.c
View File

@@ -1,4 +1,4 @@
#ifdef __aarch64__
#if defined __aarch64__ || defined _M_ARM64
#include <stdlib.h>
#include <stdint.h>
@@ -332,9 +332,13 @@ void codegen_backend_init()
codegen_allocator_clean_blocks(block->head_mem_block);
#if !defined _MSC_VER || defined __clang__
asm("mrs %0, fpcr\n"
: "=r" (cpu_state.old_fp_control)
);
#else
cpu_state.old_fp_control = _controlfp();
#endif
}
void codegen_set_rounding_mode(int mode)

2
src/codegen_new/codegen_backend_arm64_ops.c
View File

@@ -1,4 +1,4 @@
#ifdef __aarch64__
#if defined __aarch64__ || defined _M_ARM64
#include <stdint.h>
#include <86box/86box.h>

2
src/codegen_new/codegen_backend_arm64_uops.c
View File

@@ -1,4 +1,4 @@
#ifdef __aarch64__
#if defined __aarch64__ || defined _M_ARM64
#include <stdint.h>
#include <86box/86box.h>

2
src/codegen_new/codegen_backend_arm_ops.c
View File

@@ -1,4 +1,4 @@
#if defined __ARM_EABI__ || defined _ARM_
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#include <stdint.h>
#include <86box/86box.h>

2
src/codegen_new/codegen_backend_arm_uops.c
View File

@@ -1,4 +1,4 @@
#if defined __ARM_EABI__ || defined _ARM_
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#include <math.h>
#include <stdint.h>

22
src/codegen_new/codegen_backend_x86-64.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdint.h>
#include <86box/86box.h>
@@ -22,6 +22,8 @@
#include <windows.h>
#endif
#include <xmmintrin.h>
void *codegen_mem_load_byte;
void *codegen_mem_load_word;
void *codegen_mem_load_long;
@@ -51,7 +53,7 @@ host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] =
host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
{
#if WIN64
#if _WIN64
/*Windows x86-64 calling convention preserves XMM6-XMM15*/
{REG_XMM6, 0},
{REG_XMM7, 0},
@@ -123,7 +125,7 @@ static void build_load_routine(codeblock_t *block, int size, int is_float)
*misaligned_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)misaligned_offset) - 1;
host_x86_PUSH(block, REG_RAX);
host_x86_PUSH(block, REG_RDX);
#if WIN64
#if _WIN64
host_x86_SUB64_REG_IMM(block, REG_RSP, 0x20);
//host_x86_MOV32_REG_REG(block, REG_ECX, uop->imm_data);
#else
@@ -155,7 +157,7 @@ static void build_load_routine(codeblock_t *block, int size, int is_float)
host_x86_CALL(block, (void *)readmemql);
host_x86_MOVQ_XREG_REG(block, REG_XMM_TEMP, REG_RAX);
}
#if WIN64
#if _WIN64
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x20);
#endif
host_x86_POP(block, REG_RDX);
@@ -221,7 +223,7 @@ static void build_store_routine(codeblock_t *block, int size, int is_float)
*misaligned_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)misaligned_offset) - 1;
host_x86_PUSH(block, REG_RAX);
host_x86_PUSH(block, REG_RDX);
#if WIN64
#if _WIN64
host_x86_SUB64_REG_IMM(block, REG_RSP, 0x28);
if (size == 4 && is_float)
host_x86_MOVD_REG_XREG(block, REG_EDX, REG_XMM_TEMP); //data
@@ -248,7 +250,7 @@ static void build_store_routine(codeblock_t *block, int size, int is_float)
host_x86_CALL(block, (void *)writememll);
else if (size == 8)
host_x86_CALL(block, (void *)writememql);
#if WIN64
#if _WIN64
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x28);
#else
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x8);
@@ -317,7 +319,7 @@ void codegen_backend_init()
build_loadstore_routines(&codeblock[block_current]);
codegen_gpf_rout = &codeblock[block_current].data[block_pos];
#if WIN64
#if _WIN64
host_x86_XOR32_REG_REG(block, REG_ECX, REG_ECX);
host_x86_XOR32_REG_REG(block, REG_EDX, REG_EDX);
#else
@@ -340,11 +342,7 @@ void codegen_backend_init()
block_write_data = NULL;
asm(
"stmxcsr %0\n"
: "=m" (cpu_state.old_fp_control)
);
cpu_state.trunc_fp_control = cpu_state.old_fp_control | 0x6000;
cpu_state.trunc_fp_control = _mm_getcsr() | 0x6000;
}
void codegen_set_rounding_mode(int mode)

2
src/codegen_new/codegen_backend_x86-64_ops.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdint.h>
#include <86box/86box.h>

2
src/codegen_new/codegen_backend_x86-64_ops_sse.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdint.h>
#include <86box/86box.h>

14
src/codegen_new/codegen_backend_x86-64_uops.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdint.h>
#include <86box/86box.h>
@@ -803,7 +803,7 @@ static int codegen_FP_ENTER(codeblock_t *block, uop_t *uop)
host_x86_TEST32_REG_IMM(block, REG_ECX, 0xc);
branch_offset = host_x86_JZ_long(block);
host_x86_MOV32_ABS_IMM(block, &cpu_state.oldpc, uop->imm_data);
#if WIN64
#if _WIN64
host_x86_MOV32_REG_IMM(block, REG_ECX, 7);
#else
host_x86_MOV32_REG_IMM(block, REG_EDI, 7);
@@ -822,7 +822,7 @@ static int codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
host_x86_TEST32_REG_IMM(block, REG_ECX, 0xc);
branch_offset = host_x86_JZ_long(block);
host_x86_MOV32_ABS_IMM(block, &cpu_state.oldpc, uop->imm_data);
#if WIN64
#if _WIN64
host_x86_MOV32_REG_IMM(block, REG_ECX, 7);
#else
host_x86_MOV32_REG_IMM(block, REG_EDI, 7);
@@ -852,7 +852,7 @@ static int codegen_LOAD_FUNC_ARG0(codeblock_t *block, uop_t *uop)
if (REG_IS_W(src_size))
{
#if WIN64
#if _WIN64
host_x86_MOVZX_REG_32_16(block, REG_ECX, src_reg);
#else
host_x86_MOVZX_REG_32_16(block, REG_EDI, src_reg);
@@ -888,7 +888,7 @@ static int codegen_LOAD_FUNC_ARG3(codeblock_t *block, uop_t *uop)
static int codegen_LOAD_FUNC_ARG0_IMM(codeblock_t *block, uop_t *uop)
{
#if WIN64
#if _WIN64
host_x86_MOV32_REG_IMM(block, REG_ECX, uop->imm_data);
#else
host_x86_MOV32_REG_IMM(block, REG_EDI, uop->imm_data);
@@ -897,7 +897,7 @@ static int codegen_LOAD_FUNC_ARG0_IMM(codeblock_t *block, uop_t *uop)
}
static int codegen_LOAD_FUNC_ARG1_IMM(codeblock_t *block, uop_t *uop)
{
#if WIN64
#if _WIN64
host_x86_MOV32_REG_IMM(block, REG_EDX, uop->imm_data);
#else
host_x86_MOV32_REG_IMM(block, REG_ESI, uop->imm_data);
@@ -928,7 +928,7 @@ static int codegen_LOAD_SEG(codeblock_t *block, uop_t *uop)
if (!REG_IS_W(src_size))
fatal("LOAD_SEG %02x %p\n", uop->src_reg_a_real, uop->p);
#endif
#if WIN64
#if _WIN64
host_x86_MOV16_REG_REG(block, REG_CX, src_reg);
host_x86_MOV64_REG_IMM(block, REG_EDX, (uint64_t)uop->p);
#else

6
src/cpu/386_common.c
View File

@@ -1023,12 +1023,6 @@ enter_smm(int in_hlt)
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cx6x86)
return;
if (cpu_iscyrix) {
if (!cyrix.smhr & SMHR_VALID)
cyrix.smhr = (cyrix.arr[3].base + cyrix.arr[3].size) | SMHR_VALID;
smram_state = cyrix.smhr & SMHR_ADDR_MASK;
}
x386_common_log("enter_smm(): smbase = %08X\n", smbase);
x386_common_log("CS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
cpu_state.seg_cs.seg, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low,

16
src/cpu/cpu.c
View File

@@ -375,40 +375,40 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
if (cpu_s->cpu_flags & CPU_FIXED_MULTIPLIER) {
return 1; /* don't care about multiplier compatibility on fixed multiplier CPUs */
} else if (cpu_family->package & CPU_PKG_SOCKET5_7) {
if ((multi == 1.5) && (cpu_s->cpu_type & CPU_5K86) && (machine_s->cpu_min_multi > 1.5)) /* K5 5k86 */
if ((multi == 1.5) && (cpu_s->cpu_type == CPU_5K86) && (machine_s->cpu_min_multi > 1.5)) /* K5 5k86 */
multi = 2.0;
else if (multi == 1.75) /* K5 5k86 */
multi = 2.5;
else if (multi == 2.0) {
if (cpu_s->cpu_type & CPU_5K86) /* K5 5k86 */
if (cpu_s->cpu_type == CPU_5K86) /* K5 5k86 */
multi = 3.0;
else if (cpu_s->cpu_type & (CPU_K6_2P | CPU_K6_3P)) /* K6-2+ / K6-3+ */
else if (cpu_s->cpu_type == CPU_K6_2P || cpu_s->cpu_type == CPU_K6_3P) /* K6-2+ / K6-3+ */
multi = 2.5;
else if ((cpu_s->cpu_type & (CPU_WINCHIP | CPU_WINCHIP2)) && (machine_s->cpu_min_multi > 2.0)) /* WinChip (2) */
else if ((cpu_s->cpu_type == CPU_WINCHIP || cpu_s->cpu_type == CPU_WINCHIP2) && (machine_s->cpu_min_multi > 2.0)) /* WinChip (2) */
multi = 2.5;
}
else if (multi == (7.0 / 3.0)) /* WinChip 2A - 2.33x */
multi = 5.0;
else if (multi == (8.0 / 3.0)) /* WinChip 2A - 2.66x */
multi = 5.5;
else if ((multi == 3.0) && (cpu_s->cpu_type & (CPU_Cx6x86 | CPU_Cx6x86L))) /* 6x86(L) */
else if ((multi == 3.0) && (cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86L)) /* 6x86(L) */
multi = 1.5;
else if (multi == (10.0 / 3.0)) /* WinChip 2A - 3.33x */
multi = 2.0;
else if ((multi == 3.5) && (machine_s->cpu_min_multi < 3.5)) /* standard set by the Pentium MMX */
multi = 1.5;
else if (multi == 4.0) {
if (cpu_s->cpu_type & (CPU_WINCHIP | CPU_WINCHIP2)) { /* WinChip (2) */
if (cpu_s->cpu_type == CPU_WINCHIP || cpu_s->cpu_type == CPU_WINCHIP2) { /* WinChip (2) */
if (machine_s->cpu_min_multi >= 1.5)
multi = 1.5;
else if (machine_s->cpu_min_multi >= 3.5)
multi = 3.5;
else if (machine_s->cpu_min_multi >= 4.5)
multi = 4.5;
} else if (cpu_s->cpu_type & (CPU_Cx6x86 | CPU_Cx6x86L)) /* 6x86(L) */
} else if (cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86L) /* 6x86(L) */
multi = 3.0;
}
else if ((multi == 5.0) && (cpu_s->cpu_type & (CPU_WINCHIP | CPU_WINCHIP2)) && (machine_s->cpu_min_multi > 5.0)) /* WinChip (2) */
else if ((multi == 5.0) && (cpu_s->cpu_type == CPU_WINCHIP || cpu_s->cpu_type == CPU_WINCHIP2) && (machine_s->cpu_min_multi > 5.0)) /* WinChip (2) */
multi = 5.5;
else if ((multi == 6.0) && (machine_s->cpu_max_multi < 6.0)) /* K6-2(+) / K6-3(+) */
multi = 2.0;

100
src/cpu/cpu.h
View File

@@ -32,58 +32,58 @@ enum {
};
enum {
CPU_8088 = (1ULL << 0), /* 808x class CPUs */
CPU_8086 = (1ULL << 1),
CPU_8088, /* 808x class CPUs */
CPU_8086,
#ifdef USE_NEC_808X
CPU_V20 = (1ULL << 2), /* NEC 808x class CPUs - future proofing */
CPU_V30 = (1ULL << 3),
CPU_V20, /* NEC 808x class CPUs - future proofing */
CPU_V30,
#endif
CPU_286 = (1ULL << 4), /* 286 class CPUs */
CPU_386SX = (1ULL << 5), /* 386 class CPUs */
CPU_386DX = (1ULL << 6),
CPU_IBM386SLC = (1ULL << 7),
CPU_IBM486SLC = (1ULL << 8),
CPU_IBM486BL = (1ULL << 9),
CPU_RAPIDCAD = (1ULL << 10),
CPU_486SLC = (1ULL << 11),
CPU_486DLC = (1ULL << 12),
CPU_i486SX = (1ULL << 13), /* 486 class CPUs */
CPU_Am486SX = (1ULL << 14),
CPU_Cx486S = (1ULL << 15),
CPU_i486SX2 = (1ULL << 16),
CPU_Am486SX2 = (1ULL << 17),
CPU_i486DX = (1ULL << 18),
CPU_i486DX2 = (1ULL << 19),
CPU_Am486DX = (1ULL << 20),
CPU_Am486DX2 = (1ULL << 21),
CPU_Cx486DX = (1ULL << 22),
CPU_Cx486DX2 = (1ULL << 23),
CPU_iDX4 = (1ULL << 24),
CPU_Am486DX4 = (1ULL << 25),
CPU_Cx486DX4 = (1ULL << 26),
CPU_Am5x86 = (1ULL << 27),
CPU_Cx5x86 = (1ULL << 28),
CPU_P24T = (1ULL << 29),
CPU_WINCHIP = (1ULL << 30), /* 586 class CPUs */
CPU_WINCHIP2 = (1ULL << 31),
CPU_PENTIUM = (1ULL << 32),
CPU_PENTIUMMMX = (1ULL << 33),
CPU_Cx6x86 = (1ULL << 34),
CPU_Cx6x86MX = (1ULL << 35),
CPU_Cx6x86L = (1ULL << 36),
CPU_CxGX1 = (1ULL << 37),
CPU_K5 = (1ULL << 38),
CPU_5K86 = (1ULL << 39),
CPU_K6 = (1ULL << 40),
CPU_K6_2 = (1ULL << 41),
CPU_K6_2C = (1ULL << 42),
CPU_K6_3 = (1ULL << 43),
CPU_K6_2P = (1ULL << 44),
CPU_K6_3P = (1ULL << 45),
CPU_CYRIX3S = (1ULL << 46),
CPU_PENTIUMPRO = (1ULL << 47), /* 686 class CPUs */
CPU_PENTIUM2 = (1ULL << 48),
CPU_PENTIUM2D = (1ULL << 49)
CPU_286, /* 286 class CPUs */
CPU_386SX, /* 386 class CPUs */
CPU_386DX,
CPU_IBM386SLC,
CPU_IBM486SLC,
CPU_IBM486BL,
CPU_RAPIDCAD,
CPU_486SLC,
CPU_486DLC,
CPU_i486SX, /* 486 class CPUs */
CPU_Am486SX,
CPU_Cx486S,
CPU_i486SX2,
CPU_Am486SX2,
CPU_i486DX,
CPU_i486DX2,
CPU_Am486DX,
CPU_Am486DX2,
CPU_Cx486DX,
CPU_Cx486DX2,
CPU_iDX4,
CPU_Am486DX4,
CPU_Cx486DX4,
CPU_Am5x86,
CPU_Cx5x86,
CPU_P24T,
CPU_WINCHIP, /* 586 class CPUs */
CPU_WINCHIP2,
CPU_PENTIUM,
CPU_PENTIUMMMX,
CPU_Cx6x86,
CPU_Cx6x86MX,
CPU_Cx6x86L,
CPU_CxGX1,
CPU_K5,
CPU_5K86,
CPU_K6,
CPU_K6_2,
CPU_K6_2C,
CPU_K6_3,
CPU_K6_2P,
CPU_K6_3P,
CPU_CYRIX3S,
CPU_PENTIUMPRO, /* 686 class CPUs */
CPU_PENTIUM2,
CPU_PENTIUM2D
};
enum {

14
src/cpu/x87_ops.h
View File

@@ -46,6 +46,12 @@ static int rounding_modes[4] = {FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARDZ
#define STATUS_ZERODIVIDE 4
#if defined(_MSC_VER) && !defined(__clang__)
# define X87_INLINE_ASM defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
#else
# define X87_INLINE_ASM defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64 || defined __amd64__
#endif
#ifdef FPU_8087
#define x87_div(dst, src1, src2) do \
{ \
@@ -311,7 +317,7 @@ static __inline void x87_stmmx(MMX_REG r)
static __inline uint16_t x87_compare(double a, double b)
{
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64
#if X87_INLINE_ASM
uint32_t result;
double ea = a, eb = b;
const uint64_t ia = 0x3fec1a6ff866a936ull;
@@ -325,7 +331,7 @@ static __inline uint16_t x87_compare(double a, double b)
((a == INFINITY) || (a == -INFINITY)) && ((b == INFINITY) || (b == -INFINITY)))
eb = ea;
#ifndef _MSC_VER
#if !defined(_MSC_VER) || defined(__clang__)
/* Memory barrier, to force GCC to write to the input parameters
* before the compare rather than after */
__asm volatile ("" : : : "memory");
@@ -373,10 +379,10 @@ static __inline uint16_t x87_compare(double a, double b)
static __inline uint16_t x87_ucompare(double a, double b)
{
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64 || defined __amd64__
#if X87_INLINE_ASM
uint32_t result;
#ifndef _MSC_VER
#if !defined(_MSC_VER) || defined(__clang__)
/* Memory barrier, to force GCC to write to the input parameters
* before the compare rather than after */
asm volatile ("" : : : "memory");

9
src/disk/hdc_ide_cmd640.c
View File

@@ -378,6 +378,7 @@ cmd640_init(const device_t *info)
dev->regs[0x01] = 0x10;
dev->regs[0x02] = 0x40; /* PCI-0640B */
dev->regs[0x03] = 0x06;
dev->regs[0x04] = 0x01; /* Apparently required by the ASUS PCI/I-P5SP4 AND PCI/I-P54SP4 */
dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
dev->regs[0x08] = 0x02; /* Revision 02 */
dev->regs[0x09] = info->local; /* Programming interface */
@@ -395,7 +396,7 @@ cmd640_init(const device_t *info)
dev->regs[0x3c] = 0x14; /* IRQ 14 */
dev->regs[0x3d] = 0x01; /* INTA */
device_add(&ide_vlb_2ch_device);
device_add(&ide_pci_2ch_device);
dev->slot = pci_add_card(PCI_ADD_IDE, cmd640_pci_read, cmd640_pci_write, dev);
dev->irq_mode[0] = dev->irq_mode[1] = 0;
@@ -410,7 +411,7 @@ cmd640_init(const device_t *info)
ide_board_set_force_ata3(0, 1);
ide_board_set_force_ata3(1, 1);
ide_pri_disable();
// ide_pri_disable();
} else if (info->flags & DEVICE_VLB) {
if ((info->local & 0xffff) == 0x0078)
dev->regs[0x50] |= 0x20; /* 0 = 178h, 17Ch; 1 = 078h, 07Ch */
@@ -418,9 +419,9 @@ cmd640_init(const device_t *info)
accessing the configuration registers */
dev->in_cfg = 1; /* Configuration register are accessible */
device_add(&ide_pci_2ch_device);
device_add(&ide_vlb_2ch_device);
io_sethandler(0x0078, 0x0008,
io_sethandler(info->local & 0xffff, 0x0008,
cmd640_vlb_read, cmd640_vlb_readw, cmd640_vlb_readl,
cmd640_vlb_write, cmd640_vlb_writew, cmd640_vlb_writel,
dev);

2
src/include/86box/chipset.h
View File

@@ -95,9 +95,7 @@ extern const device_t sis_85c461_device;
extern const device_t sis_85c471_device;
extern const device_t sis_85c496_device;
extern const device_t sis_85c496_ls486e_device;
#if defined(DEV_BRANCH) && defined(USE_SIS_85C50X)
extern const device_t sis_85c50x_device;
#endif
/* ST */
#if defined(DEV_BRANCH) && defined(USE_STPC)

7
src/include/86box/machine.h
View File

@@ -301,6 +301,7 @@ extern int machine_at_403tg_init(const machine_t *);
extern int machine_at_pc330_6571_init(const machine_t *);
extern int machine_at_sis401_init(const machine_t *);
extern int machine_at_av4_init(const machine_t *);
extern int machine_at_valuepoint433_init(const machine_t *);
extern int machine_at_vli486sv2g_init(const machine_t *);
@@ -354,10 +355,8 @@ extern int machine_at_excalibur_init(const machine_t *);
extern int machine_at_batman_init(const machine_t *);
extern int machine_at_ambradp60_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_DELLS4)
extern int machine_at_dellxp60_init(const machine_t *);
extern int machine_at_opti560l_init(const machine_t *);
#endif
extern int machine_at_valuepointp60_init(const machine_t *);
extern int machine_at_p5mp3_init(const machine_t *);
extern int machine_at_pb520r_init(const machine_t *);
@@ -376,6 +375,10 @@ extern int machine_at_vectra54_init(const machine_t *);
extern int machine_at_powermate_v_init(const machine_t *);
extern int machine_at_acerv30_init(const machine_t *);
extern int machine_at_p5sp4_init(const machine_t *);
extern int machine_at_p54sp4_init(const machine_t *);
extern int machine_at_sq588_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_endeavor_get_device(void);
#define at_vectra54_get_device at_endeavor_get_device

1
src/include/86box/sio.h
View File

@@ -23,6 +23,7 @@ extern const device_t f82c710_device;
extern const device_t fdc37c661_device;
extern const device_t fdc37c663_device;
extern const device_t fdc37c665_device;
extern const device_t fdc37c665_ide_device;
extern const device_t fdc37c666_device;
extern const device_t fdc37c669_device;
extern const device_t fdc37c669_370_device;

1
src/include/86box/vid_svga.h
View File

@@ -22,6 +22,7 @@
#define FLAG_ADDR_BY8 2
#define FLAG_EXT_WRITE 4
#define FLAG_LATCH8 8
#define FLAG_NOSKEW 16
typedef struct {

12
src/include/86box/vid_voodoo_codegen_x86-64.h
View File

@@ -9,13 +9,17 @@
#include <sys/mman.h>
#include <unistd.h>
#endif
#if WIN64
#if _WIN64
#define BITMAP windows_BITMAP
#include <windows.h>
#undef BITMAP
#endif
#ifdef _MSC_VER
#include <intrin.h>
#else
#include <xmmintrin.h>
#endif
#define BLOCK_NUM 8
#define BLOCK_MASK (BLOCK_NUM-1)
@@ -752,7 +756,7 @@ static inline void voodoo_generate(uint8_t *code_block, voodoo_t *voodoo, voodoo
addbyte(0x6f);
addbyte(0x07 | (3 << 3));
#if WIN64
#if _WIN64
addbyte(0x48); /*MOV RDI, RCX (voodoo_state)*/
addbyte(0x89);
addbyte(0xcf);
@@ -3428,7 +3432,7 @@ void voodoo_codegen_init(voodoo_t *voodoo)
{
int c;
#if WIN64
#if _WIN64
voodoo->codegen_data = VirtualAlloc(NULL, sizeof(voodoo_x86_data_t) * BLOCK_NUM * 4, MEM_COMMIT, PAGE_EXECUTE_READWRITE);
#else
voodoo->codegen_data = mmap(0, sizeof(voodoo_x86_data_t) * BLOCK_NUM*4, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_ANON|MAP_PRIVATE, 0, 0);
@@ -3458,7 +3462,7 @@ void voodoo_codegen_init(voodoo_t *voodoo)
void voodoo_codegen_close(voodoo_t *voodoo)
{
#if WIN64
#if _WIN64
VirtualFree(voodoo->codegen_data, 0, MEM_RELEASE);
#else
munmap(voodoo->codegen_data, sizeof(voodoo_x86_data_t) * BLOCK_NUM*4);

4
src/include/86box/vid_voodoo_codegen_x86.h
View File

@@ -15,7 +15,11 @@
#undef BITMAP
#endif
#ifdef _MSC_VER
#include <intrin.h>
#else
#include <xmmintrin.h>
#endif
#define BLOCK_NUM 8
#define BLOCK_MASK (BLOCK_NUM-1)

2
src/include/86box/vid_voodoo_render.h
View File

@@ -1,4 +1,4 @@
#if !(defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined WIN32 || defined _WIN32 || defined _WIN32) && !(defined __amd64__)
#if !(defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64)
#define NO_CODEGEN
#endif

11
src/include/slirp/libslirp.h
View File

@@ -16,6 +16,17 @@
#include "libslirp-version.h"
/* Windows does not define ssize_t, so we need to define it here. */
#ifndef _SSIZE_T_DEFINED
# define _SSIZE_T_DEFINED
# undef ssize_t
# ifdef _WIN64
# define ssize_t int64_t
# else
# define ssize_t int32_t
# endif
#endif
#ifdef __cplusplus
extern "C" {
#endif

11
src/include/tinyglib.h
View File

@@ -77,6 +77,17 @@
/* Types */
/* Windows does not define ssize_t, so we need to define it here. */
#ifndef _SSIZE_T_DEFINED
# define _SSIZE_T_DEFINED
# undef ssize_t
# ifdef _WIN64
# define ssize_t int64_t
# else
# define ssize_t int32_t
# endif
#endif
#define gboolean int
#define gchar char
#define gint int

22
src/machine/m_at_386dx_486.c
View File

@@ -102,6 +102,27 @@ machine_at_sis401_init(const machine_t *model)
return ret;
}
int
machine_at_av4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/av4/amibios_486dx_isa_bios_aa4025963.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&sis_85c460_device);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
return ret;
}
int
machine_at_valuepoint433_init(const machine_t *model) // hangs without the PS/2 mouse
{
@@ -121,6 +142,7 @@ machine_at_valuepoint433_init(const machine_t *model) // hangs without the PS/2
return ret;
}
int
machine_at_ecs386_init(const machine_t *model)
{

92
src/machine/m_at_socket4_5.c
View File

@@ -122,7 +122,6 @@ machine_at_batman_init(const machine_t *model)
}
#if defined(DEV_BRANCH) && defined(USE_DELLS4)
int
machine_at_dellxp60_init(const machine_t *model)
{
@@ -184,7 +183,6 @@ machine_at_opti560l_init(const machine_t *model)
return ret;
}
#endif
int
@@ -646,3 +644,93 @@ machine_at_acerv30_init(const machine_t *model)
return ret;
}
static void
machine_at_sp4_common_init(const machine_t *model)
{
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
/* Excluded: 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14 */
pci_register_slot(0x0D, PCI_CARD_IDE, 1, 2, 3, 4);
/* Excluded: 02, 03*, 04*, 05*, 06*, 07*, 08* */
/* Slots: 09 (04), 0A (03), 0B (02), 0C (07) */
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_85c50x_device);
device_add(&ide_cmd640_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
int
machine_at_p5sp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p5sp4/0106.001",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_sp4_common_init(model);
return ret;
}
int
machine_at_p54sp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p54sp4/SI5I0204.AWD",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_sp4_common_init(model);
return ret;
}
int
machine_at_sq588_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/sq588/sq588b03.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
/* Correct: 0D (01), 0F (02), 11 (03), 13 (04) */
pci_register_slot(0x02, PCI_CARD_IDE, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_85c50x_device);
device_add(&ide_cmd640_pci_single_channel_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_ide_device);
device_add(&sst_flash_29ee010_device);
return ret;
}

10
src/machine/machine_table.c
View File

@@ -187,6 +187,7 @@ const machine_t machines[] = {
{ "[OPTi 802G] IBM PC 330 (type 6571)", "pc330_6571", MACHINE_TYPE_486, CPU_PKG_SOCKET3_PC330, 0, 25000000, 33333333, 0, 0, 2.0, 3.0, MACHINE_VLB | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_pc330_6571_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB, 1024, 65536, 1024, 127, machine_at_403tg_init, NULL },
{ "[SiS 401] AMI 486 Clone", "sis401", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_sis401_init, NULL },
{ "[SiS 460] ABIT AV4", "av4", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_av4_init, NULL },
{ "[SiS 461] IBM PS/ValuePoint 433DX/Si", "valuepoint433", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_valuepoint433_init, NULL },
{ "[SiS 471] AMI 486 Clone", "ami471", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_ami471_init, NULL },
{ "[SiS 471] AMI WinBIOS 486 clone", "win471", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_win471_init, NULL },
@@ -230,10 +231,8 @@ const machine_t machines[] = {
/* Socket 4 machines */
/* 430LX */
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 196608, 2048, 127, machine_at_p5mp3_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_DELLS4)
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 131072, 2048, 127, machine_at_dellxp60_init, NULL },
{ "[i430LX] Dell OptiPlex 560/L", "opti560l", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_opti560l_init, NULL },
#endif
{ "[i430LX] IBM Ambra DP60 PCI", "ambradp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_ambradp60_init, NULL },
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_valuepointp60_init, NULL },
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_batman_init, NULL },
@@ -243,6 +242,9 @@ const machine_t machines[] = {
/* OPTi 596/597 */
{ "[OPTi 597] AMI Excalibur VLB", "excalibur", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_VLB | MACHINE_IDE, 2048, 65536, 2048, 127, machine_at_excalibur_init, NULL },
/* SiS 85C50x */
{ "[SiS 85C50x] ASUS PCI/I-P5SP4", "p5sp4", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p5sp4_init, NULL },
/* Socket 5 machines */
/* 430NX */
{ "[i430NX] Intel Premiere/PCI II", "plato", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_plato_init, NULL },
@@ -257,6 +259,10 @@ const machine_t machines[] = {
{ "[i430FX] NEC PowerMate V", "powermate_v", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_powermate_v_init, NULL },
{ "[i430FX] PC Partner MB500N", "mb500n", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mb500n_init, NULL },
/* SiS 85C50x */
{ "[SiS 85C50x] ASUS PCI/I-P54SP4", "p54sp4", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54sp4_init, NULL },
{ "[SiS 85C50x] BCM SQ-588", "sq588", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_sq588_init, NULL },
/* Socket 7 machines */
/* 430FX */
{ "[i430FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3600, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54tp4xe_init, NULL },

2
src/network/network.c
View File

@@ -54,7 +54,7 @@
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <sys/time.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>

24
src/network/slirp/ip.h
View File

@@ -71,6 +71,9 @@ typedef uint32_t n_long; /* long as received from the net */
/*
* Structure of an internet header, naked of options.
*/
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct ip {
#if G_BYTE_ORDER == G_BIG_ENDIAN
uint8_t ip_v : 4, /* version */
@@ -91,6 +94,9 @@ struct ip {
uint16_t ip_sum; /* checksum */
struct in_addr ip_src, ip_dst; /* source and dest address */
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
#define IP_MAXPACKET 65535 /* maximum packet size */
@@ -134,6 +140,9 @@ struct ip {
/*
* Time stamp option structure.
*/
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct ip_timestamp {
uint8_t ipt_code; /* IPOPT_TS */
uint8_t ipt_len; /* size of structure (variable) */
@@ -153,6 +162,9 @@ struct ip_timestamp {
} ipt_ta[1];
} ipt_timestamp;
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
/* flag bits for ipt_flg */
#define IPOPT_TS_TSONLY 0 /* timestamps only */
@@ -178,6 +190,9 @@ struct ip_timestamp {
#define IP_MSS 576 /* default maximum segment size */
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
#if GLIB_SIZEOF_VOID_P == 4
struct mbuf_ptr {
struct mbuf *mptr;
@@ -188,6 +203,9 @@ struct mbuf_ptr {
struct mbuf *mptr;
} SLIRP_PACKED;
#endif
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
struct qlink {
void *next, *prev;
};
@@ -195,6 +213,9 @@ struct qlink {
/*
* Overlay for ip header used by other protocols (tcp, udp).
*/
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct ipovly {
struct mbuf_ptr ih_mbuf; /* backpointer to mbuf */
uint8_t ih_x1; /* (unused) */
@@ -203,6 +224,9 @@ struct ipovly {
struct in_addr ih_src; /* source internet address */
struct in_addr ih_dst; /* destination internet address */
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
/*
* Ip reassembly queue structure. Each fragment

6
src/network/slirp/ip6_icmp.h
View File

@@ -115,6 +115,9 @@ G_STATIC_ASSERT(sizeof(struct icmp6) == 40);
/*
* NDP Options
*/
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct ndpopt {
uint8_t ndpopt_type; /* Option type */
uint8_t ndpopt_len; /* /!\ In units of 8 octets */
@@ -142,6 +145,9 @@ struct ndpopt {
#define ndpopt_rdnss ndpopt_body.rdnss
} ndpopt_body;
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
/* NDP options type */
#define NDPOPT_LINKLAYER_SOURCE 1 /* Source Link-Layer Address */

11
src/network/slirp/libslirp.h
View File

@@ -16,6 +16,17 @@
#include "libslirp-version.h"
/* Windows does not define ssize_t, so we need to define it here. */
#ifndef _SSIZE_T_DEFINED
# define _SSIZE_T_DEFINED
# undef ssize_t
# ifdef _WIN64
# define ssize_t int64_t
# else
# define ssize_t int32_t
# endif
#endif
#ifdef __cplusplus
extern "C" {
#endif

4
src/network/slirp/misc.c
View File

@@ -8,7 +8,7 @@
#include <sys/un.h>
#endif
inline void insque(void *a, void *b)
extern inline void insque(void *a, void *b)
{
register struct quehead *element = (struct quehead *)a;
register struct quehead *head = (struct quehead *)b;
@@ -19,7 +19,7 @@ inline void insque(void *a, void *b)
(struct quehead *)element;
}
inline void remque(void *a)
extern inline void remque(void *a)
{
register struct quehead *element = (struct quehead *)a;
((struct quehead *)(element->qh_link))->qh_rlink = element->qh_rlink;

6
src/network/slirp/slirp.h
View File

@@ -75,6 +75,9 @@ struct ethhdr {
unsigned short h_proto; /* packet type ID field */
};
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct slirp_arphdr {
unsigned short ar_hrd; /* format of hardware address */
unsigned short ar_pro; /* format of protocol address */
@@ -90,6 +93,9 @@ struct slirp_arphdr {
unsigned char ar_tha[ETH_ALEN]; /* target hardware address */
uint32_t ar_tip; /* target IP address */
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
#define ARP_TABLE_SIZE 16

6
src/network/slirp/tftp.h
View File

@@ -20,6 +20,9 @@
#define TFTP_FILENAME_MAX 512
#define TFTP_BLOCKSIZE_MAX 1428
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct tftp_t {
struct udphdr udp;
uint16_t tp_op;
@@ -35,6 +38,9 @@ struct tftp_t {
char tp_buf[TFTP_BLOCKSIZE_MAX + 2];
} x;
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
struct tftp_session {
Slirp *slirp;

15
src/network/slirp/util.h
View File

@@ -30,10 +30,11 @@
#include <stdio.h>
#include <assert.h>
#include <errno.h>
#ifndef _WIN32
#include <unistd.h>
#endif
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <inttypes.h>
#ifdef _WIN32
@@ -45,8 +46,10 @@
#include <netinet/in.h>
#endif
#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
#define SLIRP_PACKED __attribute__((gcc_struct, packed))
#if defined(_MSC_VER) && !defined(__clang__)
#define SLIRP_PACKED
#elif defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
#define SLIRP_PACKED __attribute__((gcc_struct, packed))
#else
#define SLIRP_PACKED __attribute__((packed))
#endif
@@ -56,11 +59,7 @@
#endif
#ifndef container_of
#define container_of(ptr, type, member) \
__extension__({ \
void *__mptr = (void *)(ptr); \
((type *)(__mptr - offsetof(type, member))); \
})
#define container_of(ptr, type, member) ((type *)((char *)(ptr) - offsetof(type, member)));
#endif
#ifndef G_SIZEOF_MEMBER

2
src/network/slirp/vmstate.h
View File

@@ -39,7 +39,9 @@
#ifndef VMSTATE_H_
#define VMSTATE_H_
#ifndef _WIN32
#include <unistd.h>
#endif
#include <stdint.h>
#include <stdbool.h>
#include "slirp.h"

35
src/sio/sio_fdc37c66x.c
View File

@@ -38,7 +38,7 @@
typedef struct {
uint8_t chip_id, tries,
regs[16];
has_ide, regs[16];
int cur_reg,
com3_addr, com4_addr;
fdc_t *fdc;
@@ -131,6 +131,18 @@ fdc_handler(fdc37c66x_t *dev)
}
static void
ide_handler(fdc37c66x_t *dev)
{
ide_sec_disable();
ide_set_base(1, (dev->regs[0x05] & 0x02) ? 0x170 : 0x1f0);
ide_set_side(1, (dev->regs[0x05] & 0x02) ? 0x376 : 0x3f6);
if (dev->regs[0x00] & 0x01)
ide_sec_enable();
}
static void
fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
{
@@ -152,6 +164,8 @@ fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
switch(dev->cur_reg) {
case 0:
if (dev->has_ide && (valxor & 0x01))
ide_handler(dev);
if (valxor & 0x10)
fdc_handler(dev);
break;
@@ -183,6 +197,8 @@ fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
case 5:
if (valxor & 0x01)
fdc_handler(dev);
if (dev->has_ide && (valxor & 0x02))
ide_handler(dev);
if (valxor & 0x18)
fdc_update_densel_force(dev->fdc, (dev->regs[5] & 0x18) >> 3);
if (valxor & 0x20)
@@ -237,6 +253,9 @@ fdc37c66x_reset(fdc37c66x_t *dev)
dev->regs[0x6] = 0xff;
dev->regs[0xd] = dev->chip_id;
dev->regs[0xe] = 0x01;
if (dev->has_ide)
ide_handler(dev);
}
@@ -260,7 +279,10 @@ fdc37c66x_init(const device_t *info)
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->chip_id = info->local;
dev->chip_id = info->local & 0xff;
dev->has_ide = !!(info->local & 0x100);
if (dev->has_ide)
io_sethandler(0x03f0, 0x0002,
fdc37c66x_read, NULL, NULL, fdc37c66x_write, NULL, NULL, dev);
@@ -291,6 +313,15 @@ const device_t fdc37c665_device = {
NULL
};
const device_t fdc37c665_ide_device = {
"SMC FDC37C665 Super I/O",
0,
0x165,
fdc37c66x_init, fdc37c66x_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t fdc37c666_device = {
"SMC FDC37C666 Super I/O",
0,

4
src/sound/resid-fp/sid.cc
View File

@@ -29,7 +29,7 @@ enum host_cpu_feature {
};
/* This code is appropriate for 32-bit and 64-bit x86 CPUs. */
#if defined(__x86_64__) || defined(__i386__) || defined(_MSC_VER)
#if defined(__x86_64__) || defined(__i386__) || defined(_M_IX86) || (defined(_M_X64) && !(defined(_MSC_VER) && !defined(__clang__)))
struct cpu_x86_regs_s {
unsigned int eax;
@@ -43,7 +43,7 @@ static cpu_x86_regs_t get_cpuid_regs(unsigned int index)
{
cpu_x86_regs_t retval;
#if defined(_MSC_VER) /* MSVC assembly */
#if defined(_MSC_VER) && !defined(__clang__) /* MSVC assembly */
__asm {
mov eax, [index]
cpuid

2
src/sound/resid-fp/siddefs-fp.h
View File

@@ -74,7 +74,7 @@ const char* resid_version_string = VERSION;
// Inlining on/off.
#define RESID_INLINE inline
#if defined(__SSE__) || (defined(_MSC_VER) && (_MSC_VER >= 1300))
#if defined(__SSE__) || (defined(_M_IX86_FP ) && _M_IX86_FP >= 1) || defined(_M_X64)
#define RESID_USE_SSE 1
#else
#define RESID_USE_SSE 0

1
src/video/vid_et4000w32.c
View File

@@ -1312,6 +1312,7 @@ void *et4000w32p_init(const device_t *info)
et4000->svga.clock_gen = et4000->svga.ramdac;
et4000->svga.getclock = stg_getclock;
et4000->svga.adv_flags |= FLAG_NOSKEW;
break;
case ET4000W32_DIAMOND:

4
src/video/vid_svga.c
View File

@@ -445,7 +445,7 @@ svga_recalctimings(svga_t *svga)
svga->interlace = 0;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]);
svga->ca_adj = 0;
svga->rowcount = svga->crtc[9] & 31;
@@ -459,6 +459,8 @@ svga_recalctimings(svga_t *svga)
svga->hdisp *= (svga->seqregs[1] & 1) ? 16 : 18;
} else {
svga->render = svga_render_text_80;
if (!(svga->adv_flags & FLAG_NOSKEW))
svga->ma_latch += ((svga->crtc[8] & 0x60) >> 5);
svga->hdisp *= (svga->seqregs[1] & 1) ? 8 : 9;
}
svga->hdisp_old = svga->hdisp;

29
src/video/vid_voodoo_banshee.c
View File

@@ -2083,8 +2083,8 @@ static void banshee_overlay_draw(svga_t *svga, int displine)
case VIDPROCCFG_FILTER_MODE_DITHER_4X4:
if (banshee->voodoo->scrfilter && banshee->voodoo->scrfilterEnabled)
{
uint8_t fil[(svga->overlay_latch.xsize) * 3];
uint8_t fil3[(svga->overlay_latch.xsize) * 3];
uint8_t *fil = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *fil3 = malloc((svga->overlay_latch.xsize) * 3);
if (banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE) /* leilei HACK - don't know of real 4x1 hscaled behavior yet, double for now */
{
@@ -2146,6 +2146,9 @@ static void banshee_overlay_draw(svga_t *svga, int displine)
fil[(x)*3+2] = vb_filter_v1_rb [fil[x*3+2]] [fil3[(x+1) *3+2]];
p[x] = (fil[x*3+2] << 16) | (fil[x*3+1] << 8) | fil[x*3];
}
free(fil);
free(fil3);
}
else /* filter disabled by emulator option */
{
@@ -2168,14 +2171,14 @@ static void banshee_overlay_draw(svga_t *svga, int displine)
case VIDPROCCFG_FILTER_MODE_DITHER_2X2:
if (banshee->voodoo->scrfilter && banshee->voodoo->scrfilterEnabled)
{
uint8_t fil[(svga->overlay_latch.xsize) * 3];
uint8_t soak[(svga->overlay_latch.xsize) * 3];
uint8_t soak2[(svga->overlay_latch.xsize) * 3];
uint8_t *fil = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *soak = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *soak2 = malloc((svga->overlay_latch.xsize) * 3);
uint8_t samp1[(svga->overlay_latch.xsize) * 3];
uint8_t samp2[(svga->overlay_latch.xsize) * 3];
uint8_t samp3[(svga->overlay_latch.xsize) * 3];
uint8_t samp4[(svga->overlay_latch.xsize) * 3];
uint8_t *samp1 = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *samp2 = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *samp3 = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *samp4 = malloc((svga->overlay_latch.xsize) * 3);
src = &svga->vram[src_addr2 & svga->vram_mask];
OVERLAY_SAMPLE(banshee->overlay_buffer[1]);
@@ -2229,6 +2232,14 @@ static void banshee_overlay_draw(svga_t *svga, int displine)
p[x] = (fil[x*3+2] << 16) | (fil[x*3+1] << 8) | fil[x*3];
}
}
free(fil);
free(soak);
free(soak2);
free(samp1);
free(samp2);
free(samp3);
free(samp4);
}
else /* filter disabled by emulator option */
{

12
src/video/vid_voodoo_display.c
View File

@@ -368,7 +368,7 @@ static void voodoo_filterline_v1(voodoo_t *voodoo, uint8_t *fil, int column, uin
int x;
// Scratchpad for avoiding feedback streaks
uint8_t fil3[(voodoo->h_disp) * 3];
uint8_t *fil3 = malloc((voodoo->h_disp) * 3);
/* 16 to 32-bit */
for (x=0; x<column;x++)
@@ -426,6 +426,8 @@ static void voodoo_filterline_v1(voodoo_t *voodoo, uint8_t *fil, int column, uin
fil[(x)*3+1] = voodoo->thefilterg[fil3[x*3+1]][fil3[ (x+1) *3+1]];
fil[(x)*3+2] = voodoo->thefilter[fil3[x*3+2]][fil3[ (x+1) *3+2]];
}
free(fil3);
}
@@ -434,7 +436,7 @@ static void voodoo_filterline_v2(voodoo_t *voodoo, uint8_t *fil, int column, uin
int x;
// Scratchpad for blending filter
uint8_t fil3[(voodoo->h_disp) * 3];
uint8_t *fil3 = malloc((voodoo->h_disp) * 3);
/* 16 to 32-bit */
for (x=0; x<column;x++)
@@ -491,6 +493,8 @@ static void voodoo_filterline_v2(voodoo_t *voodoo, uint8_t *fil, int column, uin
fil3[(column-1)*3] = voodoo->thefilterb [fil[(column-1)*3]][((src[column] & 31) << 3)];
fil3[(column-1)*3+1] = voodoo->thefilterg [fil[(column-1)*3+1]][(((src[column] >> 5) & 63) << 2)];
fil3[(column-1)*3+2] = voodoo->thefilter [fil[(column-1)*3+2]][(((src[column] >> 11) & 31) << 3)];
free(fil3);
}
void voodoo_callback(void *p)
@@ -545,7 +549,7 @@ void voodoo_callback(void *p)
if (voodoo->scrfilter && voodoo->scrfilterEnabled)
{
uint8_t fil[(voodoo->h_disp) * 3]; /* interleaved 24-bit RGB */
uint8_t *fil = malloc((voodoo->h_disp) * 3); /* interleaved 24-bit RGB */
if (voodoo->type == VOODOO_2)
voodoo_filterline_v2(voodoo, fil, voodoo->h_disp, src, voodoo->line);
@@ -556,6 +560,8 @@ void voodoo_callback(void *p)
{
p[x] = (voodoo->clutData256[fil[x*3]].b << 0 | voodoo->clutData256[fil[x*3+1]].g << 8 | voodoo->clutData256[fil[x*3+2]].r << 16);
}
free(fil);
}
else
{

4
src/video/vid_voodoo_render.c
View File

@@ -684,9 +684,9 @@ static inline void voodoo_tmu_fetch_and_blend(voodoo_t *voodoo, voodoo_params_t
state->tex_a[0] ^= 0xff;
}
#if (defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined WIN32 || defined _WIN32 || defined _WIN32) && !(defined __amd64__)
#if (defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86) && !(defined __amd64__ || defined _M_X64)
#include <86box/vid_voodoo_codegen_x86.h>
#elif (defined __amd64__)
#elif (defined __amd64__ || defined _M_X64)
#include <86box/vid_voodoo_codegen_x86-64.h>
#else
int voodoo_recomp = 0;

4
src/win/86Box.rc
View File

@@ -15,11 +15,9 @@
* Copyright 2016-2019 Miran Grca.
* Copyright 2018,2019 David Hrdlička.
*/
#include <inttypes.h>
#define IN_RESOURCE_H
#include <86box/resource.h>
#include <86box/86box.h>
#include <86box/plat.h>
#include <86box/language.h>
#include <86box/version.h>
#undef IN_RESOURCE_H

12
src/win/Makefile.mingw
View File

@@ -96,9 +96,6 @@ ifeq ($(DEV_BUILD), y)
ifndef USE_VECT486VL
USE_VECT486VL := y
endif
ifndef USE_DELLS4
USE_DELLS4 := y
endif
else
ifndef DEBUG
DEBUG := n
@@ -169,9 +166,6 @@ else
ifndef USE_VECT486VL
USE_VECT486VL := n
endif
ifndef USE_DELLS4
USE_DELLS4 := n
endif
endif
# Defaults for several build options (possibly defined in a chained file.)
@@ -570,10 +564,6 @@ ifeq ($(USE_VECT486VL), y)
OPTS += -DUSE_VECT486VL
endif
ifeq ($(USE_DELLS4), y)
OPTS += -DUSE_DELLS4
endif
endif
@@ -606,7 +596,7 @@ CPUOBJ := cpu.o cpu_table.o \
CHIPSETOBJ := acc2168.o cs8230.o ali1429.o headland.o intel_82335.o cs4031.o \
intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o opti495.o opti895.o opti5x7.o scamp.o scat.o via_vt82c49x.o via_vt82c505.o \
sis_85c310.o sis_85c4xx.o sis_85c496.o opti283.o opti291.o umc491.o \
sis_85c310.o sis_85c4xx.o sis_85c496.o sis_85c50x.o opti283.o opti291.o umc491.o \
via_apollo.o via_pipc.o wd76c10.o vl82c480.o
MCHOBJ := machine.o machine_table.o \