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Merge branch 'temp' into temp

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This commit is contained in:
nerd73
2020-03-23 02:29:33 -06:00
committed by GitHub
parent 1ced5064ec ab3f76f09c
commit d555614739
25 changed files with 219 additions and 5857 deletions
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23
src/chipset/intel_4x0.c
View File

@@ -60,8 +60,6 @@ typedef struct
static void
i4x0_map(uint32_t addr, uint32_t size, int state)
{
// pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state);
switch (state & 3) {
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
@@ -97,7 +95,6 @@ pm2_cntrl_read(uint16_t addr, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
// pclog("PM2_CTL read: %02X\n", dev->pm2_cntrl & 0x01);
return dev->pm2_cntrl & 0x01;
}
@@ -107,7 +104,6 @@ pm2_cntrl_write(uint16_t addr, uint8_t val, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
// pclog("PM2_CTL write: %02X\n", val);
dev->pm2_cntrl = val & 0x01;
}
@@ -120,13 +116,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
uint8_t *regs_l = (uint8_t *) dev->regs_locked[func];
int i;
if (func > dev->max_func) {
// pclog("invalid write %02X to %02X:%02X\n", val, func, addr);
return;
}
// pclog("write %02X to %02X:%02X\n", val, func, addr);
if (func > dev->max_func)
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
@@ -668,7 +659,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
// pclog("430TX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis");
break;
case INTEL_440BX:
regs[0x79] = val;
@@ -682,7 +672,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
// pclog("440BX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis");
break;
}
break;
@@ -918,10 +907,9 @@ i4x0_read(int func, int addr, void *priv)
uint8_t ret = 0xff;
uint8_t *regs = (uint8_t *) dev->regs[func];
if (func > dev->max_func) {
ret = 0xff;
// pclog("invalid read %02X from %02X:%02X\n", ret, func, addr);
} else {
if (func > dev->max_func)
ret = 0xff;
else {
ret = regs[addr];
#if defined(DEV_BRANCH) && defined(USE_I686)
/* Special behavior for 440FX register 0x93 which is basically TRC in PCI space
@@ -929,7 +917,6 @@ i4x0_read(int func, int addr, void *priv)
if ((func == 0) && (addr == 0x93) && (dev->type == INTEL_440FX))
ret = (ret & 0xf9) | (trc_read(0x0093, NULL) & 0x06);
#endif
// pclog("read %02X from %02X:%02X\n", ret, func, addr);
}
return ret;

529
src/chipset/intel_4x0.c.old
View File

@@ -1,529 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel PCISet chips from 420TX to 440FX.
*
* Version: @(#)intel_4x0.c 1.0.3 2020/01/24
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2019,2020 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "86box.h"
#include "cpu.h"
#include "mem.h"
#include "86box_io.h"
#include "rom.h"
#include "pci.h"
#include "device.h"
#include "keyboard.h"
#include "chipset.h"
enum
{
INTEL_420TX,
INTEL_430LX,
INTEL_430NX,
INTEL_430FX,
INTEL_430FX_PB640,
INTEL_430HX,
INTEL_430VX,
INTEL_430TX
#if defined(DEV_BRANCH) && defined(USE_I686)
,INTEL_440FX
#endif
};
typedef struct
{
uint8_t pm2_cntrl;
uint8_t regs[256];
int type;
} i4x0_t;
static void
i4x0_map(uint32_t addr, uint32_t size, int state)
{
// pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state);
switch (state & 3) {
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
static void
i4x0_write(int func, int addr, uint8_t val, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
if (func)
return;
pclog("write %02X to %08X\n", val, addr);
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
if (dev->type >= INTEL_430FX) {
if (dev->type == INTEL_430FX_PB640)
val &= 0x06;
else
val &= 0x02;
} else
val &= 0x42;
val |= 0x04;
break;
case 0x05:
if (dev->type >= INTEL_430FX)
val = 0;
else
val &= 0x01;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
if (dev->type >= INTEL_430HX) {
val &= 0x80;
val |= 0x02;
} else {
val = 0x02;
if (dev->type == INTEL_430FX_PB640)
val |= 0x20;
}
break;
case 0x52: /*Cache Control Register*/
#if defined(DEV_BRANCH) && defined(USE_I686)
if (dev->type < INTEL_440FX) {
#endif
cpu_cache_ext_enabled = (val & 0x01);
cpu_update_waitstates();
#if defined(DEV_BRANCH) && defined(USE_I686)
}
#endif
break;
case 0x59: /*PAM0*/
if ((dev->regs[0x59] ^ val) & 0xf0) {
i4x0_map(0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
break;
case 0x5a: /*PAM1*/
if ((dev->regs[0x5a] ^ val) & 0x0f)
i4x0_map(0xc0000, 0x04000, val & 0xf);
if ((dev->regs[0x5a] ^ val) & 0xf0)
i4x0_map(0xc4000, 0x04000, val >> 4);
break;
case 0x5b: /*PAM2*/
if ((dev->regs[0x5b] ^ val) & 0x0f)
i4x0_map(0xc8000, 0x04000, val & 0xf);
if ((dev->regs[0x5b] ^ val) & 0xf0)
i4x0_map(0xcc000, 0x04000, val >> 4);
break;
case 0x5c: /*PAM3*/
if ((dev->regs[0x5c] ^ val) & 0x0f)
i4x0_map(0xd0000, 0x04000, val & 0xf);
if ((dev->regs[0x5c] ^ val) & 0xf0)
i4x0_map(0xd4000, 0x04000, val >> 4);
break;
case 0x5d: /*PAM4*/
if ((dev->regs[0x5d] ^ val) & 0x0f)
i4x0_map(0xd8000, 0x04000, val & 0xf);
if ((dev->regs[0x5d] ^ val) & 0xf0)
i4x0_map(0xdc000, 0x04000, val >> 4);
break;
case 0x5e: /*PAM5*/
if ((dev->regs[0x5e] ^ val) & 0x0f)
i4x0_map(0xe0000, 0x04000, val & 0xf);
if ((dev->regs[0x5e] ^ val) & 0xf0)
i4x0_map(0xe4000, 0x04000, val >> 4);
break;
case 0x5f: /*PAM6*/
if ((dev->regs[0x5f] ^ val) & 0x0f)
i4x0_map(0xe8000, 0x04000, val & 0xf);
if ((dev->regs[0x5f] ^ val) & 0xf0)
i4x0_map(0xec000, 0x04000, val >> 4);
break;
case 0x72: /*SMRAM*/
if ((dev->type >= INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x48))
i4x0_map(0xa0000, 0x20000, ((val & 0x48) == 0x48) ? 3 : 0);
else if ((dev->type < INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x20))
i4x0_map(0xa0000, 0x20000, ((val & 0x20) == 0x20) ? 3 : 0);
break;
case 0x73: case 0x74:
// pclog("Access %i at %08X\n", dev->regs[0x73] & 3, dev->regs[0x74] << 19);
break;
}
dev->regs[addr] = val;
}
static uint8_t
i4x0_read(int func, int addr, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
uint8_t ret = 0xff;
if (!func) {
ret = dev->regs[addr];
pclog("read %02X from %08X\n", ret, addr);
// if (addr == 0x50)
// pclog("read %02X from %08X\n", ret, addr);
}
return ret;
}
static void
i4x0_reset(void *priv)
{
i4x0_t *i4x0 = (i4x0_t *)priv;
i4x0_write(0, 0x59, 0x00, priv);
i4x0_write(0, 0x5e, 0x00, priv);
i4x0_write(0, 0x5f, 0x00, priv);
if (i4x0->type >= INTEL_430FX)
i4x0_write(0, 0x72, 0x02, priv);
smbase = 0xa0000;
}
static void
i4x0_close(void *p)
{
i4x0_t *i4x0 = (i4x0_t *)p;
free(i4x0);
}
static uint8_t
pm2_cntrl_read(uint16_t addr, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
return dev->pm2_cntrl & 0x01;
}
static void
pm2_cntrl_write(uint16_t addr, uint8_t val, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
dev->pm2_cntrl = val & 0x01;
}
static void
*i4x0_init(const device_t *info)
{
i4x0_t *i4x0 = (i4x0_t *) malloc(sizeof(i4x0_t));
memset(i4x0, 0, sizeof(i4x0_t));
i4x0->type = info->local;
i4x0->regs[0x00] = 0x86; i4x0->regs[0x01] = 0x80; /*Intel*/
switch(i4x0->type) {
case INTEL_420TX:
i4x0->regs[0x02] = 0x83; i4x0->regs[0x03] = 0x04; /*82424TX/ZX*/
i4x0->regs[0x08] = 0x03; /*A3 stepping*/
i4x0->regs[0x50] = 0x80;
// i4x0->regs[0x50] = 0x23;
i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
break;
case INTEL_430LX:
i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
i4x0->regs[0x08] = 0x03; /*A3 stepping*/
i4x0->regs[0x50] = 0x80;
i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
break;
case INTEL_430NX:
i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
i4x0->regs[0x08] = 0x10; /*A0 stepping*/
i4x0->regs[0x50] = 0xA0;
i4x0->regs[0x52] = 0x44; /*256kb PLB cache*/
i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
break;
case INTEL_430FX:
case INTEL_430FX_PB640:
i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/
if (i4x0->type == INTEL_430FX_PB640)
i4x0->regs[0x08] = 0x02; /*???? stepping*/
else
i4x0->regs[0x08] = 0x00; /*A0 stepping*/
i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
break;
case INTEL_430HX:
i4x0->regs[0x02] = 0x50; i4x0->regs[0x03] = 0x12; /*82439HX*/
i4x0->regs[0x08] = 0x00; /*A0 stepping*/
i4x0->regs[0x51] = 0x20;
i4x0->regs[0x52] = 0xB5; /*512kb cache*/
i4x0->regs[0x56] = 0x52; /*DRAM control*/
// i4x0->regs[0x59] = 0x40;
// i4x0->regs[0x5A] = i4x0->regs[0x5B] = i4x0->regs[0x5C] = i4x0->regs[0x5D] = 0x44;
// i4x0->regs[0x5E] = i4x0->regs[0x5F] = 0x44;
i4x0->regs[0x65] = i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
i4x0->regs[0x68] = 0x11;
break;
case INTEL_430VX:
i4x0->regs[0x02] = 0x30; i4x0->regs[0x03] = 0x70; /*82437VX*/
// i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/
i4x0->regs[0x08] = 0x00; /*A0 stepping*/
i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/
i4x0->regs[0x53] = 0x14;
i4x0->regs[0x56] = 0x52; /*DRAM control*/
i4x0->regs[0x67] = 0x11;
i4x0->regs[0x69] = 0x03;
i4x0->regs[0x70] = 0x20;
i4x0->regs[0x74] = 0x0e;
i4x0->regs[0x78] = 0x23;
break;
case INTEL_430TX:
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, i4x0);
i4x0->regs[0x02] = 0x00; i4x0->regs[0x03] = 0x71; /*82439TX*/
i4x0->regs[0x08] = 0x01; /*A0 stepping*/
i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/
i4x0->regs[0x53] = 0x14;
i4x0->regs[0x56] = 0x52; /*DRAM control*/
i4x0->regs[0x65] = 0x02;
i4x0->regs[0x67] = 0x80;
i4x0->regs[0x69] = 0x03;
i4x0->regs[0x70] = 0x20;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX:
i4x0->regs[0x02] = 0x37; i4x0->regs[0x03] = 0x12; /*82441FX*/
i4x0->regs[0x08] = 0x02; /*A0 stepping*/
i4x0->regs[0x2c] = 0xf4;
i4x0->regs[0x2d] = 0x1a;
i4x0->regs[0x2f] = 0x11;
i4x0->regs[0x51] = 0x01;
i4x0->regs[0x53] = 0x80;
i4x0->regs[0x58] = 0x10;
i4x0->regs[0x5a] = i4x0->regs[0x5b] = i4x0->regs[0x5c] = i4x0->regs[0x5d] = 0x11;
i4x0->regs[0x5e] = 0x11;
i4x0->regs[0x5f] = 0x31;
break;
#endif
}
i4x0->regs[0x04] = 0x06; i4x0->regs[0x05] = 0x00;
#if defined(DEV_BRANCH) && defined(USE_I686)
if (i4x0->type == INTEL_440FX)
i4x0->regs[0x06] = 0x80;
#endif
if (i4x0->type == INTEL_430FX)
i4x0->regs[0x07] = 0x82;
#if defined(DEV_BRANCH) && defined(USE_I686)
else if (i4x0->type != INTEL_440FX)
#else
else
#endif
i4x0->regs[0x07] = 0x02;
i4x0->regs[0x0b] = 0x06;
if (i4x0->type >= INTEL_430FX)
i4x0->regs[0x57] = 0x01;
else
i4x0->regs[0x57] = 0x31;
i4x0->regs[0x60] = i4x0->regs[0x61] = i4x0->regs[0x62] = i4x0->regs[0x63] = 0x02;
i4x0->regs[0x64] = 0x02;
if (i4x0->type >= INTEL_430FX)
i4x0->regs[0x72] = 0x02;
#if defined(DEV_BRANCH) && defined(USE_I686)
if (i4x0->type == INTEL_440FX) {
cpu_cache_ext_enabled = 1;
cpu_update_waitstates();
}
#endif
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, i4x0);
i4x0_write(0, 0x59, 0x00, i4x0);
i4x0_write(0, 0x5a, 0x00, i4x0);
i4x0_write(0, 0x5b, 0x00, i4x0);
i4x0_write(0, 0x5c, 0x00, i4x0);
i4x0_write(0, 0x5d, 0x00, i4x0);
i4x0_write(0, 0x5e, 0x00, i4x0);
i4x0_write(0, 0x5f, 0x00, i4x0);
smbase = 0xa0000;
return i4x0;
}
const device_t i420tx_device =
{
"Intel 82424TX",
DEVICE_PCI,
INTEL_420TX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430lx_device =
{
"Intel 82434LX",
DEVICE_PCI,
INTEL_430LX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430nx_device =
{
"Intel 82434NX",
DEVICE_PCI,
INTEL_430NX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430fx_device =
{
"Intel SB82437FX-66",
DEVICE_PCI,
INTEL_430FX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430fx_pb640_device =
{
"Intel SB82437FX-66 (PB640)",
DEVICE_PCI,
INTEL_430FX_PB640,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430hx_device =
{
"Intel 82439HX",
DEVICE_PCI,
INTEL_430HX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430vx_device =
{
"Intel 82437VX",
DEVICE_PCI,
INTEL_430VX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430tx_device =
{
"Intel 82439TX",
DEVICE_PCI,
INTEL_430TX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
#if defined(DEV_BRANCH) && defined(USE_I686)
const device_t i440fx_device =
{
"Intel 82441FX",
DEVICE_PCI,
INTEL_440FX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
#endif

9
src/chipset/sis_85c496.c
View File

@@ -120,8 +120,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
if ((addr >= 4 && addr < 8) || addr >= 0x40)
dev->pci_conf[addr] = val;
pclog("SiS 496 Write: %02X %02X %02X\n", func, addr, val);
valxor = old ^ val;
switch (addr) {
@@ -144,7 +142,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
port_92_remove(dev->port_92);
if (val & 0x02)
port_92_add(dev->port_92);
pclog("Port 92: %sabled\n", (val & 0x02) ? "En" : "Dis");
}
break;
@@ -199,10 +196,8 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x67:
if (valxor & 0x60) {
if (valxor & 0x60)
port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40));
pclog("[Port 92] Set features: %sreset, %sA20\n", !!(val & 0x20) ? "" : "no ", !!(val & 0x40) ? "" : "no ");
}
break;
case 0x82:
@@ -252,8 +247,6 @@ sis_85c496_read(int func, int addr, void *priv)
break;
}
pclog("SiS 496 Read: %02X %02X %02X\n", func, addr, ret);
return ret;
}

8
src/cpu_new/codegen_ops_misc.c
View File

@@ -359,11 +359,11 @@ uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
return -1;
case 0x28: /*JMP far*/
uop_MOVZX(ir, IREG_pc, src_reg);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1);
uop_CALL_FUNC(ir, loadcsjmp);
uop_MOVZX(ir, IREG_pc, src_reg);
return -1;
case 0x30: /*PUSH*/
@@ -466,11 +466,11 @@ uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
return -1;
case 0x28: /*JMP far*/
uop_MOV(ir, IREG_pc, src_reg);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1);
uop_CALL_FUNC(ir, loadcsjmp);
uop_MOV(ir, IREG_pc, src_reg);
return -1;
case 0x30: /*PUSH*/

32
src/disk/hdc_ide.c
View File

@@ -278,6 +278,8 @@ ide_irq_raise(ide_t *ide)
/* ide_log("Raising IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */
ide_log("IDE %i: IRQ raise\n", ide->board);
if (!(ide->fdisk & 2)) {
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq)
ide_bm[ide->board]->set_irq(ide->board | 0x40, ide_bm[ide->board]->priv);
@@ -298,6 +300,8 @@ ide_irq_lower(ide_t *ide)
/* ide_log("Lowering IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */
ide_log("IDE %i: IRQ lower\n", ide->board);
if (ide->irqstat) {
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq)
ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv);
@@ -318,6 +322,7 @@ ide_irq_update(ide_t *ide)
/* ide_log("Raising IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */
if (!(ide->fdisk & 2) && ide->irqstat) {
ide_log("IDE %i: IRQ update raise\n", ide->board);
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq) {
ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv);
ide_bm[ide->board]->set_irq(ide->board | 0x40, ide_bm[ide->board]->priv);
@@ -326,6 +331,7 @@ ide_irq_update(ide_t *ide)
picint(1 << ide_boards[ide->board]->irq);
}
} else if (ide->fdisk & 2) {
ide_log("IDE %i: IRQ update lower\n", ide->board);
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq)
ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv);
else if (ide_boards[ide->board]->irq != -1)
@@ -877,11 +883,17 @@ ide_atapi_callback(ide_t *ide)
switch(ide->sc->packet_status) {
case PHASE_IDLE:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_IDLE\n");
#endif
ide->sc->pos = 0;
ide->sc->phase = 1;
ide->sc->status = READY_STAT | DRQ_STAT | (ide->sc->status & ERR_STAT);
return;
case PHASE_COMMAND:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_COMMAND\n");
#endif
ide->sc->status = BUSY_STAT | (ide->sc->status & ERR_STAT);
if (ide->packet_command) {
ide->packet_command(ide->sc, ide->sc->atapi_cdb);
@@ -890,6 +902,9 @@ ide_atapi_callback(ide_t *ide)
}
return;
case PHASE_COMPLETE:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_COMPLETE\n");
#endif
ide->sc->status = READY_STAT;
ide->sc->phase = 3;
ide->sc->packet_status = PHASE_NONE;
@@ -897,12 +912,18 @@ ide_atapi_callback(ide_t *ide)
return;
case PHASE_DATA_IN:
case PHASE_DATA_OUT:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_DATA_IN or PHASE_DATA_OUT\n");
#endif
ide->sc->status = READY_STAT | DRQ_STAT | (ide->sc->status & ERR_STAT);
ide->sc->phase = !(ide->sc->packet_status & 0x01) << 1;
ide_irq_raise(ide);
return;
case PHASE_DATA_IN_DMA:
case PHASE_DATA_OUT_DMA:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_DATA_IN_DMA or PHASE_DATA_OUT_DMA\n");
#endif
out = (ide->sc->packet_status & 0x01);
if (ide_bm[ide->board] && ide_bm[ide->board]->dma) {
@@ -932,11 +953,17 @@ ide_atapi_callback(ide_t *ide)
return;
case PHASE_ERROR:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_ERROR\n");
#endif
ide->sc->status = READY_STAT | ERR_STAT;
ide->sc->phase = 3;
ide->sc->packet_status = PHASE_NONE;
ide_irq_raise(ide);
return;
default:
ide_log("PHASE_UNKNOWN %02X\n", ide->sc->packet_status);
return;
}
}
@@ -1001,6 +1028,9 @@ ide_atapi_packet_read(ide_t *ide, int length)
if (!dev || !dev->temp_buffer || (dev->packet_status != PHASE_DATA_IN))
return 0;
if (dev->packet_status == PHASE_DATA_IN)
ide_log("PHASE_DATA_IN read: %i, %i< %i, %i\n", dev->request_pos, dev->max_transfer_len, dev->pos, dev->packet_len);
bufferw = (uint16_t *) dev->temp_buffer;
bufferl = (uint32_t *) dev->temp_buffer;
@@ -1689,7 +1719,7 @@ ide_read_data(ide_t *ide, int length)
ide->secount = (ide->secount - 1) & 0xff;
if (ide->secount) {
ide_next_sector(ide);
ide->atastat = BSY_STAT;
ide->atastat = BSY_STAT | READY_STAT | DSC_STAT;
if (ide->command == WIN_READ_MULTIPLE)
ide_callback(ide_boards[ide->board]);
else

13
src/disk/hdc_ide_sff8038i.c
View File

@@ -373,14 +373,16 @@ sff_bus_master_set_irq(int channel, void *priv)
channel &= 0x01;
if (dev->status & 0x04) {
if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0))
sff_log("SFF8038i: Channel %i IRQ raise\n", channel);
if ((dev->irq_mode == 2) && channel && pci_use_mirq(0))
pci_set_mirq(0, 0);
else if (dev->irq_mode == 1)
pci_set_irq(dev->slot, dev->irq_pin);
else
picint(1 << (14 + channel));
} else {
if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0))
sff_log("SFF8038i: Channel %i IRQ lower\n", channel);
if ((dev->irq_mode == 2) && channel && pci_use_mirq(0))
pci_clear_mirq(0, 0);
else if (dev->irq_mode == 1)
pci_clear_irq(dev->slot, dev->irq_pin);
@@ -419,6 +421,10 @@ sff_reset(void *p)
{
int i = 0;
#ifdef ENABLE_SFF_LOG
sff_log("SFF8038i: Reset\n");
#endif
for (i = 0; i < CDROM_NUM; i++) {
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) &&
(cdrom[i].ide_channel < 4) && cdrom[i].priv)
@@ -429,6 +435,9 @@ sff_reset(void *p)
(zip_drives[i].ide_channel < 4) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
}
sff_bus_master_set_irq(0x00, p);
sff_bus_master_set_irq(0x01, p);
}

2
src/disk/hdc_st506_at.c
View File

@@ -463,7 +463,7 @@ mfm_readw(uint16_t port, void *priv)
mfm->secount = (mfm->secount - 1) & 0xff;
if (mfm->secount) {
next_sector(mfm);
mfm->status = STAT_BUSY;
mfm->status = STAT_BUSY | STAT_READY | STAT_DSC;
timer_set_delay_u64(&mfm->callback_timer, SECTOR_TIME);
} else
ui_sb_update_icon(SB_HDD|HDD_BUS_MFM, 0);

47
src/floppy/fdc.c
View File

@@ -702,10 +702,6 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->stat = 0x00;
fdc->pnum = fdc->ptot = 0;
}
if (val&4) {
fdc->stat = 0x80;
fdc->pnum = fdc->ptot = 0;
}
if ((val&4) && !(fdc->dor&4)) {
timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
fdc->interrupt = -1;
@@ -775,7 +771,16 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->stat |= 0x10;
fdc_log("Starting FDC command %02X\n",fdc->command);
switch (fdc->command & 0x1f) {
if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) ||
((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) ||
((fdc->command & 0x1f) == 0x0c) || ((fdc->command & 0x1f) == 0x0d) ||
((fdc->command & 0x1f) == 0x11) || ((fdc->command & 0x1f) == 0x16) ||
((fdc->command & 0x1f) == 0x19) || ((fdc->command & 0x1f) == 0x1d))
fdc->processed_cmd = fdc->command & 0x1f;
else
fdc->processed_cmd = fdc->command;
switch (fdc->processed_cmd) {
case 0x01: /*Mode*/
if (fdc->flags & FDC_FLAG_NSC) {
fdc->pnum = 0;
@@ -921,7 +926,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
}
if (fdc->pnum == fdc->ptot) {
fdc_log("Got all params %02X\n", fdc->command);
fdc->interrupt = fdc->command & 0x1F;
fdc->interrupt = fdc->processed_cmd;
fdc->reset_stat = 0;
/* Disable timer if enabled. */
timer_disable(&fdc->timer);
@@ -950,7 +955,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
break;
}
/* Process the firt phase of the command. */
switch (fdc->interrupt & 0x1F) {
switch (fdc->processed_cmd) {
case 0x02: /* Read a track */
fdc_io_command_phase1(fdc, 0);
fdc->read_track_sector.id.c = fdc->params[1];
@@ -1072,7 +1077,8 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->stat = (1 << fdc->drive);
if (!(fdc->flags & FDC_FLAG_PCJR))
fdc->stat |= 0x80;
fdc->head = (fdc->params[0] & 4) ? 1 : 0;
/* fdc->head = (fdc->params[0] & 4) ? 1 : 0; */
fdc->head = 0; /* TODO: See if this is correct. */
fdc->st0 = fdc->params[0] & 0x03;
fdc->st0 |= (fdc->params[0] & 4);
fdc->st0 |= 0x80;
@@ -1210,21 +1216,22 @@ fdc_read(uint16_t addr, void *priv)
}
} else {
if (is486 || !fdc->enable_3f1)
return 0xff;
ret = 0xff;
else {
ret = 0x70;
ret = 0x70;
drive = real_drive(fdc, fdc->dor & 3);
drive = real_drive(fdc, fdc->dor & 3);
if (drive)
ret &= ~0x40;
else
ret &= ~0x20;
if (drive)
ret &= ~0x40;
else
ret &= ~0x20;
if (fdc->dor & 0x10)
ret |= 1;
if (fdc->dor & 0x20)
ret |= 2;
if (fdc->dor & 0x10)
ret |= 1;
if (fdc->dor & 0x20)
ret |= 2;
}
}
break;
case 2:

2
src/floppy/fdc.h
View File

@@ -36,7 +36,7 @@
typedef struct {
uint8_t dor, stat, command, dat, st0, swap;
uint8_t dor, stat, command, processed_cmd, dat, st0, swap;
uint8_t swwp, disable_write;
uint8_t params[256], res[256];
uint8_t specify[256], format_dat[256];

2
src/floppy/fdd_86f.c
View File

@@ -826,7 +826,7 @@ d86f_byteperiod(int drive)
int
d86f_is_mfm(int drive)
{
return (d86f_track_flags(drive) & 8) ? 1 : 0;
return ((d86f_track_flags(drive) & 0x18) == 0x08) ? 1 : 0;
}

1
src/hwm.c
View File

@@ -14,6 +14,7 @@
* Copyright 2020 RichardG.
*/
#include <stdint.h>
#include "device.h"
#include "hwm.h"

2
src/intel_piix.c
View File

@@ -35,6 +35,7 @@
#include "device.h"
#include "apm.h"
#include "keyboard.h"
#include "machine.h"
#include "mem.h"
#include "timer.h"
#include "nvr.h"
@@ -1209,6 +1210,7 @@ static void
*piix_init(const device_t *info)
{
int i;
CPU *cpu_s = &machines[machine].cpu[cpu_manufacturer].cpus[cpu];
piix_t *dev = (piix_t *) malloc(sizeof(piix_t));
memset(dev, 0, sizeof(piix_t));

3
src/keyboard_at.c
View File

@@ -2210,7 +2210,8 @@ kbd_read(uint16_t port, void *priv)
atkbd_t *dev = (atkbd_t *)priv;
uint8_t ret = 0xff;
sub_cycles(ISA_CYCLES(8));
if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_NOREF)
sub_cycles(ISA_CYCLES(8));
if (((dev->flags & KBC_VEN_MASK) == KBC_VEN_XI8088) && (port == 0x63))
port = 0x61;

19
src/machine/m_at_socket7_s7.c
View File

@@ -315,7 +315,7 @@ machine_at_tc430hx_init(const machine_t *model)
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
@@ -526,13 +526,8 @@ machine_at_txp4_init(const machine_t *model)
{
int ret;
#if 0
ret = bios_load_linear(L"roms/machines/txp4/5itw003.bin",
ret = bios_load_linear(L"roms/machines/txp4/0112L.001",
0x000e0000, 131072, 0);
#else
ret = bios_load_linear(L"roms/machines/txp4/TX5I0108.AWD",
0x000e0000, 131072, 0);
#endif
if (bios_only || !ret)
return ret;
@@ -605,13 +600,11 @@ machine_at_sp586tx_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);

22
src/mouse_ps2.c
View File

@@ -143,6 +143,27 @@ ps2_write(uint8_t val, void *priv)
keyboard_at_adddata_mouse(dev->sample_rate);
break;
case 0xeb: /* Get mouse data */
keyboard_at_adddata_mouse(0xfa);
temp = 0;
if (dev->x < 0)
temp |= 0x10;
if (dev->y < 0)
temp |= 0x20;
if (mouse_buttons & 1)
temp |= 1;
if (mouse_buttons & 2)
temp |= 2;
if ((mouse_buttons & 4) && (dev->flags & FLAG_INTELLI))
temp |= 4;
keyboard_at_adddata_mouse(temp);
keyboard_at_adddata_mouse(dev->x & 0xff);
keyboard_at_adddata_mouse(dev->y & 0xff);
if (dev->flags & FLAG_INTMODE)
keyboard_at_adddata_mouse(dev->z);
break;
case 0xf2: /* read ID */
keyboard_at_adddata_mouse(0xfa);
if (dev->flags & FLAG_INTMODE)
@@ -169,6 +190,7 @@ ps2_write(uint8_t val, void *priv)
case 0xff: /* reset */
dev->mode = MODE_STREAM;
dev->flags &= 0x88;
mouse_queue_start = mouse_queue_end = 0;
keyboard_at_adddata_mouse(0xfa);
keyboard_at_adddata_mouse(0xaa);
keyboard_at_adddata_mouse(0x00);

56
src/pic.c
View File

@@ -345,6 +345,35 @@ pic2_write(uint16_t addr, uint8_t val, void *priv)
pic.pend &= ~4;
pic_updatepending();
} else if (!(val & 8)) { /*OCW2*/
#ifdef ENABLE_PIC_LOG
switch ((val >> 5) & 0x07) {
case 0x00:
pic_log("Rotate in automatic EOI mode (clear)\n");
break;
case 0x01:
pic_log("Non-specific EOI command\n");
break;
case 0x02:
pic_log("No operation\n");
break;
case 0x03:
pic_log("Specific EOI command\n");
break;
case 0x04:
pic_log("Rotate in automatic EOI mode (set)\n");
break;
case 0x05:
pic_log("Rotate on on-specific EOI command\n");
break;
case 0x06:
pic_log("Set priority command\n");
break;
case 0x07:
pic_log("Rotate on specific EOI command\n");
break;
}
#endif
pic2.ocw2 = val;
if ((val & 0xE0) == 0x60) {
pic2.ins &= ~(1 << (val & 7));
@@ -512,21 +541,32 @@ pic_process_interrupt(PIC* target_pic, int c)
{
uint8_t pending = target_pic->pend & ~target_pic->mask;
int ret = -1;
/* TODO: On init, a PIC need to get a pointer to one of these, and rotate as needed
if in rotate mode. */
/* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
int priority_xt[16] = { 7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1 };
int priority_at[16] = { 14, 13, -1, 4, 3, 2, 1, 0, 12, 11, 10, 9, 8, 7, 6, 5 };
int i;
int pic_int = c & 7;
int pic_int_num = 1 << pic_int;
int in_service = 0;
in_service = (target_pic->ins & (pic_int_num - 1)); /* Is anything of higher priority already in service? */
in_service |= (target_pic->ins & pic_int_num); /* Is the current IRQ already in service? */
if (AT) {
/* AT-specific stuff. */
if (c >= 8)
in_service |= (pic.ins & 0x03); /* IRQ 8 to 15, are IRQ's with higher priorities than the
cascade IRQ already in service? */
/* For IRQ 0 to 7, the cascade IRQ's in service bit indicates that one or
more IRQ's between 8 and 15 are already in service. */
for (i = 0; i < 16; i++) {
if ((priority_at[i] != -1) && (priority_at[i] >= priority_at[c])) {
if (i < 8)
in_service |= (pic.ins & (1 << i));
else
in_service |= (pic2.ins & (1 << i));
}
}
} else {
for (i = 0; i < 16; i++) {
if ((priority_xt[i] != -1) && (priority_xt[i] >= priority_xt[c]))
in_service |= (pic.ins & (1 << i));
}
}
if ((pending & pic_int_num) && !in_service) {

3
src/scsi/scsi.c
View File

@@ -74,7 +74,8 @@ static SCSI_CARD scsi_cards[] = {
{ "[MCA] BusLogic BT-640A", "bt640a", &buslogic_640a_device, },
{ "[PCI] BusLogic BT-958D", "bt958d", &buslogic_pci_device, },
{ "[PCI] NCR 53C810", "ncr53c810", &ncr53c810_pci_device, },
//{ "[PCI] NCR 53C825A", "ncr53c825a", &ncr53c825a_pci_device, },
{ "[PCI] NCR 53C825A", "ncr53c825a", &ncr53c825a_pci_device, },
{ "[PCI] NCR 53C860", "ncr53c860", &ncr53c860_pci_device, },
{ "[PCI] NCR 53C875", "ncr53c875", &ncr53c875_pci_device, },
{ "[VLB] BusLogic BT-445S", "bt445s", &buslogic_445s_device, },
{ "", "", NULL, },

67
src/scsi/scsi_ncr53c8xx.c
View File

@@ -49,8 +49,11 @@
#define NCR53C8XX_ROM L"roms/scsi/ncr53c8xx/NCR307.BIN"
#define HA_ID 7
#define CHIP_810 0x01
#define CHIP_825 0x03
#define CHIP_860 0x06
#define CHIP_875 0x0f
#define NCR_SCNTL0_TRG 0x01
@@ -302,6 +305,10 @@ typedef struct {
uint32_t adder;
pc_timer_t timer;
#ifdef USE_WDTR
uint8_t tr_set[16];
#endif
} ncr53c8xx_t;
@@ -401,7 +408,7 @@ ncr53c8xx_soft_reset(ncr53c8xx_t *dev)
dev->scntl3 = 0;
dev->sstat0 = 0;
dev->sstat1 = 0;
dev->scid = 7;
dev->scid = HA_ID;
dev->sxfer = 0;
dev->socl = 0;
dev->sdid = 0;
@@ -428,13 +435,21 @@ ncr53c8xx_soft_reset(ncr53c8xx_t *dev)
if (dev->chip >= CHIP_825) {
/* This *IS* a wide SCSI controller, so reset all SCSI
devices. */
for (i = 0; i < 16; i++)
for (i = 0; i < 16; i++) {
#ifdef USE_WDTR
dev->tr_set[i] = 0;
#endif
scsi_device_reset(&scsi_devices[i]);
}
} else {
/* This is *NOT* a wide SCSI controller, so do not touch
SCSI devices with ID's >= 8. */
for (i = 0; i < 8; i++)
for (i = 0; i < 8; i++) {
#ifdef USE_WDTR
dev->tr_set[i] = 0;
#endif
scsi_device_reset(&scsi_devices[i]);
}
}
}
@@ -802,9 +817,9 @@ ncr53c8xx_do_wdtr(ncr53c8xx_t *dev, int exponent)
ncr53c8xx_log("Target-initiated WDTR (%08X)\n", dev);
ncr53c8xx_set_phase(dev, PHASE_MI);
dev->msg_action = 4;
ncr53c8xx_add_msg_byte(dev, 0x01); /* EXTENDED MESSAGE */
ncr53c8xx_add_msg_byte(dev, 0x02); /* EXTENDED MESSAGE LENGTH */
ncr53c8xx_add_msg_byte(dev, 0x03); /* WIDE DATA TRANSFER REQUEST */
ncr53c8xx_add_msg_byte(dev, 0x01); /* EXTENDED MESSAGE */
ncr53c8xx_add_msg_byte(dev, 0x02); /* EXTENDED MESSAGE LENGTH */
ncr53c8xx_add_msg_byte(dev, 0x03); /* WIDE DATA TRANSFER REQUEST */
ncr53c8xx_add_msg_byte(dev, exponent); /* TRANSFER WIDTH EXPONENT (16-bit) */
}
#endif
@@ -925,13 +940,14 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
break;
case 3:
ncr53c8xx_log("WDTR (ignored)\n");
#ifdef USE_WDTR
dev->tr_set[dev->sdid] = 1;
#endif
if (arg > 0x01) {
ncr53c8xx_bad_message(dev, msg);
return;
}
#ifdef USE_WDTR
ncr53c8xx_set_phase(dev, PHASE_CMD);
#endif
break;
case 5:
ncr53c8xx_log("PPR (ignored)\n");
@@ -960,9 +976,14 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
scsi_device_command_stop(sd);
ncr53c8xx_disconnect(dev);
break;
case 0x0c:
/* BUS DEVICE RESET message, reset wide transfer request. */
#ifdef USE_WDTR
dev->tr_set[dev->sdid] = 0;
#endif
/* FALLTHROUGH */
case 0x06:
case 0x0e:
case 0x0c:
/* clear the current I/O process */
scsi_device_command_stop(sd);
ncr53c8xx_disconnect(dev);
@@ -977,10 +998,11 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
dev->current_lun = msg & 7;
ncr53c8xx_log("Select LUN %d\n", dev->current_lun);
#ifdef USE_WDTR
ncr53c8xx_do_wdtr(dev, 0x01);
#else
ncr53c8xx_set_phase(dev, PHASE_CMD);
if ((dev->chip == CHIP_875) && !dev->tr_set[dev->sdid])
ncr53c8xx_do_wdtr(dev, 0x01);
else
#endif
ncr53c8xx_set_phase(dev, PHASE_CMD);
}
break;
}
@@ -2625,6 +2647,7 @@ ncr53c8xx_init(const device_t *info)
ncr53c8xx_pci_bar[0].addr_regs[0] = 1;
ncr53c8xx_pci_bar[1].addr_regs[0] = 0;
dev->chip = info->local;
ncr53c8xx_pci_regs[0x04] = 3;
ncr53c8xx_mem_init(dev, 0x0fffff00);
@@ -2632,12 +2655,14 @@ ncr53c8xx_init(const device_t *info)
dev->has_bios = device_get_config_int("bios");
if (dev->has_bios)
rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (dev->chip >= CHIP_825) {
if (dev->chip == CHIP_875) {
dev->chip_rev = 0x04;
dev->nvr_path = L"ncr53c875.nvr";
} else if (dev->chip == CHIP_860) {
dev->chip_rev = 0x04;
dev->nvr_path = L"ncr53c860.nvr";
} else {
dev->chip_rev = 0x26;
dev->nvr_path = L"ncr53c825a.nvr";
@@ -2654,8 +2679,8 @@ ncr53c8xx_init(const device_t *info)
ncr53c8xx_bios_disable(dev);
#endif
} else {
if (dev->has_bios)
rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
/* if (dev->has_bios)
rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); */
dev->nvr_path = L"ncr53c810.nvr";
}
@@ -2715,6 +2740,16 @@ const device_t ncr53c825a_pci_device =
ncr53c8xx_pci_config
};
const device_t ncr53c860_pci_device =
{
"NCR 53c860 (SCSI)",
DEVICE_PCI,
CHIP_860,
ncr53c8xx_init, ncr53c8xx_close, NULL,
NULL, NULL, NULL,
ncr53c8xx_pci_config
};
const device_t ncr53c875_pci_device =
{
"NCR 53c875 (SCSI)",

1
src/scsi/scsi_ncr53c8xx.h
View File

@@ -27,6 +27,7 @@
extern const device_t ncr53c810_pci_device;
extern const device_t ncr53c825a_pci_device;
extern const device_t ncr53c860_pci_device;
extern const device_t ncr53c875_pci_device;

321
src/sio_um8669f - Cópia.c
View File

@@ -1,321 +0,0 @@
/*um8669f :
aa to 108 unlocks
next 108 write is register select (Cx?)
data read/write to 109
55 to 108 locks
C1
bit 7 - enable PnP registers
PnP registers :
07 - device :
0 = FDC
1 = COM1
2 = COM2
3 = LPT1
5 = Game port
30 - enable
60/61 - addr
70 - IRQ
74 - DMA*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "86box.h"
#include "device.h"
#include "86box_io.h"
#include "timer.h"
#include "pci.h"
#include "lpt.h"
#include "serial.h"
#include "fdd.h"
#include "fdc.h"
#include "sio.h"
#define DEV_FDC 0
#define DEV_COM1 1
#define DEV_COM2 2
#define DEV_LPT1 3
#define DEV_GAME 5
#define REG_DEVICE 0x07
#define REG_ENABLE 0x30
#define REG_ADDRHI 0x60
#define REG_ADDRLO 0x61
#define REG_IRQ 0x70
#define REG_DMA 0x74
typedef struct um8669f_t
{
int locked, cur_reg_108,
cur_reg, cur_device,
pnp_active;
uint8_t regs_108[256];
struct {
int enable;
uint16_t addr;
int irq;
int dma;
} dev[8];
fdc_t *fdc;
serial_t *uart[2];
} um8669f_t;
static void
um8669f_pnp_write(uint16_t port, uint8_t val, void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
uint8_t valxor = 0;
uint8_t lpt_irq = 0xff;
if (port == 0x279)
dev->cur_reg = val;
else {
if (dev->cur_reg == REG_DEVICE)
dev->cur_device = val & 7;
else {
switch (dev->cur_reg) {
case REG_ENABLE:
valxor = dev->dev[dev->cur_device].enable ^ val;
dev->dev[dev->cur_device].enable = val;
break;
case REG_ADDRLO:
valxor = (dev->dev[dev->cur_device].addr & 0xff) ^ val;
dev->dev[dev->cur_device].addr = (dev->dev[dev->cur_device].addr & 0xff00) | val;
break;
case REG_ADDRHI:
valxor = ((dev->dev[dev->cur_device].addr >> 8) & 0xff) ^ val;
dev->dev[dev->cur_device].addr = (dev->dev[dev->cur_device].addr & 0x00ff) | (val << 8);
break;
case REG_IRQ:
valxor = dev->dev[dev->cur_device].irq ^ val;
dev->dev[dev->cur_device].irq = val;
break;
case REG_DMA:
valxor = dev->dev[dev->cur_device].dma ^ val;
dev->dev[dev->cur_device].dma = val;
break;
default:
valxor = 0;
break;
}
switch (dev->cur_device) {
case DEV_FDC:
if ((dev->cur_reg == REG_ENABLE) && valxor) {
fdc_remove(dev->fdc);
if (dev->dev[DEV_FDC].enable & 1)
fdc_set_base(dev->fdc, 0x03f0);
}
break;
case DEV_COM1:
if ((dev->cur_reg == REG_ENABLE) && valxor) {
serial_remove(dev->uart[0]);
if (dev->dev[DEV_COM1].enable & 1)
serial_setup(dev->uart[0], dev->dev[DEV_COM1].addr, dev->dev[DEV_COM1].irq);
}
break;
case DEV_COM2:
if ((dev->cur_reg == REG_ENABLE) && valxor) {
serial_remove(dev->uart[1]);
if (dev->dev[DEV_COM2].enable & 1)
serial_setup(dev->uart[1], dev->dev[DEV_COM2].addr, dev->dev[DEV_COM2].irq);
}
break;
case DEV_LPT1:
if ((dev->cur_reg == REG_ENABLE) && valxor) {
lpt1_remove();
if (dev->dev[DEV_LPT1].enable & 1)
lpt1_init(dev->dev[DEV_LPT1].addr);
}
if (dev->dev[DEV_LPT1].irq <= 15)
lpt_irq = dev->dev[DEV_LPT1].irq;
lpt1_irq(lpt_irq);
break;
}
}
}
}
static uint8_t
um8669f_pnp_read(uint16_t port, void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
uint8_t ret = 0xff;
switch (dev->cur_reg) {
case REG_DEVICE:
ret = dev->cur_device;
break;
case REG_ENABLE:
ret = dev->dev[dev->cur_device].enable;
break;
case REG_ADDRLO:
ret = dev->dev[dev->cur_device].addr & 0xff;
break;
case REG_ADDRHI:
ret = dev->dev[dev->cur_device].addr >> 8;
break;
case REG_IRQ:
ret = dev->dev[dev->cur_device].irq;
break;
case REG_DMA:
ret = dev->dev[dev->cur_device].dma;
break;
}
return ret;
}
void um8669f_write(uint16_t port, uint8_t val, void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
int new_pnp_active;
if (dev->locked) {
if ((port == 0x108) && (val == 0xaa))
dev->locked = 0;
} else {
if (port == 0x108) {
if (val == 0x55)
dev->locked = 1;
else
dev->cur_reg_108 = val;
} else {
dev->regs_108[dev->cur_reg_108] = val;
if (dev->cur_reg_108 == 0xc1) {
new_pnp_active = !!(dev->regs_108[0xc1] & 0x80);
if (new_pnp_active != dev->pnp_active) {
if (new_pnp_active) {
io_sethandler(0x0279, 0x0001,
NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_sethandler(0x0a79, 0x0001,
NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_sethandler(0x03e3, 0x0001,
um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev);
} else {
io_removehandler(0x0279, 0x0001,
NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_removehandler(0x0a79, 0x0001,
NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_removehandler(0x03e3, 0x0001,
um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev);
}
dev->pnp_active = new_pnp_active;
}
}
}
}
}
uint8_t um8669f_read(uint16_t port, void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
uint8_t ret = 0xff;
if (!dev->locked) {
if (port == 0x108)
ret = dev->cur_reg_108; /* ??? */
else
ret = dev->regs_108[dev->cur_reg_108];
}
return ret;
}
void
um8669f_reset(um8669f_t *dev)
{
fdc_reset(dev->fdc);
serial_remove(dev->uart[0]);
serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
serial_remove(dev->uart[1]);
serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
lpt1_remove();
lpt1_init(0x378);
if (dev->pnp_active) {
io_removehandler(0x0279, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_removehandler(0x0a79, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_removehandler(0x03e3, 0x0001, um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev);
dev->pnp_active = 0;
}
dev->locked = 1;
dev->dev[DEV_FDC].enable = 1;
dev->dev[DEV_FDC].addr = 0x03f0;
dev->dev[DEV_FDC].irq = 6;
dev->dev[DEV_FDC].dma = 2;
dev->dev[DEV_COM1].enable = 1;
dev->dev[DEV_COM1].addr = 0x03f8;
dev->dev[DEV_COM1].irq = 4;
dev->dev[DEV_COM2].enable = 1;
dev->dev[DEV_COM2].addr = 0x02f8;
dev->dev[DEV_COM2].irq = 3;
dev->dev[DEV_LPT1].enable = 1;
dev->dev[DEV_LPT1].addr = 0x0378;
dev->dev[DEV_LPT1].irq = 7;
}
static void
um8669f_close(void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
free(dev);
}
static void *
um8669f_init(const device_t *info)
{
um8669f_t *dev = (um8669f_t *) malloc(sizeof(um8669f_t));
memset(dev, 0, sizeof(um8669f_t));
dev->fdc = device_add(&fdc_at_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
io_sethandler(0x0108, 0x0002,
um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, dev);
um8669f_reset(dev);
return dev;
}
const device_t um8669f_device = {
"UMC UM8669F Super I/O",
0,
0,
um8669f_init, um8669f_close, NULL,
NULL, NULL, NULL,
NULL
};

27
src/sio_um8669f.c
View File

@@ -80,8 +80,6 @@ um8669f_pnp_write(uint16_t port, uint8_t val, void *priv)
uint8_t valxor = 0;
uint8_t lpt_irq = 0xff;
pclog("Write %02X at %04X\n", val, port);
if (port == 0x279)
dev->cur_reg = val;
else {
@@ -189,8 +187,6 @@ um8669f_write(uint16_t port, uint8_t val, void *priv)
um8669f_t *dev = (um8669f_t *) priv;
int new_pnp_active;
pclog("Write %02X at %04X\n", val, port);
if (dev->locked) {
if ((port == 0x108) && (val == 0xaa))
dev->locked = 0;
@@ -297,20 +293,6 @@ um8669f_close(void *priv)
}
void
um8669f_detect_write(uint16_t port, uint8_t val, void *priv)
{
pclog("Write %02X at %04X\n", val, port);
}
uint8_t
um8669f_detect_read(uint16_t port, void *priv)
{
return 0xff;
}
static void *
um8669f_init(const device_t *info)
{
@@ -325,15 +307,6 @@ um8669f_init(const device_t *info)
io_sethandler(0x0108, 0x0002,
um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, dev);
io_sethandler(0x0370, 0x0002,
um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
io_sethandler(0x03bd, 0x0001,
um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
io_sethandler(0x03bf, 0x0001,
um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
io_sethandler(0x03f0, 0x0002,
um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
um8669f_reset(dev);
return dev;

9
src/sound/snd_sb.c
View File

@@ -679,13 +679,9 @@ void sb_ct1745_mixer_write(uint16_t addr, uint8_t val, void *p)
sb_ct1745_mixer_t *mixer = &sb->mixer_sb16;
if (!(addr & 1))
{
pclog("CT1745: write IDX : %02X\n", val);
mixer->index = val;
}
else
{
pclog("CT1745: write REG%02X: %02X\n", mixer->index, val);
// TODO: and this? 001h:
/*DESCRIPTION
Contains previously selected register value. Mixer Data Register value
@@ -868,10 +864,8 @@ uint8_t sb_ct1745_mixer_read(uint16_t addr, void *p)
sb_ct1745_mixer_t *mixer = &sb->mixer_sb16;
uint8_t temp, ret = 0xff;
if (!(addr & 1)) {
if (!(addr & 1))
ret = mixer->index;
pclog("CT1745: read IDX : %02X\n", ret);
}
sb_log("sb_ct1745: received register READ: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]);
@@ -1008,7 +1002,6 @@ uint8_t sb_ct1745_mixer_read(uint16_t addr, void *p)
break;
}
pclog("CT1745: read REG%02X: %02X\n", mixer->index, ret);
return ret;
}

BIN
src/video/86Box.exe
View File

Binary file not shown.

4876
src/video/vid_mga - Cópia.c
View File

File diff suppressed because it is too large Load Diff

2
src/video/vid_mga.c
View File

@@ -4765,7 +4765,7 @@ mystique_pci_write(int func, int addr, uint8_t val, void *p)
case 0x48: case 0x49: case 0x4a: case 0x4b:
addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) |
(addr & 3);
pclog("mystique_ctrl_write_b(%04X, %02X)\n", addr, val);
/* pclog("mystique_ctrl_write_b(%04X, %02X)\n", addr, val); */
mystique_ctrl_write_b(addr, val, mystique);
break;
}