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Merge branch 'master' of ssh://github.com/86Box/86Box into feature/mtrr

Browse Source 
# Conflicts:
#	src/include/86box/machine.h
This commit is contained in:
RichardG867
2020-06-06 19:20:17 -03:00
parent b039e29770 6cf083c96d
commit c08053a814
41 changed files with 1101 additions and 434 deletions
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3
src/acpi.c
View File

@@ -787,6 +787,7 @@ acpi_reset(void *priv)
int i;
memset(&dev->regs, 0x00, sizeof(acpi_regs_t));
dev->regs.gpireg[0] = dev->regs.gpireg[1] = dev->regs.gpireg[2] = 0xff;
for (i = 0; i < 4; i++)
dev->regs.gporeg[i] = dev->gporeg_default[i];
}
@@ -832,6 +833,8 @@ acpi_init(const device_t *info)
timer_add(&dev->timer, acpi_timer_count, dev, 0);
timer_set_delay_u64(&dev->timer, ACPICONST);
dev->regs.gpireg[0] = dev->regs.gpireg[1] = dev->regs.gpireg[2] = 0xff;
return dev;
}

54
src/chipset/acc2168.c
View File

@@ -43,44 +43,30 @@ typedef struct acc2168_t
} acc2168_t;
/*
Based on reverse engineering using the AMI 386DX Clone BIOS:
Bit 0 of register 02 controls shadowing of C0000-C7FFF (1 = enabled, 0 = disabled);
Bit 1 of register 02 controls shadowing of C8000-CFFFF (1 = enabled, 0 = disabled);
Bit 2 of register 02 controls shadowing of D0000-DFFFF (1 = enabled, 0 = disabled);
Bit 3 of register 02 controls shadowing of E0000-EFFFF (1 = enabled, 0 = disabled);
Bit 4 of register 02 controls shadowing of F0000-FFFFF (1 = enabled, 0 = disabled);
Bit 5 is most likely: 1 = shadow enabled, 0 = shadow disabled;
Bit 6 of register 02 controls shadow RAM cacheability (1 = cacheable, 0 = non-cacheable).
*/
static void
acc2168_shadow_recalc(acc2168_t *dev)
{
if (dev->regs[0x02] & 8) {
switch (dev->regs[0x02] & 0x30) {
case 0x00:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 0x10:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x30:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
}
} else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
int state;
if (dev->regs[0x02] & 4) {
switch (dev->regs[0x02] & 0x30) {
case 0x00:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 0x10:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x30:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
}
} else
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (dev->regs[0x02] & 0x20)
state = (dev->regs[0x02] & 0x20) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_set_mem_state(0xc0000, 0x08000, (dev->regs[0x02] & 0x01) ? state : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0xc8000, 0x08000, (dev->regs[0x02] & 0x02) ? state : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0xd0000, 0x10000, (dev->regs[0x02] & 0x04) ? state : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0xe0000, 0x10000, (dev->regs[0x02] & 0x08) ? state : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0xf0000, 0x10000, (dev->regs[0x02] & 0x10) ? state : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
}

212
src/chipset/intel_4x0.c
View File

@@ -43,6 +43,8 @@ enum
INTEL_430VX,
INTEL_430TX,
INTEL_440FX,
INTEL_440LX,
INTEL_440EX,
INTEL_440BX,
INTEL_440ZX
};
@@ -94,7 +96,7 @@ i4x0_smram_handler_phase0(i4x0_t *dev)
/* Disable any active mappings. */
if (dev->type >= INTEL_430FX) {
if (dev->type >= INTEL_440BX) {
if (dev->type >= INTEL_440LX) {
/* Disable high extended SMRAM. */
/* TODO: This area should point to A0000-FFFFF. */
for (i = 0x100a0000; i < 0x100fffff; i += MEM_GRANULARITY_SIZE) {
@@ -257,7 +259,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
break;
case INTEL_430FX: case INTEL_430FX_PB640: case INTEL_430HX: case INTEL_430VX: case INTEL_430TX:
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX: case INTEL_440EX:
regs[0x04] = (regs[0x04] & ~0x02) | (val & 0x02);
break;
}
@@ -265,7 +267,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x05:
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX:
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX: case INTEL_440EX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01);
break;
@@ -278,6 +280,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x07] &= ~(val & 0x70);
break;
case INTEL_430FX: case INTEL_430FX_PB640: case INTEL_430VX: case INTEL_430TX:
case INTEL_440LX: case INTEL_440EX:
regs[0x07] &= ~(val & 0x30);
break;
case INTEL_440FX:
@@ -331,6 +334,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
case 0x34:
switch (dev->type) {
case INTEL_440LX: case INTEL_440EX:
regs[0x34] = (val & 0xa0);
}
break;
case 0x4f:
switch (dev->type) {
case INTEL_430HX:
@@ -365,6 +376,12 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x50] = (val & 0xf4);
break;
case INTEL_440LX:
regs[0x50] = (val & 0x03);
break;
case INTEL_440EX:
regs[0x50] = (val & 0x23);
break;
case INTEL_440BX:
regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
break;
@@ -382,6 +399,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x51] = (val & 0xc3);
break;
case INTEL_440LX: case INTEL_440EX:
regs[0x51] = (val & 0x80);
break;
case INTEL_440BX: case INTEL_440ZX:
regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f);
break;
@@ -400,6 +420,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x52] = val;
break;
case INTEL_440LX:
regs[0x52] = (val & 0xd0);
break;
case INTEL_440BX: case INTEL_440ZX:
regs[0x52] = val & 0x07;
break;
@@ -417,7 +440,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430TX:
regs[0x53] = val & 0x3f;
break;
case INTEL_440BX:
case INTEL_440LX:
regs[0x53] = val & 0x0a;
break;
case INTEL_440EX: case INTEL_440BX:
/* Not applicable to 440ZX as that does not support ECC. */
regs[0x53] = val;
break;
@@ -438,6 +464,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x54] = val & 0x82;
break;
case INTEL_440LX:
regs[0x54] = val;
break;
}
break;
case 0x55:
@@ -445,7 +474,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430TX:
regs[0x55] = val & 0x01;
break;
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX:
case INTEL_440EX:
regs[0x55] = val;
break;
}
@@ -461,7 +491,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430TX:
regs[0x56] = val & 0x76;
break;
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX:
case INTEL_440EX:
regs[0x56] = val;
break;
}
@@ -472,7 +503,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430LX: default:
regs[0x57] = val & 0x3f;
break;
case INTEL_430NX:
case INTEL_430NX: case INTEL_440EX:
regs[0x57] = val;
break;
case INTEL_430FX: case INTEL_430FX_PB640:
@@ -485,6 +516,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x57] = val & 0x77;
break;
case INTEL_440LX:
regs[0x57] = val & 0x11;
break;
case INTEL_440BX:
regs[0x57] = val & 0x3f;
break;
@@ -499,7 +533,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430LX: default:
regs[0x58] = val & 0x01;
break;
case INTEL_430NX:
case INTEL_430NX: case INTEL_440LX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x58] = val & 0x03;
break;
@@ -513,6 +547,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430TX:
regs[0x57] = val & 0x7b;
break;
case INTEL_440EX:
regs[0x58] = val & 0xbf;
break;
}
break;
case 0x59: /* PAM0 */
@@ -576,7 +613,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_420TX: case INTEL_420ZX:
case INTEL_430LX: case INTEL_430NX:
case INTEL_430HX:
case INTEL_440FX:
case INTEL_440FX:
case INTEL_440LX: case INTEL_440EX:
case INTEL_440BX: case INTEL_440ZX:
default:
regs[addr] = val;
@@ -596,6 +634,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430LX: case INTEL_430NX:
case INTEL_430HX:
case INTEL_440FX:
case INTEL_440LX: case INTEL_440EX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
@@ -610,7 +649,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x66:
switch (dev->type) {
case INTEL_430NX: case INTEL_430HX:
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
@@ -619,7 +659,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x67:
switch (dev->type) {
case INTEL_430NX: case INTEL_430HX:
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
@@ -640,7 +681,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430FX: case INTEL_430FX_PB640:
regs[0x68] = val & 0x1f;
break;
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX:
case INTEL_440EX:
regs[0x68] = val & 0xc0;
break;
case INTEL_440BX:
@@ -668,6 +710,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x6a: case 0x6b:
switch (dev->type) {
case INTEL_430NX:
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
regs[addr] = val;
break;
@@ -681,6 +725,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x6c: case 0x6d: case 0x6e:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
regs[addr] = val;
break;
@@ -692,6 +738,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
case 0x6f:
switch (dev->type){
case INTEL_440LX:
case INTEL_440EX:
regs[addr] = val;
break;
}
break;
case 0x70:
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX:
@@ -704,7 +758,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430TX:
regs[addr] = val & 0xfc;
break;
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX:
case INTEL_440EX:
regs[addr] = val & 0xf8;
break;
}
@@ -715,10 +770,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430LX:
regs[addr] = val & 0x4d;
break;
case INTEL_430TX:
case INTEL_430TX: case INTEL_440EX:
regs[addr] = val;
break;
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX:
regs[addr] = val & 0x1f;
break;
}
@@ -853,6 +908,12 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x80] = val & 0x1b;
break;
case INTEL_440LX:
regs[0x80] = val & 0x08;
break;
case INTEL_440EX:
regs[0x80] = val & 0x18;
break;
case INTEL_440BX: case INTEL_440ZX:
regs[0x7c] = val;
break;
@@ -861,7 +922,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x91:
switch (dev->type) {
case INTEL_430HX: case INTEL_440BX:
case INTEL_440FX:
case INTEL_440FX: case INTEL_440LX:
case INTEL_440EX:
/* Not applicable on 82443ZX. */
regs[0x91] &= ~(val & 0x11);
break;
@@ -869,6 +931,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x92:
switch (dev->type) {
case INTEL_440LX: case INTEL_440EX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x92] &= ~(val & 0x1f);
break;
@@ -877,6 +940,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x93:
switch (dev->type) {
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440EX:
regs[0x93] = (val & 0x0f);
trc_write(0x0093, val & 0x06, NULL);
break;
@@ -898,6 +963,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xb1:
switch (dev->type) {
case INTEL_440EX:
regs[0xb1] = (val & 0x22);
break;
case INTEL_440BX: case INTEL_440ZX:
regs[0xb1] = (val & 0xa0);
break;
@@ -918,7 +986,31 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
case 0xba: case 0xbb:
switch (dev->type) {
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
}
break;
case 0xbc:
switch (dev->type) {
case INTEL_440EX:
regs[addr] = (val & 0xf8);
break;
}
break;
case 0xbd:
switch (dev->type) {
case INTEL_440EX:
regs[addr] = (val & 0xf8);
break;
}
break;
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
switch (dev->type) {
case INTEL_440BX: case INTEL_440ZX:
@@ -1097,7 +1189,7 @@ i4x0_reset(void *priv)
else
i4x0_write(0, 0x72, 0x00, priv);
if ((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) {
if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) {
for (i = 0; i <= dev->max_func; i++)
memset(dev->regs_locked[i], 0x00, 256 * sizeof(uint8_t));
}
@@ -1268,6 +1360,50 @@ static void
regs[0x71] = 0x10;
regs[0x72] = 0x02;
break;
case INTEL_440LX:
dev->max_func = 1;
regs[0x02] = 0x80; regs[0x03] = 0x71; /* 82443LX */
regs[0x06] = 0x90;
regs[0x10] = 0x08;
regs[0x34] = 0xa0;
if (cpu_busspeed <= 66666667)
regs[0x51] |= 0x00;
else if ((cpu_busspeed > 66666667) && (cpu_busspeed <= 100000000))
regs[0x51] |= 0x20;
regs[0x53] = 0x83;
regs[0x57] = 0x28;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01;
regs[0x6c] = regs[0x6d] = regs[0x6e] = regs[0x6f] = 0x55;
regs[0x72] = 0x02;
regs[0xa0] = 0x02;
regs[0xa2] = 0x10;
regs[0xa4] = 0x03;
regs[0xa5] = 0x02;
regs[0xa7] = 0x1f;
break;
case INTEL_440EX:
dev->max_func = 1;
regs[0x02] = 0x80; regs[0x03] = 0x71; /* 82443EX. Same Vendor ID as 440LX*/
regs[0x06] = 0x90;
regs[0x10] = 0x08;
regs[0x34] = 0xa0;
if (cpu_busspeed <= 66666667)
regs[0x51] |= 0x00;
else if ((cpu_busspeed > 66666667) && (cpu_busspeed <= 100000000))
regs[0x51] |= 0x20;
regs[0x53] = 0x83;
regs[0x57] = 0x28;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01;
regs[0x6c] = regs[0x6d] = regs[0x6e] = regs[0x6f] = 0x55;
regs[0x72] = 0x02;
regs[0xa0] = 0x02;
regs[0xa2] = 0x10;
regs[0xa4] = 0x03;
regs[0xa5] = 0x02;
regs[0xa7] = 0x1f;
break;
case INTEL_440BX: case INTEL_440ZX:
regs[0x7a] = (info->local >> 8) & 0xff;
dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1;
@@ -1313,6 +1449,20 @@ static void
i4x0_write(regs[0x5f], 0x5f, 0x00, dev);
i4x0_write(regs[0x72], 0x72, 0x00, dev);
if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && (dev->max_func == 1)) {
regs = (uint8_t *) dev->regs[1];
regs[0x00] = 0x86; regs[0x01] = 0x80; /* Intel */
regs[0x02] = 0x81; regs[0x03] = 0x71; /* 82443LX */
regs[0x06] = 0xa0; regs[0x07] = 0x02;
regs[0x0a] = 0x04; regs[0x0b] = 0x06;
regs[0x0e] = 0x01;
regs[0x1c] = 0xf0;
regs[0x1e] = 0xa0; regs[0x1f] = 0x02;
regs[0x20] = 0xf0; regs[0x21] = 0xff;
regs[0x24] = 0xf0; regs[0x25] = 0xff;
}
if (((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) && (dev->max_func == 1)) {
regs = (uint8_t *) dev->regs[1];
@@ -1484,6 +1634,34 @@ const device_t i440fx_device =
NULL
};
const device_t i440lx_device =
{
"Intel 82443LX",
DEVICE_PCI,
INTEL_440LX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i440ex_device =
{
"Intel 82443EX",
DEVICE_PCI,
INTEL_440EX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i440bx_device =
{

125
src/chipset/opti5x7.c Normal file
View File

@@ -0,0 +1,125 @@
/*Based off the OPTI 82C546/82C547 datasheet.
The earlier 596/597 appears to be register compatible with the 546/547 from testing.*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t cur_reg,
regs[64];
port_92_t *port_92;
} opti5x7_t;
static void
opti5x7_recalcmapping(opti5x7_t *dev)
{
uint32_t shflags = 0;
shadowbios = 0;
shadowbios_write = 0;
shadowbios |= !!(dev->regs[0x06] & 0x05);
shadowbios_write |= !!(dev->regs[0x06] & 0x0a);
shflags = (dev->regs[0x06] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state(0xe0000, 0x10000, shflags);
shflags = (dev->regs[0x06] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state(0xf0000, 0x10000, shflags);
flushmmucache();
}
static void
opti5x7_write(uint16_t addr, uint8_t val, void *priv)
{
opti5x7_t *dev = (opti5x7_t *) priv;
// pclog("Write %02x to OPTi 5x7 address %02x\n", val, addr);
switch (addr) {
case 0x22:
dev->cur_reg = val;
break;
case 0x24:
dev->regs[dev->cur_reg] = val;
if (dev->cur_reg == 0x02) {
cpu_cache_ext_enabled = val & 0x10;
}
if (dev->cur_reg == 0x06) {
opti5x7_recalcmapping(dev);
}
break;
}
}
static uint8_t
opti5x7_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
opti5x7_t *dev = (opti5x7_t *) priv;
switch (addr) {
case 0x24:
// pclog("Read from OPTI 5x7 register %02x\n", dev->cur_reg);
ret = dev->regs[dev->cur_reg];
break;
}
return ret;
}
static void
opti5x7_close(void *priv)
{
opti5x7_t *dev = (opti5x7_t *) priv;
free(dev);
}
static void *
opti5x7_init(const device_t *info)
{
opti5x7_t *dev = (opti5x7_t *) malloc(sizeof(opti5x7_t));
memset(dev, 0, sizeof(opti5x7_t));
io_sethandler(0x0022, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
dev->port_92 = device_add(&port_92_device);
// pclog("OPTi 5x7 init\n");
opti5x7_recalcmapping(dev);
return dev;
}
const device_t opti5x7_device = {
"OPTi 82C5x6/82C5x7",
0,
0,
opti5x7_init, opti5x7_close, NULL,
NULL, NULL, NULL,
NULL
};

119
src/chipset/rabbit.c Normal file
View File

@@ -0,0 +1,119 @@
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t cur_reg,
regs[16];
} rabbit_t;
/*
static void
rabbit_recalcmapping(rabbit_t *dev)
{
uint32_t base;
uint32_t i, shflags = 0;
shadowbios = 0;
shadowbios_write = 0;
for (i = 0; i < 8; i++) {
base = 0xc0000 + (i << 15);
if (dev->regs[0x00] & 0x08) {
shadowbios |= (base >= 0xe0000) && (dev->regs[0x02] & 0x80);
shadowbios_write |= (base >= 0xe0000) && !(dev->regs[0x02] & 0x40);
shflags = (dev->regs[0x00] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[0x00] & 0x08) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
mem_set_mem_state(base, 0x8000, shflags);
} else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTERNAL);
}
flushmmucache();
}
*/
static void
rabbit_write(uint16_t addr, uint8_t val, void *priv)
{
rabbit_t *dev = (rabbit_t *) priv;
switch (addr) {
case 0x22:
dev->cur_reg = val;
break;
case 0x23:
dev->regs[dev->cur_reg] = val;
/*
if (dev->cur_reg == 0x00) {
rabbit_recalcmapping(dev);
}
*/
break;
}
}
static uint8_t
rabbit_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
rabbit_t *dev = (rabbit_t *) priv;
switch (addr) {
case 0x23:
ret = dev->regs[dev->cur_reg];
break;
}
return ret;
}
static void
rabbit_close(void *priv)
{
rabbit_t *dev = (rabbit_t *) priv;
free(dev);
}
static void *
rabbit_init(const device_t *info)
{
rabbit_t *dev = (rabbit_t *) malloc(sizeof(rabbit_t));
memset(dev, 0, sizeof(rabbit_t));
io_sethandler(0x0022, 0x0001, rabbit_read, NULL, NULL, rabbit_write, NULL, NULL, dev);
io_sethandler(0x0023, 0x0001, rabbit_read, NULL, NULL, rabbit_write, NULL, NULL, dev);
return dev;
}
const device_t rabbit_device = {
"SiS Rabbit",
0,
0,
rabbit_init, rabbit_close, NULL,
NULL, NULL, NULL,
NULL
};

79
src/cpu_common/cpu.c
View File

@@ -141,7 +141,7 @@ CPU *cpu_s;
int cpu_effective;
int cpu_multi;
double cpu_dmulti;
int cpu_16bitbus;
int cpu_16bitbus, cpu_64bitbus;
int cpu_busspeed;
int cpu_cyrix_alignment;
int CPUID;
@@ -309,7 +309,7 @@ cpu_set(void)
isdx4 = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP);
is_am486 = (cpu_s->cpu_type == CPU_Am486SX) || (cpu_s->cpu_type == CPU_Am486SX2) || (cpu_s->cpu_type == CPU_Am486DX) ||
(cpu_s->cpu_type == CPU_Am486DX2) || (cpu_s->cpu_type == CPU_Am486DX4) || (cpu_s->cpu_type == CPU_Am5x86);
is_pentium = (cpu_s->cpu_type == CPU_PENTIUM) || (cpu_s->cpu_type == CPU_PENTIUMMMX);
is_pentium = (cpu_s->cpu_type == CPU_P24T) || (cpu_s->cpu_type == CPU_PENTIUM) || (cpu_s->cpu_type == CPU_PENTIUMMMX);
/* Not Pentiums, but they share the same SMM save state table layout. */
is_pentium |= (cpu_s->cpu_type == CPU_i486DX2) || (cpu_s->cpu_type == CPU_iDX4);
/* The WinChip datasheet claims these are Pentium-compatible. */
@@ -335,7 +335,8 @@ cpu_set(void)
#endif
cpu_16bitbus = (cpu_s->cpu_type == CPU_286 || cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC );
cpu_64bitbus = (cpu_s->cpu_type >= CPU_WINCHIP);
if (cpu_s->multi)
cpu_busspeed = cpu_s->rspeed / cpu_s->multi;
else
@@ -995,6 +996,7 @@ cpu_set(void)
#endif
break;
case CPU_P24T:
case CPU_PENTIUM:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
@@ -1787,7 +1789,8 @@ cpu_CPUID(void)
break;
}
break;
case CPU_P24T:
case CPU_PENTIUM:
if (!EAX)
{
@@ -2414,27 +2417,31 @@ void cpu_RDMSR()
EAX = tsc & 0xffffffff;
EDX = tsc >> 32;
break;
case 0x2a:
case 0x2A:
EAX = 0xC4000000;
EDX = 0;
if (cpu_dmulti == 3)
EAX = ((0 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
EAX |= ((0 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
else if (cpu_dmulti == 3.5)
EAX = ((0 << 25) | (1 << 24) | (0 << 23) | (1 << 22));
EAX |= ((0 << 25) | (1 << 24) | (0 << 23) | (1 << 22));
else if (cpu_dmulti == 4)
EAX = ((0 << 25) | (0 << 24) | (1 << 23) | (0 << 22));
EAX |= ((0 << 25) | (0 << 24) | (1 << 23) | (0 << 22));
else if (cpu_dmulti == 4.5)
EAX = ((0 << 25) | (1 << 24) | (1 << 23) | (0 << 22));
EAX |= ((0 << 25) | (1 << 24) | (1 << 23) | (0 << 22));
else if (cpu_dmulti == 5)
EAX = 0;
EAX |= 0;
else if (cpu_dmulti == 5.5)
EAX = ((0 << 25) | (1 << 24) | (0 << 23) | (0 << 22));
EAX |= ((0 << 25) | (1 << 24) | (0 << 23) | (0 << 22));
else if (cpu_dmulti == 6)
EAX = ((1 << 25) | (0 << 24) | (1 << 23) | (1 << 22));
EAX |= ((1 << 25) | (0 << 24) | (1 << 23) | (1 << 22));
else if (cpu_dmulti == 6.5)
EAX = ((1 << 25) | (1 << 24) | (1 << 23) | (1 << 22));
EAX |= ((1 << 25) | (1 << 24) | (1 << 23) | (1 << 22));
else if (cpu_dmulti == 7)
EAX = ((1 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
EAX |= ((1 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
else
EAX = ((0 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
EAX |= ((0 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
if (cpu_busspeed >= 84000000)
EAX |= (1 << 19);
break;
case 0x1107:
EAX = msr.fcr;
@@ -2693,6 +2700,7 @@ void cpu_RDMSR()
}
break;
case CPU_P24T:
case CPU_PENTIUM:
case CPU_PENTIUMMMX:
EAX = EDX = 0;
@@ -2740,8 +2748,38 @@ void cpu_RDMSR()
/* pclog("APIC_BASE read : %08X%08X\n", EDX, EAX); */
break;
case 0x2A:
EAX = 0xC5800000;
EDX = 0;
EAX = 0xC4000000;
EDX = 0;
if (cpu_dmulti == 2.5)
EAX |= ((0 << 25) | (1 << 24) | (1 << 23) | (1 << 22));
else if (cpu_dmulti == 3)
EAX |= ((0 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
else if (cpu_dmulti == 3.5)
EAX |= ((0 << 25) | (1 << 24) | (0 << 23) | (1 << 22));
else if (cpu_dmulti == 4)
EAX |= ((0 << 25) | (0 << 24) | (1 << 23) | (0 << 22));
else if (cpu_dmulti == 4.5)
EAX |= ((0 << 25) | (1 << 24) | (1 << 23) | (0 << 22));
else if (cpu_dmulti == 5)
EAX |= 0;
else if (cpu_dmulti == 5.5)
EAX |= ((0 << 25) | (1 << 24) | (0 << 23) | (0 << 22));
else if (cpu_dmulti == 6)
EAX |= ((1 << 25) | (0 << 24) | (1 << 23) | (1 << 22));
else if (cpu_dmulti == 6.5)
EAX |= ((1 << 25) | (1 << 24) | (1 << 23) | (1 << 22));
else if (cpu_dmulti == 7)
EAX |= ((1 << 25) | (0 << 24) | (0 << 23) | (1 << 22));
else if (cpu_dmulti == 7.5)
EAX |= ((1 << 25) | (1 << 24) | (0 << 23) | (1 << 22));
else if (cpu_dmulti == 8)
EAX |= ((1 << 25) | (0 << 24) | (1 << 23) | (0 << 22));
else
EAX |= ((0 << 25) | (1 << 24) | (1 << 23) | (1 << 22));
if (machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpu_type != CPU_PENTIUMPRO) {
if (cpu_busspeed >= 84000000)
EAX |= (1 << 19);
}
break;
case 0x79:
EAX = ecx79_msr & 0xffffffff;
@@ -3154,7 +3192,8 @@ void cpu_WRMSR()
break;
}
break;
case CPU_P24T:
case CPU_PENTIUM:
case CPU_PENTIUMMMX:
switch (ECX)
@@ -3163,8 +3202,8 @@ void cpu_WRMSR()
tsc = EAX | ((uint64_t)EDX << 32);
break;
case 0x8B:
cpu_log("WRMSR: Invalid MSR: 0x8B/n"); /*Needed for Vista to correctly break on Pentium*/
x86gpf(NULL, 0);
cpu_log("WRMSR: Invalid MSR: 0x8B\n");
x86gpf(NULL, 0); /*Needed for Vista to correctly break on Pentium*/
break;
}
break;

9
src/cpu_common/cpu.h
View File

@@ -52,6 +52,7 @@ enum {
CPU_Cx486DX4,
CPU_Am5x86,
CPU_Cx5x86,
CPU_P24T,
CPU_WINCHIP, /* 586 class CPUs */
CPU_WINCHIP2,
CPU_PENTIUM,
@@ -145,7 +146,7 @@ extern CPU cpus_6x86SS7[];
#endif
extern CPU cpus_Cyrix3[];
extern CPU cpus_PentiumPro[];
extern CPU cpus_PentiumII_28v[];
extern CPU cpus_PentiumII66[];
extern CPU cpus_PentiumII[];
extern CPU cpus_Xeon[];
extern CPU cpus_Celeron[];
@@ -370,7 +371,7 @@ COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128)
/* Global variables. */
extern int cpu_iscyrix;
extern int cpu_16bitbus;
extern int cpu_16bitbus, cpu_64bitbus;
extern int cpu_busspeed, cpu_pci_speed;
extern int cpu_multi;
extern double cpu_dmulti;
@@ -379,8 +380,8 @@ extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4;
extern int is_am486, is_pentium, is_k5, is_k6, is_p6;
extern int hascache;
extern int isibm486;
extern int hascache;
extern int isibm486;
extern int is_rapidcad;
extern int hasfpu;
#define CPU_FEATURE_RDTSC (1 << 0)

16
src/cpu_common/cpu_table.c
View File

@@ -288,8 +288,8 @@ CPU cpus_i486[] = {
{"iDX4/100", CPU_iDX4, 100000000, 3.0, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3.0, 0x1480, 0x1480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3.0, 0x1480, 0x1480, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12},
{"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 2.5, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 2.5, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"Pentium OverDrive 63", CPU_P24T, 62500000, 2.5, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"Pentium OverDrive 83", CPU_P24T, 83333333, 2.5, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"", -1, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0, 0}
};
@@ -686,7 +686,8 @@ CPU cpus_PentiumPro[] = {
{"Pentium II Overdrive 333", CPU_PENTIUM2D, 333333333, 5.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_PentiumII_28v[] = {
CPU cpus_PentiumII66[] = {
/*Intel Pentium II Klamath*/
{"Pentium II Klamath 50", CPU_PENTIUM2, 50000000, 1.0, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium II Klamath 60", CPU_PENTIUM2, 60000000, 1.0, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
@@ -695,6 +696,15 @@ CPU cpus_PentiumII_28v[] = {
{"Pentium II Klamath 233", CPU_PENTIUM2, 233333333, 3.5, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"Pentium II Klamath 266", CPU_PENTIUM2, 266666666, 4.0, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
{"Pentium II Klamath 300/66", CPU_PENTIUM2, 300000000, 4.5, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
/*Intel Pentium II Deschutes*/
{"Pentium II Deschutes 50", CPU_PENTIUM2D, 50000000, 1.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium II Deschutes 60", CPU_PENTIUM2D, 60000000, 1.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"Pentium II Deschutes 66", CPU_PENTIUM2D, 66666666, 1.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Pentium II Deschutes 75", CPU_PENTIUM2D, 75000000, 1.5, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium II Deschutes 266", CPU_PENTIUM2D, 266666666, 4.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
{"Pentium II Deschutes 300/66", CPU_PENTIUM2D, 300000000, 4.5, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
{"Pentium II Deschutes 333", CPU_PENTIUM2D, 333333333, 5.0, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};

42
src/disk/hdc_esdi_at.c
View File

@@ -528,14 +528,8 @@ esdi_callback(void *priv)
irq_raise(esdi);
break;
}
if (hdd_image_read_ex(drive->hdd_num, addr, 1, (uint8_t *)esdi->buffer)) {
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(esdi);
break;
}
hdd_image_read(drive->hdd_num, addr, 1, (uint8_t *)esdi->buffer);
esdi->pos = 0;
esdi->status = STAT_DRQ|STAT_READY|STAT_DSC;
irq_raise(esdi);
@@ -556,14 +550,8 @@ esdi_callback(void *priv)
irq_raise(esdi);
break;
}
if (hdd_image_write_ex(drive->hdd_num, addr, 1, (uint8_t *)esdi->buffer)) {
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(esdi);
break;
}
hdd_image_write(drive->hdd_num, addr, 1, (uint8_t *)esdi->buffer);
irq_raise(esdi);
esdi->secount = (esdi->secount - 1) & 0xff;
if (esdi->secount) {
@@ -590,13 +578,7 @@ esdi_callback(void *priv)
break;
}
if (hdd_image_read_ex(drive->hdd_num, addr, 1, (uint8_t *)esdi->buffer)) {
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(esdi);
break;
}
hdd_image_read(drive->hdd_num, addr, 1, (uint8_t *)esdi->buffer);
ui_sb_update_icon(SB_HDD|HDD_BUS_ESDI, 1);
next_sector(esdi);
esdi->secount = (esdi->secount - 1) & 0xff;
@@ -623,14 +605,8 @@ esdi_callback(void *priv)
irq_raise(esdi);
break;
}
if (hdd_image_zero_ex(drive->hdd_num, addr, esdi->secount)) {
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(esdi);
break;
}
hdd_image_zero(drive->hdd_num, addr, esdi->secount);
esdi->status = STAT_READY|STAT_DSC;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD|HDD_BUS_ESDI, 1);
@@ -829,8 +805,8 @@ wd1007vse1_init(const device_t *info)
esdi_read, esdi_readw, NULL,
esdi_write, esdi_writew, NULL, esdi);
io_sethandler(0x01f1, 7,
esdi_read, NULL, NULL,
esdi_write, NULL, NULL, esdi);
esdi_read, esdi_readw, NULL,
esdi_write, esdi_writew, NULL, esdi);
io_sethandler(0x03f6, 1, NULL, NULL, NULL,
esdi_write, NULL, NULL, esdi);

34
src/disk/hdc_ide.c
View File

@@ -182,67 +182,67 @@ ide_get_period(ide_t *ide, int size)
switch(ide->mdma_mode & 0x300) {
case 0x000: /* PIO */
switch(ide->mdma_mode & 0xff) {
case 0:
case 0x01:
period = (10.0 / 3.0);
break;
case 1:
case 0x02:
period = (20.0 / 3.83);
break;
case 2:
case 0x04:
period = (25.0 / 3.0);
break;
case 3:
case 0x08:
period = (100.0 / 9.0);
break;
case 4:
case 0x10:
period = (50.0 / 3.0);
break;
}
break;
case 0x100: /* Single Word DMA */
switch(ide->mdma_mode & 0xff) {
case 0:
case 0x01:
period = (25.0 / 12.0);
break;
case 1:
case 0x02:
period = (25.0 / 6.0);
break;
case 2:
case 0x04:
period = (25.0 / 3.0);
break;
}
break;
case 0x200: /* Multiword DMA */
switch(ide->mdma_mode & 0xff) {
case 0:
case 0x01:
period = (25.0 / 6.0);
break;
case 1:
case 0x02:
period = (40.0 / 3.0);
break;
case 2:
case 0x04:
period = (50.0 / 3.0);
break;
}
break;
case 0x300: /* Ultra DMA */
switch(ide->mdma_mode & 0xff) {
case 0:
case 0x01:
period = (50.0 / 3.0);
break;
case 1:
case 0x02:
period = 25.0;
break;
case 2:
case 0x04:
period = (100.0 / 3.0);
break;
case 3:
case 0x08:
period = (400.0 / 9.0);
break;
case 4:
case 0x10:
period = (200.0 / 3.0);
break;
case 5:
case 0x20:
period = 100.0;
break;
}

4
src/hwm_lm75.c
View File

@@ -128,7 +128,7 @@ lm75_read(lm75_t *dev, uint8_t reg)
/* The AS99127F hardware monitor uses the addresses of its LM75 devices
to access some of its proprietary registers. Pass this operation on to
the main monitor address through an internal SMBus call, if necessary. */
if ((reg >= 0x80) && (dev->as99127f_smbus_addr))
if ((reg > 0x7) && ((reg & 0xf8) != 0x50) && (dev->as99127f_smbus_addr))
ret = smbus_read_byte_cmd(dev->as99127f_smbus_addr, reg);
else
ret = dev->regs[reg & 0x7];
@@ -191,7 +191,7 @@ lm75_write(lm75_t *dev, uint8_t reg, uint8_t val)
/* The AS99127F hardware monitor uses the addresses of its LM75 devices
to access some of its proprietary registers. Pass this operation on to
the main monitor address through an internal SMBus call, if necessary. */
if ((reg >= 0x80) && (dev->as99127f_smbus_addr)) {
if ((reg > 0x7) && ((reg & 0xf8) != 0x50) && (dev->as99127f_smbus_addr)) {
smbus_write_byte_cmd(dev->as99127f_smbus_addr, reg, val);
return 1;
}

12
src/hwm_lm78.c
View File

@@ -180,11 +180,11 @@ lm78_read(lm78_t *dev, uint8_t reg, uint8_t bank)
uint8_t ret = 0;
lm75_t *lm75;
if (((reg >> 4) == 0x5) && (bank != 0)) {
if (((reg & 0xf8) == 0x50) && (bank != 0)) {
/* LM75 registers */
lm75 = device_get_priv(dev->lm75[bank - 1]);
if (lm75)
ret = lm75_read(lm75, reg & 0x7);
ret = lm75_read(lm75, reg);
} else {
/* regular registers */
if ((reg == 0x4f) && (dev->local & LM78_WINBOND)) /* special case for two-byte vendor ID register */
@@ -192,7 +192,7 @@ lm78_read(lm78_t *dev, uint8_t reg, uint8_t bank)
else if ((reg >= 0x60) && (reg <= 0x7f)) /* read auto-increment value RAM registers from their non-auto-increment locations */
ret = dev->regs[reg & 0x3f];
else if ((reg >= 0x80) && (reg <= 0x92)) /* AS99127F mirrors [0x00:0x12] to [0x80:0x92] */
ret = dev->regs[reg - 0x7f];
ret = dev->regs[reg & 0x7f];
else
ret = dev->regs[reg];
}
@@ -260,11 +260,11 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
lm78_log("LM78: write(%02X, %d, %02X)\n", reg, bank, val);
if (((reg >> 4) == 0x5) && (bank != 0)) {
if (((reg & 0xf8) == 0x50) && (bank != 0)) {
/* LM75 registers */
lm75 = device_get_priv(dev->lm75[bank - 1]);
if (lm75)
lm75_write(lm75, reg & 0x7, val);
lm75_write(lm75, reg, val);
return 1;
}
@@ -325,6 +325,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
if (dev->local & LM78_SMBUS) {
for (uint8_t i = 0; i <= 1; i++) {
lm75 = device_get_priv(dev->lm75[i]);
if (!lm75)
continue;
if (dev->regs[0x4a] & (0x08 * (0x10 * i))) /* DIS_T2 and DIS_T3 bit disable those interfaces */
lm75->smbus_addr = 0x00;
else

1
src/include/86box/86box.h
View File

@@ -171,7 +171,6 @@ extern void pc_close(void *threadid);
extern void pc_reset_hard_close(void);
extern void pc_reset_hard_init(void);
extern void pc_reset_hard(void);
extern void pc_reset(int hard);
extern void pc_full_speed(void);
extern void pc_speed_changed(void);
extern void pc_send_cad(void);

4
src/include/86box/chipset.h
View File

@@ -42,11 +42,14 @@ extern const device_t i430hx_device;
extern const device_t i430vx_device;
extern const device_t i430tx_device;
extern const device_t i440fx_device;
extern const device_t i440lx_device;
extern const device_t i440ex_device;
extern const device_t i440bx_device;
extern const device_t i440zx_device;
/* OPTi */
extern const device_t opti495_device;
extern const device_t opti5x7_device;
/* C&T */
extern const device_t neat_device;
@@ -56,6 +59,7 @@ extern const device_t scat_sx_device;
extern const device_t cs8230_device;
/* SiS */
extern const device_t rabbit_device;
extern const device_t sis_85c471_device;
extern const device_t sis_85c496_device;
#if defined(DEV_BRANCH) && defined(USE_SIS_85C50X)

33
src/include/86box/machine.h
View File

@@ -216,6 +216,7 @@ extern const device_t *at_commodore_sl386sx_get_device(void);
/* m_at_386dx_486.c */
extern int machine_at_acc386_init(const machine_t *);
extern int machine_at_asus386_init(const machine_t *);
extern int machine_at_ecs386_init(const machine_t *);
extern int machine_at_micronics386_init(const machine_t *);
@@ -255,6 +256,8 @@ extern const device_t *at_cpqiii_get_device(void);
#endif
/* m_at_socket4_5.c */
extern int machine_at_excalibur_init(const machine_t *);
extern int machine_at_batman_init(const machine_t *);
extern int machine_at_ambradp60_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_VPP60)
@@ -300,25 +303,18 @@ extern int machine_at_p55tvp4_init(const machine_t *);
extern int machine_at_p55va_init(const machine_t *);
extern int machine_at_i430vx_init(const machine_t *);
extern int machine_at_brio80xx_init(const machine_t *);
extern int machine_at_8500tvxa_init(const machine_t *);
extern int machine_at_pb680_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern int machine_at_p55xb2_init(const machine_t *);
#endif
extern int machine_at_nupro592_init(const machine_t *);
extern int machine_at_tx97_init(const machine_t *);
extern int machine_at_ym430tx_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern int machine_at_586t2_init(const machine_t *);
extern int machine_at_807ds_init(const machine_t *);
#endif
extern int machine_at_mb540n_init(const machine_t *);
extern int machine_at_p5mms98_init(const machine_t *);
extern int machine_at_ficva502_init(const machine_t *);
extern int machine_at_ficpa2012_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern int machine_at_advanceii_init(const machine_t *);
#endif
#ifdef EMU_DEVICE_H
extern const device_t *at_pb640_get_device(void);
@@ -340,28 +336,33 @@ extern int machine_at_p65up5_cp6nd_init(const machine_t *);
/* m_at_slot1.c */
extern int machine_at_p65up5_cpknd_init(const machine_t *);
extern int machine_at_p6kfx_init(const machine_t *);
extern int machine_at_kn97_init(const machine_t *);
extern int machine_at_p6i440e2_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern int machine_at_6bxc_init(const machine_t *);
#endif
extern int machine_at_p2bls_init(const machine_t *);
extern int machine_at_p3bf_init(const machine_t *);
extern int machine_at_bf6_init(const machine_t *);
extern int machine_at_atc6310bxii_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern int machine_at_tsunamiatx_init(const machine_t *);
#endif
extern int machine_at_p6sba_init(const machine_t *);
#ifdef EMU_DEVICE_H
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern const device_t *at_tsunamiatx_get_device(void);
#endif
#endif
/* m_at_slot2.c */
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern int machine_at_s2dge_init(const machine_t *);
#endif
/* m_at_socket370.c */
#if defined(DEV_BRANCH) && defined(NO_SIO)
extern int machine_at_s370slm_init(const machine_t *);
#endif
extern int machine_at_cubx_init(const machine_t *);
extern int machine_at_atc7020bxii_init(const machine_t *);
extern int machine_at_63a_init(const machine_t *);

4
src/include/86box/pci.h
View File

@@ -51,6 +51,7 @@ enum {
PCI_CARD_NORMAL,
PCI_CARD_ONBOARD,
PCI_CARD_SCSI,
PCI_CARD_SOUND,
PCI_CARD_SPECIAL
};
@@ -59,7 +60,8 @@ enum {
PCI_ADD_SOUTHBRIDGE,
PCI_ADD_NORMAL,
PCI_ADD_VIDEO,
PCI_ADD_SCSI
PCI_ADD_SCSI,
PCI_ADD_SOUND
};
typedef union {

7
src/include/86box/sound.h
View File

@@ -28,6 +28,12 @@ extern int sound_gain;
#define CD_BUFLEN (CD_FREQ / 10)
enum {
SOUND_NONE = 0,
SOUND_INTERNAL
};
extern int ppispeakon;
extern int gated,
speakval,
@@ -79,6 +85,7 @@ extern const device_t azt1605_device;
/* Ensoniq AudioPCI */
extern const device_t es1371_device;
extern const device_t es1371_onboard_device;
/* Creative Labs Game Blaster */
extern const device_t cms_device;

19
src/machine/m_at_386dx_486.c
View File

@@ -63,6 +63,25 @@ machine_at_acc386_init(const machine_t *model)
return ret;
}
int
machine_at_asus386_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/asus386/ASUS_ISA-386C_BIOS.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&rabbit_device);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
return ret;
}
int
machine_at_ecs386_init(const machine_t *model)
{

150
src/machine/m_at_slot1.c
View File

@@ -40,6 +40,7 @@
#include <86box/video.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/sound.h>
int
machine_at_p65up5_cpknd_init(const machine_t *model)
@@ -58,11 +59,11 @@ machine_at_p65up5_cpknd_init(const machine_t *model)
}
int
machine_at_p6kfx_init(const machine_t *model)
machine_at_kn97_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p6kfx/kfxa22.bin",
ret = bios_load_linear(L"roms/machines/kn97/0116I.001",
0x000e0000, 131072, 0);
if (bios_only || !ret)
@@ -72,29 +73,48 @@ machine_at_p6kfx_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device); /*Didn't post with regular PS/2 PCI*/
device_add(&keyboard_ps2_pci_device);
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
hwm_values_t machine_hwm = {
{ /* fan speeds (incorrect divisor for some reason) */
6000, /* Chassis */
6000, /* CPU */
6000 /* Power */
}, { /* temperatures */
30 /* MB */
}, { /* voltages */
2800, /* VCORE (2.8V by default) */
0, /* unused */
3300, /* +3.3V */
RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */
RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */
RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */
RESISTOR_DIVIDER(5000, 1, 2) /* -5V (divider values bruteforced) */
}
};
hwm_set_values(machine_hwm);
device_add(&lm78_device);
return ret;
}
#if defined(DEV_BRANCH) && defined(NO_SIO)
int
machine_at_6bxc_init(const machine_t *model)
machine_at_p6i440e2_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/6bxc/powleap.bin",
0x000c0000, 262144, 0);
ret = bios_load_linear(L"roms/machines/p6i440e2/E2_v14sl.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
@@ -103,22 +123,43 @@ machine_at_6bxc_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&i440ex_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
device_add(&um8669f_device); /*ITE 8671*/
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
device_add(&w83977tf_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x03, 256);
hwm_values_t machine_hwm = {
{ /* fan speeds */
3000, /* Chassis */
3000, /* CPU */
3000 /* Power */
}, { /* temperatures */
30, /* MB */
0, /* unused */
27 /* CPU */
}, { /* voltages */
2050, /* VCORE (2.05V by default) */
0, /* unused */
3300, /* +3.3V */
RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */
RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */
RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */
RESISTOR_DIVIDER(5000, 1, 2) /* -5V (divider values bruteforced) */
}
};
if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2)
machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */
hwm_set_values(machine_hwm);
device_add(&w83781d_device);
return ret;
}
#endif
int
machine_at_p2bls_init(const machine_t *model)
@@ -236,6 +277,8 @@ machine_at_p3bf_init(const machine_t *model)
};
if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2)
machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */
else if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_CYRIX3S)
machine_hwm.voltages[0] = 2800; /* P3B-F specific issue: it believes the Cyrix III is a Klamath, and therefore expects a toasty 2.8V */
hwm_set_values(machine_hwm);
device_add(&as99127f_device);
@@ -276,6 +319,38 @@ machine_at_bf6_init(const machine_t *model)
return ret;
}
int
machine_at_atc6310bxii_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/atc6310bxii/6310s102.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&slc90e66_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83977ef_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
int
machine_at_p6sba_init(const machine_t *model)
{
@@ -343,9 +418,9 @@ machine_at_p6sba_init(const machine_t *model)
int
machine_at_tsunamiatx_init(const machine_t *model)
{
//AMI 440BX Board. Requires the PC87309 and
//doesn't like the i686 CPU's
/* AMI 440BX board. Requires the PC87309
and doesn't like the i686 CPUs */
int ret;
ret = bios_load_linear(L"roms/machines/tsunamiatx/bx46200f.rom",
@@ -358,20 +433,31 @@ machine_at_tsunamiatx_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_SOUND, 1, 0, 0, 0);
pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&pc87306_device); //PC87309
if (sound_card_current == SOUND_INTERNAL)
device_add(&es1371_onboard_device);
device_add(&pc87306_device); /* PC87309 */
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
#endif
const device_t *
at_tsunamiatx_get_device(void)
{
return &es1371_onboard_device;
}
#endif

4
src/machine/m_at_socket370.c
View File

@@ -41,7 +41,6 @@
#include "cpu.h"
#include <86box/machine.h>
#if defined(DEV_BRANCH) && defined(NO_SIO)
int
machine_at_s370slm_init(const machine_t *model)
{
@@ -65,7 +64,7 @@ machine_at_s370slm_init(const machine_t *model)
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440bx_device); /*i440LX*/
device_add(&i440lx_device);
device_add(&piix4e_device);
device_add(&w83977tf_device);
device_add(&keyboard_ps2_ami_pci_device);
@@ -96,7 +95,6 @@ machine_at_s370slm_init(const machine_t *model)
return ret;
}
#endif
int
machine_at_cubx_init(const machine_t *model)

20
src/machine/m_at_socket4_5.c
View File

@@ -41,6 +41,26 @@
#include <86box/sio.h>
#include <86box/video.h>
#include <86box/machine.h>
int
machine_at_excalibur_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted(L"roms/machines/excalibur/S75P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_vlb_device);
device_add(&opti5x7_device);
device_add(&fdc37c663_device);
device_add(&keyboard_at_ami_device);
return ret;
}
static void

164
src/machine/m_at_socket7_s7.c
View File

@@ -586,6 +586,35 @@ machine_at_brio80xx_init(const machine_t *model)
return ret;
}
int
machine_at_8500tvxa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/8500tvxa/tvx0619b.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 3, 2, 1);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&um8669f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_pb680_init(const machine_t *model)
{
@@ -619,14 +648,14 @@ machine_at_pb680_init(const machine_t *model)
return ret;
}
#if defined(DEV_BRANCH) && defined(NO_SIO)
int
machine_at_p55xb2_init(const machine_t *model)
machine_at_nupro592_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p55xb2/XB20721.BIN",
0x000e0000, 131072, 0);
ret = bios_load_linear(L"roms/machines/nupro592/np590b10.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
@@ -635,21 +664,57 @@ machine_at_p55xb2_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2); /*Strongly suspect these are on-board slots*/
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4); /* PIIX4 */
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
// device_add(&ali_m513x_device);
device_add(&w83977ef_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
hwm_values_t machine_hwm = {
{ /* fan speeds */
3000, /* Chassis */
3000, /* CPU */
3000, /* Power */
0
}, { /* temperatures */
30, /* MB */
0, /* unused */
27, /* CPU */
0
}, { /* voltages */
3300, /* VCORE (3.3V by default) */
0, /* unused */
3300, /* +3.3V */
RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */
RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */
RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */
RESISTOR_DIVIDER(5000, 1, 2), /* -5V (divider values bruteforced) */
0
}
};
/* Pentium, Pentium OverDrive MMX, Pentium Mobile MMX: 3.3V (real Pentium Mobile MMX is 2.45V).
Pentium MMX: 2.8 V.
AMD K6 Model 6: 2.9 V for 166/200, 3.2 V for 233.
AMD K6 Model 7: 2.2 V. */
if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUMMMX)
machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Pentium MMX */
else if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_K6)
machine_hwm.voltages[0] = 2200; /* set higher VCORE (2.8V) for Pentium MMX */
else if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_K6_2)
machine_hwm.voltages[0] = 2200; /* set higher VCORE (2.8V) for Pentium MMX */
hwm_set_values(machine_hwm);
device_add(&w83781d_device);
return ret;
}
#endif
int
machine_at_tx97_init(const machine_t *model)
@@ -751,13 +816,12 @@ machine_at_ym430tx_init(const machine_t *model)
return ret;
}
#if defined(DEV_BRANCH) && defined(NO_SIO)
int
machine_at_586t2_init(const machine_t *model)
machine_at_mb540n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/586t2/5itw001.bin",
ret = bios_load_linear(L"roms/machines/mb540n/Tx0720ug.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
@@ -767,53 +831,21 @@ machine_at_586t2_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
device_add(&um8669f_device); /*Placeholder for ITE 8679*/
device_add(&um8669f_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
int
machine_at_807ds_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/807ds/Tx0212g.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&um8669f_device); /*Placeholder for ITE 8679*/
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
#endif
int
machine_at_p5mms98_init(const machine_t *model)
{
@@ -936,33 +968,3 @@ machine_at_ficpa2012_init(const machine_t *model)
return ret;
}
#if defined(DEV_BRANCH) && defined(NO_SIO)
int
machine_at_advanceii_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/advanceii/VP3_V27.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
device_add(&via_vp3_device);
device_add(&via_vt82c586b_device);
device_add(&keyboard_ps2_pci_device);
device_add(&um8669f_device); //IT8661F
device_add(&sst_flash_39sf010_device);
return ret;
}
#endif

45
src/machine/machine_table.c
View File

@@ -160,6 +160,7 @@ const machine_t machines[] = {
/* 386DX machines */
{ "[386DX ISA] Compaq Portable III (386)", "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_portableiii386_init, at_cpqiii_get_device },
{ "[386DX ISA] AMI 386DX clone", "acc386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 16384, 128, 127, machine_at_acc386_init, NULL },
{ "[386DX ISA] ASUS 386DX ISA", "asus386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 16384, 128, 127, machine_at_asus386_init, NULL },
{ "[386DX ISA] ECS 386/32", "ecs386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 32, 1, 127, machine_at_ecs386_init, NULL },
{ "[386DX ISA] Micronics 386 clone", "micronics386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_micronics386_init, NULL },
@@ -206,6 +207,9 @@ const machine_t machines[] = {
{ "[486 PCI] Zida Tomato 4DP", "4dps", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 127, machine_at_4dps_init, NULL },
/* Socket 4 machines */
/* OPTi 596/597 */
{ "[Socket 4 OPTi] AMI Excalibur VLB", "excalibur", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_excalibur_init, NULL },
/* 430LX */
{ "[Socket 4 LX] IBM Ambra DP60 PCI", "ambradp60", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_ambradp60_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_VPP60)
@@ -254,18 +258,14 @@ const machine_t machines[] = {
{ "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
{ "[Socket 7 VX] Epox P55-VA", "p55va", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL },
{ "[Socket 7 VX] HP Brio 80xx", "brio80xx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_brio80xx_init, NULL },
{ "[Socket 7 VX] Biostar 8500TVX-A", "8500tvxa", {{ "Intel", cpus_Pentium}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_8500tvxa_init, NULL },
{ "[Socket 7 VX] Packard Bell PB680", "pb680", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_pb680_init, NULL },
/* 430TX */
{ "[Socket 7 TX] ADLink NuPRO-592", "nupro592", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_nupro592_init, NULL },
{ "[Socket 7 TX] ASUS TX97", "tx97", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_tx97_init, NULL },
#if defined(DEV_BRANCH) && defined(NO_SIO)
{ "[Socket 7 TX] Gigabyte GA-586T2", "586t2", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_586t2_init, NULL },
#endif
{ "[Socket 7 TX] Intel YM430TX", "ym430tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_ym430tx_init, NULL },
#if defined(DEV_BRANCH) && defined(NO_SIO)
{ "[Socket 7 TX] Iwill P55XB2", "p55xb2", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_p55xb2_init, NULL },
{ "[Socket 7 TX] PC Partner TXA807DS", "807ds", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_807ds_init, NULL },
#endif
{ "[Socket 7 TX] PC Partner MB540N", "mb540n", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_mb540n_init, NULL },
{ "[Socket 7 TX] Supermicro P5MMS98", "p5mms98", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_p5mms98_init, NULL },
@@ -274,9 +274,6 @@ const machine_t machines[] = {
/* Apollo VP3 */
{ "[Socket 7 VP3] FIC PA-2012", "ficpa2012", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_ficpa2012_init, NULL },
#if defined(DEV_BRANCH) && defined(NO_SIO)
{ "[Socket 7 VP3] QDI Advance II", "advanceii", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_advanceii_init, NULL },
#endif
/* Super Socket 7 machines */
/* Apollo MVP3 */
@@ -285,8 +282,8 @@ const machine_t machines[] = {
/* Socket 8 machines */
/* 440FX */
{ "[Socket 8 FX] Gigabyte GA-686NX", "686nx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_686nx_init, NULL },
{ "[Socket 8 FX] PC Partner MB600N", "mb600n", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_mb600n_init, NULL },
{ "[Socket 8 FX] Gigabyte GA-686NX", "686nx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 127, machine_at_686nx_init, NULL },
{ "[Socket 8 FX] PC Partner MB600N", "mb600n", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 127, machine_at_mb600n_init, NULL },
{ "[Socket 8 FX] Biostar MB-8500ttc", "8500ttc", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_8500ttc_init, NULL },
{ "[Socket 8 FX] Micronics M6MI", "m6mi", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 384, 8, 127, machine_at_m6mi_init, NULL },
{ "[Socket 8 FX] ASUS P/I-P65UP5 (C-P6ND)", "p65up5_cp6nd", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p65up5_cp6nd_init, NULL },
@@ -294,42 +291,40 @@ const machine_t machines[] = {
/* Slot 1 machines */
/* 440FX */
{ "[Slot 1 FX] ASUS P/I-P65UP5 (C-PKND)", "p65up5_cpknd", {{"Intel", cpus_PentiumII_28v},{"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p65up5_cpknd_init, NULL },
{ "[Slot 1 FX] ECS P6KFX-A", "p6kfx", {{"Intel", cpus_PentiumII_28v},{"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 384, 8, 127, machine_at_p6kfx_init, NULL },
{ "[Slot 1 FX] ASUS P/I-P65UP5 (C-PKND)", "p65up5_cpknd", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p65up5_cpknd_init, NULL },
{ "[Slot 1 FX] ASUS KN97", "kn97", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 384, 8, 127, machine_at_kn97_init, NULL },
/* 440LX */
/* 440EX */
{ "[Slot 1 EX] QDI EXCELLENT II", "p6i440e2", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_p6i440e2_init, NULL },
/* 440BX */
#if defined(DEV_BRANCH) && defined(NO_SIO)
{ "[Slot 1 BX] Gigabyte GA-6BXC", "6bxc", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_6bxc_init, NULL },
#endif
{ "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
{ "[Slot 1 BX] ASUS P2B-LS (coreboot BIOS)","p2bls_cb", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"", NULL}, {"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_COREBOOT, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
{ "[Slot 1 BX] ASUS P3B-F", "p3bf", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p3bf_init, NULL },
{ "[Slot 1 BX] ASUS P3B-F (coreboot BIOS)", "p3bf_cb", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"", NULL}, {"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_COREBOOT, 8, 1024, 8, 255, machine_at_p3bf_init, NULL },
{ "[Slot 1 BX] ABit BF6", "bf6", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_bf6_init, NULL },
{ "[Slot 1 BX] A-Trend ATC6310BXII", "atc6310bxii", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_atc6310bxii_init, NULL },
#if defined(DEV_BRANCH) && defined(NO_SIO)
{ "[Slot 1 BX] Tyan Tsunami ATX", "tsunamiatx", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_tsunamiatx_init, NULL },
{ "[Slot 1 BX] Tyan Tsunami ATX", "tsunamiatx", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_SOUND, 8, 1024, 8, 255, machine_at_tsunamiatx_init, at_tsunamiatx_get_device },
#endif
{ "[Slot 1 BX] Supermicro P6SBA", "p6sba", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_p6sba_init, NULL },
/* Slot 2 machines */
/* 440GX */
/* Slot 2 machines */
/* 440GX */
#if defined(DEV_BRANCH) && defined(NO_SIO)
{ "[Slot 2 GX] Supermicro S2DGE", "s2dge", {{"Intel", cpus_Xeon}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_s2dge_init, NULL },
#endif
/* PGA370 machines */
/* 440LX */
#if defined(DEV_BRANCH) && defined(NO_SIO)
/* 440LX */
{ "[Socket 370 LX] Supermicro 370SLM", "s370slm", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_s370slm_init, NULL },
#endif
/* 440BX */
{ "[Socket 370 BX] ASUS CUBX", "cubx", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_cubx_init, NULL },
{ "[Socket 370 BX] A-Trend ATC7020BXII", "atc7020bxii", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_atc7020bxii_init, NULL },
/* 440ZX */
{ "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL },
{ "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL },
/* VIA Apollo Pro */
{ "[Socket 370 APRO] PC Partner APAS3", "apas3", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_apas3_init, NULL },

12
src/mem.c
View File

@@ -1814,9 +1814,9 @@ void
mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *p)
{
#ifdef USE_DYNAREC
if (val != p->mem[addr & 0xfff] || codegen_in_recompile) {
if ((p == NULL) || (p->mem == NULL) || (val != p->mem[addr & 0xfff]) || codegen_in_recompile) {
#else
if (val != p->mem[addr & 0xfff]) {
if ((p == NULL) || (p->mem == NULL) || (val != p->mem[addr & 0xfff])) {
#endif
uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
p->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask;
@@ -1829,9 +1829,9 @@ void
mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *p)
{
#ifdef USE_DYNAREC
if (val != *(uint16_t *)&p->mem[addr & 0xfff] || codegen_in_recompile) {
if ((p == NULL) || (p->mem == NULL) || (val != *(uint16_t *)&p->mem[addr & 0xfff]) || codegen_in_recompile) {
#else
if (val != *(uint16_t *)&p->mem[addr & 0xfff]) {
if ((p == NULL) || (p->mem == NULL) || (val != *(uint16_t *)&p->mem[addr & 0xfff])) {
#endif
uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
if ((addr & 0xf) == 0xf)
@@ -1846,9 +1846,9 @@ void
mem_write_raml_page(uint32_t addr, uint32_t val, page_t *p)
{
#ifdef USE_DYNAREC
if (val != *(uint32_t *)&p->mem[addr & 0xfff] || codegen_in_recompile) {
if ((p == NULL) || (p->mem == NULL) || (val != *(uint32_t *)&p->mem[addr & 0xfff]) || codegen_in_recompile) {
#else
if (val != *(uint32_t *)&p->mem[addr & 0xfff]) {
if ((p == NULL) || (p->mem == NULL) || (val != *(uint32_t *)&p->mem[addr & 0xfff])) {
#endif
uint64_t mask = (uint64_t)1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
if ((addr & 0xf) >= 0xd)

1
src/network/network.c
View File

@@ -350,6 +350,7 @@ network_attach(void *dev, uint8_t *mac, NETRXCB rx, NETWAITCB wait, NETSETLINKST
first_pkt[0] = first_pkt[1] = NULL;
last_pkt[0] = last_pkt[1] = NULL;
memset(&network_rx_queue_timer, 0x00, sizeof(pc_timer_t));
timer_add(&network_rx_queue_timer, network_rx_queue, NULL, 0);
/* 10 mbps. */
timer_on_auto(&network_rx_queue_timer, 0.762939453125 * 2.0);

20
src/pc.c
View File

@@ -819,26 +819,6 @@ pc_reset_hard(void)
}
void
pc_reset(int hard)
{
plat_pause(1);
plat_delay_ms(100);
nvr_save();
config_save();
if (hard)
pc_reset_hard();
else
pc_send_cad();
plat_pause(0);
}
void
pc_close(thread_t *ptr)
{

9
src/pci.c
View File

@@ -809,12 +809,12 @@ pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv),
pci_log("pci_add_card(): Adding PCI CARD at specific slot %02X [SPECIFIC]\n", add_type);
if (! PCI) {
pci_log("pci_add_card(): Adding PCI CARD failed (non-PCI machine) [%s]\n", (add_type == PCI_ADD_NORMAL) ? "NORMAL" : ((add_type == PCI_ADD_VIDEO) ? "VIDEO" : ((add_type == PCI_ADD_SCSI) ? "SCSI" : "SPECIFIC")));
pci_log("pci_add_card(): Adding PCI CARD failed (non-PCI machine) [%s]\n", (add_type == PCI_ADD_NORMAL) ? "NORMAL" : ((add_type == PCI_ADD_VIDEO) ? "VIDEO" : ((add_type == PCI_ADD_SCSI) ? "SCSI" : ((add_type == PCI_ADD_SOUND) ? "SOUND" : "SPECIFIC"))));
return 0xff;
}
if (! last_pci_card) {
pci_log("pci_add_card(): Adding PCI CARD failed (no PCI slots) [%s]\n", (add_type == PCI_ADD_NORMAL) ? "NORMAL" : ((add_type == PCI_ADD_VIDEO) ? "VIDEO" : ((add_type == PCI_ADD_SCSI) ? "SCSI" : "SPECIFIC")));
pci_log("pci_add_card(): Adding PCI CARD failed (no PCI slots) [%s]\n", (add_type == PCI_ADD_NORMAL) ? "NORMAL" : ((add_type == PCI_ADD_VIDEO) ? "VIDEO" : ((add_type == PCI_ADD_SCSI) ? "SCSI" : ((add_type == PCI_ADD_SOUND) ? "SOUND" : "SPECIFIC"))));
return 0xff;
}
@@ -825,19 +825,20 @@ pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv),
if (((dev->type == PCI_CARD_NORMAL) && (add_type >= PCI_ADD_NORMAL)) ||
((dev->type == PCI_CARD_ONBOARD) && (add_type == PCI_ADD_VIDEO)) ||
((dev->type == PCI_CARD_SCSI) && (add_type == PCI_ADD_SCSI)) ||
((dev->type == PCI_CARD_SOUND) && (add_type == PCI_ADD_SOUND)) ||
((dev->type == PCI_CARD_NORTHBRIDGE) && (add_type == PCI_ADD_NORTHBRIDGE)) ||
((dev->type == PCI_CARD_SOUTHBRIDGE) && (add_type == PCI_ADD_SOUTHBRIDGE)) ||
((dev->id == add_type) && (add_type < PCI_ADD_NORTHBRIDGE))) {
dev->read = read;
dev->write = write;
dev->priv = priv;
pci_log("pci_add_card(): Adding PCI CARD to pci_cards[%i] (slot %02X) [%s]\n", i, dev->id, (add_type == PCI_ADD_NORMAL) ? "NORMAL" : ((add_type == PCI_ADD_VIDEO) ? "VIDEO" : ((add_type == PCI_ADD_SCSI) ? "SCSI" : "SPECIFIC")));
pci_log("pci_add_card(): Adding PCI CARD to pci_cards[%i] (slot %02X) [%s]\n", i, dev->id, (add_type == PCI_ADD_NORMAL) ? "NORMAL" : ((add_type == PCI_ADD_VIDEO) ? "VIDEO" : ((add_type == PCI_ADD_SCSI) ? "SCSI" : ((add_type == PCI_ADD_SOUND) ? "SOUND" : "SPECIFIC"))));
return dev->id;
}
}
}
pci_log("pci_add_card(): Adding PCI CARD failed (unable to find a suitable PCI slot) [%s]\n", (add_type == PCI_ADD_NORMAL) ? "NORMAL" : ((add_type == PCI_ADD_VIDEO) ? "VIDEO" : ((add_type == PCI_ADD_SCSI) ? "SCSI" : "SPECIFIC")));
pci_log("pci_add_card(): Adding PCI CARD failed (unable to find a suitable PCI slot) [%s]\n", (add_type == PCI_ADD_NORMAL) ? "NORMAL" : ((add_type == PCI_ADD_VIDEO) ? "VIDEO" : ((add_type == PCI_ADD_SCSI) ? "SCSI" : ((add_type == PCI_ADD_SOUND) ? "SOUND" : "SPECIFIC"))));
return 0xff;
}

6
src/pit.c
View File

@@ -1029,8 +1029,10 @@ pit_set_clock(int clock)
TIMER_USEC = (uint64_t)((cpuclock / 1000000.0) * (double)(1ull << 32));
isa_timing = (cpuclock / (double)8000000.0);
bus_timing = (cpuclock / (double)cpu_busspeed);
if (cpu_64bitbus)
bus_timing = (cpuclock / ((double)cpu_busspeed) / 2);
else
bus_timing = (cpuclock / (double)cpu_busspeed);
pci_timing = (cpuclock / (double)cpu_pci_speed);
/* PCICLK in us for use with timer_on_auto(). */

3
src/postcard.c
View File

@@ -99,9 +99,6 @@ postcard_write(uint16_t port, uint8_t val, void *priv)
if (postcard_written && val == postcard_code)
return;
if (val == 0x13)
pclog("[%04X:%08X] POST 13\n", CS, cpu_state.pc);
postcard_prev_code = postcard_code;
postcard_code = val;
if (postcard_written < 2)

39
src/sound/snd_ad1848.c
View File

@@ -1,6 +1,5 @@
/*PCem v0.8 by Tom Walker
AD1848 CODEC emulation (Windows Sound System compatible)*/
/*
AD1848 / CS4248 / CS4231 CODEC emulation (Windows Sound System compatible)*/
#include <stdio.h>
#include <stdint.h>
@@ -14,6 +13,7 @@
#include <86box/sound.h>
#include <86box/snd_ad1848.h>
#define CS4231 0x80
static int ad1848_vols_6bits[64];
static uint32_t ad1848_vols_5bits_aux_gain[32];
@@ -40,7 +40,11 @@ uint8_t ad1848_read(uint16_t addr, void *p)
break;
case 1:
temp = ad1848->regs[ad1848->index];
break;
if (ad1848->index == 0x0b) {
temp ^= 0x20;
ad1848->regs[ad1848->index] = temp;
}
break;
case 2:
temp = ad1848->status;
break;
@@ -97,6 +101,10 @@ void ad1848_write(uint16_t addr, uint8_t val, void *p)
}
break;
case 11:
break;
case 12:
if (ad1848->type != AD1848_TYPE_DEFAULT)
ad1848->regs[12] = ((ad1848->regs[12] & 0x0f) + (val & 0xf0)) | 0x80;
@@ -105,6 +113,14 @@ void ad1848_write(uint16_t addr, uint8_t val, void *p)
case 14:
ad1848->count = ad1848->regs[15] | (val << 8);
break;
case 24:
if (! (val & 0x70))
ad1848->status &= 0xfe;
break;
case 25:
break;
}
ad1848->regs[ad1848->index] = val;
@@ -197,7 +213,7 @@ static void ad1848_poll(void *p)
if (!(ad1848->status & 0x01))
{
ad1848->status |= 0x01;
if (ad1848->regs[0xa] & 2)
if (ad1848->regs[10] & 2)
picint(1 << ad1848->irq);
}
}
@@ -221,9 +237,9 @@ void ad1848_init(ad1848_t *ad1848, int type)
ad1848->mce = 0x40;
ad1848->regs[0] = ad1848->regs[1] = 0;
ad1848->regs[2] = ad1848->regs[3] = 0x80; /* AZT2316A Line-in */
ad1848->regs[2] = ad1848->regs[3] = 0x80; /* Line-in */
ad1848->regs[4] = ad1848->regs[5] = 0x80;
ad1848->regs[6] = ad1848->regs[7] = 0x80; /* AZT2316A Master? */
ad1848->regs[6] = ad1848->regs[7] = 0x80; /* Left/right Output */
ad1848->regs[8] = 0;
ad1848->regs[9] = 0x08;
ad1848->regs[10] = ad1848->regs[11] = 0;
@@ -236,8 +252,13 @@ void ad1848_init(ad1848_t *ad1848, int type)
if (type == AD1848_TYPE_CS4231)
{
ad1848->regs[0x12] = ad1848->regs[0x13] = 0x80; // AZT2316A CD
ad1848->regs[0x1A] = 0x80; // AZT2316A Mic
ad1848->regs[16] = ad1848->regs[17] = 0;
ad1848->regs[18] = ad1848->regs[19] = 0x88;
ad1848->regs[22] = 0x80;
ad1848->regs[24] = 0;
ad1848->regs[25] = CS4231;
ad1848->regs[26] = 0x80;
ad1848->regs[29] = 0x80;
}
ad1848->out_l = 0;

36
src/sound/snd_audiopci.c
View File

@@ -1313,7 +1313,7 @@ static void *es1371_init(const device_t *info)
sound_add_handler(es1371_get_buffer, es1371);
es1371->card = pci_add_card(PCI_ADD_NORMAL, es1371_pci_read, es1371_pci_write, es1371);
es1371->card = pci_add_card(info->local ? PCI_ADD_SOUND : PCI_ADD_NORMAL, es1371_pci_read, es1371_pci_write, es1371);
timer_add(&es1371->dac[1].timer, es1371_poll, es1371, 1);
@@ -1382,14 +1382,28 @@ void es1371_add_status_info_dac(es1371_t *es1371, char *s, int max_len, int dac_
const device_t es1371_device =
{
"Ensoniq AudioPCI (ES1371)",
DEVICE_PCI,
0,
es1371_init,
es1371_close,
NULL,
NULL,
es1371_speed_changed,
NULL,
NULL
"Ensoniq AudioPCI (ES1371)",
DEVICE_PCI,
0,
es1371_init,
es1371_close,
NULL,
NULL,
es1371_speed_changed,
NULL,
NULL
};
const device_t es1371_onboard_device =
{
"Ensoniq AudioPCI (ES1371) (On-Board)",
DEVICE_PCI,
1,
es1371_init,
es1371_close,
NULL,
NULL,
es1371_speed_changed,
NULL,
NULL
};

80
src/sound/snd_gus.c
View File

@@ -14,6 +14,8 @@
#include <86box/device.h>
#include <86box/sound.h>
#include <86box/midi.h>
#include <86Box/snd_ad1848.h>
#include <math.h>
enum
{
@@ -108,6 +110,12 @@ typedef struct gus_t
uint16_t gp1_addr, gp2_addr;
uint8_t usrr;
uint8_t max_ctrl;
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
ad1848_t ad1848;
#endif
} gus_t;
static int gus_gf1_irqs[8] = {-1, 2, 5, 3, 7, 11, 12, 15};
@@ -182,6 +190,9 @@ void writegus(uint16_t addr, uint8_t val, void *p)
int c, d;
int old;
uint16_t port;
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
uint16_t csioport;
#endif
if ((addr == 0x388) || (addr == 0x389))
port = addr;
@@ -526,10 +537,16 @@ gus->curx[gus->voice]=(gus->curx[gus->voice]&0xFFF8000)|((val&0x7F)<<8);
}
else
gus->irq_midi = gus_midi_irqs[(val >> 3) & 7];
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
ad1848_setirq(&gus->ad1848, gus->irq);
#endif
gus->sb_nmi = val & 0x80;
} else {
gus->dma = gus_dmas[val & 7];
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
ad1848_setdma(&gus->ad1848, gus->dma);
#endif
}
break;
case 1:
@@ -584,6 +601,25 @@ gus->curx[gus->voice]=(gus->curx[gus->voice]&0xFFF8000)|((val&0x7F)<<8);
case 0x20f:
gus->reg_ctrl = val;
break;
case 0x306: case 0x706:
if (gus->dma >= 4)
val |= 0x30;
gus->max_ctrl = (val >> 6) & 1;
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
if (val & 0x40) {
if ((val & 0xF) != ((addr >> 4) & 0xF)) {
csioport = 0x30c | ((addr >> 4) & 0xf);
io_removehandler(csioport, 4,
ad1848_read,NULL,NULL,
ad1848_write,NULL,NULL,&gus->ad1848);
csioport = 0x30c | ((val & 0xf) << 4);
io_sethandler(csioport, 4,
ad1848_read,NULL,NULL,
ad1848_write,NULL,NULL, &gus->ad1848);
}
}
#endif
break;
}
}
@@ -632,7 +668,11 @@ uint8_t readgus(uint16_t addr, void *p)
return val;
case 0x20F:
return 0;
if (gus->max_ctrl)
val = 0x02;
else
val = 0x00;
break;
case 0x302:
return gus->voice;
@@ -719,8 +759,14 @@ uint8_t readgus(uint16_t addr, void *p)
break;
}
break;
case 0x306: case 0x706: /*Revision level*/
return 0xff; /*Pre 3.7 - no mixer*/
case 0x306: case 0x706:
if (gus->max_ctrl)
val = 0x0a; /* GUS MAX */
else
val = 0xff; /*Pre 3.7 - no mixer*/
break;
break;
case 0x307: /*DRAM access*/
val=gus->ram[gus->addr];
gus->addr&=0xFFFFF;
@@ -1031,13 +1077,25 @@ static void gus_get_buffer(int32_t *buffer, int len, void *p)
gus_t *gus = (gus_t *)p;
int c;
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
if (gus->max_ctrl)
ad1848_update(&gus->ad1848);
#endif
gus_update(gus);
for (c = 0; c < len * 2; c++)
{
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
if (gus->max_ctrl)
buffer[c] += (int32_t)(gus->ad1848.buffer[c] / 2);
#endif
buffer[c] += (int32_t)gus->buffer[c & 1][c >> 1];
}
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
if (gus->max_ctrl)
gus->ad1848.pos = 0;
#endif
gus->pos = 0;
}
@@ -1119,6 +1177,15 @@ void *gus_init(const device_t *info)
io_sethandler(0x0100+gus->base, 0x0010, readgus, NULL, NULL, writegus, NULL, NULL, gus);
io_sethandler(0x0506+gus->base, 0x0001, readgus, NULL, NULL, writegus, NULL, NULL, gus);
io_sethandler(0x0388, 0x0002, readgus, NULL, NULL, writegus, NULL, NULL, gus);
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
ad1848_init(&gus->ad1848, AD1848_TYPE_CS4231);
ad1848_setirq(&gus->ad1848, 5);
ad1848_setdma(&gus->ad1848, 3);
io_sethandler(0x10C+gus->base, 4,
ad1848_read,NULL,NULL, ad1848_write,NULL,NULL, &gus->ad1848);
#endif
timer_add(&gus->samp_timer, gus_poll_wave, gus, 1);
timer_add(&gus->timer_1, gus_poll_timer_1, gus, 1);
timer_add(&gus->timer_2, gus_poll_timer_2, gus, 1);
@@ -1147,6 +1214,11 @@ void gus_speed_changed(void *p)
gus->samp_latch = (uint64_t)(TIMER_USEC * (1000000.0 / 44100.0));
else
gus->samp_latch = (uint64_t)(TIMER_USEC * (1000000.0 / gusfreqs[gus->voices - 14]));
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
if (gus->max_ctrl)
ad1848_speed_changed(&gus->ad1848);
#endif
}
static const device_config_t gus_config[] = {
@@ -1156,7 +1228,7 @@ static const device_config_t gus_config[] = {
{
"Classic", GUS_CLASSIC
},
#if 0
#if defined(DEV_BRANCH) && defined(USE_GUSMAX)
{
"MAX", GUS_MAX
},

5
src/sound/sound.c
View File

@@ -29,6 +29,7 @@
#include <86box/cdrom.h>
#include <86box/hdc_ide.h>
#include <86box/plat.h>
#include <86box/machine.h>
#include <86box/sound.h>
#include <86box/midi.h>
#include <86box/snd_opl.h>
@@ -79,6 +80,7 @@ static int cd_thread_enable = 0;
static const SOUND_CARD sound_cards[] =
{
{ "None", "none", NULL },
{ "Internal", "internal", NULL },
{ "[ISA] Adlib", "adlib", &adlib_device },
{ "[ISA] Adlib Gold", "adlibgold", &adgold_device },
{ "[ISA] Aztech Sound Galaxy Pro 16 AB (Washington)", "azt2316a", &azt2316a_device },
@@ -126,6 +128,9 @@ sound_log(const char *fmt, ...)
int
sound_card_available(int card)
{
if ((card == SOUND_INTERNAL) && !(machines[machine].flags & MACHINE_SOUND))
return 0;
if (sound_cards[card].device)
return device_available(sound_cards[card].device);

15
src/timer.c
View File

@@ -110,8 +110,10 @@ timer_remove_head(void)
if (timer_head) {
timer = timer_head;
timer_head = timer->next;
if (timer_head)
if (timer_head) {
timer_head->prev = NULL;
timer->next->prev = NULL;
}
timer->next = timer->prev = NULL;
timer->flags &= ~TIMER_ENABLED;
}
@@ -151,6 +153,17 @@ timer_process(void)
void
timer_close(void)
{
pc_timer_t *t = timer_head, *r;
/* Set all timers' prev and next to NULL so it is assured that
timers that are not in malloc'd structs don't keep pointing
to timers that may be in malloc'd structs. */
while (t != NULL) {
r = t;
r->prev = r->next = NULL;
t = r->next;
}
timer_head = NULL;
timer_inited = 0;

24
src/video/vid_ati68860_ramdac.c
View File

@@ -255,25 +255,25 @@ ati68860_hwcursor_draw(svga_t *svga, int displine)
uint32_t col0 = ramdac->pallook[0];
uint32_t col1 = ramdac->pallook[1];
offset = svga->hwcursor_latch.xoff;
for (x = 0; x < 64 - svga->hwcursor_latch.xoff; x += 4) {
dat = svga->vram[svga->hwcursor_latch.addr + (offset >> 2)];
if (!(dat & 2)) buffer32->line[displine][svga->hwcursor_latch.x + x + svga->x_add] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3) buffer32->line[displine][svga->hwcursor_latch.x + x + svga->x_add] ^= 0xFFFFFF;
offset = svga->dac_hwcursor_latch.xoff;
for (x = 0; x < 64 - svga->dac_hwcursor_latch.xoff; x += 4) {
dat = svga->vram[svga->dac_hwcursor_latch.addr + (offset >> 2)];
if (!(dat & 2)) buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3) buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add] ^= 0xFFFFFF;
dat >>= 2;
if (!(dat & 2)) buffer32->line[displine][svga->hwcursor_latch.x + x + svga->x_add + 1] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3) buffer32->line[displine][svga->hwcursor_latch.x + x + svga->x_add + 1] ^= 0xFFFFFF;
if (!(dat & 2)) buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 1] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3) buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 1] ^= 0xFFFFFF;
dat >>= 2;
if (!(dat & 2)) buffer32->line[displine][svga->hwcursor_latch.x + x + svga->x_add + 2] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3) buffer32->line[displine][svga->hwcursor_latch.x + x + svga->x_add + 2] ^= 0xFFFFFF;
if (!(dat & 2)) buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 2] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3) buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 2] ^= 0xFFFFFF;
dat >>= 2;
if (!(dat & 2)) buffer32->line[displine][svga->hwcursor_latch.x + x + svga->x_add + 3] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3) buffer32->line[displine][svga->hwcursor_latch.x + x + svga->x_add + 3] ^= 0xFFFFFF;
if (!(dat & 2)) buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 3] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3) buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 3] ^= 0xFFFFFF;
dat >>= 2;
offset += 4;
}
svga->hwcursor_latch.addr += 16;
svga->dac_hwcursor_latch.addr += 16;
}

32
src/video/vid_ati_mach64.c
View File

@@ -875,6 +875,16 @@ static void mach64_accel_write_fifo_w(mach64_t *mach64, uint32_t addr, uint16_t
mach64_blit(val, 16, mach64);
break;
case 0x32c:
mach64->context_load_cntl = (mach64->context_load_cntl & 0xffff0000) | val;
break;
case 0x32e:
mach64->context_load_cntl = (mach64->context_load_cntl & 0x0000ffff) | (val << 16);
if (val & 0x30000)
mach64_load_context(mach64);
break;
default:
mach64_accel_write_fifo(mach64, addr, val);
mach64_accel_write_fifo(mach64, addr + 1, val >> 8);
@@ -2098,6 +2108,7 @@ uint8_t mach64_ext_readb(uint32_t addr, void *p)
}
uint16_t mach64_ext_readw(uint32_t addr, void *p)
{
mach64_t *mach64 = (mach64_t *)p;
uint16_t ret;
if (!(addr & 0x400))
{
@@ -2106,6 +2117,13 @@ uint16_t mach64_ext_readw(uint32_t addr, void *p)
}
else switch (addr & 0x3ff)
{
case 0xb4: case 0xb6:
ret = (mach64->bank_w[(addr & 2) >> 1] >> 15);
break;
case 0xb8: case 0xba:
ret = (mach64->bank_r[(addr & 2) >> 1] >> 15);
break;
default:
ret = mach64_ext_readb(addr, p);
ret |= mach64_ext_readb(addr + 1, p) << 8;
@@ -2137,7 +2155,7 @@ uint32_t mach64_ext_readl(uint32_t addr, void *p)
case 0xb8:
ret = (mach64->bank_r[0] >> 15) | ((mach64->bank_r[1] >> 15) << 16);
break;
default:
ret = mach64_ext_readw(addr, p);
ret |= mach64_ext_readw(addr + 2, p) << 16;
@@ -2276,19 +2294,19 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *p)
break;
case 0x68: case 0x69: case 0x6a: case 0x6b:
WRITE8(addr, mach64->cur_offset, val);
svga->hwcursor.addr = (mach64->cur_offset & 0xfffff) * 8;
svga->dac_hwcursor.addr = (mach64->cur_offset & 0xfffff) * 8;
mach64_cursor_dump(mach64);
break;
case 0x6c: case 0x6d: case 0x6e: case 0x6f:
WRITE8(addr, mach64->cur_horz_vert_posn, val);
svga->hwcursor.x = mach64->cur_horz_vert_posn & 0x7ff;
svga->hwcursor.y = (mach64->cur_horz_vert_posn >> 16) & 0x7ff;
svga->dac_hwcursor.x = mach64->cur_horz_vert_posn & 0x7ff;
svga->dac_hwcursor.y = (mach64->cur_horz_vert_posn >> 16) & 0x7ff;
mach64_cursor_dump(mach64);
break;
case 0x70: case 0x71: case 0x72: case 0x73:
WRITE8(addr, mach64->cur_horz_vert_off, val);
svga->hwcursor.xoff = mach64->cur_horz_vert_off & 0x3f;
svga->hwcursor.yoff = (mach64->cur_horz_vert_off >> 16) & 0x3f;
svga->dac_hwcursor.xoff = mach64->cur_horz_vert_off & 0x3f;
svga->dac_hwcursor.yoff = (mach64->cur_horz_vert_off >> 16) & 0x3f;
mach64_cursor_dump(mach64);
break;
@@ -2348,7 +2366,7 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *p)
WRITE8(addr, mach64->gen_test_cntl, val);
ati_eeprom_write(&mach64->eeprom, mach64->gen_test_cntl & 0x10, mach64->gen_test_cntl & 2, mach64->gen_test_cntl & 1);
mach64->gen_test_cntl = (mach64->gen_test_cntl & ~8) | (ati_eeprom_read(&mach64->eeprom) ? 8 : 0);
svga->hwcursor.ena = mach64->gen_test_cntl & 0x80;
svga->dac_hwcursor.ena = mach64->gen_test_cntl & 0x80;
mach64_cursor_dump(mach64);
break;

50
src/video/vid_et4000.c
View File

@@ -277,56 +277,6 @@ et4000_out(uint16_t addr, uint8_t val, void *priv)
svga_recalctimings(svga);
}
}
/*
* Note - Silly hack to determine video memory
* size automatically by ET4000 BIOS.
*/
if ((svga->crtcreg == 0x37) && (dev->type != 1)) {
switch (val & 0x0b) {
case 0x00:
case 0x01:
if (svga->vram_max == 64 * 1024)
mem_mapping_enable(&svga->mapping);
else
mem_mapping_disable(&svga->mapping);
break;
case 0x02:
if (svga->vram_max == 128 * 1024)
mem_mapping_enable(&svga->mapping);
else
mem_mapping_disable(&svga->mapping);
break;
case 0x03:
case 0x08:
case 0x09:
if (svga->vram_max == 256 * 1024)
mem_mapping_enable(&svga->mapping);
else
mem_mapping_disable(&svga->mapping);
break;
case 0x0a:
if (svga->vram_max == 512 * 1024)
mem_mapping_enable(&svga->mapping);
else
mem_mapping_disable(&svga->mapping);
break;
case 0x0b:
if (svga->vram_max == 1024 * 1024)
mem_mapping_enable(&svga->mapping);
else
mem_mapping_disable(&svga->mapping);
break;
default:
mem_mapping_enable(&svga->mapping);
break;
}
}
break;
}

2
src/video/vid_et4000w32.c
View File

@@ -1210,7 +1210,7 @@ uint8_t et4000w32p_pci_read(int func, int addr, void *p)
case 0x09: return 0; /*Programming interface*/
case 0x0a: return 0x00; /*Supports VGA interface, XGA compatible*/
case 0x0b: return is_pentium ? 0x03 : 0x00; /* This has to be done in order to make this card work with the two 486 PCI machines. */
case 0x0b: return cpu_64bitbus ? 0x03 : 0x00; /* This has to be done in order to make this card work with the two 486 PCI machines. */
case 0x10: return 0x00; /*Linear frame buffer address*/
case 0x11: return 0x00;

16
src/win/Makefile.mingw
View File

@@ -8,7 +8,7 @@
#
# Makefile for Win32 (MinGW32) environment.
#
# Version: @(#)Makefile.mingw 1.0.143 2020/01/25
# Version: @(#)Makefile.mingw 1.0.144 2020/06/06
#
# Authors: Miran Grca, <mgrca8@gmail.com>
# Fred N. van Kempen, <decwiz@yahoo.com>
@@ -86,6 +86,9 @@ ifeq ($(DEV_BUILD), y)
ifndef NO_SIO
NO_SIO := y
endif
ifndef GUSMAX
GUSMAX := y
endif
else
ifndef DEBUG
DEBUG := n
@@ -141,6 +144,9 @@ else
ifndef NO_SIO
NO_SIO := n
endif
ifndef GUSMAX
GUSMAX := n
endif
endif
# Defaults for several build options (possibly defined in a chained file.)
@@ -471,6 +477,10 @@ ifeq ($(NO_SIO), y)
OPTS += -DNO_SIO
endif
ifeq ($(GUSMAX), y)
OPTS += -DUSE_GUSMAX
endif
endif
@@ -515,8 +525,8 @@ CPUOBJ := cpu.o cpu_table.o \
$(DYNARECOBJ)
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
intel_4x0.o neat.o opti495.o scamp.o scat.o \
sis_85c471.o sis_85c496.o \
intel_4x0.o neat.o opti495.o opti5x7.o scamp.o scat.o \
rabbit.o sis_85c471.o sis_85c496.o \
via_apollo.o via_vpx.o wd76c10.o
MCHOBJ := machine.o machine_table.o \

16
src/win/Makefile_ndr.mingw
View File

@@ -8,7 +8,7 @@
#
# Makefile for Win32 (MinGW32) environment.
#
# Version: @(#)Makefile.mingw 1.0.142 2020/01/25
# Version: @(#)Makefile.mingw 1.0.143 2020/06/06
#
# Authors: Miran Grca, <mgrca8@gmail.com>
# Fred N. van Kempen, <decwiz@yahoo.com>
@@ -86,6 +86,9 @@ ifeq ($(DEV_BUILD), y)
ifndef NO_SIO
NO_SIO := y
endif
ifndef GUSMAX
GUSMAX := y
endif
else
ifndef DEBUG
DEBUG := n
@@ -144,6 +147,9 @@ else
ifndef NO_SIO
NO_SIO := n
endif
ifndef GUSMAX
GUSMAX := n
endif
endif
# Defaults for several build options (possibly defined in a chained file.)
@@ -480,6 +486,10 @@ ifeq ($(NO_SIO), y)
OPTS += -DNO_SIO
endif
ifeq ($(GUSMAX), y)
OPTS += -DUSE_GUSMAX
endif
endif
@@ -519,8 +529,8 @@ CPUOBJ := cpu.o cpu_table.o \
$(DYNARECOBJ)
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
intel_4x0.o neat.o opti495.o scamp.o scat.o \
sis_85c471.o sis_85c496.o \
intel_4x0.o neat.o opti495.o opti5x7.o scamp.o scat.o \
rabbit.o sis_85c471.o sis_85c496.o \
via_apollo.o via_vpx.o wd76c10.o
MCHOBJ := machine.o machine_table.o \

9
src/win/win_ui.c
View File

@@ -314,12 +314,12 @@ MainWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
win_notify_dlg_open();
i = ui_msgbox(MBX_QUESTION_YN, (wchar_t *)IDS_2112);
if (i == 0)
pc_reset(1);
pc_reset_hard();
win_notify_dlg_closed();
break;
case IDM_ACTION_RESET_CAD:
pc_reset(0);
pc_send_cad();
break;
case IDM_ACTION_EXIT:
@@ -733,7 +733,7 @@ MainWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
win_notify_dlg_open();
i = ui_msgbox(MBX_QUESTION_YN, (wchar_t *)IDS_2112);
if (i == 0)
pc_reset(1);
pc_reset_hard();
win_notify_dlg_closed();
break;
@@ -757,7 +757,7 @@ MainWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
if (manager_wm)
break;
manager_wm = 1;
pc_reset(0);
pc_send_cad();
manager_wm = 0;
break;
@@ -1307,4 +1307,5 @@ plat_set_input(HWND h)
input_orig_proc = GetWindowLongPtr(h, GWLP_WNDPROC);
input_orig_hwnd = h;
SetWindowLongPtr(h, GWLP_WNDPROC, (LONG_PTR)&input_proc);
ImmAssociateContext(h, NULL);
}