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Merge pull request #3430 from jriwanek-forks/sonarlint

Browse Source 
Next round of sonarlint cleanups
This commit is contained in:
Miran Grča
2023-06-28 04:22:31 +02:00
committed by GitHub
parent 8123ba6e08 922c4335ae
commit bff8e92297
90 changed files with 1455 additions and 1023 deletions
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23
src/86box.c
View File

@@ -208,16 +208,20 @@ char exe_path[2048]; /* path (dir) of executable */
char usr_path[1024]; /* path (dir) of user data */
char cfg_path[1024]; /* full path of config file */
FILE *stdlog = NULL; /* file to log output to */
// int scrnsz_x = SCREEN_RES_X; /* current screen size, X */
// int scrnsz_y = SCREEN_RES_Y; /* current screen size, Y */
#if 0
int scrnsz_x = SCREEN_RES_X; /* current screen size, X */
int scrnsz_y = SCREEN_RES_Y; /* current screen size, Y */
#endif
int config_changed; /* config has changed */
int title_update;
int framecountx = 0;
int hard_reset_pending = 0;
// int unscaled_size_x = SCREEN_RES_X; /* current unscaled size X */
// int unscaled_size_y = SCREEN_RES_Y; /* current unscaled size Y */
// int efscrnsz_y = SCREEN_RES_Y;
#if 0
int unscaled_size_x = SCREEN_RES_X; /* current unscaled size X */
int unscaled_size_y = SCREEN_RES_Y; /* current unscaled size Y */
int efscrnsz_y = SCREEN_RES_Y;
#endif
static wchar_t mouse_msg[3][200];
@@ -416,7 +420,6 @@ pc_init(int argc, char *argv[])
time_t now;
int c;
int lvmp = 0;
int i;
#ifdef ENABLE_NG
int ng = 0;
#endif
@@ -467,7 +470,7 @@ pc_init(int argc, char *argv[])
if (!strcasecmp(argv[c], "--help") || !strcasecmp(argv[c], "-?")) {
usage:
for (i = 0; i < FDD_NUM; i++) {
for (uint8_t i = 0; i < FDD_NUM; i++) {
if (fn[i] != NULL) {
free(fn[i]);
fn[i] = NULL;
@@ -776,7 +779,7 @@ usage:
/* Load the configuration file. */
config_load();
for (i = 0; i < FDD_NUM; i++) {
for (uint8_t i = 0; i < FDD_NUM; i++) {
if (fn[i] != NULL) {
if (strlen(fn[i]) <= 511)
strncpy(floppyfns[i], fn[i], 511);
@@ -1433,14 +1436,14 @@ reset_screen_size_monitor(int monitor_index)
void
reset_screen_size(void)
{
for (int i = 0; i < MONITORS_NUM; i++)
for (uint8_t i = 0; i < MONITORS_NUM; i++)
set_screen_size(monitors[i].mon_unscaled_size_x, monitors[i].mon_efscrnsz_y);
}
void
set_screen_size_natural(void)
{
for (int i = 0; i < MONITORS_NUM; i++)
for (uint8_t i = 0; i < MONITORS_NUM; i++)
set_screen_size(monitors[i].mon_unscaled_size_x, monitors[i].mon_unscaled_size_y);
}

5
src/cdrom/cdrom_image_viso.c
View File

@@ -117,7 +117,7 @@ typedef struct {
uint64_t vol_size_offsets[2];
uint64_t pt_meta_offsets[2];
int format;
int use_version_suffix : 1;
uint8_t use_version_suffix : 1;
size_t metadata_sectors, all_sectors, entry_map_size, sector_size, file_fifo_pos;
uint8_t *metadata;
@@ -631,6 +631,9 @@ pad_susp:
if (!(*q & 1)) /* padding for even file ID lengths */
*p++ = 0;
break;
default:
break;
}
if ((p - data) > 255)

2
src/cdrom/cdrom_mitsumi.c
View File

@@ -116,7 +116,9 @@ typedef struct {
/* The addresses sent from the guest are absolute, ie. a LBA of 0 corresponds to a MSF of 00:00:00. Otherwise, the counter displayed by the guest is wrong:
there is a seeming 2 seconds in which audio plays but counter does not move, while a data track before audio jumps to 2 seconds before the actual start
of the audio while audio still plays. With an absolute conversion, the counter is fine. */
#ifdef MSFtoLBA
#undef MSFtoLBA
#endif
#define MSFtoLBA(m, s, f) ((((m * 60) + s) * 75) + f)
#define CD_BCD(x) (((x) % 10) | (((x) / 10) << 4))

32
src/chipset/82c100.c
View File

@@ -33,19 +33,19 @@
#include <86box/rom.h>
#include <86box/chipset.h>
typedef struct
{
typedef struct ems_page_t {
int enabled;
uint32_t virt, phys;
uint32_t virt;
uint32_t phys;
} ems_page_t;
typedef struct
{
uint8_t index, access;
uint16_t ems_io_base;
uint32_t ems_window_base;
uint8_t ems_page_regs[4],
regs[256];
typedef struct ct_82c100_t {
uint8_t index;
uint8_t access;
uint16_t ems_io_base;
uint32_t ems_window_base;
uint8_t ems_page_regs[4];
uint8_t regs[256];
ems_page_t ems_pages[4];
mem_mapping_t ems_mappings[4];
} ct_82c100_t;
@@ -120,9 +120,7 @@ ct_82c100_ems_in(uint16_t port, void *priv)
static void
ct_82c100_ems_update(ct_82c100_t *dev)
{
int i;
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
ct_82c100_log("Disabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14));
io_handler(0, dev->ems_io_base + (i << 14), 1,
ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
@@ -130,7 +128,7 @@ ct_82c100_ems_update(ct_82c100_t *dev)
dev->ems_io_base = 0x0208 + (dev->regs[0x4c] & 0xf0);
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
ct_82c100_log("Enabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14));
io_handler(1, dev->ems_io_base + (i << 14), 1,
ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
@@ -222,6 +220,9 @@ ct_82c100_out(uint16_t port, uint8_t val, void *priv)
dev->regs[0x4c] = val;
ct_82c100_ems_update(dev);
break;
default:
break;
}
dev->access = 0;
}
@@ -258,6 +259,9 @@ ct_82c100_in(uint16_t port, void *priv)
case 0x4c:
ret = dev->regs[dev->index];
break;
default:
break;
}
dev->access = 0;
}

13
src/chipset/acc2168.c
View File

@@ -58,20 +58,21 @@ acc2168_log(const char *fmt, ...)
#endif
typedef struct acc2168_t {
uint8_t reg_idx, regs[256];
uint8_t reg_idx;
uint8_t regs[256];
} acc2168_t;
static void
acc2168_shadow_recalc(acc2168_t *dev)
{
for (uint32_t i = 0; i < 5; i++)
for (uint8_t i = 0; i < 5; i++)
mem_set_mem_state_both(SHADOW_ADDR, SHADOW_SIZE, SHADOW_RECALC);
}
static void
acc2168_write(uint16_t addr, uint8_t val, void *p)
acc2168_write(uint16_t addr, uint8_t val, void *priv)
{
acc2168_t *dev = (acc2168_t *) p;
acc2168_t *dev = (acc2168_t *) priv;
switch (addr) {
case 0xf2:
@@ -165,9 +166,9 @@ acc2168_write(uint16_t addr, uint8_t val, void *p)
}
static uint8_t
acc2168_read(uint16_t addr, void *p)
acc2168_read(uint16_t addr, void *priv)
{
acc2168_t *dev = (acc2168_t *) p;
acc2168_t *dev = (acc2168_t *) priv;
return (addr == 0xf3) ? dev->regs[dev->reg_idx] : dev->reg_idx;
}

10
src/chipset/ali1429.c
View File

@@ -115,10 +115,12 @@ ali1429_log(const char *fmt, ...)
# define ali1429_log(fmt, ...)
#endif
typedef struct
{
uint8_t is_g, index, cfg_locked, reg_57h,
regs[90];
typedef struct ali_1429_t {
uint8_t is_g;
uint8_t index;
uint8_t cfg_locked;
uint8_t reg_57h;
uint8_t regs[90];
} ali1429_t;
static void

13
src/chipset/ali1435.c
View File

@@ -43,10 +43,11 @@
#define MEM_STATE_SHADOW_W 0x02
#define MEM_STATE_SMRAM 0x04
typedef struct
{
uint8_t index, cfg_locked,
regs[16], pci_regs[256];
typedef struct ali_1435_t {
uint8_t index;
uint8_t cfg_locked;
uint8_t regs[16];
uint8_t pci_regs[256];
} ali1435_t;
#define ENABLE_ALI1435_LOG 1
@@ -276,9 +277,9 @@ ali1435_reset(void *priv)
}
static void
ali1435_close(void *p)
ali1435_close(void *priv)
{
ali1435_t *dev = (ali1435_t *) p;
ali1435_t *dev = (ali1435_t *) priv;
free(dev);
}

22
src/chipset/ali1489.c
View File

@@ -62,10 +62,14 @@ ali1489_log(const char *fmt, ...)
# define ali1489_log(fmt, ...)
#endif
typedef struct
{
uint8_t index, ide_index, ide_chip_id, pci_slot,
regs[256], pci_conf[256], ide_regs[256];
typedef struct ali1489_t {
uint8_t index;
uint8_t ide_index;
uint8_t ide_chip_id;
uint8_t pci_slot;
uint8_t regs[256];
uint8_t pci_conf[256];
uint8_t ide_regs[256];
port_92_t *port_92;
smram_t *smram;
@@ -76,11 +80,9 @@ static void ali1489_ide_handler(ali1489_t *dev);
static void
ali1489_shadow_recalc(ali1489_t *dev)
{
uint32_t i;
shadowbios = shadowbios_write = 0;
for (i = 0; i < 8; i++) {
for (uint8_t i = 0; i < 8; i++) {
if (dev->regs[0x13] & (1 << i)) {
ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n",
0xc0000 + (i << 14), 0xc3fff + (i << 14), !!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20));
@@ -91,7 +93,7 @@ ali1489_shadow_recalc(ali1489_t *dev)
}
}
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
if (dev->regs[0x14] & (1 << i)) {
ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n",
0xe0000 + (i << 15), 0xe7fff + (i << 15), !!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20));
@@ -445,6 +447,7 @@ ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
case 0x07:
dev->pci_conf[0x07] &= ~(val & 0xb8);
break;
default:
break;
}
@@ -543,10 +546,12 @@ ali1489_ide_write(uint16_t addr, uint8_t val, void *priv)
dev->ide_regs[dev->ide_index] = val;
ali1489_ide_handler(dev);
break;
default:
break;
}
break;
default:
break;
}
@@ -566,6 +571,7 @@ ali1489_ide_read(uint16_t addr, void *priv)
ret = dev->ide_regs[dev->ide_index];
ali1489_log("M1489-IDE: dev->regs[%02x] (%02x)\n", dev->ide_index, ret);
break;
default:
break;
}

6
src/chipset/ali1531.c
View File

@@ -83,6 +83,7 @@ ali1531_smram_recalc(uint8_t val, ali1531_t *dev)
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
break;
default:
break;
}
@@ -314,7 +315,6 @@ static void
ali1531_reset(void *priv)
{
ali1531_t *dev = (ali1531_t *) priv;
int i;
/* Default Registers */
dev->pci_conf[0x00] = 0xb9;
@@ -350,10 +350,10 @@ ali1531_reset(void *priv)
ali1531_write(0, 0x47, 0x00, dev);
ali1531_write(0, 0x48, 0x00, dev);
for (i = 0; i < 4; i++)
for (uint8_t i = 0; i < 4; i++)
ali1531_write(0, 0x4c + i, 0x00, dev);
for (i = 0; i < 16; i += 2) {
for (uint8_t i = 0; i < 16; i += 2) {
ali1531_write(0, 0x60 + i, 0x08, dev);
ali1531_write(0, 0x61 + i, 0x40, dev);
}

10
src/chipset/ali1541.c
View File

@@ -572,7 +572,6 @@ static void
ali1541_reset(void *priv)
{
ali1541_t *dev = (ali1541_t *) priv;
int i;
/* Default Registers */
dev->pci_conf[0x00] = 0xb9;
@@ -615,12 +614,13 @@ ali1541_reset(void *priv)
ali1541_write(0, 0x54, 0x00, dev);
ali1541_write(0, 0x55, 0x00, dev);
for (i = 0; i < 4; i++)
for (uint8_t i = 0; i < 4; i++)
ali1541_write(0, 0x56 + i, 0x00, dev);
ali1541_write(0, 0x60 + i, 0x07, dev);
ali1541_write(0, 0x61 + i, 0x40, dev);
for (i = 0; i < 14; i += 2) {
ali1541_write(0, 0x60, 0x07, dev);
ali1541_write(0, 0x61, 0x40, dev);
for (uint8_t i = 0; i < 14; i += 2) {
ali1541_write(0, 0x62 + i, 0x00, dev);
ali1541_write(0, 0x63 + i, 0x00, dev);
}

19
src/chipset/ali1543.c
View File

@@ -47,10 +47,19 @@
#include <86box/chipset.h>
typedef struct ali1543_t {
uint8_t pci_conf[256], pmu_conf[256], usb_conf[256], ide_conf[256],
pci_slot, ide_slot, usb_slot, pmu_slot, usb_dev_enable, ide_dev_enable,
pmu_dev_enable, type;
int offset;
uint8_t pci_conf[256];
uint8_t pmu_conf[256];
uint8_t usb_conf[256];
uint8_t ide_conf[256];
uint8_t pci_slot;
uint8_t ide_slot;
uint8_t usb_slot;
uint8_t pmu_slot;
uint8_t usb_dev_enable;
uint8_t ide_dev_enable;
uint8_t pmu_dev_enable;
uint8_t type;
int offset;
apm_t *apm;
acpi_t *acpi;
@@ -523,6 +532,7 @@ ali5229_ide_irq_handler(ali1543_t *dev)
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2);
break;
default:
break;
}
@@ -562,6 +572,7 @@ ali5229_ide_irq_handler(ali1543_t *dev)
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2);
break;
default:
break;
}

3
src/chipset/ali6117.c
View File

@@ -38,7 +38,8 @@ typedef struct ali6117_t {
uint32_t local;
/* Main registers (port 22h/23h) */
uint8_t unlocked, mode;
uint8_t unlocked;
uint8_t mode;
uint8_t reg_offset;
uint8_t regs[256];
} ali6117_t;

17
src/chipset/contaq_82c59x.c
View File

@@ -48,16 +48,17 @@ contaq_82c59x_log(const char *fmt, ...)
# define contaq_82c59x_log(fmt, ...)
#endif
typedef struct
{
uint32_t phys, virt;
typedef struct mem_remapping_t {
uint32_t phys;
uint32_t virt;
} mem_remapping_t;
typedef struct
{
uint8_t index, green,
smi_status_set,
regs[256], smi_status[2];
typedef struct contaq_82c59x_t {
uint8_t index;
uint8_t green;
uint8_t smi_status_set;
uint8_t regs[256];
uint8_t smi_status[2];
smram_t *smram[2];
} contaq_82c59x_t;

7
src/chipset/cs4031.c
View File

@@ -31,10 +31,9 @@
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t index,
regs[256];
typedef struct cs4031_t {
uint8_t index;
uint8_t regs[256];
port_92_t *port_92;
} cs4031_t;

23
src/chipset/cs8230.c
View File

@@ -30,8 +30,7 @@
#include <86box/fdc.h>
#include <86box/chipset.h>
typedef struct
{
typedef struct cs8230_t {
int idx;
uint8_t regs[256];
} cs8230_t;
@@ -62,9 +61,7 @@ shadow_control(uint32_t addr, uint32_t size, int state)
static void
rethink_shadow_mappings(cs8230_t *cs8230)
{
int c;
for (c = 0; c < 32; c++) {
for (uint8_t c = 0; c < 32; c++) {
/* Addresses 40000-bffff in 16k blocks */
if (cs8230->regs[0xa + (c >> 3)] & (1 << (c & 7)))
mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); /* I/O channel */
@@ -72,7 +69,7 @@ rethink_shadow_mappings(cs8230_t *cs8230)
mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /* System board */
}
for (c = 0; c < 16; c++) {
for (uint8_t c = 0; c < 16; c++) {
/* Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here */
if (cs8230->regs[0xe + (c >> 3)] & (1 << (c & 7)))
mem_set_mem_state(0xc0000 + (c << 14), 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /* I/O channel */
@@ -82,9 +79,9 @@ rethink_shadow_mappings(cs8230_t *cs8230)
}
static uint8_t
cs8230_read(uint16_t port, void *p)
cs8230_read(uint16_t port, void *priv)
{
cs8230_t *cs8230 = (cs8230_t *) p;
cs8230_t *cs8230 = (cs8230_t *) priv;
uint8_t ret = 0xff;
if (port & 1) {
@@ -115,6 +112,7 @@ cs8230_read(uint16_t port, void *p)
case 0x2a:
ret = cs8230->regs[cs8230->idx];
break;
default:
break;
}
@@ -124,9 +122,9 @@ cs8230_read(uint16_t port, void *p)
}
static void
cs8230_write(uint16_t port, uint8_t val, void *p)
cs8230_write(uint16_t port, uint8_t val, void *priv)
{
cs8230_t *cs8230 = (cs8230_t *) p;
cs8230_t *cs8230 = (cs8230_t *) priv;
if (!(port & 1))
cs8230->idx = val;
@@ -156,9 +154,8 @@ cs8230_close(void *priv)
free(cs8230);
}
static void
*
cs8230_init(UNUSED(const device_t *info))
static void *
cs8230_init(UNUSED(const device_t *info))
{
cs8230_t *cs8230 = (cs8230_t *) malloc(sizeof(cs8230_t));
memset(cs8230, 0, sizeof(cs8230_t));

6
src/chipset/et6000.c
View File

@@ -34,9 +34,9 @@
#define INDEX (dev->index - 0x10)
typedef struct
{
uint8_t index, regs[256];
typedef struct et6000_t {
uint8_t index;
uint8_t regs[256];
} et6000_t;
#ifdef ENABLE_ET6000_LOG

3
src/chipset/gc100.c
View File

@@ -44,8 +44,7 @@
#include <86box/io.h>
#include <86box/video.h>
typedef struct
{
typedef struct gc100_t {
uint8_t reg[0x10];
} gc100_t;

19
src/chipset/headland.c
View File

@@ -53,8 +53,9 @@ enum {
#define HEADLAND_HAS_CRI 0x10
#define HEADLAND_HAS_SLEEP 0x20
typedef struct {
uint8_t valid, enabled;
typedef struct headland_mr_t {
uint8_t valid;
uint8_t enabled;
uint16_t mr;
uint32_t virt_base;
@@ -63,7 +64,8 @@ typedef struct {
typedef struct headland_t {
uint8_t revision;
uint8_t has_cri, has_sleep;
uint8_t has_cri;
uint8_t has_sleep;
uint8_t cri;
uint8_t cr[7];
@@ -73,8 +75,8 @@ typedef struct headland_t {
uint8_t ems_mar;
headland_mr_t null_mr,
ems_mr[64];
headland_mr_t null_mr;
headland_mr_t ems_mr[64];
mem_mapping_t low_mapping;
mem_mapping_t ems_mapping[64];
@@ -591,7 +593,6 @@ headland_init(const device_t *info)
{
headland_t *dev;
int ht386 = 0;
uint32_t i;
dev = (headland_t *) malloc(sizeof(headland_t));
memset(dev, 0x00, sizeof(headland_t));
@@ -616,7 +617,7 @@ headland_init(const device_t *info)
dev->null_mr.mr = 0xff;
dev->null_mr.headland = dev;
for (i = 0; i < 64; i++) {
for (uint8_t i = 0; i < 64; i++) {
dev->ems_mr[i].valid = 1;
dev->ems_mr[i].mr = 0x00;
dev->ems_mr[i].headland = dev;
@@ -648,7 +649,7 @@ headland_init(const device_t *info)
mem_mapping_enable(&dev->high_mapping);
}
for (i = 0; i < 24; i++) {
for (uint8_t i = 0; i < 24; i++) {
mem_mapping_add(&dev->upper_mapping[i],
0x40000 + (i << 14), 0x4000,
mem_read_b, mem_read_w, mem_read_l,
@@ -674,7 +675,7 @@ headland_init(const device_t *info)
MEM_MAPPING_INTERNAL, &dev->null_mr);
mem_mapping_disable(&dev->shadow_mapping[1]);
for (i = 0; i < 64; i++) {
for (uint8_t i = 0; i < 64; i++) {
dev->ems_mr[i].mr = 0x00;
mem_mapping_add(&dev->ems_mapping[i],
((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14, 0x04000,

14
src/chipset/ims8848.c
View File

@@ -119,10 +119,11 @@
Bit 0: HADS# Delay After LB. Cycle (1: Enabled / 0: Disable)
*/
typedef struct
{
uint8_t idx, access_data,
regs[256], pci_conf[256];
typedef struct ims8848_t {
uint8_t idx;
uint8_t access_data;
uint8_t regs[256];
uint8_t pci_conf[256];
smram_t *smram;
} ims8848_t;
@@ -149,7 +150,6 @@ ims8848_log(const char *fmt, ...)
static void
ims8848_recalc(ims8848_t *dev)
{
int i;
int state_on;
uint32_t base;
ims8848_log("SHADOW: 00 = %02X, 08 = %02X, 1B = %02X, 1C = %02X\n",
@@ -158,7 +158,7 @@ ims8848_recalc(ims8848_t *dev)
state_on = MEM_READ_INTERNAL;
state_on |= (dev->regs[0x08] & 0x04) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
for (i = 0; i < 2; i++) {
for (uint8_t i = 0; i < 2; i++) {
base = 0xe0000 + (i << 16);
if (dev->regs[0x00] & (1 << (i + 2)))
mem_set_mem_state_both(base, 0x10000, state_on);
@@ -166,7 +166,7 @@ ims8848_recalc(ims8848_t *dev)
mem_set_mem_state_both(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
}
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
if (dev->regs[0x1c] & (1 << i))
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);

52
src/chipset/intel_420ex.c
View File

@@ -46,19 +46,20 @@
#define MEM_STATE_SHADOW_W 0x02
#define MEM_STATE_SMRAM 0x04
typedef struct
{
uint8_t has_ide, smram_locked,
regs[256];
typedef struct i420ex_t {
uint8_t has_ide;
uint8_t smram_locked;
uint8_t regs[256];
uint16_t timer_base,
timer_latch;
uint16_t timer_base;
uint16_t timer_latch;
smram_t *smram;
double fast_off_period;
pc_timer_t timer, fast_off_timer;
pc_timer_t timer;
pc_timer_t fast_off_timer;
apm_t *apm;
port_92_t *port_92;
@@ -438,42 +439,41 @@ i420ex_fast_off_count(void *priv)
}
static void
i420ex_reset(void *p)
i420ex_reset(void *priv)
{
i420ex_t *dev = (i420ex_t *) p;
int i;
i420ex_t *dev = (i420ex_t *) priv;
i420ex_write(0, 0x48, 0x00, p);
i420ex_write(0, 0x48, 0x00, priv);
/* Disable the PIC mouse latch. */
i420ex_write(0, 0x4e, 0x03, p);
i420ex_write(0, 0x4e, 0x03, priv);
for (i = 0; i < 7; i++)
i420ex_write(0, 0x59 + i, 0x00, p);
for (uint8_t i = 0; i < 7; i++)
i420ex_write(0, 0x59 + i, 0x00, priv);
for (i = 0; i <= 4; i++)
i420ex_write(0, 0x60 + i, 0x01, p);
for (uint8_t i = 0; i <= 4; i++)
i420ex_write(0, 0x60 + i, 0x01, priv);
dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */
dev->smram_locked = 0;
i420ex_write(0, 0x70, 0x00, p);
i420ex_write(0, 0x70, 0x00, priv);
mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
i420ex_write(0, 0xa0, 0x08, p);
i420ex_write(0, 0xa2, 0x00, p);
i420ex_write(0, 0xa4, 0x00, p);
i420ex_write(0, 0xa5, 0x00, p);
i420ex_write(0, 0xa6, 0x00, p);
i420ex_write(0, 0xa7, 0x00, p);
i420ex_write(0, 0xa8, 0x0f, p);
i420ex_write(0, 0xa0, 0x08, priv);
i420ex_write(0, 0xa2, 0x00, priv);
i420ex_write(0, 0xa4, 0x00, priv);
i420ex_write(0, 0xa5, 0x00, priv);
i420ex_write(0, 0xa6, 0x00, priv);
i420ex_write(0, 0xa7, 0x00, priv);
i420ex_write(0, 0xa8, 0x0f, priv);
}
static void
i420ex_close(void *p)
i420ex_close(void *priv)
{
i420ex_t *dev = (i420ex_t *) p;
i420ex_t *dev = (i420ex_t *) priv;
smram_del(dev->smram);

36
src/chipset/intel_4x0.c
View File

@@ -51,17 +51,20 @@ enum {
INTEL_440ZX
};
typedef struct
{
uint8_t pm2_cntrl,
smram_locked, max_drb,
drb_unit, drb_default;
uint8_t regs[256], regs_locked[256];
typedef struct i4x0_t {
uint8_t pm2_cntrl;
uint8_t smram_locked;
uint8_t max_drb;
uint8_t drb_unit;
uint8_t drb_default;
uint8_t regs[256];
uint8_t regs_locked[256];
uint8_t mem_state[256];
int type;
smram_t *smram_low, *smram_high;
smram_t *smram_low;
smram_t *smram_high;
agpgart_t *agpgart;
void (*write_drbs)(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit);
void (*write_drbs)(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit);
} i4x0_t;
#ifdef ENABLE_I4X0_LOG
@@ -1493,6 +1496,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
default:
break;
}
}
@@ -1518,7 +1524,6 @@ static void
i4x0_reset(void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
int i;
if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX))
memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
@@ -1528,10 +1533,10 @@ i4x0_reset(void *priv)
else
i4x0_write(0, 0x59, 0x0f, priv);
for (i = 0; i < 6; i++)
for (uint8_t i = 0; i < 6; i++)
i4x0_write(0, 0x5a + i, 0x00, priv);
for (i = 0; i <= dev->max_drb; i++)
for (uint8_t i = 0; i <= dev->max_drb; i++)
i4x0_write(0, 0x60 + i, dev->drb_default, priv);
if (dev->type >= INTEL_430FX) {
@@ -1552,9 +1557,9 @@ i4x0_reset(void *priv)
}
static void
i4x0_close(void *p)
i4x0_close(void *priv)
{
i4x0_t *dev = (i4x0_t *) p;
i4x0_t *dev = (i4x0_t *) priv;
smram_del(dev->smram_high);
smram_del(dev->smram_low);
@@ -1562,9 +1567,8 @@ i4x0_close(void *p)
free(dev);
}
static void
*
i4x0_init(const device_t *info)
static void *
i4x0_init(const device_t *info)
{
i4x0_t *dev = (i4x0_t *) malloc(sizeof(i4x0_t));
uint8_t *regs;

10
src/chipset/intel_82335.c
View File

@@ -57,12 +57,10 @@
#define DEFINE_RC1_REMAP_SIZE ((dev->regs[0x24] & 0x02) ? 128 : 256)
#define DEFINE_RC2_REMAP_SIZE ((dev->regs[0x26] & 0x02) ? 128 : 256)
typedef struct
{
typedef struct intel_82335_t {
uint16_t regs[256];
uint16_t regs[256],
cfg_locked;
uint16_t cfg_locked;
} intel_82335_t;
@@ -140,8 +138,8 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv)
shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize);
mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC);
}
break;
}
break;
default:
break;

3
src/chipset/intel_i450kx.c
View File

@@ -62,7 +62,8 @@ i450kx_log(const char *fmt, ...)
typedef struct i450kx_t {
smram_t *smram[2];
uint8_t pb_pci_conf[256], mc_pci_conf[256];
uint8_t pb_pci_conf[256];
uint8_t mc_pci_conf[256];
uint8_t mem_state[2][256];
uint8_t bus_index;

114
src/chipset/intel_piix.c
View File

@@ -51,7 +51,7 @@
#include <86box/smbus.h>
#include <86box/chipset.h>
typedef struct {
typedef struct piix_io_trap_t {
struct _piix_ *dev;
void *trap;
uint8_t dev_id;
@@ -59,14 +59,20 @@ typedef struct {
} piix_io_trap_t;
typedef struct _piix_ {
uint8_t cur_readout_reg, rev,
type, func_shift,
max_func, pci_slot,
no_mirq0, pad,
regs[4][256],
readout_regs[256], board_config[2];
uint16_t func0_id, nvr_io_base,
acpi_io_base;
uint8_t cur_readout_reg;
uint8_t rev;
uint8_t type;
uint8_t func_shift;
uint8_t max_func;
uint8_t pci_slot;
uint8_t no_mirq0;
uint8_t pad;
uint8_t regs[4][256];
uint8_t readout_regs[256];
uint8_t board_config[2];
uint16_t func0_id;
uint16_t nvr_io_base;
uint16_t acpi_io_base;
double fast_off_period;
sff8038i_t *bm[2];
smbus_piix4_t *smbus;
@@ -1449,73 +1455,73 @@ piix_usb_update_interrupt(usb_t* usb, void *priv)
}
static void
piix_reset(void *p)
piix_reset(void *priv)
{
piix_t *dev = (piix_t *) p;
piix_t *dev = (piix_t *) priv;
if (dev->type > 3) {
piix_write(3, 0x04, 0x00, p);
piix_write(3, 0x5b, 0x00, p);
piix_write(3, 0x04, 0x00, priv);
piix_write(3, 0x5b, 0x00, priv);
} else {
piix_write(0, 0xa0, 0x08, p);
piix_write(0, 0xa2, 0x00, p);
piix_write(0, 0xa4, 0x00, p);
piix_write(0, 0xa5, 0x00, p);
piix_write(0, 0xa6, 0x00, p);
piix_write(0, 0xa7, 0x00, p);
piix_write(0, 0xa8, 0x0f, p);
piix_write(0, 0xa0, 0x08, priv);
piix_write(0, 0xa2, 0x00, priv);
piix_write(0, 0xa4, 0x00, priv);
piix_write(0, 0xa5, 0x00, priv);
piix_write(0, 0xa6, 0x00, priv);
piix_write(0, 0xa7, 0x00, priv);
piix_write(0, 0xa8, 0x0f, priv);
}
/* Disable the PIC mouse latch. */
piix_write(0, 0x4e, 0x03, p);
piix_write(0, 0x4e, 0x03, priv);
if (dev->type == 5)
piix_write(0, 0xe1, 0x40, p);
piix_write(1, 0x04, 0x00, p);
piix_write(0, 0xe1, 0x40, priv);
piix_write(1, 0x04, 0x00, priv);
if (dev->type == 5) {
piix_write(1, 0x09, 0x8a, p);
piix_write(1, 0x10, 0xf1, p);
piix_write(1, 0x11, 0x01, p);
piix_write(1, 0x14, 0xf5, p);
piix_write(1, 0x15, 0x03, p);
piix_write(1, 0x18, 0x71, p);
piix_write(1, 0x19, 0x01, p);
piix_write(1, 0x1c, 0x75, p);
piix_write(1, 0x1d, 0x03, p);
piix_write(1, 0x09, 0x8a, priv);
piix_write(1, 0x10, 0xf1, priv);
piix_write(1, 0x11, 0x01, priv);
piix_write(1, 0x14, 0xf5, priv);
piix_write(1, 0x15, 0x03, priv);
piix_write(1, 0x18, 0x71, priv);
piix_write(1, 0x19, 0x01, priv);
piix_write(1, 0x1c, 0x75, priv);
piix_write(1, 0x1d, 0x03, priv);
} else
piix_write(1, 0x09, 0x80, p);
piix_write(1, 0x20, 0x01, p);
piix_write(1, 0x21, 0x00, p);
piix_write(1, 0x41, 0x00, p);
piix_write(1, 0x43, 0x00, p);
piix_write(1, 0x09, 0x80, priv);
piix_write(1, 0x20, 0x01, priv);
piix_write(1, 0x21, 0x00, priv);
piix_write(1, 0x41, 0x00, priv);
piix_write(1, 0x43, 0x00, priv);
ide_pri_disable();
ide_sec_disable();
if (dev->type >= 3) {
piix_write(2, 0x04, 0x00, p);
piix_write(2, 0x04, 0x00, priv);
if (dev->type == 5) {
piix_write(2, 0x10, 0x00, p);
piix_write(2, 0x11, 0x00, p);
piix_write(2, 0x12, 0x00, p);
piix_write(2, 0x13, 0x00, p);
piix_write(2, 0x10, 0x00, priv);
piix_write(2, 0x11, 0x00, priv);
piix_write(2, 0x12, 0x00, priv);
piix_write(2, 0x13, 0x00, priv);
} else {
piix_write(2, 0x20, 0x01, p);
piix_write(2, 0x21, 0x00, p);
piix_write(2, 0x22, 0x00, p);
piix_write(2, 0x23, 0x00, p);
piix_write(2, 0x20, 0x01, priv);
piix_write(2, 0x21, 0x00, priv);
piix_write(2, 0x22, 0x00, priv);
piix_write(2, 0x23, 0x00, priv);
}
}
if (dev->type >= 4) {
piix_write(0, 0xb0, is_pentium ? 0x00 : 0x04, p);
piix_write(3, 0x40, 0x01, p);
piix_write(3, 0x41, 0x00, p);
piix_write(3, 0x5b, 0x00, p);
piix_write(3, 0x80, 0x00, p);
piix_write(3, 0x90, 0x01, p);
piix_write(3, 0x91, 0x00, p);
piix_write(3, 0xd2, 0x00, p);
piix_write(0, 0xb0, is_pentium ? 0x00 : 0x04, priv);
piix_write(3, 0x40, 0x01, priv);
piix_write(3, 0x41, 0x00, priv);
piix_write(3, 0x5b, 0x00, priv);
piix_write(3, 0x80, 0x00, priv);
piix_write(3, 0x90, 0x01, priv);
piix_write(3, 0x91, 0x00, priv);
piix_write(3, 0xd2, 0x00, priv);
}
sff_set_irq_mode(dev->bm[0], 0, 0);

53
src/chipset/intel_sio.c
View File

@@ -33,18 +33,19 @@
#include <86box/port_92.h>
#include <86box/machine.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
typedef struct
{
uint8_t id,
regs[256];
typedef struct sio_t {
uint8_t id;
uint8_t regs[256];
uint16_t timer_base,
timer_latch;
uint16_t timer_base;
uint16_t timer_latch;
double fast_off_period;
pc_timer_t timer, fast_off_timer;
pc_timer_t timer;
pc_timer_t fast_off_timer;
apm_t *apm;
port_92_t *port_92;
@@ -335,12 +336,13 @@ sio_read(int func, int addr, void *priv)
}
static void
sio_config_write(uint16_t addr, uint8_t val, void *priv)
sio_config_write(UNUSED(uint16_t addr), UNUSED(uint8_t val), UNUSED(void *priv))
{
//
}
static uint8_t
sio_config_read(uint16_t port, void *priv)
sio_config_read(uint16_t port, UNUSED(void *priv))
{
uint8_t ret = 0x00;
@@ -367,6 +369,9 @@ sio_config_read(uint16_t port, void *priv)
break;
}
break;
default:
break;
}
return ret;
@@ -427,9 +432,9 @@ sio_reset_hard(void *priv)
}
static void
sio_apm_out(uint16_t port, uint8_t val, void *p)
sio_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
{
sio_t *dev = (sio_t *) p;
sio_t *dev = (sio_t *) priv;
if (dev->apm->do_smi)
dev->regs[0xaa] |= 0x80;
@@ -445,32 +450,32 @@ sio_fast_off_count(void *priv)
}
static void
sio_reset(void *p)
sio_reset(void *priv)
{
sio_t *dev = (sio_t *) p;
sio_t *dev = (sio_t *) priv;
/* Disable the PIC mouse latch. */
sio_write(0, 0x4d, 0x40, p);
sio_write(0, 0x4d, 0x40, priv);
sio_write(0, 0x57, 0x04, p);
sio_write(0, 0x57, 0x04, priv);
dma_set_params(1, 0xffffffff);
if (dev->id == 0x03) {
sio_write(0, 0xa0, 0x08, p);
sio_write(0, 0xa2, 0x00, p);
sio_write(0, 0xa4, 0x00, p);
sio_write(0, 0xa5, 0x00, p);
sio_write(0, 0xa6, 0x00, p);
sio_write(0, 0xa7, 0x00, p);
sio_write(0, 0xa8, 0x0f, p);
sio_write(0, 0xa0, 0x08, priv);
sio_write(0, 0xa2, 0x00, priv);
sio_write(0, 0xa4, 0x00, priv);
sio_write(0, 0xa5, 0x00, priv);
sio_write(0, 0xa6, 0x00, priv);
sio_write(0, 0xa7, 0x00, priv);
sio_write(0, 0xa8, 0x0f, priv);
}
}
static void
sio_close(void *p)
sio_close(void *priv)
{
sio_t *dev = (sio_t *) p;
sio_t *dev = (sio_t *) priv;
free(dev);
}

63
src/chipset/neat.c
View File

@@ -201,7 +201,7 @@
#define RB11_EMSLEN 0xe0 /* EMS memory chunk size */
#define RB11_EMSLEN_SH 5
typedef struct {
typedef struct emspage_t {
int8_t enabled; /* 1=ENABLED */
char pad;
uint16_t page; /* selected page in EMS block */
@@ -210,18 +210,18 @@ typedef struct {
mem_mapping_t mapping; /* mapping entry for page */
} emspage_t;
typedef struct {
typedef struct neat_t {
uint8_t regs[128]; /* all the CS8221 registers */
uint8_t indx; /* programmed index into registers */
char pad;
uint16_t ems_base, /* configured base address */
ems_oldbase;
uint32_t ems_frame, /* configured frame address */
ems_oldframe;
uint16_t ems_size, /* EMS size in KB */
ems_pages; /* EMS size in pages */
uint16_t ems_base; /* configured base address */
uint16_t ems_oldbase;
uint32_t ems_frame; /* configured frame address */
uint32_t ems_oldframe;
uint16_t ems_size; /* EMS size in KB */
uint16_t ems_pages; /* EMS size in pages */
emspage_t ems[EMS_MAXPAGE]; /* EMS page registers */
} neat_t;
@@ -377,12 +377,12 @@ ems_read(uint16_t port, void *priv)
static void
ems_init(neat_t *dev, int en)
{
int i;
uint8_t j;
/* Remove if needed. */
if (!en) {
if (dev->ems_base > 0)
for (i = 0; i < EMS_MAXPAGE; i++) {
for (uint8_t i = 0; i < EMS_MAXPAGE; i++) {
/* Disable for now. */
mem_mapping_disable(&dev->ems[i].mapping);
@@ -399,19 +399,19 @@ ems_init(neat_t *dev, int en)
}
/* Get configured I/O address. */
i = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH;
dev->ems_base = 0x0208 + (0x10 * i);
j = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH;
dev->ems_base = 0x0208 + (0x10 * j);
/* Get configured frame address. */
i = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH;
dev->ems_frame = 0xC0000 + (EMS_PGSIZE * i);
j = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH;
dev->ems_frame = 0xC0000 + (EMS_PGSIZE * j);
/*
* For each supported page (we can have a maximum of 4),
* create, initialize and disable the mappings, and set
* up the I/O control handler.
*/
for (i = 0; i < EMS_MAXPAGE; i++) {
for (uint8_t i = 0; i < EMS_MAXPAGE; i++) {
/* Create and initialize a page mapping. */
mem_mapping_add(&dev->ems[i].mapping,
dev->ems_frame + (EMS_PGSIZE * i), EMS_PGSIZE,
@@ -672,14 +672,14 @@ static void *
neat_init(UNUSED(const device_t *info))
{
neat_t *dev;
int i;
uint8_t dram_mode = 0;
/* Create an instance. */
dev = (neat_t *) malloc(sizeof(neat_t));
memset(dev, 0x00, sizeof(neat_t));
/* Initialize some of the registers to specific defaults. */
for (i = REG_RA0; i <= REG_RB11; i++) {
for (uint8_t i = REG_RA0; i <= REG_RB11; i++) {
dev->indx = i;
neat_write(0x0023, 0x00, dev);
}
@@ -691,7 +691,6 @@ neat_init(UNUSED(const device_t *info))
* TODO: We might also want to set 'valid' waitstate
* bits, based on our cpu speed.
*/
i = 0;
switch (mem_size) {
case 512: /* 512KB */
/* 256K, 0, 0, 0 */
@@ -699,7 +698,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
i = 2;
dram_mode = 2;
break;
case 640: /* 640KB */
@@ -708,7 +707,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
i = 4;
dram_mode = 4;
break;
case 1024: /* 1MB */
@@ -717,7 +716,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
i = 5;
dram_mode = 5;
break;
case 1536: /* 1.5MB */
@@ -726,7 +725,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */
i = 7;
dram_mode = 7;
break;
case 1664: /* 1.64MB */
@@ -735,7 +734,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */
i = 10;
dram_mode = 10;
break;
case 2048: /* 2MB */
@@ -746,14 +745,14 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */
i = 11;
dram_mode = 11;
#else
/* 1M, 0, 0, 0 */
dev->regs[REG_RB6] &= ~RB6_BANKS; /* one bank */
dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
i = 3;
dram_mode = 3;
#endif
break;
@@ -763,7 +762,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
i = 8;
dram_mode = 8;
break;
case 4096: /* 4MB */
@@ -772,7 +771,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
i = 6;
dram_mode = 6;
break;
case 4224: /* 4.64MB */
@@ -781,7 +780,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
i = 12;
dram_mode = 12;
break;
case 5120: /* 5MB */
@@ -790,7 +789,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
i = 13;
dram_mode = 13;
break;
case 6144: /* 6MB */
@@ -799,7 +798,7 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
i = 9;
dram_mode = 9;
break;
case 8192: /* 8MB */
@@ -809,13 +808,13 @@ neat_init(UNUSED(const device_t *info))
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */
i = 14;
dram_mode = 14;
break;
default:
neat_log("NEAT: **INVALID DRAM SIZE %iKB !**\n", mem_size);
}
if (i > 0) {
if (dram_mode > 0) {
neat_log("NEAT: using DRAM mode #%i (mem=%iKB)\n", i, mem_size);
}

3
src/chipset/olivetti_eva.c
View File

@@ -34,8 +34,7 @@
#include <86box/mem.h>
#include <86box/plat_unused.h>
typedef struct
{
typedef struct olivetti_eva_t {
uint8_t reg_065;
uint8_t reg_067;
uint8_t reg_069;

16
src/chipset/opti283.c
View File

@@ -50,15 +50,15 @@ opti283_log(const char *fmt, ...)
# define opti283_log(fmt, ...)
#endif
typedef struct
{
uint32_t phys, virt;
typedef struct mem_remapping_t {
uint32_t phys;
uint32_t virt;
} mem_remapping_t;
typedef struct
{
uint8_t index, shadow_high,
regs[256];
typedef struct opti283_t {
uint8_t index;
uint8_t shadow_high;
uint8_t regs[256];
mem_remapping_t mem_remappings[2];
mem_mapping_t mem_mappings[2];
} opti283_t;
@@ -235,10 +235,12 @@ opti283_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[dev->index] = val;
opti283_shadow_recalc(dev);
break;
default:
break;
}
break;
default:
break;
}

8
src/chipset/opti291.c
View File

@@ -50,9 +50,9 @@ opti291_log(const char *fmt, ...)
# define opti291_log(fmt, ...)
#endif
typedef struct
{
uint8_t index, regs[256];
typedef struct opti291_t {
uint8_t index;
uint8_t regs[256];
port_92_t *port_92;
} opti291_t;
@@ -108,10 +108,12 @@ opti291_write(uint16_t addr, uint8_t val, void *priv)
case 0x2c:
dev->regs[dev->index] = val;
break;
default:
break;
}
break;
default:
break;
}

19
src/chipset/opti391.c
View File

@@ -48,20 +48,19 @@ opti391_log(const char *fmt, ...)
# define opti391_log(fmt, ...)
#endif
typedef struct
{
uint32_t phys, virt;
typedef struct mem_remapping_t {
uint32_t phys;
uint32_t virt;
} mem_remapping_t;
typedef struct
{
uint8_t index, regs[256];
typedef struct opti391_t {
uint8_t index;
uint8_t regs[256];
} opti391_t;
static void
opti391_shadow_recalc(opti391_t *dev)
{
uint32_t i;
uint32_t base;
uint8_t sh_enable;
uint8_t sh_master;
@@ -79,7 +78,7 @@ opti391_shadow_recalc(opti391_t *dev)
sh_write_internal = (dev->regs[0x26] & 0x40);
/* D0000-EFFFF */
for (i = 0; i < 8; i++) {
for (uint8_t i = 0; i < 8; i++) {
base = 0xd0000 + (i << 14);
if (base >= 0xe0000) {
sh_master = (dev->regs[0x22] & 0x40);
@@ -109,7 +108,7 @@ opti391_shadow_recalc(opti391_t *dev)
/* C0000-CFFFF */
sh_master = !(dev->regs[0x26] & 0x10);
sh_wp = (dev->regs[0x26] & 0x20);
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
sh_enable = dev->regs[0x26] & (1 << i);
@@ -165,10 +164,12 @@ opti391_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[dev->index] = val;
opti391_shadow_recalc(dev);
break;
default:
break;
}
break;
default:
break;
}

14
src/chipset/opti495.c
View File

@@ -31,11 +31,10 @@
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t idx,
regs[256],
scratch[2];
typedef struct opti495_t {
uint8_t idx;
uint8_t regs[256];
uint8_t scratch[2];
} opti495_t;
#ifdef ENABLE_OPTI495_LOG
@@ -60,7 +59,6 @@ static void
opti495_recalc(opti495_t *dev)
{
uint32_t base;
uint32_t i;
uint32_t shflags = 0;
shadowbios = 0;
@@ -78,7 +76,7 @@ opti495_recalc(opti495_t *dev)
mem_set_mem_state_both(0xf0000, 0x10000, shflags);
for (i = 0; i < 8; i++) {
for (uint8_t i = 0; i < 8; i++) {
base = 0xd0000 + (i << 14);
if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && (dev->regs[0x23] & (1 << i))) {
@@ -95,7 +93,7 @@ opti495_recalc(opti495_t *dev)
mem_set_mem_state_both(base, 0x4000, shflags);
}
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) {

14
src/chipset/opti499.c
View File

@@ -32,10 +32,10 @@
#include <86box/plat_unused.h>
#include <86box/chipset.h>
typedef struct
{
typedef struct opti499_t {
uint8_t idx,
regs[256], scratch[2];
uint8_t regs[256];
uint8_t scratch[2];
} opti499_t;
#ifdef ENABLE_OPTI499_LOG
@@ -60,7 +60,6 @@ static void
opti499_recalc(opti499_t *dev)
{
uint32_t base;
uint32_t i;
uint32_t shflags = 0;
shadowbios = 0;
@@ -78,7 +77,7 @@ opti499_recalc(opti499_t *dev)
mem_set_mem_state_both(0xf0000, 0x10000, shflags);
for (i = 0; i < 8; i++) {
for (uint8_t i = 0; i < 8; i++) {
base = 0xd0000 + (i << 14);
if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && (dev->regs[0x23] & (1 << i))) {
@@ -94,7 +93,7 @@ opti499_recalc(opti499_t *dev)
mem_set_mem_state_both(base, 0x4000, shflags);
}
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) {
@@ -155,6 +154,7 @@ opti499_write(uint16_t addr, uint8_t val, void *priv)
case 0x2d:
opti499_recalc(dev);
break;
default:
break;
}
@@ -165,6 +165,7 @@ opti499_write(uint16_t addr, uint8_t val, void *priv)
case 0xe2:
dev->scratch[~addr & 0x01] = val;
break;
default:
break;
}
@@ -193,6 +194,7 @@ opti499_read(uint16_t addr, void *priv)
case 0xe2:
ret = dev->scratch[~addr & 0x01];
break;
default:
break;
}

10
src/chipset/opti5x7.c
View File

@@ -32,10 +32,10 @@
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t idx, is_pci,
regs[16];
typedef struct opti5x7_t {
uint8_t idx;
uint8_t is_pci;
uint8_t regs[16];
} opti5x7_t;
#ifdef ENABLE_OPTI5X7_LOG
@@ -84,7 +84,7 @@ opti5x7_shadow_map(int cur_reg, opti5x7_t *dev)
mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[6] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
}
} else {
for (int i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
if (dev->is_pci)
mem_set_mem_state_cpu_both(0xc0000 + ((cur_reg & 1) << 16) + (i << 14), 0x4000, ((dev->regs[cur_reg] & (1 << (2 * i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[cur_reg] & (2 << (2 * i))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
else

8
src/chipset/opti822.c
View File

@@ -41,10 +41,9 @@
#include <86box/chipset.h>
#include <86box/spd.h>
typedef struct
{
uint8_t irq_convert,
pci_regs[256];
typedef struct opti822_t {
uint8_t irq_convert;
uint8_t pci_regs[256];
} opti822_t;
// #define ENABLE_OPTI822_LOG 1
@@ -328,6 +327,7 @@ opti822_pci_write(int func, int addr, uint8_t val, void *priv)
}
opti822_update_irqs(dev, 1);
break;
default:
break;
}

20
src/chipset/opti895.c
View File

@@ -32,12 +32,12 @@
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t idx, forced_green,
is_pci,
regs[256],
scratch[2];
typedef struct opti895_t {
uint8_t idx;
uint8_t forced_green;
uint8_t is_pci;
uint8_t regs[256];
uint8_t scratch[2];
smram_t *smram;
} opti895_t;
@@ -64,7 +64,6 @@ static void
opti895_recalc(opti895_t *dev)
{
uint32_t base;
uint32_t i;
uint32_t shflags = 0;
shadowbios = 0;
@@ -85,7 +84,7 @@ opti895_recalc(opti895_t *dev)
else
mem_set_mem_state_both(0xf0000, 0x10000, shflags);
for (i = 0; i < 8; i++) {
for (uint8_t i = 0; i < 8; i++) {
base = 0xd0000 + (i << 14);
if (dev->regs[0x23] & (1 << i)) {
@@ -109,7 +108,7 @@ opti895_recalc(opti895_t *dev)
mem_set_mem_state_both(base, 0x4000, shflags);
}
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
if (dev->regs[0x26] & (1 << i)) {
@@ -185,6 +184,7 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
break;
}
break;
default:
break;
}
@@ -195,6 +195,7 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
case 0xe2:
dev->scratch[addr - 0xe1] = val;
break;
default:
break;
}
@@ -222,6 +223,7 @@ opti895_read(uint16_t addr, void *priv)
case 0xe2:
ret = dev->scratch[addr - 0xe1];
break;
default:
break;
}

48
src/chipset/scamp.c
View File

@@ -67,20 +67,21 @@ enum {
BANK_4M_INTERLEAVED
};
typedef struct {
typedef struct ram_struct_t {
void *parent;
int bank;
} ram_struct_t;
typedef struct {
typedef struct ems_struct_t {
void *parent;
int segment;
} ems_struct_t;
typedef struct {
typedef struct scamp_t {
int cfg_index;
uint8_t cfg_regs[256];
int cfg_enable, ram_config;
int cfg_enable;
int ram_config;
int ems_index;
int ems_autoinc;
@@ -92,21 +93,23 @@ typedef struct {
ram_struct_t ram_struct[2];
ems_struct_t ems_struct[20];
uint32_t ram_virt_base[2], ram_phys_base[2];
uint32_t ram_virt_base[2];
uint32_t ram_phys_base[2];
uint32_t ram_mask[2];
int row_virt_shift[2], row_phys_shift[2];
int ram_interleaved[2], ibank_shift[2];
int row_virt_shift[2];
int row_phys_shift[2];
int ram_interleaved[2];
int ibank_shift[2];
port_92_t *port_92;
} scamp_t;
static const struct
{
static const struct {
int size_kb;
int rammap;
int bank[2];
} ram_configs[] = {
{512, 0x0, { BANK_256K, BANK_NONE } },
{ 512, 0x0, { BANK_256K, BANK_NONE } },
{ 1024, 0x1, { BANK_256K_INTERLEAVED, BANK_NONE } },
{ 1536, 0x2, { BANK_256K_INTERLEAVED, BANK_256K } },
{ 2048, 0x3, { BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED }},
@@ -119,12 +122,11 @@ static const struct
{ 16384, 0x9, { BANK_4M_INTERLEAVED, BANK_NONE } },
};
static const struct
{
static const struct {
int bank[2];
int remapped;
} rammap[16] = {
{{ BANK_256K, BANK_NONE }, 0},
{ { BANK_256K, BANK_NONE }, 0},
{ { BANK_256K_INTERLEAVED, BANK_NONE }, 0},
{ { BANK_256K_INTERLEAVED, BANK_256K }, 0},
{ { BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED }, 0},
@@ -425,6 +427,7 @@ recalc_mappings(void *priv)
virt_base += (1 << 24);
dev->row_virt_shift[bank_nr] = 12;
break;
default:
break;
}
@@ -492,6 +495,7 @@ recalc_mappings(void *priv)
virt_base += (1 << 24);
dev->row_virt_shift[bank_nr] = 12;
break;
default:
break;
}
@@ -539,6 +543,7 @@ recalc_mappings(void *priv)
ram_mirrored_interleaved_write, NULL, NULL);
}
break;
default:
break;
}
@@ -591,7 +596,6 @@ scamp_ems_write(uint32_t addr, uint8_t val, void *priv)
static void
recalc_ems(scamp_t *dev)
{
int segment;
const uint32_t ems_base[12] = {
0xc0000, 0xc4000, 0xc8000, 0xcc000,
0xd0000, 0xd4000, 0xd8000, 0xdc000,
@@ -600,7 +604,7 @@ recalc_ems(scamp_t *dev)
uint32_t new_mappings[20];
uint16_t ems_enable;
for (segment = 0; segment < 20; segment++)
for (int segment = 0; segment < 20; segment++)
new_mappings[segment] = 0xa0000 + segment * 0x4000;
if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB)
@@ -608,7 +612,7 @@ recalc_ems(scamp_t *dev)
else
ems_enable = 0;
for (segment = 0; segment < 12; segment++) {
for (int segment = 0; segment < 12; segment++) {
if (ems_enable & (1 << segment)) {
uint32_t phys_addr = dev->ems[segment] << 14;
@@ -620,7 +624,7 @@ recalc_ems(scamp_t *dev)
}
}
for (segment = 0; segment < 20; segment++) {
for (int segment = 0; segment < 20; segment++) {
if (new_mappings[segment] != dev->mappings[segment]) {
dev->mappings[segment] = new_mappings[segment];
if (new_mappings[segment] < (mem_size * 1024)) {
@@ -778,6 +782,7 @@ scamp_write(uint16_t addr, uint8_t val, void *priv)
mem_a20_recalc();
}
break;
default:
break;
}
@@ -822,6 +827,7 @@ scamp_read(uint16_t addr, void *priv)
softresetx86();
cpu_set_edx();
break;
default:
break;
}
@@ -841,7 +847,6 @@ static void *
scamp_init(UNUSED(const device_t *info))
{
uint32_t addr;
int c;
scamp_t *dev = (scamp_t *) malloc(sizeof(scamp_t));
memset(dev, 0x00, sizeof(scamp_t));
@@ -862,7 +867,7 @@ scamp_init(UNUSED(const device_t *info))
dev->ram_config = 0;
/* Find best fit configuration for the requested memory size */
for (c = 0; c < NR_ELEMS(ram_configs); c++) {
for (uint8_t c = 0; c < NR_ELEMS(ram_configs); c++) {
if (mem_size < ram_configs[c].size_kb)
break;
@@ -878,7 +883,7 @@ scamp_init(UNUSED(const device_t *info))
mem_mapping_set_exec(&ram_mid_mapping, ram + 0xf0000);
addr = 0;
for (c = 0; c < 2; c++) {
for (uint8_t c = 0; c < 2; c++) {
dev->ram_struct[c].parent = dev;
dev->ram_struct[c].bank = c;
mem_mapping_add(&dev->ram_mapping[c], 0, 0,
@@ -939,6 +944,7 @@ scamp_init(UNUSED(const device_t *info))
dev->ibank_shift[c] = 23;
dev->ram_interleaved[c] = 1;
break;
default:
break;
}
@@ -946,7 +952,7 @@ scamp_init(UNUSED(const device_t *info))
mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
for (c = 0; c < 20; c++) {
for (uint8_t c = 0; c < 20; c++) {
dev->ems_struct[c].parent = dev;
dev->ems_struct[c].segment = c;
mem_mapping_add(&dev->ems_mappings[c],

75
src/chipset/scat.c
View File

@@ -55,8 +55,9 @@
#define SCATSX_HIGH_PERFORMANCE_REFRESH 0x63
#define SCATSX_CAS_TIMING_FOR_DMA 0x64
typedef struct {
uint8_t valid, pad;
typedef struct ems_page_t {
uint8_t valid;
uint8_t pad;
uint8_t regs_2x8;
uint8_t regs_2x9;
@@ -75,7 +76,8 @@ typedef struct scat_t {
int external_is_RAS;
ems_page_t null_page, page[32];
ems_page_t null_page;
ems_page_t page[32];
mem_mapping_t low_mapping[32];
mem_mapping_t remap_mapping[6];
@@ -931,9 +933,8 @@ static void
memmap_state_update(scat_t *dev)
{
uint32_t addr;
int i;
for (i = (((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0 : 16); i < 44; i++) {
for (uint8_t i = (((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0 : 16); i < 44; i++) {
addr = get_addr(dev, 0x40000 + (i << 14), &dev->null_page);
mem_mapping_set_exec(&dev->efff_mapping[i],
addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
@@ -947,37 +948,40 @@ memmap_state_update(scat_t *dev)
mem_mapping_set_exec(&dev->low_mapping[1],
addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
for (i = 2; i < 32; i++) {
for (uint8_t i = 2; i < 32; i++) {
addr = get_addr(dev, i << 19, &dev->null_page);
mem_mapping_set_exec(&dev->low_mapping[i],
addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
}
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) {
for (i = 0; i < max_map[(dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2)]; i++)
mem_mapping_enable(&dev->low_mapping[i]);
uint8_t j = 0;
for (; i < 32; i++)
mem_mapping_disable(&dev->low_mapping[i]);
for (j = 0; j < max_map[(dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2)]; j++)
mem_mapping_enable(&dev->low_mapping[j]);
for (i = 24; i < 36; i++) {
for (; j < 32; j++)
mem_mapping_disable(&dev->low_mapping[j]);
for (j = 24; j < 36; j++) {
if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40)) < 4)
mem_mapping_disable(&dev->efff_mapping[i]);
mem_mapping_disable(&dev->efff_mapping[j]);
else
mem_mapping_enable(&dev->efff_mapping[i]);
mem_mapping_enable(&dev->efff_mapping[j]);
}
} else {
for (i = 0; i < max_map_sx[dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f]; i++)
mem_mapping_enable(&dev->low_mapping[i]);
uint8_t j = 0;
for (j = 0; j < max_map_sx[dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f]; j++)
mem_mapping_enable(&dev->low_mapping[j]);
for (; i < 32; i++)
mem_mapping_disable(&dev->low_mapping[i]);
for (; j < 32; j++)
mem_mapping_disable(&dev->low_mapping[j]);
for (i = 24; i < 36; i++) {
for (j = 24; j < 36; j++) {
if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 2 || (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)
mem_mapping_disable(&dev->efff_mapping[i]);
mem_mapping_disable(&dev->efff_mapping[j]);
else
mem_mapping_enable(&dev->efff_mapping[i]);
mem_mapping_enable(&dev->efff_mapping[j]);
}
}
@@ -985,21 +989,21 @@ memmap_state_update(scat_t *dev)
if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)) {
mem_mapping_disable(&dev->low_mapping[2]);
for (i = 0; i < 6; i++) {
for (uint8_t i = 0; i < 6; i++) {
addr = get_addr(dev, 0x100000 + (i << 16), &dev->null_page);
mem_mapping_set_exec(&dev->remap_mapping[i],
addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
mem_mapping_enable(&dev->remap_mapping[i]);
}
} else {
for (i = 0; i < 6; i++)
for (uint8_t i = 0; i < 6; i++)
mem_mapping_disable(&dev->remap_mapping[i]);
if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) > 4) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) > 3))
mem_mapping_enable(&dev->low_mapping[2]);
}
} else {
for (i = 0; i < 6; i++)
for (uint8_t i = 0; i < 6; i++)
mem_mapping_disable(&dev->remap_mapping[i]);
mem_mapping_enable(&dev->low_mapping[2]);
@@ -1191,6 +1195,7 @@ scat_out(uint16_t port, uint8_t val, void *priv)
if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
dev->reg_2xA = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? val : val & 0xc3;
break;
default:
break;
}
@@ -1378,7 +1383,7 @@ static void *
scat_init(const device_t *info)
{
scat_t *dev;
uint32_t i;
uint32_t j;
uint32_t k;
int sx;
@@ -1388,7 +1393,7 @@ scat_init(const device_t *info)
sx = (dev->type == 32) ? 1 : 0;
for (i = 0; i < sizeof(dev->regs); i++)
for (uint32_t i = 0; i < sizeof(dev->regs); i++)
dev->regs[i] = 0xff;
if (sx) {
@@ -1449,7 +1454,7 @@ scat_init(const device_t *info)
mem_write_scatb, mem_write_scatw, mem_write_scatl,
ram + 0xf0000, MEM_MAPPING_INTERNAL, &dev->null_page);
for (i = 2; i < 32; i++) {
for (uint8_t i = 2; i < 32; i++) {
mem_mapping_add(&dev->low_mapping[i], (i << 19), 0x80000,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,
@@ -1457,27 +1462,27 @@ scat_init(const device_t *info)
}
if (sx) {
i = 16;
j = 16;
k = 0x40000;
} else {
i = 0;
j = 0;
k = (dev->regs[SCAT_VERSION] < 4) ? 0x40000 : 0x60000;
}
mem_mapping_set_addr(&dev->low_mapping[31], 0xf80000, k);
for (; i < 44; i++) {
mem_mapping_add(&dev->efff_mapping[i], 0x40000 + (i << 14), 0x4000,
for (; j < 44; j++) {
mem_mapping_add(&dev->efff_mapping[j], 0x40000 + (j << 14), 0x4000,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,
mem_size > (256 + (i << 4)) ? ram + 0x40000 + (i << 14) : NULL,
mem_size > (256 + (j << 4)) ? ram + 0x40000 + (j << 14) : NULL,
MEM_MAPPING_INTERNAL, &dev->null_page);
if (sx)
mem_mapping_enable(&dev->efff_mapping[i]);
mem_mapping_enable(&dev->efff_mapping[j]);
}
if (sx) {
for (i = 24; i < 32; i++) {
for (uint8_t i = 24; i < 32; i++) {
dev->page[i].valid = 1;
dev->page[i].regs_2x8 = 0xff;
dev->page[i].regs_2x9 = 0x03;
@@ -1489,7 +1494,7 @@ scat_init(const device_t *info)
mem_mapping_disable(&dev->ems_mapping[i]);
}
} else {
for (i = 0; i < 32; i++) {
for (uint8_t i = 0; i < 32; i++) {
dev->page[i].valid = 1;
dev->page[i].regs_2x8 = 0xff;
dev->page[i].regs_2x9 = 0x03;
@@ -1502,7 +1507,7 @@ scat_init(const device_t *info)
}
}
for (i = 0; i < 6; i++) {
for (uint8_t i = 0; i < 6; i++) {
mem_mapping_add(&dev->remap_mapping[i], 0x100000 + (i << 16), 0x10000,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,

17
src/chipset/sis_5511.c
View File

@@ -66,10 +66,13 @@ sis_5511_log(const char *fmt, ...)
#endif
typedef struct sis_5511_t {
uint8_t pci_conf[256], pci_conf_sb[2][256],
index, regs[16];
uint8_t pci_conf[256];
uint8_t pci_conf_sb[2][256];
uint8_t index;
uint8_t regs[16];
int nb_pci_slot, sb_pci_slot;
int nb_pci_slot;
int sb_pci_slot;
sff8038i_t *ide_drive[2];
smram_t *smram;
@@ -122,6 +125,7 @@ sis_5511_smram_recalc(sis_5511_t *dev)
case 2:
smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1);
break;
default:
break;
}
@@ -334,6 +338,7 @@ sis_5511_write(UNUSED(int func), int addr, uint8_t val, void *priv)
case 0x93: /* 5512 General Purpose Register Index */
dev->pci_conf[addr] = val;
break;
default:
break;
}
@@ -433,6 +438,7 @@ sis_5513_pci_to_isa_write(int addr, uint8_t val, sis_5511_t *dev)
case 0x6a: /* GPIO Status Register */
dev->pci_conf_sb[0][addr] &= val & 0x15;
break;
default:
break;
}
@@ -521,6 +527,7 @@ sis_5513_ide_write(int addr, uint8_t val, sis_5511_t *dev)
case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */
dev->pci_conf_sb[1][addr] = val;
break;
default:
break;
}
@@ -537,6 +544,7 @@ sis_5513_write(int func, int addr, uint8_t val, void *priv)
case 1:
sis_5513_ide_write(addr, val, dev);
break;
default:
break;
}
@@ -578,6 +586,7 @@ sis_5513_isa_write(uint16_t addr, uint8_t val, void *priv)
case 2:
cpu_set_isa_pci_div(3);
break;
default:
break;
}
@@ -600,11 +609,13 @@ sis_5513_isa_write(uint16_t addr, uint8_t val, void *priv)
case 0x0b:
dev->regs[dev->index] = val;
break;
default:
break;
}
sis_5511_log("SiS 5513-ISA: dev->regs[%02x] = %02x POST: %02x\n", dev->index + 0x50, dev->regs[dev->index], inb(0x80));
break;
default:
break;
}

17
src/chipset/sis_5571.c
View File

@@ -75,9 +75,11 @@ sis_5571_log(const char *fmt, ...)
#endif
typedef struct sis_5571_t {
uint8_t pci_conf[256], pci_conf_sb[3][256];
uint8_t pci_conf[256];
uint8_t pci_conf_sb[3][256];
int nb_pci_slot, sb_pci_slot;
int nb_pci_slot;
int sb_pci_slot;
port_92_t *port_92;
sff8038i_t *ide_drive[2];
@@ -118,6 +120,7 @@ sis_5571_smm_recalc(sis_5571_t *dev)
case 0x03:
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x10000, (dev->pci_conf[0xa3] & 0x10), 1);
break;
default:
break;
}
@@ -327,6 +330,7 @@ memory_pci_bridge_write(UNUSED(int func), int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0xd0;
sis_5571_smm_recalc(dev);
break;
default:
break;
}
@@ -380,6 +384,7 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
case 2:
cpu_set_isa_pci_div(3);
break;
default:
break;
}
@@ -505,6 +510,7 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x77: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */
dev->pci_conf_sb[0][addr] = val;
break;
default:
break;
}
@@ -586,6 +592,7 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */
dev->pci_conf_sb[1][addr] = val;
break;
default:
break;
}
@@ -626,10 +633,14 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x3c: /* Interrupt Line */
dev->pci_conf_sb[2][addr] = val;
break;
default:
break;
}
sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] = %02x\n", addr, val);
default:
break;
}
}
@@ -648,6 +659,7 @@ pci_isa_bridge_read(int func, int addr, void *priv)
case 2:
sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[2][addr]);
return dev->pci_conf_sb[2][addr];
default:
return 0xff;
}
@@ -667,6 +679,7 @@ sis_5571_usb_update_interrupt(usb_t* usb, void* priv)
case 0x08:
case 0x0d:
break;
default:
if (usb->irq_level)
picint(1 << dev->pci_conf_sb[0][0x68] & 0x0f);

9
src/chipset/sis_85c310.c
View File

@@ -13,10 +13,10 @@
#include <86box/plat_unused.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t cur_reg, tries,
regs[258];
typedef struct rabbit_t {
uint8_t cur_reg;
uint8_t tries;
uint8_t regs[258];
} rabbit_t;
static void
@@ -111,6 +111,7 @@ rabbit_read(uint16_t addr, void *priv)
} else
ret = dev->regs[dev->cur_reg];
break;
default:
break;
}

9
src/chipset/sis_85c496.c
View File

@@ -40,9 +40,10 @@
#include <86box/spd.h>
typedef struct sis_85c496_t {
uint8_t cur_reg, rmsmiblk_count,
regs[127],
pci_conf[256];
uint8_t cur_reg;
uint8_t rmsmiblk_count;
uint8_t regs[127];
uint8_t pci_conf[256];
smram_t *smram;
pc_timer_t rmsmiblk_timer;
port_92_t *port_92;
@@ -466,6 +467,7 @@ sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0x6e;
nvr_bank_set(0, !!(val & 0x40), dev->nvr);
break;
default:
break;
}
@@ -490,6 +492,7 @@ sis_85c49x_pci_read(UNUSED(int func), int addr, void *priv)
case 0x83: /*Port 70h Mirror*/
ret = inb(0x70);
break;
default:
break;
}

23
src/chipset/sis_85c4xx.c
View File

@@ -36,14 +36,19 @@
#include <86box/machine.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t cur_reg, tries,
reg_base, reg_last,
reg_00, is_471,
force_flush, shadowed,
smram_enabled, pad,
regs[39], scratch[2];
typedef struct sis_85c4xx_t {
uint8_t cur_reg;
uint8_t tries;
uint8_t reg_base;
uint8_t reg_last;
uint8_t reg_00;
uint8_t is_471;
uint8_t force_flush;
uint8_t shadowed;
uint8_t smram_enabled;
uint8_t pad;
uint8_t regs[39];
uint8_t scratch[2];
uint32_t mem_state[8];
smram_t *smram;
port_92_t *port_92;
@@ -278,6 +283,8 @@ sis_85c4xx_in(uint16_t port, void *priv)
case 0xe1:
case 0xe2:
ret = dev->scratch[port - 0xe1];
break;
default:
break;
}

12
src/chipset/sis_85c50x.c
View File

@@ -58,9 +58,10 @@ sis_85c50x_log(const char *fmt, ...)
#endif
typedef struct sis_85c50x_t {
uint8_t index,
pci_conf[256], pci_conf_sb[256],
regs[256];
uint8_t index;
uint8_t pci_conf[256];
uint8_t pci_conf_sb[256];
uint8_t regs[256];
smram_t *smram[2];
port_92_t *port_92;
@@ -218,6 +219,7 @@ sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
case 0x69:
dev->pci_conf[addr] &= ~val;
break;
default:
break;
}
@@ -272,6 +274,7 @@ sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
dev->pci_conf_sb[addr] = val;
break;
default:
break;
}
@@ -321,10 +324,12 @@ sis_85c50x_isa_write(uint16_t addr, uint8_t val, void *priv)
case 0x85:
outb(0x70, val);
break;
default:
break;
}
break;
default:
break;
}
@@ -347,6 +352,7 @@ sis_85c50x_isa_read(uint16_t addr, void *priv)
else
ret = dev->regs[dev->index];
break;
default:
break;
}

3
src/chipset/stpc.c
View File

@@ -249,6 +249,7 @@ stpc_nb_write(int func, int addr, uint8_t val, void *priv)
case 0x52:
val &= 0x70;
break;
default:
break;
}
@@ -435,6 +436,7 @@ stpc_ide_write(int func, int addr, uint8_t val, void *priv)
sff_bus_master_set_irq(0x00, dev->bm[1]);
}
break;
default:
break;
}
@@ -494,6 +496,7 @@ stpc_isab_write(int func, int addr, uint8_t val, void *priv)
case 0x05:
val &= 0x01;
break;
default:
break;
}

10
src/chipset/umc_8886.c
View File

@@ -121,10 +121,10 @@ umc_8886_log(const char *fmt, ...)
#define SB_ID dev->sb_id
typedef struct umc_8886_t {
uint8_t max_func, /* Last function number */
pci_conf_sb[2][256]; /* PCI Registers */
uint16_t sb_id; /* Southbridge Revision */
int has_ide; /* Check if Southbridge Revision is AF or F */
uint8_t max_func; /* Last function number */
uint8_t pci_conf_sb[2][256]; /* PCI Registers */
uint16_t sb_id; /* Southbridge Revision */
int has_ide; /* Check if Southbridge Revision is AF or F */
} umc_8886_t;
static void
@@ -349,7 +349,7 @@ umc_8886_reset(void *priv)
umc_8886_ide_handler(1);
}
for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
for (uint8_t i = 1; i < 5; i++) /* Disable all IRQ interrupts */
pci_set_irq_routing(i, PCI_IRQ_DISABLED);
cpu_set_isa_pci_div(3);

7
src/chipset/umc_hb4.c
View File

@@ -143,9 +143,10 @@ hb4_log(const char *fmt, ...)
#endif
typedef struct hb4_t {
uint8_t shadow,
shadow_read, shadow_write,
pci_conf[256]; /* PCI Registers */
uint8_t shadow;
uint8_t shadow_read;
uint8_t shadow_write;
uint8_t pci_conf[256]; /* PCI Registers */
int mem_state[9];
smram_t *smram[3]; /* SMRAM Handlers */
} hb4_t;

1
src/chipset/via_apollo.c
View File

@@ -460,6 +460,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3);
break;
default:
break;
}

79
src/chipset/via_pipc.c
View File

@@ -110,22 +110,28 @@ enum {
typedef struct {
struct _pipc_ *dev;
void *trap;
uint32_t *sts_reg, *en_reg, mask;
uint32_t *sts_reg;
uint32_t *en_reg;
uint32_t mask;
} pipc_io_trap_t;
typedef struct _pipc_ {
uint32_t local;
uint8_t max_func, max_pcs;
uint8_t max_func;
uint8_t max_pcs;
uint8_t pci_isa_regs[256],
ide_regs[256],
usb_regs[2][256],
power_regs[256],
ac97_regs[2][256], fmnmi_regs[4], fmnmi_status;
uint8_t pci_isa_regs[256];
uint8_t ide_regs[256];
uint8_t usb_regs[2][256];
uint8_t power_regs[256];
uint8_t ac97_regs[2][256];
uint8_t fmnmi_regs[4];
uint8_t fmnmi_status;
sff8038i_t *bm[2];
nvr_t *nvr;
int nvr_enabled, slot;
int nvr_enabled;
int slot;
ddma_t *ddma;
smbus_piix4_t *smbus;
usb_t *usb[2];
@@ -133,9 +139,14 @@ typedef struct _pipc_ {
acpi_t *acpi;
pipc_io_trap_t io_traps[TRAP_MAX];
void *gameport, *ac97, *sio, *hwm;
void *gameport;
void *ac97;
void *sio;
void *hwm;
sb_t *sb;
uint16_t midigame_base, sb_base, fmnmi_base;
uint16_t midigame_base;
uint16_t sb_base;
uint16_t fmnmi_base;
} pipc_t;
#ifdef ENABLE_PIPC_LOG
@@ -1576,36 +1587,36 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
}
static void
pipc_reset(void *p)
pipc_reset(void *priv)
{
pipc_t *dev = (pipc_t *) p;
pipc_t *dev = (pipc_t *) priv;
uint8_t pm_func = dev->usb[1] ? 4 : 3;
pipc_write(pm_func, 0x41, 0x00, p);
pipc_write(pm_func, 0x48, 0x01, p);
pipc_write(pm_func, 0x49, 0x00, p);
pipc_write(pm_func, 0x41, 0x00, priv);
pipc_write(pm_func, 0x48, 0x01, priv);
pipc_write(pm_func, 0x49, 0x00, priv);
pipc_write(1, 0x04, 0x80, p);
pipc_write(1, 0x09, 0x85, p);
pipc_write(1, 0x10, 0xf1, p);
pipc_write(1, 0x11, 0x01, p);
pipc_write(1, 0x14, 0xf5, p);
pipc_write(1, 0x15, 0x03, p);
pipc_write(1, 0x18, 0x71, p);
pipc_write(1, 0x19, 0x01, p);
pipc_write(1, 0x1c, 0x75, p);
pipc_write(1, 0x1d, 0x03, p);
pipc_write(1, 0x20, 0x01, p);
pipc_write(1, 0x21, 0xcc, p);
pipc_write(1, 0x04, 0x80, priv);
pipc_write(1, 0x09, 0x85, priv);
pipc_write(1, 0x10, 0xf1, priv);
pipc_write(1, 0x11, 0x01, priv);
pipc_write(1, 0x14, 0xf5, priv);
pipc_write(1, 0x15, 0x03, priv);
pipc_write(1, 0x18, 0x71, priv);
pipc_write(1, 0x19, 0x01, priv);
pipc_write(1, 0x1c, 0x75, priv);
pipc_write(1, 0x1d, 0x03, priv);
pipc_write(1, 0x20, 0x01, priv);
pipc_write(1, 0x21, 0xcc, priv);
if (dev->local <= VIA_PIPC_586B)
pipc_write(1, 0x40, 0x04, p);
pipc_write(1, 0x40, 0x04, priv);
else
pipc_write(1, 0x40, 0x00, p);
pipc_write(1, 0x40, 0x00, priv);
if (dev->local < VIA_PIPC_586B)
pipc_write(0, 0x44, 0x00, p);
pipc_write(0, 0x44, 0x00, priv);
pipc_write(0, 0x77, 0x00, p);
pipc_write(0, 0x77, 0x00, priv);
}
static void *
@@ -1691,13 +1702,13 @@ pipc_init(const device_t *info)
}
static void
pipc_close(void *p)
pipc_close(void *priv)
{
pipc_t *dev = (pipc_t *) p;
pipc_t *dev = (pipc_t *) priv;
pipc_log("PIPC: close()\n");
for (int i = 0; i < TRAP_MAX; i++)
for (uint8_t i = 0; i < TRAP_MAX; i++)
io_trap_remove(dev->io_traps[i].trap);
free(dev);

20
src/chipset/via_vt82c49x.c
View File

@@ -35,13 +35,14 @@
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct
{
uint8_t has_ide, index,
regs[256];
typedef struct vt82c49x_t {
uint8_t has_ide;
uint8_t index;
uint8_t regs[256];
smram_t *smram_smm, *smram_low,
*smram_high;
smram_t *smram_smm;
smram_t *smram_low;
smram_t *smram_high;
} vt82c49x_t;
#ifdef ENABLE_VT82C49X_LOG
@@ -65,7 +66,6 @@ vt82c49x_log(const char *fmt, ...)
static void
vt82c49x_recalc(vt82c49x_t *dev)
{
int i;
int relocate;
uint8_t reg;
uint8_t bit;
@@ -78,7 +78,7 @@ vt82c49x_recalc(vt82c49x_t *dev)
shadowbios = 0;
shadowbios_write = 0;
for (i = 0; i < 8; i++) {
for (uint8_t i = 0; i < 8; i++) {
base = 0xc0000 + (i << 14);
reg = 0x30 + (i >> 2);
bit = (i & 3) << 1;
@@ -123,7 +123,7 @@ vt82c49x_recalc(vt82c49x_t *dev)
mem_set_mem_state_both(base, 0x4000, state);
}
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
base = 0xe0000 + (i << 15);
bit = 6 - (i & 2);
@@ -287,6 +287,7 @@ vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
break;
}
break;
default:
break;
}
@@ -310,6 +311,7 @@ vt82c49x_read(uint16_t addr, void *priv)
else if (dev->index < 0x80)
ret = dev->regs[dev->index];
break;
default:
break;
}

1
src/chipset/via_vt82c505.c
View File

@@ -117,6 +117,7 @@ vt82c505_write(int func, int addr, uint8_t val, void *priv)
case 0x93:
dev->pci_conf[addr] = val & 0xe0;
break;
default:
break;
}

18
src/chipset/vl82c480.c
View File

@@ -29,9 +29,9 @@
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct {
uint8_t idx,
regs[256];
typedef struct vl82c480_t {
uint8_t idx;
uint8_t regs[256];
} vl82c480_t;
static int
@@ -81,9 +81,9 @@ vl82c480_recalc(vl82c480_t *dev)
}
static void
vl82c480_write(uint16_t addr, uint8_t val, void *p)
vl82c480_write(uint16_t addr, uint8_t val, void *priv)
{
vl82c480_t *dev = (vl82c480_t *) p;
vl82c480_t *dev = (vl82c480_t *) priv;
switch (addr) {
case 0xec:
@@ -132,9 +132,9 @@ vl82c480_write(uint16_t addr, uint8_t val, void *p)
}
static uint8_t
vl82c480_read(uint16_t addr, void *p)
vl82c480_read(uint16_t addr, void *priv)
{
vl82c480_t *dev = (vl82c480_t *) p;
vl82c480_t *dev = (vl82c480_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
@@ -164,9 +164,9 @@ vl82c480_read(uint16_t addr, void *p)
}
static void
vl82c480_close(void *p)
vl82c480_close(void *priv)
{
vl82c480_t *dev = (vl82c480_t *) p;
vl82c480_t *dev = (vl82c480_t *) priv;
free(dev);
}

47
src/chipset/wd76c10.c
View File

@@ -64,17 +64,33 @@ wd76c10_log(const char *fmt, ...)
# define wd76c10_log(fmt, ...)
#endif
typedef struct
{
uint16_t lock_reg, oscillator_40mhz, cache_flush, ems_page_reg,
ems_page_reg_pointer, port_shadow, pmc_interrupt,
high_mem_protect_boundry, delay_line, diagnostic,
nmi_status, pmc_input, pmc_timer,
pmc_output, ems_control_low_address_boundry, shadow_ram,
split_addr, bank32staddr, bank10staddr,
non_page_mode_dram_timing, mem_control,
refresh_control, disk_chip_select, prog_chip_sel_addr,
bus_timing_power_down_ctl, clk_control;
typedef struct wd76c10_t {
uint16_t lock_reg;
uint16_t oscillator_40mhz;
uint16_t cache_flush;
uint16_t ems_page_reg;
uint16_t ems_page_reg_pointer;
uint16_t port_shadow;
uint16_t pmc_interrupt;
uint16_t high_mem_protect_boundry;
uint16_t delay_line;
uint16_t diagnostic;
uint16_t nmi_status;
uint16_t pmc_input;
uint16_t pmc_timer;
uint16_t pmc_output;
uint16_t ems_control_low_address_boundry;
uint16_t shadow_ram;
uint16_t split_addr;
uint16_t bank32staddr;
uint16_t bank10staddr;
uint16_t non_page_mode_dram_timing;
uint16_t mem_control;
uint16_t refresh_control;
uint16_t disk_chip_select;
uint16_t prog_chip_sel_addr;
uint16_t bus_timing_power_down_ctl;
uint16_t clk_control;
int lock;
@@ -139,6 +155,9 @@ wd76c10_refresh_control(wd76c10_t *dev)
lpt1_init(0x278);
lpt1_irq(7);
break;
default:
break;
}
}
@@ -320,6 +339,9 @@ wd76c10_write(uint16_t addr, uint16_t val, void *priv)
dev->cache_flush = val;
flushmmucache();
break;
default:
break;
}
wd76c10_log("WD76C10: dev->regs[%04x] = %04x\n", addr, val);
}
@@ -337,6 +359,9 @@ wd76c10_write(uint16_t addr, uint16_t val, void *priv)
dev->lock_reg = val & 0x00ff;
LOCK = !(val & 0x00da);
break;
default:
break;
}
}

2
src/cpu/386_dynarec.c
View File

@@ -431,7 +431,7 @@ exec386_dynarec_dyn(void)
uint64_t mask = (uint64_t) 1 << ((phys_addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
# ifdef USE_NEW_DYNAREC
int byte_offset = (phys_addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
uint64_t byte_mask = 1ull << (PAGE_BYTE_MASK_MASK & 0x3f);
uint64_t byte_mask = 1ULL << (PAGE_BYTE_MASK_MASK & 0x3f);
if ((page->code_present_mask & mask) || (page->byte_code_present_mask[byte_offset] & byte_mask))
# else

190
src/cpu/cpu.c
View File

@@ -80,66 +80,147 @@ fpu_state_t fpu_state;
uint32_t abrt_error;
#ifdef USE_DYNAREC
const OpFn *x86_dynarec_opcodes, *x86_dynarec_opcodes_0f,
*x86_dynarec_opcodes_d8_a16, *x86_dynarec_opcodes_d8_a32,
*x86_dynarec_opcodes_d9_a16, *x86_dynarec_opcodes_d9_a32,
*x86_dynarec_opcodes_da_a16, *x86_dynarec_opcodes_da_a32,
*x86_dynarec_opcodes_db_a16, *x86_dynarec_opcodes_db_a32,
*x86_dynarec_opcodes_dc_a16, *x86_dynarec_opcodes_dc_a32,
*x86_dynarec_opcodes_dd_a16, *x86_dynarec_opcodes_dd_a32,
*x86_dynarec_opcodes_de_a16, *x86_dynarec_opcodes_de_a32,
*x86_dynarec_opcodes_df_a16, *x86_dynarec_opcodes_df_a32,
*x86_dynarec_opcodes_REPE, *x86_dynarec_opcodes_REPNE,
*x86_dynarec_opcodes_3DNOW;
const OpFn *x86_dynarec_opcodes;
const OpFn *x86_dynarec_opcodes_0f;
const OpFn *x86_dynarec_opcodes_d8_a16;
const OpFn *x86_dynarec_opcodes_d8_a32;
const OpFn *x86_dynarec_opcodes_d9_a16;
const OpFn *x86_dynarec_opcodes_d9_a32;
const OpFn *x86_dynarec_opcodes_da_a16;
const OpFn *x86_dynarec_opcodes_da_a32;
const OpFn *x86_dynarec_opcodes_db_a16;
const OpFn *x86_dynarec_opcodes_db_a32;
const OpFn *x86_dynarec_opcodes_dc_a16;
const OpFn *x86_dynarec_opcodes_dc_a32;
const OpFn *x86_dynarec_opcodes_dd_a16;
const OpFn *x86_dynarec_opcodes_dd_a32;
const OpFn *x86_dynarec_opcodes_de_a16;
const OpFn *x86_dynarec_opcodes_de_a32;
const OpFn *x86_dynarec_opcodes_df_a16;
const OpFn *x86_dynarec_opcodes_df_a32;
const OpFn *x86_dynarec_opcodes_REPE;
const OpFn *x86_dynarec_opcodes_REPNE;
const OpFn *x86_dynarec_opcodes_3DNOW;
#endif
const OpFn *x86_opcodes, *x86_opcodes_0f,
*x86_opcodes_d8_a16, *x86_opcodes_d8_a32,
*x86_opcodes_d9_a16, *x86_opcodes_d9_a32,
*x86_opcodes_da_a16, *x86_opcodes_da_a32,
*x86_opcodes_db_a16, *x86_opcodes_db_a32,
*x86_opcodes_dc_a16, *x86_opcodes_dc_a32,
*x86_opcodes_dd_a16, *x86_opcodes_dd_a32,
*x86_opcodes_de_a16, *x86_opcodes_de_a32,
*x86_opcodes_df_a16, *x86_opcodes_df_a32,
*x86_opcodes_REPE, *x86_opcodes_REPNE,
*x86_opcodes_3DNOW;
const OpFn *x86_opcodes;
const OpFn *x86_opcodes_0f;
const OpFn *x86_opcodes_d8_a16;
const OpFn *x86_opcodes_d8_a32;
const OpFn *x86_opcodes_d9_a16;
const OpFn *x86_opcodes_d9_a32;
const OpFn *x86_opcodes_da_a16;
const OpFn *x86_opcodes_da_a32;
const OpFn *x86_opcodes_db_a16;
const OpFn *x86_opcodes_db_a32;
const OpFn *x86_opcodes_dc_a16;
const OpFn *x86_opcodes_dc_a32;
const OpFn *x86_opcodes_dd_a16;
const OpFn *x86_opcodes_dd_a32;
const OpFn *x86_opcodes_de_a16;
const OpFn *x86_opcodes_de_a32;
const OpFn *x86_opcodes_df_a16;
const OpFn *x86_opcodes_df_a32;
const OpFn *x86_opcodes_REPE;
const OpFn *x86_opcodes_REPNE;
const OpFn *x86_opcodes_3DNOW;
uint16_t cpu_fast_off_count, cpu_fast_off_val;
uint16_t cpu_fast_off_count;
uint16_t cpu_fast_off_val;
uint16_t temp_seg_data[4] = { 0, 0, 0, 0 };
int isa_cycles, cpu_inited,
int isa_cycles;
int cpu_inited;
cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l,
cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles,
cpu_waitstates, cpu_cache_int_enabled, cpu_cache_ext_enabled,
cpu_isa_speed, cpu_pci_speed, cpu_isa_pci_div, cpu_agp_speed, cpu_alt_reset,
int cpu_cycles_read;
int cpu_cycles_read_l;
int cpu_cycles_write;
int cpu_cycles_write_l;
int cpu_prefetch_cycles;
int cpu_prefetch_width;
int cpu_mem_prefetch_cycles;
int cpu_rom_prefetch_cycles;
int cpu_waitstates;
int cpu_cache_int_enabled;
int cpu_cache_ext_enabled;
int cpu_isa_speed;
int cpu_pci_speed;
int cpu_isa_pci_div;
int cpu_agp_speed;
int cpu_alt_reset;
cpu_override, cpu_effective, cpu_multi, cpu_16bitbus, cpu_64bitbus,
cpu_cyrix_alignment, CPUID,
int cpu_override;
int cpu_effective;
int cpu_multi;
int cpu_16bitbus;
int cpu_64bitbus;
int cpu_cyrix_alignment;
int CPUID;
is186, is_nec,
is286, is386, is6117, is486 = 1,
cpu_isintel, cpu_iscyrix, hascache, isibm486, israpidcad, is_vpc,
is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
int is186;
int is_nec;
int is286;
int is386;
int is6117;
int is486 = 1;
int cpu_isintel;
int cpu_iscyrix;
int hascache;
int isibm486;
int israpidcad;
int is_vpc;
int is_am486;
int is_am486dxl;
int is_pentium;
int is_k5;
int is_k6;
int is_p6;
int is_cxsmm;
int hasfpu;
timing_rr, timing_mr, timing_mrl, timing_rm, timing_rml,
timing_mm, timing_mml, timing_bt, timing_bnt,
timing_int, timing_int_rm, timing_int_v86, timing_int_pm,
timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm,
timing_iret_pm_outer, timing_call_rm, timing_call_pm, timing_call_pm_gate,
timing_call_pm_gate_inner, timing_retf_rm, timing_retf_pm, timing_retf_pm_outer,
timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate, timing_misaligned;
uint32_t cpu_features, cpu_fast_off_flags;
int timing_rr;
int timing_mr;
int timing_mrl;
int timing_rm;
int timing_rml;
int timing_mm;
int timing_mml;
int timing_bt;
int timing_bnt;
int timing_int;
int timing_int_rm;
int timing_int_v86;
int timing_int_pm;
int timing_int_pm_outer;
int timing_iret_rm;
int timing_iret_v86;
int timing_iret_pm;
int timing_iret_pm_outer;
int timing_call_rm;
int timing_call_pm;
int timing_call_pm_gate;
int timing_call_pm_gate_inner;
int timing_retf_rm;
int timing_retf_pm;
int timing_retf_pm_outer;
int timing_jmp_rm;
int timing_jmp_pm;
int timing_jmp_pm_gate;
int timing_misaligned;
uint32_t cpu_features;
uint32_t cpu_fast_off_flags;
uint32_t _tr[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
uint32_t cache_index = 0;
uint8_t _cache[2048];
uint64_t cpu_CR4_mask, tsc = 0;
uint64_t cpu_CR4_mask;
uint64_t tsc = 0;
uint64_t pmc[2] = { 0, 0 };
double cpu_dmulti, cpu_busspeed;
double cpu_dmulti;
double cpu_busspeed;
msr_t msr;
@@ -148,11 +229,18 @@ cyrix_t cyrix;
cpu_family_t *cpu_f;
CPU *cpu_s;
uint8_t do_translate = 0, do_translate2 = 0;
uint8_t do_translate = 0;
uint8_t do_translate2 = 0;
void (*cpu_exec)(int cycs);
static uint8_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6;
static uint8_t ccr0;
static uint8_t ccr1;
static uint8_t ccr2;
static uint8_t ccr3;
static uint8_t ccr4;
static uint8_t ccr5;
static uint8_t ccr6;
static int cyrix_addr;
@@ -225,7 +313,8 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
{
const machine_t *machine_s = &machines[machine];
const CPU *cpu_s = &cpu_family->cpus[cpu];
uint32_t packages, bus_speed;
uint32_t packages;
uint32_t bus_speed;
uint8_t i;
double multi;
@@ -1647,7 +1736,7 @@ cpu_current_pc(char *bufp)
sprintf(bufp, "%04X:%04X", CS, cpu_state.pc);
return (bufp);
return bufp;
}
void
@@ -3225,7 +3314,7 @@ cpu_write(uint16_t addr, uint8_t val, void *priv)
if (!(ccr3 & CCR3_SMI_LOCK) || in_smm) {
cyrix.arr[3].base = (cyrix.arr[3].base & ~0x0000f000) | ((val & 0xf0) << 8);
if ((val & 0xf) == 0xf)
cyrix.arr[3].size = 1ull << 32; /* 4 GB */
cyrix.arr[3].size = 1ULL << 32; /* 4 GB */
else if (val & 0xf)
cyrix.arr[3].size = 2048 << (val & 0xf);
else
@@ -3287,6 +3376,9 @@ cpu_read(uint16_t addr, void *priv)
return cpu_s->cyrix_id & 0xff;
case 0xff:
return cpu_s->cyrix_id >> 8;
default:
break;
}
if ((cyrix_addr & 0xf0) == 0xc0)

232
src/cpu/cpu.h
View File

@@ -150,8 +150,10 @@ typedef struct {
uint32_t cpuid_model;
uint16_t cyrix_id;
uint8_t cpu_flags;
int8_t mem_read_cycles, mem_write_cycles;
int8_t cache_read_cycles, cache_write_cycles;
int8_t mem_read_cycles;
int8_t mem_write_cycles;
int8_t cache_read_cycles;
int8_t cache_write_cycles;
int8_t atclk_div;
} CPU;
@@ -215,17 +217,19 @@ typedef union {
uint32_t l;
uint16_t w;
struct {
uint8_t l,
h;
uint8_t l;
uint8_t h;
} b;
} x86reg;
typedef struct {
uint32_t base;
uint32_t limit;
uint8_t access, ar_high;
uint8_t access;
uint8_t ar_high;
uint16_t seg;
uint32_t limit_low, limit_high;
uint32_t limit_low;
uint32_t limit_high;
int checked; /*Non-zero if selector is known to be valid*/
} x86seg;
@@ -243,8 +247,9 @@ typedef union {
typedef struct {
/* IDT WinChip and WinChip 2 MSR's */
uint32_t tr1, tr12; /* 0x00000002, 0x0000000e */
uint32_t cesr; /* 0x00000011 */
uint32_t tr1; /* 0x00000002, 0x0000000e */
uint32_t tr12; /* 0x00000002, 0x0000000e */
uint32_t cesr; /* 0x00000011 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */
@@ -259,8 +264,9 @@ typedef struct {
uint64_t mtrr_cap; /* 0x000000fe */
/* IDT WinChip and WinChip 2 MSR's that are also on the VIA Cyrix III */
uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
uint64_t fcr2, fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
uint64_t fcr2; /* 0x00000108 (IDT), 0x00001108 (VIA) */
uint64_t fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx116; /* 0x00000116 */
@@ -276,8 +282,9 @@ typedef struct {
uint64_t mcg_ctl; /* 0x0000017b - Machine Check Architecture */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx186, ecx187; /* 0x00000186, 0x00000187 */
uint64_t ecx1e0; /* 0x000001e0 */
uint64_t ecx186; /* 0x00000186, 0x00000187 */
uint64_t ecx187; /* 0x00000186, 0x00000187 */
uint64_t ecx1e0; /* 0x000001e0 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
on the VIA Cyrix III */
@@ -325,7 +332,8 @@ typedef struct {
uint64_t amd_epmr; /* 0xc0000086 */
/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
uint64_t amd_psor, amd_pfir; /* 0xc0000087, 0xc0000088 */
uint64_t amd_psor; /* 0xc0000087, 0xc0000088 */
uint64_t amd_pfir; /* 0xc0000087, 0xc0000088 */
/* K6-3, K6-2P, and K6-3P MSR's */
uint64_t amd_l2aar; /* 0xc0000089 */
@@ -345,33 +353,38 @@ typedef struct {
uint32_t eaaddr;
int flags_op;
uint32_t flags_res,
flags_op1, flags_op2;
uint32_t flags_res;
uint32_t flags_op1;
uint32_t flags_op2;
uint32_t pc,
oldpc, op32;
uint32_t pc;
uint32_t oldpc;
uint32_t op32;
int TOP;
union {
struct {
int8_t rm,
mod,
reg;
int8_t rm;
int8_t mod;
int8_t reg;
} rm_mod_reg;
int32_t rm_mod_reg_data;
} rm_data;
uint8_t ssegs, ismmx,
abrt, _smi_line;
uint8_t ssegs;
uint8_t ismmx;
uint8_t abrt;
uint8_t _smi_line;
int _cycles;
#ifdef FPU_CYCLES
int _cycles, _fpu_cycles, _in_smm;
#else
int _cycles, _in_smm;
int _fpu_cycles;
#endif
int _in_smm;
uint16_t npxs, npxc;
uint16_t npxs;
uint16_t npxc;
double ST[8];
@@ -380,26 +393,34 @@ typedef struct {
MMX_REG MM[8];
#ifdef USE_NEW_DYNAREC
uint32_t old_fp_control, new_fp_control;
uint32_t old_fp_control;
uint32_t new_fp_control;
# if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
uint16_t old_fp_control2, new_fp_control2;
uint16_t old_fp_control2;
uint16_t new_fp_control2;
# endif
# if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64
uint32_t trunc_fp_control;
uint32_t trunc_fp_control;
# endif
#else
uint16_t old_npxc, new_npxc;
uint16_t old_npxc;
uint16_t new_npxc;
#endif
x86seg seg_cs, seg_ds, seg_es, seg_ss,
seg_fs, seg_gs;
x86seg seg_cs;
x86seg seg_ds;
x86seg seg_es;
x86seg seg_ss;
x86seg seg_fs;
x86seg seg_gs;
union {
uint32_t l;
uint16_t w;
} CR0;
uint16_t flags, eflags;
uint16_t flags;
uint16_t eflags;
uint32_t _smbase;
} cpu_state_t;
@@ -415,13 +436,15 @@ typedef struct {
uint16_t fds;
floatx80 st_space[8];
unsigned char tos;
unsigned char align1, align2, align3;
unsigned char align1;
unsigned char align2;
unsigned char align3;
} fpu_state_t;
#define in_smm cpu_state._in_smm
#define smi_line cpu_state._smi_line
#define smbase cpu_state._smbase
#define smbase cpu_state._smbase
/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block
to be valid*/
@@ -508,7 +531,8 @@ extern int cpu_override;
extern int cpu_isintel;
extern int cpu_iscyrix;
extern int cpu_16bitbus, cpu_64bitbus;
extern int cpu_16bitbus;
extern int cpu_64bitbus;
extern int cpu_pci_speed;
extern int cpu_multi;
extern double cpu_dmulti;
@@ -517,8 +541,19 @@ extern double cpu_busspeed;
extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
penalties when crossing 8-byte boundaries*/
extern int is8086, is186, is286, is386, is6117, is486;
extern int is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
extern int is8086;
extern int is186;
extern int is286;
extern int is386;
extern int is6117;
extern int is486;
extern int is_am486;
extern int is_am486dxl;
extern int is_pentium;
extern int is_k5;
extern int is_k6;
extern int is_p6;
extern int is_cxsmm;
extern int hascache;
extern int isibm486;
extern int is_nec;
@@ -536,7 +571,8 @@ extern int hasfpu;
extern uint32_t cpu_features;
extern int smi_latched, smm_in_hlt;
extern int smi_latched;
extern int smm_in_hlt;
extern int smi_block;
#ifdef USE_NEW_DYNAREC
@@ -552,12 +588,21 @@ extern int cgate16;
extern int cpl_override;
extern int CPUID;
extern uint64_t xt_cpu_multi;
extern int isa_cycles, cpu_inited;
extern uint32_t oldds, oldss, olddslimit, oldsslimit, olddslimitw, oldsslimitw;
extern int isa_cycles;
extern int cpu_inited;
extern uint32_t oldds;
extern uint32_t oldss;
extern uint32_t olddslimit;
extern uint32_t oldsslimit;
extern uint32_t olddslimitw;
extern uint32_t oldsslimitw;
extern uint32_t pccache;
extern uint8_t *pccache2;
extern double bus_timing, isa_timing, pci_timing, agp_timing;
extern double bus_timing;
extern double isa_timing;
extern double pci_timing;
extern double agp_timing;
extern uint64_t pmc[2];
extern uint16_t temp_seg_data[4];
extern uint16_t cs_msr;
@@ -565,13 +610,16 @@ extern uint32_t esp_msr;
extern uint32_t eip_msr;
/* For the AMD K6. */
extern uint64_t amd_efer, star;
extern uint64_t amd_efer;
extern uint64_t star;
#define FPU_CW_Reserved_Bits (0xe0c0)
#define cr0 cpu_state.CR0.l
#define msw cpu_state.CR0.w
extern uint32_t cr2, cr3, cr4;
#define cr0 cpu_state.CR0.l
#define msw cpu_state.CR0.w
extern uint32_t cr2;
extern uint32_t cr3;
extern uint32_t cr4;
extern uint32_t dr[8];
extern uint32_t _tr[8];
extern uint32_t cache_index;
@@ -581,7 +629,10 @@ extern uint8_t _cache[2048];
_cs,_ds,_es,_ss are the segment structures
CS,DS,ES,SS is the 16-bit data
cs,ds,es,ss are defines to the bases*/
extern x86seg gdt, ldt, idt, tr;
extern x86seg gdt;
extern x86seg ldt;
extern x86seg idt;
extern x86seg tr;
extern x86seg _oldds;
#define CS cpu_state.seg_cs.seg
#define DS cpu_state.seg_ds.seg
@@ -598,37 +649,67 @@ extern x86seg _oldds;
#define ISA_CYCLES(x) (x * isa_cycles)
extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
extern int cpu_cycles_read;
extern int cpu_cycles_read_l;
extern int cpu_cycles_write;
extern int cpu_cycles_write_l;
extern int cpu_prefetch_cycles;
extern int cpu_prefetch_width;
extern int cpu_mem_prefetch_cycles;
extern int cpu_rom_prefetch_cycles;
extern int cpu_waitstates;
extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
extern int cpu_isa_speed, cpu_pci_speed, cpu_agp_speed;
extern int cpu_cache_int_enabled;
extern int cpu_cache_ext_enabled;
extern int cpu_isa_speed;
extern int cpu_pci_speed;
extern int cpu_agp_speed;
extern int timing_rr;
extern int timing_mr, timing_mrl;
extern int timing_rm, timing_rml;
extern int timing_mm, timing_mml;
extern int timing_bt, timing_bnt;
extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm;
extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm;
extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm;
extern int timing_call_pm_gate, timing_call_pm_gate_inner;
extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
extern int timing_mr;
extern int timing_mrl;
extern int timing_rm;
extern int timing_rml;
extern int timing_mm;
extern int timing_mml;
extern int timing_bt;
extern int timing_bnt;
extern int timing_int;
extern int timing_int_rm;
extern int timing_int_v86;
extern int timing_int_pm;
extern int timing_int_pm_outer;
extern int timing_iret_rm;
extern int timing_iret_v86;
extern int timing_iret_pm;
extern int timing_iret_pm_outer;
extern int timing_call_rm;
extern int timing_call_pm;
extern int timing_call_pm_gate;
extern int timing_call_pm_gate_inner;
extern int timing_retf_rm;
extern int timing_retf_pm;
extern int timing_retf_pm_outer;
extern int timing_jmp_rm;
extern int timing_jmp_pm;
extern int timing_jmp_pm_gate;
extern int timing_misaligned;
extern int in_sys, unmask_a20_in_smm;
extern int in_sys;
extern int unmask_a20_in_smm;
extern int cycles_main;
extern uint32_t old_rammask;
#ifdef USE_ACYCS
extern int acycs;
#endif
extern int pic_pending, is_vpc;
extern int soft_reset_mask, alt_access;
extern int pic_pending;
extern int is_vpc;
extern int soft_reset_mask;
extern int alt_access;
extern int cpu_end_block_after_ins;
extern uint16_t cpu_fast_off_count, cpu_fast_off_val;
extern uint16_t cpu_fast_off_count;
extern uint16_t cpu_fast_off_val;
extern uint32_t cpu_fast_off_flags;
/* Functions. */
@@ -703,7 +784,8 @@ extern void x87_dumpregs(void);
extern void x87_reset(void);
#endif
extern int cpu_effective, cpu_alt_reset;
extern int cpu_effective;
extern int cpu_alt_reset;
extern void cpu_dynamic_switch(int new_cpu);
extern void cpu_ven_reset(void);
@@ -728,22 +810,23 @@ void cyrix_write_seg_descriptor(uint32_t addr, x86seg *seg);
#define SMHR_VALID (1 << 0)
#define SMHR_ADDR_MASK (0xfffffffc)
typedef struct
{
struct
{
typedef struct {
struct {
uint32_t base;
uint64_t size;
} arr[8];
uint32_t smhr;
} cyrix_t;
extern uint32_t addr64, addr64_2;
extern uint32_t addr64a[8], addr64a_2[8];
extern uint32_t addr64;
extern uint32_t addr64_2;
extern uint32_t addr64a[8];
extern uint32_t addr64a_2[8];
extern int soft_reset_pci;
extern int reset_on_hlt, hlt_reset_pending;
extern int reset_on_hlt;
extern int hlt_reset_pending;
extern cyrix_t cyrix;
@@ -751,7 +834,8 @@ extern uint8_t use_custom_nmi_vector;
extern uint32_t custom_nmi_vector;
extern void (*cpu_exec)(int cycs);
extern uint8_t do_translate, do_translate2;
extern uint8_t do_translate;
extern uint8_t do_translate2;
extern void SF_FPU_reset(void);

3
src/device/cartridge.c
View File

@@ -29,8 +29,7 @@
#include <86box/machine.h>
#include <86box/cartridge.h>
typedef struct
{
typedef struct cart_t {
uint8_t *buf;
uint32_t base;
} cart_t;

9
src/device/cassette.c
View File

@@ -552,9 +552,8 @@ pc_cas_print_state(UNUSED(const pc_cassette_t *cas))
static void
pc_cas_clock_pcm(pc_cassette_t *cas, unsigned long cnt)
{
unsigned long i;
unsigned long n;
int v = 0;
uint64_t n;
int v = 0;
n = cas->srate * cnt + cas->clk_pcm;
@@ -567,11 +566,11 @@ pc_cas_clock_pcm(pc_cassette_t *cas, unsigned long cnt)
}
if (cas->save) {
for (i = 0; i < n; i++) {
for (uint64_t i = 0; i < n; i++) {
pc_cas_write_smp(cas, cas->pcm_out_val);
}
} else {
for (i = 0; i < n; i++) {
for (uint64_t i = 0; i < n; i++) {
v = pc_cas_read_smp(cas);
}

15
src/device/clock_ics9xxx.c
View File

@@ -52,26 +52,26 @@ ics9xxx_log(const char *fmt, ...)
,
#define agp_div ram_mult /* temporarily saves space while neither field matters */
typedef struct {
typedef struct ics9xxx_frequency_t {
uint16_t bus : 15;
uint8_t ram_mult : 2; /* change to full float when this becomes useful */
uint8_t pci_div : 3;
} ics9xxx_frequency_t;
typedef struct {
typedef struct ics9xxx_model_t {
#if defined(ENABLE_ICS9xxx_LOG) || defined(ENABLE_ICS9xxx_DETECT)
const char *name; /* populated by macro */
#endif
uint8_t max_reg : 3; /* largest register index */
uint8_t regs[7]; /* default registers */
struct { /* for each hardware frequency select bit [FS0:FS4]: */
struct fs_regs { /* for each hardware frequency select bit [FS0:FS4]: */
uint8_t normal_reg : 3; /* which register (or -1) for non-inverted input (FSn) */
uint8_t normal_bit : 3; /* which bit (0-7) for non-inverted input (FSn) */
uint8_t inv_reg : 3; /* which register (or -1) for inverted input (FSn#) */
uint8_t inv_bit : 3; /* which bit (0-7) for inverted input (FSn#) */
} fs_regs[5];
uint8_t normal_bits_fixed : 1; /* set to 1 if the non-inverted bits are straps (hardware select only) */
struct { /* hardware select bit, which should be cleared for hardware select (latched inputs), or set for programming */
struct hw_select { /* hardware select bit, which should be cleared for hardware select (latched inputs), or set for programming */
uint8_t normal_reg : 3; /* which register (or -1) */
uint8_t normal_bit : 3; /* which bit (0-7) */
} hw_select;
@@ -80,7 +80,7 @@ typedef struct {
const ics9xxx_frequency_t *frequencies; /* frequency table, if not using another model's table */
} ics9xxx_model_t;
typedef struct {
typedef struct ics9xxx_t {
uint8_t model_idx;
ics9xxx_model_t *model;
device_t *dyn_device;
@@ -942,7 +942,10 @@ ics9xxx_detect(ics9xxx_t *dev)
if (!(dev->regs[detect_reg] & 0x40))
pclog("Bit 3 of register %d is clear, probably in hardware select mode!\n", detect_reg);
uint8_t i = 0, matches = 0, val, bitmask;
uint8_t i = 0;
uint8_t matches = 0;
uint8_t val;
uint8_t bitmask;
ics9xxx_frequency_t *frequencies_ptr;
uint32_t delta;
for (uint8_t j = 0; j < ICS9xxx_MAX; j++) {

17
src/device/hasp.c
View File

@@ -52,9 +52,11 @@ enum {
HASP_TYPE_SAVQUEST = 0
};
typedef struct {
const uint8_t *password, *prodinfo;
const uint8_t password_size, prodinfo_size;
typedef struct hasp_type_t {
const uint8_t *password;
const uint8_t *prodinfo;
const uint8_t password_size;
const uint8_t prodinfo_size;
} hasp_type_t;
typedef struct
@@ -62,8 +64,13 @@ typedef struct
void *lpt;
const hasp_type_t *type;
int index, state, passindex, passmode, prodindex;
uint8_t tmppass[0x29], status;
int index;
int state;
int passindex;
int passmode;
int prodindex;
uint8_t tmppass[0x29];
uint8_t status;
} hasp_t;
static const hasp_type_t hasp_types[] = {

6
src/device/hwm_gl518sm.c
View File

@@ -36,14 +36,16 @@
#define GL518SM_VOLTAGE_TO_REG(v) ((uint8_t) round((v) / 19.0))
#define GL518SM_VDD_TO_REG(v) ((uint8_t) (((v) *4) / 95.0))
typedef struct {
typedef struct gl518sm_t {
uint32_t local;
hwm_values_t *values;
uint16_t regs[32];
uint8_t addr_register : 5;
uint8_t i2c_addr : 7, i2c_state : 2, i2c_enabled : 1;
uint8_t i2c_addr : 7;
uint8_t i2c_state : 2;
uint8_t i2c_enabled : 1;
} gl518sm_t;
static uint8_t gl518sm_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv);

3
src/device/hwm_lm75.c
View File

@@ -167,6 +167,9 @@ lm75_i2c_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv
case 0x3: /* Tos */
lm75_write(dev, (dev->i2c_state == 1) ? 0x5 : 0x6, data);
break;
default:
break;
}
}

15
src/device/hwm_lm78.c
View File

@@ -49,7 +49,7 @@
#define LM78_NEG_VOLTAGE(v, r) (v * (604.0 / ((double) r))) /* negative voltage formula from the W83781D datasheet */
#define LM78_NEG_VOLTAGE2(v, r) (((3600 + v) * (((double) r) / (((double) r) + 56.0))) - v) /* negative voltage formula from the W83782D datasheet */
typedef struct {
typedef struct lm78_t {
uint32_t local;
hwm_values_t *values;
device_t *lm75[2];
@@ -57,10 +57,10 @@ typedef struct {
uint8_t regs[256];
union {
struct {
struct w83782d {
uint8_t regs[2][16];
} w83782d;
struct {
struct as99127f {
uint8_t regs[3][128];
uint8_t nvram[1024], nvram_i2c_state : 2, nvram_updated : 1;
@@ -70,9 +70,12 @@ typedef struct {
uint8_t security_i2c_state : 1, security_addr_register : 7;
} as99127f;
};
uint8_t addr_register, data_register;
uint8_t addr_register;
uint8_t data_register;
uint8_t i2c_addr : 7, i2c_state : 1, i2c_enabled : 1;
uint8_t i2c_addr : 7;
uint8_t i2c_state : 1;
uint8_t i2c_enabled : 1;
} lm78_t;
static void lm78_remap(lm78_t *dev, uint8_t addr);
@@ -624,6 +627,7 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
i2c_sethandler(i2c_smbus, (val & 0xf8) >> 1, 4, lm78_nvram_start, lm78_nvram_read, lm78_nvram_write, NULL, dev);
}
break;
default:
break;
}
@@ -707,6 +711,7 @@ lm78_as99127f_write(void *priv, uint8_t reg, uint8_t val)
resetx86();
}
break;
default:
break;
}

3
src/device/hwm_vt82c686.c
View File

@@ -33,7 +33,7 @@
#define VT82C686_TEMP_TO_REG(t) (-1.160370e-10 * (t * t * t * t * t * t) + 3.193693e-08 * (t * t * t * t * t) - 1.464447e-06 * (t * t * t * t) - 2.525453e-04 * (t * t * t) + 1.424593e-02 * (t * t) + 2.148941e+00 * t + 7.275808e+01)
#define VT82C686_VOLTAGE_TO_REG(v, f) CLAMP((((v) * (2.628 / (f))) - 120.5) / 25, 0, 255)
typedef struct {
typedef struct vt82c686_t {
hwm_values_t *values;
uint8_t enable;
@@ -114,6 +114,7 @@ vt82c686_write(uint16_t port, uint8_t val, void *priv)
case 0x48:
val &= 0x7f;
break;
default:
break;
}

5
src/device/i2c.c
View File

@@ -38,9 +38,10 @@ typedef struct _i2c_ {
struct _i2c_ *prev, *next;
} i2c_t;
typedef struct {
typedef struct i2c_bus_t {
char *name;
i2c_t *devices[NADDRS], *last[NADDRS];
i2c_t *devices[NADDRS];
i2c_t *last[NADDRS];
} i2c_bus_t;
void *i2c_smbus;

13
src/device/i2c_gpio.c
View File

@@ -24,11 +24,18 @@
#include <86box/86box.h>
#include <86box/i2c.h>
typedef struct {
typedef struct i2c_gpio_t {
char *bus_name;
void *i2c;
uint8_t prev_scl, prev_sda, slave_sda, started,
slave_addr_received, slave_addr, slave_read, pos, byte;
uint8_t prev_scl;
uint8_t prev_sda;
uint8_t slave_sda;
uint8_t started;
uint8_t slave_addr_received;
uint8_t slave_addr;
uint8_t slave_read;
uint8_t pos;
uint8_t byte;
} i2c_gpio_t;
#ifdef ENABLE_I2C_GPIO_LOG

7
src/device/ibm_5161.c
View File

@@ -30,8 +30,7 @@
#include <86box/port_92.h>
#include <86box/machine.h>
typedef struct
{
typedef struct ibm_5161_t {
uint8_t regs[8];
} ibm_5161_t;
@@ -86,9 +85,9 @@ ibm_5161_in(uint16_t port, void *priv)
}
static void
ibm_5161_close(void *p)
ibm_5161_close(void *priv)
{
ibm_5161_t *dev = (ibm_5161_t *) p;
ibm_5161_t *dev = (ibm_5161_t *) priv;
free(dev);
}

20
src/device/isamem.c
View File

@@ -112,7 +112,7 @@
#define EXTRAM_HIGH 1
#define EXTRAM_XMS 2
typedef struct {
typedef struct emsreg_t {
int8_t enabled; /* 1=ENABLED */
uint8_t page; /* page# in EMS RAM */
uint8_t frame; /* (varies with board) */
@@ -121,15 +121,15 @@ typedef struct {
mem_mapping_t mapping; /* mapping entry for page */
} emsreg_t;
typedef struct {
typedef struct ext_ram_t {
uint32_t base;
uint8_t *ptr;
} ext_ram_t;
typedef struct {
typedef struct memdev_t {
const char *name;
uint8_t board : 6, /* board type */
reserved : 2;
uint8_t board : 6; /* board type */
uint8_t reserved : 2;
uint8_t flags;
#define FLAG_CONFIG 0x01 /* card is configured */
@@ -138,12 +138,12 @@ typedef struct {
#define FLAG_EMS 0x40 /* card has EMS mode enabled */
uint16_t total_size; /* configured size in KB */
uint32_t base_addr, /* configured I/O address */
start_addr, /* configured memory start */
frame_addr; /* configured frame address */
uint32_t base_addr; /* configured I/O address */
uint32_t start_addr; /* configured memory start */
uint32_t frame_addr; /* configured frame address */
uint16_t ems_size, /* EMS size in KB */
ems_pages; /* EMS size in pages */
uint16_t ems_size; /* EMS size in KB */
uint16_t ems_pages; /* EMS size in pages */
uint32_t ems_start; /* start of EMS in RAM */
uint8_t *ram; /* allocated RAM buffer */

59
src/device/isapnp.c
View File

@@ -82,34 +82,48 @@ enum {
typedef struct _isapnp_device_ {
uint8_t number;
uint8_t regs[256];
uint8_t mem_upperlimit, irq_types, io_16bit, io_len[8];
uint8_t mem_upperlimit;
uint8_t irq_types;
uint8_t io_16bit;
uint8_t io_len[8];
const isapnp_device_config_t *defaults;
struct _isapnp_device_ *next;
} isapnp_device_t;
typedef struct _isapnp_card_ {
uint8_t enable, state, csn, id_checksum, serial_read, serial_read_pair, serial_read_pos, *rom;
uint16_t rom_pos, rom_size;
uint8_t enable;
uint8_t state;
uint8_t csn;
uint8_t id_checksum;
uint8_t serial_read;
uint8_t serial_read_pair;
uint8_t serial_read_pos;
uint8_t *rom;
uint16_t rom_pos;
uint16_t rom_size;
void *priv;
/* ISAPnP memory and I/O addresses are awkwardly big endian, so we populate this
structure whenever something on some device changes, and pass it on instead. */
isapnp_device_config_t config;
void (*config_changed)(uint8_t ld, isapnp_device_config_t *config, void *priv);
void (*csn_changed)(uint8_t csn, void *priv);
void (*config_changed)(uint8_t ld, isapnp_device_config_t *config, void *priv);
void (*csn_changed)(uint8_t csn, void *priv);
uint8_t (*read_vendor_reg)(uint8_t ld, uint8_t reg, void *priv);
void (*write_vendor_reg)(uint8_t ld, uint8_t reg, uint8_t val, void *priv);
void (*write_vendor_reg)(uint8_t ld, uint8_t reg, uint8_t val, void *priv);
isapnp_device_t *first_ld;
struct _isapnp_card_ *next;
} isapnp_card_t;
typedef struct {
uint8_t reg, key_pos : 5;
uint8_t reg;
uint8_t key_pos : 5;
uint16_t read_data_addr;
isapnp_card_t *first_card, *isolated_card, *current_ld_card;
isapnp_card_t *first_card;
isapnp_card_t *isolated_card;
isapnp_card_t *current_ld_card;
isapnp_device_t *current_ld;
} isapnp_t;
@@ -122,36 +136,35 @@ isapnp_device_config_changed(isapnp_card_t *card, isapnp_device_t *ld)
/* Populate config structure, performing endianness conversion as needed. */
card->config.activate = ld->regs[0x30] & 0x01;
uint8_t i;
uint8_t reg_base;
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
reg_base = 0x40 + (8 * i);
card->config.mem[i].base = (ld->regs[reg_base] << 16) | (ld->regs[reg_base + 1] << 8);
card->config.mem[i].size = (ld->regs[reg_base + 3] << 16) | (ld->regs[reg_base + 4] << 8);
if (ld->regs[reg_base + 2] & 0x01) /* upper limit */
card->config.mem[i].size -= card->config.mem[i].base;
}
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
reg_base = (i == 0) ? 0x76 : (0x80 + (16 * i));
card->config.mem32[i].base = (ld->regs[reg_base] << 24) | (ld->regs[reg_base + 1] << 16) | (ld->regs[reg_base + 2] << 8) | ld->regs[reg_base + 3];
card->config.mem32[i].size = (ld->regs[reg_base + 5] << 24) | (ld->regs[reg_base + 6] << 16) | (ld->regs[reg_base + 7] << 8) | ld->regs[reg_base + 8];
if (ld->regs[reg_base + 4] & 0x01) /* upper limit */
card->config.mem32[i].size -= card->config.mem32[i].base;
}
for (i = 0; i < 8; i++) {
for (uint8_t i = 0; i < 8; i++) {
reg_base = 0x60 + (2 * i);
if (ld->regs[0x31] & 0x02)
card->config.io[i].base = 0; /* let us handle I/O range check reads */
else
card->config.io[i].base = (ld->regs[reg_base] << 8) | ld->regs[reg_base + 1];
}
for (i = 0; i < 2; i++) {
for (uint8_t i = 0; i < 2; i++) {
reg_base = 0x70 + (2 * i);
card->config.irq[i].irq = ld->regs[reg_base];
card->config.irq[i].level = ld->regs[reg_base + 1] & 0x02;
card->config.irq[i].type = ld->regs[reg_base + 1] & 0x01;
}
for (i = 0; i < 2; i++) {
for (uint8_t i = 0; i < 2; i++) {
reg_base = 0x74 + i;
card->config.dma[i].dma = ld->regs[reg_base];
}
@@ -170,10 +183,9 @@ isapnp_reset_ld_config(isapnp_device_t *ld)
/* Populate configuration registers. */
ld->regs[0x30] = !!config->activate;
uint8_t i;
uint8_t reg_base;
uint32_t size;
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
reg_base = 0x40 + (8 * i);
ld->regs[reg_base] = config->mem[i].base >> 16;
ld->regs[reg_base + 1] = config->mem[i].base >> 8;
@@ -183,7 +195,7 @@ isapnp_reset_ld_config(isapnp_device_t *ld)
ld->regs[reg_base + 3] = size >> 16;
ld->regs[reg_base + 4] = size >> 8;
}
for (i = 0; i < 4; i++) {
for (uint8_t i = 0; i < 4; i++) {
reg_base = (i == 0) ? 0x76 : (0x80 + (16 * i));
ld->regs[reg_base] = config->mem32[i].base >> 24;
ld->regs[reg_base + 1] = config->mem32[i].base >> 16;
@@ -197,17 +209,17 @@ isapnp_reset_ld_config(isapnp_device_t *ld)
ld->regs[reg_base + 7] = size >> 8;
ld->regs[reg_base + 8] = size;
}
for (i = 0; i < 8; i++) {
for (uint8_t i = 0; i < 8; i++) {
reg_base = 0x60 + (2 * i);
ld->regs[reg_base] = config->io[i].base >> 8;
ld->regs[reg_base + 1] = config->io[i].base;
}
for (i = 0; i < 2; i++) {
for (uint8_t i = 0; i < 2; i++) {
reg_base = 0x70 + (2 * i);
ld->regs[reg_base] = config->irq[i].irq;
ld->regs[reg_base + 1] = (!!config->irq[i].level << 1) | !!config->irq[i].type;
}
for (i = 0; i < 2; i++) {
for (uint8_t i = 0; i < 2; i++) {
reg_base = 0x74 + i;
ld->regs[reg_base] = config->dma[i].dma;
}
@@ -222,15 +234,14 @@ isapnp_reset_ld_regs(isapnp_device_t *ld)
ld->regs[0x74] = ld->regs[0x75] = ISAPNP_DMA_DISABLED;
/* Set the upper limit bit on memory ranges which require it. */
uint8_t i;
for (i = 0; i < 4; i++)
for (uint8_t i = 0; i < 4; i++)
ld->regs[0x42 + (8 * i)] |= !!(ld->mem_upperlimit & (1 << i));
ld->regs[0x7a] |= !!(ld->mem_upperlimit & (1 << 4));
for (i = 1; i < 4; i++)
for (uint8_t i = 1; i < 4; i++)
ld->regs[0x84 + (16 * i)] |= !!(ld->mem_upperlimit & (1 << (4 + i)));
/* Set the default IRQ type bits. */
for (i = 0; i < 2; i++) {
for (uint8_t i = 0; i < 2; i++) {
if (ld->irq_types & (0x1 << (4 * i)))
ld->regs[0x70 + (2 * i)] = 0x02;
else if (ld->irq_types & (0x2 << (4 * i)))

20
src/device/isartc.c
View File

@@ -90,7 +90,7 @@
#define ISARTC_DEBUG 0
typedef struct {
typedef struct rtcdev_t {
const char *name; /* board name */
uint8_t board; /* board type */
@@ -103,18 +103,18 @@ typedef struct {
uint32_t base_addr; /* configured I/O address */
/* Fields for the specific driver. */
void (*f_wr)(uint16_t, uint8_t, void *);
void (*f_wr)(uint16_t, uint8_t, void *);
uint8_t (*f_rd)(uint16_t, void *);
int8_t year; /* register for YEAR value */
char pad[3];
int8_t year; /* register for YEAR value */
char pad[3];
nvr_t nvr; /* RTC/NVR */
} rtcdev_t;
/************************************************************************
* *
* Driver for the NatSemi MM58167 chip. *
* *
* *
* Driver for the NatSemi MM58167 chip. *
* *
************************************************************************/
#define MM67_REGS 32
@@ -499,9 +499,9 @@ mm67_write(uint16_t port, uint8_t val, void *priv)
}
/************************************************************************
* *
* Generic code for all supported chips. *
* *
* *
* Generic code for all supported chips. *
* *
************************************************************************/
/* Initialize the device for use. */

34
src/device/kbc_at.c
View File

@@ -104,12 +104,27 @@ enum {
STATE_SCAN_AUX /* KBC is waiting for the auxiliary command response. */
};
typedef struct {
uint8_t state, command, command_phase, status,
wantdata, ib, ob, sc_or,
mem_addr, p1, p2, old_p2,
misc_flags, ami_flags, key_ctrl_queue_start, key_ctrl_queue_end,
val, channel, stat_hi, pending;
typedef struct atkbc_t {
uint8_t state;
uint8_t command;
uint8_t command_phase;
uint8_t status;
uint8_t wantdata;
uint8_t ib;
uint8_t ob;
uint8_t sc_or;
uint8_t mem_addr;
uint8_t p1;
uint8_t p2;
uint8_t old_p2;
uint8_t misc_flags;
uint8_t ami_flags;
uint8_t key_ctrl_queue_start;
uint8_t key_ctrl_queue_end;
uint8_t val;
uint8_t channel;
uint8_t stat_hi;
uint8_t pending;
uint8_t mem[0x100];
@@ -308,7 +323,7 @@ static void
kbc_send_to_ob(atkbc_t *dev, uint8_t val, uint8_t channel, uint8_t stat_hi)
{
uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
int temp = (channel == 1) ? kbc_translate(dev, val) : val;
uint8_t temp = (channel == 1) ? kbc_translate(dev, val) : val;
if (temp == -1)
return;
@@ -429,7 +444,8 @@ kbc_scan_kbd_at(atkbc_t *dev)
}
}
static void write_p2(atkbc_t *dev, uint8_t val);
static void
write_p2(atkbc_t *dev, uint8_t val);
static void
kbc_at_poll_at(atkbc_t *dev)
@@ -1299,6 +1315,7 @@ write64_olivetti(void *priv, uint8_t val)
kbc_delay_to_ob(dev, (0x0c | (is386 ? 0x00 : 0x80)) & 0xdf, 0, 0x00);
dev->p1 = ((dev->p1 + 1) & 3) | (dev->p1 & 0xfc);
return 0;
default:
break;
}
@@ -1339,6 +1356,7 @@ write60_toshiba(void *priv, uint8_t val)
kbc_at_log("ATkbc: T3100e - set color/mono switch\n");
t3100e_mono_set(val);
return 0;
default:
break;
}

2
src/device/keyboard.c
View File

@@ -167,6 +167,7 @@ keyboard_input(int down, uint16_t scan)
case 0x138: /* Right Alt */
shift |= 0x40;
break;
default:
break;
}
@@ -199,6 +200,7 @@ keyboard_input(int down, uint16_t scan)
case 0x046:
scroll_lock ^= 1;
break;
default:
break;
}

2
src/device/keyboard_at.c
View File

@@ -67,7 +67,7 @@ uint8_t keyboard_set3_all_break;
/* Global keyboard mode:
Bits 0 - 1 = scan code set. */
uint8_t keyboard_mode = 0x02;
uint8_t keyboard_mode = 0x02;
static atkbc_dev_t *SavedKbd = NULL;

10
src/device/keyboard_xt.c
View File

@@ -68,14 +68,18 @@
#define KBD_TYPE_PRAVETZ 10
#define KBD_TYPE_XTCLONE 11
typedef struct {
typedef struct xtkbd_t {
int want_irq;
int blocked;
int tandy;
uint8_t pa, pb, pd, clock;
uint8_t pa;
uint8_t pb;
uint8_t pd;
uint8_t clock;
uint8_t key_waiting;
uint8_t type, pravetz_flags;
uint8_t type;
uint8_t pravetz_flags;
pc_timer_t send_delay_timer;
} xtkbd_t;

2
src/device/mouse.c
View File

@@ -32,7 +32,7 @@
#include <86box/mouse.h>
#include <86box/plat_unused.h>
typedef struct {
typedef struct mouse_t {
const device_t *device;
} mouse_t;

32
src/device/mouse_bus.c
View File

@@ -133,16 +133,26 @@ static const uint8_t periods[4] = { 30, 50, 100, 200 };
/* Our mouse device. */
typedef struct mouse {
uint8_t current_b, control_val,
config_val, sig_val,
command_val, pad;
uint8_t current_b;
uint8_t control_val;
uint8_t config_val;
uint8_t sig_val;
uint8_t command_val;
uint8_t pad;
int8_t current_x, current_y;
int8_t current_x;
int8_t current_y;
int base, irq, bn, flags,
mouse_delayed_dx, mouse_delayed_dy,
mouse_buttons, mouse_buttons_last,
toggle_counter, timer_enabled;
int base;
int irq;
int bn;
int flags;
int mouse_delayed_dx;
int mouse_delayed_dy;
int mouse_buttons;
int mouse_buttons_last;
int toggle_counter;
int timer_enabled;
double period;
pc_timer_t timer; /* mouse event timer */
@@ -217,6 +227,7 @@ lt_read(uint16_t port, void *priv)
else
return 0xff;
break;
default:
break;
}
@@ -252,6 +263,7 @@ ms_read(uint16_t port, void *priv)
case INP_CTRL_COMMAND:
value = dev->control_val;
break;
default:
bm_log("ERROR: Reading data port in unsupported mode 0x%02x\n", dev->control_val);
}
@@ -266,6 +278,7 @@ ms_read(uint16_t port, void *priv)
case INP_PORT_CONFIG:
bm_log("ERROR: Unsupported read from port 0x%04x\n", port);
break;
default:
break;
}
@@ -388,6 +401,7 @@ ms_write(uint16_t port, uint8_t val, void *priv)
case INP_CTRL_READ_Y:
dev->command_val = val & 0x07;
break;
default:
bm_log("ERROR: Unsupported command written to port 0x%04x (value = 0x%02x)\n", port, val);
}
@@ -437,6 +451,7 @@ ms_write(uint16_t port, uint8_t val, void *priv)
dev->control_val &= INP_PERIOD_MASK;
dev->control_val |= (val & ~INP_PERIOD_MASK);
return;
default:
bm_log("ERROR: Unsupported period written to port 0x%04x (value = 0x%02x)\n", port, val);
}
@@ -444,6 +459,7 @@ ms_write(uint16_t port, uint8_t val, void *priv)
dev->control_val = val;
break;
default:
bm_log("ERROR: Unsupported write to port 0x%04x (value = 0x%02x)\n", port, val);
}

54
src/device/mouse_serial.c
View File

@@ -48,27 +48,40 @@ enum {
REPORT_PHASE_TRANSMIT
};
typedef struct {
const char *name; /* name of this device */
int8_t type, /* type of this device */
port;
uint8_t flags, but, /* device flags */
want_data,
status, format,
prompt, on_change,
id_len, id[255],
data_len, data[5];
int abs_x, abs_y,
rel_x, rel_y,
rel_z,
oldb, lastb;
typedef struct mouse_t {
const char *name; /* name of this device */
int8_t type; /* type of this device */
int8_t port;
uint8_t flags; /* device flags */
uint8_t but;
uint8_t want_data;
uint8_t status;
uint8_t format;
uint8_t prompt;
uint8_t on_change;
uint8_t id_len;
uint8_t id[255];
uint8_t data_len;
uint8_t data[5];
int abs_x;
int abs_y;
int rel_x;
int rel_y;
int rel_z;
int oldb;
int lastb;
int command_pos, command_phase,
report_pos, report_phase,
command_enabled, report_enabled;
double transmit_period, report_period,
auto_period;
pc_timer_t command_timer, report_timer;
int command_pos;
int command_phase;
int report_pos;
int report_phase;
int command_enabled;
int report_enabled;
double transmit_period;
double report_period;
double auto_period;
pc_timer_t command_timer;
pc_timer_t report_timer;
serial_t *serial;
} mouse_t;
@@ -734,6 +747,7 @@ ltsermouse_write(UNUSED(struct serial_s *serial), void *priv, uint8_t data)
case 0x6B:
ltsermouse_command_phase(dev, PHASE_BUTTONS);
break;
default:
break;
}

49
src/device/mouse_wacom_tablet.c
View File

@@ -66,37 +66,49 @@ static const uint32_t wacom_resolution_values[4] = {
1270
};
typedef struct {
typedef struct mouse_wacom_t {
const char *name; /* name of this device */
int8_t type, /* type of this device */
port;
uint8_t flags, but, /* device flags */
status, bits,
data_rec[0x200];
int abs_x, abs_y,
rel_x, rel_y,
oldb, b;
int8_t type; /* type of this device */
int8_t port;
uint8_t flags; /* device flags */
uint8_t but;
uint8_t status;
uint8_t bits;
uint8_t data_rec[0x200];
int abs_x;
int abs_y;
int rel_x;
int rel_y;
int oldb;
int b;
Fifo8 data;
int data_rec_pos, mode, interval;
int increment, suppressed_increment;
int data_rec_pos;
int mode;
int interval;
int increment;
int suppressed_increment;
int transmission_stopped;
int reset;
int transmit_id, transmit_id_pending;
int transmit_id;
int transmit_id_pending;
int pressure_mode;
int suppressed, measurement;
int suppressed;
int measurement;
int remote_req;
uint32_t x_res, y_res;
const wacom_tablet_id* tablet_type;
uint32_t x_res;
uint32_t y_res;
const wacom_tablet_id *tablet_type;
int last_abs_x, last_abs_y; /* Suppressed/Increment Mode. */
int last_abs_x; /* Suppressed/Increment Mode. */
int last_abs_y; /* Suppressed/Increment Mode. */
union {
uint32_t settings; /* Settings DWORD */
/* We don't target any architectures except x86/x64/ARM32/ARM64.
(The ABIs for those are explicit in little-endian bit ordering) */
struct {
struct settings_bits {
uint8_t remote_mode : 1;
uint8_t bitpad_two_cursor_data : 1;
uint8_t mm961_orientation : 1;
@@ -128,7 +140,8 @@ typedef struct {
};
double transmit_period;
double old_tsc, reset_tsc;
double old_tsc;
double reset_tsc;
pc_timer_t report_timer;
serial_t *serial;

11
src/device/pci_bridge.c
View File

@@ -47,10 +47,10 @@
#define AGP_BRIDGE_VIA(x) (((x) >> 16) == 0x1106)
#define AGP_BRIDGE(x) ((x) >= AGP_BRIDGE_ALI_M5243)
typedef struct
{
typedef struct pci_bridge_t {
uint32_t local;
uint8_t type, ctl;
uint8_t type;
uint8_t ctl;
uint8_t regs[256];
uint8_t bus_index;
@@ -483,7 +483,6 @@ pci_bridge_init(const device_t *info)
uint8_t interrupt_count;
uint8_t interrupt_mask;
uint8_t slot_count;
uint8_t i;
pci_bridge_t *dev = (pci_bridge_t *) malloc(sizeof(pci_bridge_t));
memset(dev, 0, sizeof(pci_bridge_t));
@@ -499,7 +498,7 @@ pci_bridge_init(const device_t *info)
interrupt_count = sizeof(interrupts);
interrupt_mask = interrupt_count - 1;
if (dev->slot < 32) {
for (i = 0; i < interrupt_count; i++)
for (uint8_t i = 0; i < interrupt_count; i++)
interrupts[i] = pci_get_int(dev->slot, PCI_INTA + i);
}
pci_bridge_log("PCI Bridge %d: upstream bus %02X slot %02X interrupts %02X %02X %02X %02X\n", dev->bus_index, (dev->slot >> 5) & 0xff, dev->slot & 31, interrupts[0], interrupts[1], interrupts[2], interrupts[3]);
@@ -509,7 +508,7 @@ pci_bridge_init(const device_t *info)
else
slot_count = 1; /* AGP bridges always have 1 slot */
for (i = 0; i < slot_count; i++) {
for (uint8_t i = 0; i < slot_count; i++) {
/* Interrupts for bridge slots are assigned in round-robin: ABCD, BCDA, CDAB and so on. */
pci_bridge_log("PCI Bridge %d: downstream slot %02X interrupts %02X %02X %02X %02X\n", dev->bus_index, i, interrupts[i & interrupt_mask], interrupts[(i + 1) & interrupt_mask], interrupts[(i + 2) & interrupt_mask], interrupts[(i + 3) & interrupt_mask]);
pci_register_bus_slot(dev->bus_index, i, AGP_BRIDGE(dev->local) ? PCI_CARD_AGP : PCI_CARD_NORMAL,

298
src/device/phoenix_486_jumper.c
View File

@@ -1,149 +1,149 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Phoenix 486 Jumper Readout
*
*
*
* Authors: Tiseno100
*
* Copyright 2020 Tiseno100
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
/*
Bit 7 = Super I/O chip: 1 = enabled, 0 = disabled;
Bit 6 = Graphics card: 1 = standalone, 0 = on-board;
Bit 5 = ???? (if 1, siren and hangs);
Bit 4 = ????;
Bit 3 = ????;
Bit 2 = ????;
Bit 1 = ????;
Bit 0 = ????.
*/
typedef struct
{
uint8_t type, jumper;
} phoenix_486_jumper_t;
#ifdef ENABLE_PHOENIX_486_JUMPER_LOG
int phoenix_486_jumper_do_log = ENABLE_PHOENIX_486_JUMPER_LOG;
static void
phoenix_486_jumper_log(const char *fmt, ...)
{
va_list ap;
if (phoenix_486_jumper_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define phoenix_486_jumper_log(fmt, ...)
#endif
static void
phoenix_486_jumper_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
phoenix_486_jumper_log("Phoenix 486 Jumper: Write %02x\n", val);
if (dev->type == 1)
dev->jumper = val & 0xbf;
else
dev->jumper = val;
}
static uint8_t
phoenix_486_jumper_read(UNUSED(uint16_t addr), void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
phoenix_486_jumper_log("Phoenix 486 Jumper: Read %02x\n", dev->jumper);
return dev->jumper;
}
static void
phoenix_486_jumper_reset(void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
if (dev->type == 1)
dev->jumper = 0x00;
else {
dev->jumper = 0x9f;
if (gfxcard[0] != 0x01)
dev->jumper |= 0x40;
}
}
static void
phoenix_486_jumper_close(void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
free(dev);
}
static void *
phoenix_486_jumper_init(const device_t *info)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) malloc(sizeof(phoenix_486_jumper_t));
memset(dev, 0, sizeof(phoenix_486_jumper_t));
dev->type = info->local;
phoenix_486_jumper_reset(dev);
io_sethandler(0x0078, 0x0001, phoenix_486_jumper_read, NULL, NULL, phoenix_486_jumper_write, NULL, NULL, dev);
return dev;
}
const device_t phoenix_486_jumper_device = {
.name = "Phoenix 486 Jumper Readout",
.internal_name = "phoenix_486_jumper",
.flags = 0,
.local = 0,
.init = phoenix_486_jumper_init,
.close = phoenix_486_jumper_close,
.reset = phoenix_486_jumper_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t phoenix_486_jumper_pci_device = {
.name = "Phoenix 486 Jumper Readout (PCI machines)",
.internal_name = "phoenix_486_jumper_pci",
.flags = 0,
.local = 1,
.init = phoenix_486_jumper_init,
.close = phoenix_486_jumper_close,
.reset = phoenix_486_jumper_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Phoenix 486 Jumper Readout
*
*
*
* Authors: Tiseno100
*
* Copyright 2020 Tiseno100
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
/*
Bit 7 = Super I/O chip: 1 = enabled, 0 = disabled;
Bit 6 = Graphics card: 1 = standalone, 0 = on-board;
Bit 5 = ???? (if 1, siren and hangs);
Bit 4 = ????;
Bit 3 = ????;
Bit 2 = ????;
Bit 1 = ????;
Bit 0 = ????.
*/
typedef struct phoenix_486_jumper_t {
uint8_t type;
uint8_t jumper;
} phoenix_486_jumper_t;
#ifdef ENABLE_PHOENIX_486_JUMPER_LOG
int phoenix_486_jumper_do_log = ENABLE_PHOENIX_486_JUMPER_LOG;
static void
phoenix_486_jumper_log(const char *fmt, ...)
{
va_list ap;
if (phoenix_486_jumper_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define phoenix_486_jumper_log(fmt, ...)
#endif
static void
phoenix_486_jumper_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
phoenix_486_jumper_log("Phoenix 486 Jumper: Write %02x\n", val);
if (dev->type == 1)
dev->jumper = val & 0xbf;
else
dev->jumper = val;
}
static uint8_t
phoenix_486_jumper_read(UNUSED(uint16_t addr), void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
phoenix_486_jumper_log("Phoenix 486 Jumper: Read %02x\n", dev->jumper);
return dev->jumper;
}
static void
phoenix_486_jumper_reset(void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
if (dev->type == 1)
dev->jumper = 0x00;
else {
dev->jumper = 0x9f;
if (gfxcard[0] != 0x01)
dev->jumper |= 0x40;
}
}
static void
phoenix_486_jumper_close(void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
free(dev);
}
static void *
phoenix_486_jumper_init(const device_t *info)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) malloc(sizeof(phoenix_486_jumper_t));
memset(dev, 0, sizeof(phoenix_486_jumper_t));
dev->type = info->local;
phoenix_486_jumper_reset(dev);
io_sethandler(0x0078, 0x0001, phoenix_486_jumper_read, NULL, NULL, phoenix_486_jumper_write, NULL, NULL, dev);
return dev;
}
const device_t phoenix_486_jumper_device = {
.name = "Phoenix 486 Jumper Readout",
.internal_name = "phoenix_486_jumper",
.flags = 0,
.local = 0,
.init = phoenix_486_jumper_init,
.close = phoenix_486_jumper_close,
.reset = phoenix_486_jumper_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t phoenix_486_jumper_pci_device = {
.name = "Phoenix 486 Jumper Readout (PCI machines)",
.internal_name = "phoenix_486_jumper_pci",
.flags = 0,
.local = 1,
.init = phoenix_486_jumper_init,
.close = phoenix_486_jumper_close,
.reset = phoenix_486_jumper_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

12
src/device/serial_passthrough.c
View File

@@ -361,12 +361,12 @@ static const device_config_t serial_passthrough_config[] = {
// clang-format on
const device_t serial_passthrough_device = {
.name = "Serial Passthrough Device",
.flags = 0,
.local = 0,
.init = serial_passthrough_dev_init,
.close = serial_passthrough_dev_close,
.reset = NULL,
.name = "Serial Passthrough Device",
.flags = 0,
.local = 0,
.init = serial_passthrough_dev_init,
.close = serial_passthrough_dev_close,
.reset = NULL,
{ .poll = NULL },
.speed_changed = serial_passthrough_speed_changed,
.force_redraw = NULL,

2
src/include/86box/86box.h
View File

@@ -193,7 +193,7 @@ extern uint16_t get_last_addr(void);
/* This is for external subtraction of cycles;
should be in cpu.c but I put it here to avoid
having to include cpu.c everywhere. */
having to include cpu.h everywhere. */
extern void sub_cycles(int c);
extern void resub_cycles(int old_cycles);

9
src/include/86box/acpi.h
View File

@@ -75,7 +75,8 @@ typedef struct
uint8_t smireg;
uint8_t gpireg[3];
uint8_t gporeg[4];
uint8_t extiotrapsts, extiotrapen;
uint8_t extiotrapsts;
uint8_t extiotrapen;
uint16_t pmsts;
uint16_t pmen;
uint16_t pmcntrl;
@@ -120,8 +121,10 @@ typedef struct
uint16_t io_base;
uint16_t aux_io_base;
int vendor;
int slot, irq_mode;
int irq_pin, irq_line;
int slot;
int irq_mode;
int irq_pin;
int irq_line;
int mirq_is_level;
pc_timer_t timer;
pc_timer_t resume_timer;

5
src/include/86box/agpgart.h
View File

@@ -20,7 +20,10 @@
typedef struct agpgart_s {
int aperture_enable;
uint32_t aperture_base, aperture_size, aperture_mask, gart_base;
uint32_t aperture_base;
uint32_t aperture_size;
uint32_t aperture_mask;
uint32_t gart_base;
mem_mapping_t aperture_mapping;
} agpgart_t;

2
src/include/86box/cassette.h
View File

@@ -24,7 +24,7 @@
#include <stdio.h>
typedef struct {
typedef struct pc_cassette_t {
char save;
char pcm;

81
src/include/86box/cdrom.h
View File

@@ -65,52 +65,50 @@ enum {
#define BUS_TYPE_IDE 1
#define BUS_TYPE_SCSI 2
static const struct
{
static const struct {
const char vendor[9];
const char model[17];
const char revision[5];
const char *name;
const char *internal_name;
const int bus_type;
} cdrom_drive_types[] =
{
{ "86BOX", "CD-ROM", "1.00", "(ATAPI/SCSI) 86BOX CD-ROM 1.00", "86BOX_CD-ROM_1.00", BUS_TYPE_ALL}, /*1*/
{ "AZT", "CDA46802I", "1.15", "(ATAPI) AZT CDA46802I 1.15", "AZT_CDA46802I_1.15", BUS_TYPE_IDE}, /*2*/
{ "BTC", "CD-ROM BCD36XH", "U1.0", "(ATAPI) BTC CD-ROM BCD36XH U1.0", "BTC_CD-ROM_BCD36XH_U1.0", BUS_TYPE_IDE}, /*3*/
{ "GOLDSTAR", "CRD-8160B", "3.14", "(ATAPI) GOLDSTAR CRD-8160B 3.14", "GOLDSTAR_CRD-8160B_3.14", BUS_TYPE_IDE}, /*4*/
{ "HITACHI", "CDR-8130", "0020", "(ATAPI) HITACHI CDR-8130 0020", "HITACHI_CDR-8130_0020", BUS_TYPE_IDE}, /*5*/
{ "KENWOOD", "CD-ROM UCR-421", "208E", "(ATAPI) KENWOOD CD-ROM UCR-421 208E", "KENWOOD_CD-ROM_UCR-421_208E", BUS_TYPE_IDE}, /*6*/
{ "MATSHITA", "CD-ROM CR-587", "7S13", "(ATAPI) MATSHITA CD-ROM CR-587 7S13", "MATSHITA_CD-ROM_CR-587_7S13", BUS_TYPE_IDE}, /*7*/
{ "MATSHITA", "CD-ROM CR-588", "LS15", "(ATAPI) MATSHITA CD-ROM CR-588 LS15", "MATSHITA_CD-ROM_CR-588_LS15", BUS_TYPE_IDE}, /*8*/
{ "MATSHITA", "CR-571", "1.0e", "(ATAPI) MATSHITA CR-571 1.0e", "MATSHITA_CR-571_1.0e", BUS_TYPE_IDE}, /*9*/
{ "MATSHITA", "CR-572", "1.0j", "(ATAPI) MATSHITA CR-572 1.0j", "MATSHITA_CR-572_1.0j", BUS_TYPE_IDE}, /*10*/
{ "MITSUMI", "CRMC-FX4820T", "D02A", "(ATAPI) MITSUMI CRMC-FX4820T D02A", "MITSUMI_CRMC-FX4820T_D02A", BUS_TYPE_IDE}, /*11*/
{ "NEC", "CD-ROM DRIVE:260", "1.00", "(ATAPI) NEC CD-ROM DRIVE:260 1.00", "NEC_CD-ROM_DRIVE260_1.00", BUS_TYPE_IDE}, /*12*/
{ "NEC", "CD-ROM DRIVE:260", "1.01", "(ATAPI) NEC CD-ROM DRIVE:260 1.01", "NEC_CD-ROM_DRIVE260_1.01", BUS_TYPE_IDE}, /*13*/
{ "NEC", "CD-ROM DRIVE:273", "4.20", "(ATAPI) NEC CD-ROM DRIVE:273 4.20", "NEC_CD-ROM_DRIVE273_4.20", BUS_TYPE_IDE}, /*14*/
{ "NEC", "CD-ROM DRIVE:280", "1.05", "(ATAPI) NEC CD-ROM DRIVE:280 1.05", "NEC_CD-ROM_DRIVE280_1.05", BUS_TYPE_IDE}, /*15*/
{ "NEC", "CD-ROM DRIVE:280", "3.08", "(ATAPI) NEC CD-ROM DRIVE:280 3.08", "NEC_CD-ROM_DRIVE280_3.08", BUS_TYPE_IDE}, /*16*/
{ "PHILIPS", "CD-ROM PCA403CD", "U31P", "(ATAPI) PHILIPS CD-ROM PCA403CD U31P", "PHILIPS_CD-ROM_PCA403CD_U31P", BUS_TYPE_IDE}, /*17*/
{ "SONY", "CD-ROM CDU76", "1.0i", "(ATAPI) SONY CD-ROM CDU76 1.0i", "SONY_CD-ROM_CDU76_1.0i", BUS_TYPE_IDE}, /*18*/
{ "SONY", "CD-ROM CDU311", "3.0h", "(ATAPI) SONY CD-ROM CDU311 3.0h", "SONY_CD-ROM_CDU311_3.0h", BUS_TYPE_IDE}, /*19*/
{ "TOSHIBA", "CD-ROM XM-5302TA", "0305", "(ATAPI) TOSHIBA CD-ROM XM-5302TA 0305", "TOSHIBA_CD-ROM_XM-5302TA_0305", BUS_TYPE_IDE}, /*20*/
{ "TOSHIBA", "CD-ROM XM-5702B", "TA70", "(ATAPI) TOSHIBA CD-ROM XM-5702B TA70", "TOSHIBA_CD-ROM_XM-5702B_TA70", BUS_TYPE_IDE}, /*21*/
{ "CHINON", "CD-ROM CDS-431", "H42 ", "(SCSI) CHINON CD-ROM CDS-431 H42", "CHINON_CD-ROM_CDS-431_H42", BUS_TYPE_SCSI}, /*22*/
{ "DEC", "RRD45 (C) DEC", "0436", "(SCSI) DEC RRD45 0436", "DEC_RRD45_0436", BUS_TYPE_SCSI}, /*23*/
{ "MATSHITA", "CD-ROM CR-501", "1.0b", "(SCSI) MATSHITA CD-ROM CR-501 1.0b", "MATSHITA_CD-ROM_CR-501_1.0b", BUS_TYPE_SCSI}, /*24*/
{ "NEC", "CD-ROM DRIVE:74", "1.00", "(SCSI) NEC CD-ROM DRIVE:74 1.00", "NEC_CD-ROM_DRIVE74_1.00", BUS_TYPE_SCSI}, /*25*/
{ "NEC", "CD-ROM DRIVE:464", "1.05", "(SCSI) NEC CD-ROM DRIVE:464 1.05", "NEC_CD-ROM_DRIVE464_1.05", BUS_TYPE_SCSI}, /*26*/
{ "SONY", "CD-ROM CDU-541", "1.0i", "(SCSI) SONY CD-ROM CDU-541 1.0i", "SONY_CD-ROM_CDU-541_1.0i", BUS_TYPE_SCSI}, /*27*/
{ "SONY", "CD-ROM CDU-76S", "1.00", "(SCSI) SONY CD-ROM CDU-76S 1.00", "SONY_CD-ROM_CDU-76S_1.00", BUS_TYPE_SCSI}, /*28*/
{ "PHILIPS", "CDD2600", "1.07", "(SCSI) PHILIPS CDD2600 1.07", "PHILIPS_CDD2600_1.07", BUS_TYPE_SCSI}, /*29*/
{ "PIONEER", "CD-ROM DRM-604X", "2403", "(SCSI) PIONEER CD-ROM DRM-604X 2403", "PIONEER_CD-ROM_DRM-604X_2403", BUS_TYPE_SCSI}, /*30*/
{ "PLEXTOR", "CD-ROM PX-32TS", "1.03", "(SCSI) PLEXTOR CD-ROM PX-32TS 1.03", "PLEXTOR_CD-ROM_PX-32TS_1.03", BUS_TYPE_SCSI}, /*31*/
{ "TEAC", "CD-R55S", "1.0R", "(SCSI) TEAC CD-R55S 1.0R", "TEAC_CD-R55S_1.0R", BUS_TYPE_SCSI}, /*32*/
{ "TOSHIBA", "CD-ROM DRIVE:XM", "3433", "(SCSI) TOSHIBA CD-ROM DRIVE:XM 3433", "TOSHIBA_CD-ROM_DRIVEXM_3433", BUS_TYPE_SCSI}, /*33*/
{ "TOSHIBA", "CD-ROM XM-3301TA", "0272", "(SCSI) TOSHIBA CD-ROM XM-3301TA 0272", "TOSHIBA_CD-ROM_XM-3301TA_0272", BUS_TYPE_SCSI}, /*34*/
{ "TOSHIBA", "CD-ROM XM-5701TA", "3136", "(SCSI) TOSHIBA CD-ROM XM-5701TA 3136", "TOSHIBA_CD-ROM_XM-5701TA_3136", BUS_TYPE_SCSI}, /*35*/
{ "", "", "", "", "", -1},
} cdrom_drive_types[] = {
{ "86BOX", "CD-ROM", "1.00", "(ATAPI/SCSI) 86BOX CD-ROM 1.00", "86BOX_CD-ROM_1.00", BUS_TYPE_ALL }, /*1*/
{ "AZT", "CDA46802I", "1.15", "(ATAPI) AZT CDA46802I 1.15", "AZT_CDA46802I_1.15", BUS_TYPE_IDE }, /*2*/
{ "BTC", "CD-ROM BCD36XH", "U1.0", "(ATAPI) BTC CD-ROM BCD36XH U1.0", "BTC_CD-ROM_BCD36XH_U1.0", BUS_TYPE_IDE }, /*3*/
{ "GOLDSTAR", "CRD-8160B", "3.14", "(ATAPI) GOLDSTAR CRD-8160B 3.14", "GOLDSTAR_CRD-8160B_3.14", BUS_TYPE_IDE }, /*4*/
{ "HITACHI", "CDR-8130", "0020", "(ATAPI) HITACHI CDR-8130 0020", "HITACHI_CDR-8130_0020", BUS_TYPE_IDE }, /*5*/
{ "KENWOOD", "CD-ROM UCR-421", "208E", "(ATAPI) KENWOOD CD-ROM UCR-421 208E", "KENWOOD_CD-ROM_UCR-421_208E", BUS_TYPE_IDE }, /*6*/
{ "MATSHITA", "CD-ROM CR-587", "7S13", "(ATAPI) MATSHITA CD-ROM CR-587 7S13", "MATSHITA_CD-ROM_CR-587_7S13", BUS_TYPE_IDE }, /*7*/
{ "MATSHITA", "CD-ROM CR-588", "LS15", "(ATAPI) MATSHITA CD-ROM CR-588 LS15", "MATSHITA_CD-ROM_CR-588_LS15", BUS_TYPE_IDE }, /*8*/
{ "MATSHITA", "CR-571", "1.0e", "(ATAPI) MATSHITA CR-571 1.0e", "MATSHITA_CR-571_1.0e", BUS_TYPE_IDE }, /*9*/
{ "MATSHITA", "CR-572", "1.0j", "(ATAPI) MATSHITA CR-572 1.0j", "MATSHITA_CR-572_1.0j", BUS_TYPE_IDE }, /*10*/
{ "MITSUMI", "CRMC-FX4820T", "D02A", "(ATAPI) MITSUMI CRMC-FX4820T D02A", "MITSUMI_CRMC-FX4820T_D02A", BUS_TYPE_IDE }, /*11*/
{ "NEC", "CD-ROM DRIVE:260", "1.00", "(ATAPI) NEC CD-ROM DRIVE:260 1.00", "NEC_CD-ROM_DRIVE260_1.00", BUS_TYPE_IDE }, /*12*/
{ "NEC", "CD-ROM DRIVE:260", "1.01", "(ATAPI) NEC CD-ROM DRIVE:260 1.01", "NEC_CD-ROM_DRIVE260_1.01", BUS_TYPE_IDE }, /*13*/
{ "NEC", "CD-ROM DRIVE:273", "4.20", "(ATAPI) NEC CD-ROM DRIVE:273 4.20", "NEC_CD-ROM_DRIVE273_4.20", BUS_TYPE_IDE }, /*14*/
{ "NEC", "CD-ROM DRIVE:280", "1.05", "(ATAPI) NEC CD-ROM DRIVE:280 1.05", "NEC_CD-ROM_DRIVE280_1.05", BUS_TYPE_IDE }, /*15*/
{ "NEC", "CD-ROM DRIVE:280", "3.08", "(ATAPI) NEC CD-ROM DRIVE:280 3.08", "NEC_CD-ROM_DRIVE280_3.08", BUS_TYPE_IDE }, /*16*/
{ "PHILIPS", "CD-ROM PCA403CD", "U31P", "(ATAPI) PHILIPS CD-ROM PCA403CD U31P", "PHILIPS_CD-ROM_PCA403CD_U31P", BUS_TYPE_IDE }, /*17*/
{ "SONY", "CD-ROM CDU76", "1.0i", "(ATAPI) SONY CD-ROM CDU76 1.0i", "SONY_CD-ROM_CDU76_1.0i", BUS_TYPE_IDE }, /*18*/
{ "SONY", "CD-ROM CDU311", "3.0h", "(ATAPI) SONY CD-ROM CDU311 3.0h", "SONY_CD-ROM_CDU311_3.0h", BUS_TYPE_IDE }, /*19*/
{ "TOSHIBA", "CD-ROM XM-5302TA", "0305", "(ATAPI) TOSHIBA CD-ROM XM-5302TA 0305", "TOSHIBA_CD-ROM_XM-5302TA_0305", BUS_TYPE_IDE }, /*20*/
{ "TOSHIBA", "CD-ROM XM-5702B", "TA70", "(ATAPI) TOSHIBA CD-ROM XM-5702B TA70", "TOSHIBA_CD-ROM_XM-5702B_TA70", BUS_TYPE_IDE }, /*21*/
{ "CHINON", "CD-ROM CDS-431", "H42 ", "(SCSI) CHINON CD-ROM CDS-431 H42", "CHINON_CD-ROM_CDS-431_H42", BUS_TYPE_SCSI }, /*22*/
{ "DEC", "RRD45 (C) DEC", "0436", "(SCSI) DEC RRD45 0436", "DEC_RRD45_0436", BUS_TYPE_SCSI }, /*23*/
{ "MATSHITA", "CD-ROM CR-501", "1.0b", "(SCSI) MATSHITA CD-ROM CR-501 1.0b", "MATSHITA_CD-ROM_CR-501_1.0b", BUS_TYPE_SCSI }, /*24*/
{ "NEC", "CD-ROM DRIVE:74", "1.00", "(SCSI) NEC CD-ROM DRIVE:74 1.00", "NEC_CD-ROM_DRIVE74_1.00", BUS_TYPE_SCSI }, /*25*/
{ "NEC", "CD-ROM DRIVE:464", "1.05", "(SCSI) NEC CD-ROM DRIVE:464 1.05", "NEC_CD-ROM_DRIVE464_1.05", BUS_TYPE_SCSI }, /*26*/
{ "SONY", "CD-ROM CDU-541", "1.0i", "(SCSI) SONY CD-ROM CDU-541 1.0i", "SONY_CD-ROM_CDU-541_1.0i", BUS_TYPE_SCSI }, /*27*/
{ "SONY", "CD-ROM CDU-76S", "1.00", "(SCSI) SONY CD-ROM CDU-76S 1.00", "SONY_CD-ROM_CDU-76S_1.00", BUS_TYPE_SCSI }, /*28*/
{ "PHILIPS", "CDD2600", "1.07", "(SCSI) PHILIPS CDD2600 1.07", "PHILIPS_CDD2600_1.07", BUS_TYPE_SCSI }, /*29*/
{ "PIONEER", "CD-ROM DRM-604X", "2403", "(SCSI) PIONEER CD-ROM DRM-604X 2403", "PIONEER_CD-ROM_DRM-604X_2403", BUS_TYPE_SCSI }, /*30*/
{ "PLEXTOR", "CD-ROM PX-32TS", "1.03", "(SCSI) PLEXTOR CD-ROM PX-32TS 1.03", "PLEXTOR_CD-ROM_PX-32TS_1.03", BUS_TYPE_SCSI }, /*31*/
{ "TEAC", "CD-R55S", "1.0R", "(SCSI) TEAC CD-R55S 1.0R", "TEAC_CD-R55S_1.0R", BUS_TYPE_SCSI }, /*32*/
{ "TOSHIBA", "CD-ROM DRIVE:XM", "3433", "(SCSI) TOSHIBA CD-ROM DRIVE:XM 3433", "TOSHIBA_CD-ROM_DRIVEXM_3433", BUS_TYPE_SCSI }, /*33*/
{ "TOSHIBA", "CD-ROM XM-3301TA", "0272", "(SCSI) TOSHIBA CD-ROM XM-3301TA 0272", "TOSHIBA_CD-ROM_XM-3301TA_0272", BUS_TYPE_SCSI }, /*34*/
{ "TOSHIBA", "CD-ROM XM-5701TA", "3136", "(SCSI) TOSHIBA CD-ROM XM-5701TA 3136", "TOSHIBA_CD-ROM_XM-5701TA_3136", BUS_TYPE_SCSI }, /*35*/
{ "", "", "", "", "", -1 },
};
/* To shut up the GCC compilers. */
@@ -179,7 +177,8 @@ typedef struct cdrom {
uint32_t cdrom_capacity;
uint32_t seek_pos;
uint32_t seek_diff;
uint32_t cd_end, type;
uint32_t cd_end;
uint32_t type;
int host_drive;
int prev_host_drive;

140
src/include/86box/config.h
View File

@@ -28,109 +28,109 @@ extern "C" {
#if 0
typedef struct {
uint8_t id,
uint8_t bus_type, /* Bus type: IDE, SCSI, etc. */
bus, : 4, /* ID of the bus (for example, for IDE,
0 = primary, 1 = secondary, etc. */
bus_id, : 4, /* ID of the device on the bus */
uint8_t type, /* Type flags, interpretation depends
on the device */
uint8_t is_image; /* This is only used for CD-ROM:
0 = Image;
1 = Host drive */
uint8_t id;
uint8_t bus_type; /* Bus type: IDE, SCSI, etc. */
uint8_t bus, : 4; /* ID of the bus (for example, for IDE,
0 = primary, 1 = secondary, etc. */
uint8_t bus_id, : 4; /* ID of the device on the bus */
uint8_t type; /* Type flags, interpretation depends
on the device */
uint8_t is_image; /* This is only used for CD-ROM:
0 = Image;
1 = Host drive */
wchar_t path[1024]; /* Name of current image file or
host drive */
wchar_t path[1024]; /* Name of current image file or
host drive */
uint32_t spt, /* Physical geometry parameters */
hpc,
tracks;
uint32_t spt; /* Physical geometry parameters */
uint32_t hpc;
uint32_t tracks;
} storage_cfg_t;
typedef struct {
/* General configuration */
int vid_resize, /* Window is resizable or not */
vid_renderer, /* Renderer */
vid_fullscreen_scale, /* Full screen scale type */
vid_fullscreen_start, /* Start emulator in full screen */
vid_force_43, /* Force 4:3 display ratio in windowed mode */
vid_scale, /* Windowed mode scale */
vid_overscan, /* EGA/(S)VGA overscan enabled */
vid_cga_contrast, /* CGA alternate contrast enabled */
vid_grayscale, /* Video is grayscale */
vid_grayscale_type, /* Video grayscale type */
vid_invert_display, /* Invert display */
rctrl_is_lalt, /* Right CTRL is left ALT */
update_icons, /* Update status bar icons */
window_remember, /* Remember window position and size */
window_w, /* Window coordinates */
window_h,
window_x,
window_y,
sound_gain; /* Sound gain */
int vid_resize; /* Window is resizable or not */
int vid_renderer; /* Renderer */
int vid_fullscreen_scale; /* Full screen scale type */
int vid_fullscreen_start; /* Start emulator in full screen */
int vid_force_43; /* Force 4:3 display ratio in windowed mode */
int vid_scale; /* Windowed mode scale */
int vid_overscan; /* EGA/(S)VGA overscan enabled */
int vid_cga_contrast; /* CGA alternate contrast enabled */
int vid_grayscale; /* Video is grayscale */
int vid_grayscale_type; /* Video grayscale type */
int vid_invert_display; /* Invert display */
int rctrl_is_lalt; /* Right CTRL is left ALT */
int update_icons; /* Update status bar icons */
int window_remember; /* Remember window position and size */
int window_w; /* Window coordinates */
int window_h;
int window_x;
int window_y;
int sound_gain; /* Sound gain */
# ifdef USE_LANGUAGE
uint16_t language_id; /* Language ID (0x0409 = English (US)) */
uint16_t language_id; /* Language ID (0x0409 = English (US)) */
# endif
/* Machine cateogory */
int machine, /* Machine */
cpu, /* CPU */
int machine; /* Machine */
int cpu; /* CPU */
# ifdef USE_DYNAREC
cpu_use_dynarec, /* CPU recompiler enabled */
int cpu_use_dynarec; /* CPU recompiler enabled */
# endif
wait_states, /* CPU wait states */
enable_external_fpu, /* FPU enabled */
time_sync; /* Time sync enabled */
uint32_t mem_size; /* Memory size */
int wait_states; /* CPU wait states */
int enable_external_fpu; /* FPU enabled */
int time_sync; /* Time sync enabled */
uint32_t mem_size; /* Memory size */
/* Video category */
int video_card, /* Video card */
voodoo_enabled; /* Voodoo enabled */
int video_card; /* Video card */
int voodoo_enabled; /* Voodoo enabled */
/* Input devices category */
int mouse_type, /* Mouse type */
joystick_type; /* Joystick type */
int mouse_type; /* Mouse type */
int joystick_type; /* Joystick type */
/* Sound category */
int sound_card, /* Sound card */
midi_device, /* Midi device */
mpu_401, /* Standalone MPU-401 enabled */
ssi_2001_enabled, /* SSI-2001 enabled */
game_blaster_enabled, /* Game blaster enabled */
gus_enabled, /* Gravis Ultrasound enabled */
opl_type, /* OPL emulation type */
sound_is_float; /* Sound is 32-bit float or 16-bit integer */
int sound_card; /* Sound card */
int midi_device; /* Midi device */
int mpu_401; /* Standalone MPU-401 enabled */
int ssi_2001_enabled; /* SSI-2001 enabled */
int game_blaster_enabled; /* Game blaster enabled */
int gus_enabled; /* Gravis Ultrasound enabled */
int opl_type; /* OPL emulation type */
int sound_is_float; /* Sound is 32-bit float or 16-bit integer */
/* Network category */
int network_type, /* Network type (SLiRP or PCap) */
network_card; /* Network card */
char network_host[520]; /* PCap device */
int network_type; /* Network type (SLiRP or PCap) */
int network_card; /* Network card */
char network_host[520]; /* PCap device */
/* Ports category */
char parallel_devices[PARALLEL_MAX][32]; /* LPT device names */
# ifdef USE_SERIAL_DEVICES
char serial_devices[SERIAL_MAX][32]; /* Serial device names */
char serial_devices[SERIAL_MAX][32]; /* Serial device names */
# endif
/* Other peripherals category */
int fdc_type, /* Floppy disk controller type */
hdc, /* Hard disk controller */
scsi_card, /* SCSI controller */
ide_ter_enabled, /* Tertiary IDE controller enabled */
ide_qua_enabled, /* Quaternary IDE controller enabled */
bugger_enabled, /* ISA bugger device enabled */
isa_rtc_type, /* ISA RTC card */
isa_mem_type[ISAMEM_MAX]; /* ISA memory boards */
int fdc_type; /* Floppy disk controller type */
int hdc; /* Hard disk controller */
int scsi_card; /* SCSI controller */
int ide_ter_enabled; /* Tertiary IDE controller enabled */
int ide_qua_enabled; /* Quaternary IDE controller enabled */
int bugger_enabled; /* ISA bugger device enabled */
int isa_rtc_type; /* ISA RTC card */
int isa_mem_type[ISAMEM_MAX]; /* ISA memory boards */
/* Hard disks category */
storage_cfg_t hdd[HDD_NUM]; /* Hard disk drives */
storage_cfg_t hdd[HDD_NUM]; /* Hard disk drives */
/* Floppy drives category */
storage_cfg_t fdd[FDD_NUM]; /* Floppy drives */
storage_cfg_t fdd[FDD_NUM]; /* Floppy drives */
/* Other removable devices category */
storage_cfg_t cdrom[CDROM_NUM], /* CD-ROM drives */
storage_cfg_t rdisk[ZIP_NUM]; /* Removable disk drives */
storage_cfg_t cdrom[CDROM_NUM]; /* CD-ROM drives */
storage_cfg_t rdisk[ZIP_NUM]; /* Removable disk drives */
} config_t;
#endif

19
src/include/86box/gameport.h
View File

@@ -57,8 +57,7 @@ typedef struct {
int id;
} pov[4];
struct
{
struct {
char name[260];
int id;
} slider[2];
@@ -84,16 +83,16 @@ typedef struct {
const char *name;
const char *internal_name;
void *(*init)(void);
void (*close)(void *p);
void *(*init)(void);
void (*close)(void *p);
uint8_t (*read)(void *p);
void (*write)(void *p);
int (*read_axis)(void *p, int axis);
void (*a0_over)(void *p);
void (*write)(void *p);
int (*read_axis)(void *p, int axis);
void (*a0_over)(void *p);
int axis_count;
int button_count;
int pov_count;
int axis_count;
int button_count;
int pov_count;
int max_joysticks;
const char *axis_names[8];
const char *button_names[32];

4
src/include/86box/hwm.h
View File

@@ -20,13 +20,13 @@
#define RESISTOR_DIVIDER(v, r1, r2) (((v) * (r2)) / ((r1) + (r2)))
typedef struct {
typedef struct hwm_values_t {
uint16_t fans[4];
uint8_t temperatures[4];
uint16_t voltages[13];
} hwm_values_t;
typedef struct {
typedef struct lm75_t {
uint32_t local;
hwm_values_t *values;
void *as99127f;

2
src/mem/sst_flash.c
View File

@@ -17,7 +17,7 @@
*
* Copyright 2008-2020 Sarah Walker.
* Copyright 2016-2020 Miran Grca.
* Copyright 2020 Melissa Goad.
* Copyright 2020 Melody Goad.
* Copyright 2022-2023 Jasmine Iwanek.
*/
#include <stdio.h>

3
src/sound/snd_ac97_codec.c
View File

@@ -445,6 +445,9 @@ rate: /* Writable only if VRA/VRM is set. */
case 0x7c: /* Vendor ID1 */
case 0x7e: /* Vendor ID2 */
return;
default:
break;
}
dev->regs[reg >> 1] = val;