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Merge remote-tracking branch 'origin/master' into feature/recompiler_improvements

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This commit is contained in:
OBattler
2026-01-28 08:50:47 +01:00
parent 7ffe6afbcb 8b1e1ab1bf
commit b210278778
146 changed files with 9128 additions and 2371 deletions
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1
.ci/AppImageBuilder.yml
View File

@@ -48,6 +48,7 @@ AppDir:
- libfreetype6
- libgomp1
- libgs9
- libinstpatch-1.0-2
- libpng16-16
- libqt5core5a # if QT:BOOL=ON
- libqt5gui5 # if QT:BOOL=ON

42
.ci/build.sh
View File

@@ -12,7 +12,7 @@
#
# Authors: RichardG, <richardg867@gmail.com>
#
# Copyright 2021-2023 RichardG.
# Copyright 2021-2026 RichardG.
#
#
@@ -334,6 +334,7 @@ toolchain_file="cmake/$toolchain.cmake"
toolchain_file_libs=
# Perform platform-specific setup.
cc_binary=gcc
strip_binary=strip
if is_windows
then
@@ -377,7 +378,7 @@ then
fi
# Establish general dependencies.
pkgs="git"
pkgs="git make"
# Gather installed architecture-specific packages for updating.
# This prevents outdated shared libraries, unmet dependencies
@@ -698,7 +699,7 @@ else
# ...and the ones we do want listed. Non-dev packages fill missing spots on the list.
libpkgs=""
longest_libpkg=0
for pkg in libc6-dev libstdc++6 libopenal-dev libfreetype6-dev libx11-dev libsdl2-dev libpng-dev librtmidi-dev qtdeclarative5-dev libwayland-dev libevdev-dev libxkbcommon-x11-dev libglib2.0-dev libslirp-dev libfaudio-dev libaudio-dev libjack-jackd2-dev libpipewire-0.3-dev libsamplerate0-dev libsndio-dev libvdeplug-dev libfluidsynth-dev libsndfile1-dev libserialport-dev
for pkg in libc6-dev libstdc++6 libopenal-dev libfreetype6-dev libx11-dev libsdl2-dev libpng-dev librtmidi-dev qtdeclarative5-dev libwayland-dev libevdev-dev libxkbcommon-x11-dev libglib2.0-dev libslirp-dev libfaudio-dev libaudio-dev libjack-jackd2-dev libpipewire-0.3-dev libsamplerate0-dev libsndio-dev libvdeplug-dev libfluidsynth-dev libsndfile1-dev libinstpatch-dev libserialport-dev
do
libpkgs="$libpkgs $pkg:$arch_deb"
length=$(echo -n $pkg | sed 's/-dev$//' | sed "s/qtdeclarative/qt/" | wc -c)
@@ -742,6 +743,7 @@ set(ENV{PKG_CONFIG_LIBDIR} "/usr/lib/$libdir/pkgconfig:/usr/share/$libdir/pkgcon
include("$(realpath "$toolchain_file")")
EOF
toolchain_file="$toolchain_file_new"
cc_binary="$arch_triplet-gcc"
strip_binary="$arch_triplet-strip"
# Create a separate toolchain file for library compilation without including
@@ -881,14 +883,14 @@ then
fi
# Download assets if we're making a release build.
git_repo=$(git remote get-url origin 2> /dev/null)
if [ "$CI" = "true" ]
then
# Backup strategy when running under Jenkins.
[ -z "$git_repo" ] && git_repo=$GIT_URL
fi
if grep -qiE "^BUILD_TYPE:[^=]+=release" build/CMakeCache.txt 2> /dev/null
then
git_repo=$(git remote get-url origin 2> /dev/null)
if [ "$CI" = "true" ]
then
# Backup strategy when running under Jenkins.
[ -z "$git_repo" ] && git_repo=$GIT_URL
fi
if [ -n "$git_repo" ]
then
echo [-] Downloading assets
@@ -905,6 +907,17 @@ then
fi
fi
# Build mdsx library.
debug_args=
grep -qiE "^CMAKE_BUILD_TYPE:[^=]+=Debug" build/CMakeCache.txt && debug_args=DEBUG=y
cd archive_tmp
git clone --depth 1 "$(dirname "$git_repo")/mdsx.git" mdsx || exit 99
make -C mdsx/src -j$(nproc) CC="$cc_binary" STRIP="$strip_binary" $debug_args || exit 99
rm -f mdsx/src/*.a
mv mdsx/src/mdsx.* . || exit 99
rm -rf mdsx
cd ..
# Archive the executable and its dependencies.
# The executable should always be archived last for the check after this block.
status=0
@@ -952,6 +965,9 @@ then
unzip -j "$discord_zip" "lib/$arch_discord/discord_game_sdk.dylib" -d "archive_tmp/"*".app/Contents/Frameworks"
[ ! -e "archive_tmp/"*".app/Contents/Frameworks/discord_game_sdk.dylib" ] && echo [!] No Discord Game SDK for architecture [$arch_discord]
# Archive mdsx library.
mv "archive_tmp/mdsx.dylib" "archive_tmp/"*".app/Contents/Frameworks/"
# Hack to convert x86_64 binaries to x86_64h when building that architecture.
if [ "$arch" = "x86_64h" ]
then
@@ -1081,7 +1097,8 @@ else
wget -qO - https://github.com/FluidSynth/fluidsynth/archive/refs/tags/v2.3.0.tar.gz | tar zxf - -C "$cache_dir" || rm -rf "$prefix"
fi
prefix_build="$prefix/build-$arch_deb"
cmake -G Ninja -D enable-dbus=OFF -D enable-jack=OFF -D enable-oss=OFF -D enable-sdl2=OFF -D enable-pulseaudio=OFF -D enable-pipewire=OFF -D enable-alsa=OFF \
cmake -G Ninja -D enable-jack=OFF -D enable-oss=OFF -D enable-sdl2=OFF -D enable-pulseaudio=OFF -D enable-pipewire=OFF -D enable-alsa=OFF \
-D enable-aufile=OFF -D enable-dbus=OFF -D enable-network=OFF -D enable-ipv6=OFF \
-D "CMAKE_TOOLCHAIN_FILE=$toolchain_file_libs" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" \
-S "$prefix" -B "$prefix_build" || exit 99
cmake --build "$prefix_build" -j$(nproc) || exit 99
@@ -1136,6 +1153,9 @@ else
7z e -y -o"archive_tmp/usr/lib" "$discord_zip" "lib/$arch_discord/discord_game_sdk.so"
[ ! -e "archive_tmp/usr/lib/discord_game_sdk.so" ] && echo [!] No Discord Game SDK for architecture [$arch_discord]
# Archive mdsx library.
mv "archive_tmp/mdsx.so" "archive_tmp/usr/lib/"
# Archive readme with library package versions.
echo Libraries used to compile this $arch build of $project: > archive_tmp/README
dpkg-query -f '${Package} ${Version}\n' -W $libpkgs | sed "s/-dev / /" | sed "s/qtdeclarative/qt/" | while IFS=" " read pkg version
@@ -1257,7 +1277,7 @@ EOF
then
rm -rf "$cache_dir/appimage-builder-"* # remove old versions
python3 -m venv "$appimage_builder_dir" # venv to solve some Debian setuptools headaches
"$appimage_builder_dir/bin/pip" install -U "git+https://github.com/AppImageCrafters/appimage-builder.git@$appimage_builder_commit"
"$appimage_builder_dir/bin/pip" install -U "git+https://github.com/AppImageCrafters/appimage-builder.git@$appimage_builder_commit" 'setuptools<81'
fi
# Symlink appimage-builder global cache directory.

1
.ci/dependencies_msys.txt
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@@ -15,3 +15,4 @@ qt5-translations
vulkan-headers
libsndfile
libserialport
make

3
CMakeLists.txt
View File

@@ -36,7 +36,7 @@ if(MUNT_EXTERNAL)
endif()
project(86Box
VERSION 5.4
VERSION 6.0
DESCRIPTION "Emulator of x86-based systems"
HOMEPAGE_URL "https://86box.net"
LANGUAGES C CXX)
@@ -180,7 +180,6 @@ cmake_dependent_option(ISAMEM_RAMPAGE "AST Rampage"
cmake_dependent_option(ISAMEM_IAB "Intel Above Board" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_BRAT "BocaRAM/AT" ON "DEV_BRANCH" OFF)
cmake_dependent_option(OPL4ML "OPL4-ML daughterboard" ON "DEV_BRANCH" OFF)
cmake_dependent_option(PCL "Generic PCL5e Printer" ON "DEV_BRANCH" OFF)
cmake_dependent_option(SIO_DETECT "Super I/O Detection Helper" ON "DEV_BRANCH" OFF)
cmake_dependent_option(WACOM "Wacom Input Devices" ON "DEV_BRANCH" OFF)
cmake_dependent_option(XL24 "ATI VGA Wonder XL24 (ATI-28800-6)" ON "DEV_BRANCH" OFF)

4
debian/changelog vendored
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@@ -1,5 +1,5 @@
86box (5.4) UNRELEASED; urgency=medium
86box (6.0) UNRELEASED; urgency=medium
* Bump release.
-- Jasmine Iwanek <jriwanek@gmail.com> Tue, 23 Dec 2025 00:27:45 +0100
-- Jasmine Iwanek <jriwanek@gmail.com> Wed, 28 Jan 2026 08:45:23 +0100

18
src/86box.c
View File

@@ -683,12 +683,12 @@ delete_nvr_file(uint8_t flash)
extern void device_find_all_descs(void);
static void
pc_show_usage(char *s)
pc_show_usage(void)
{
char p[8192] = { 0 };
sprintf(p,
"\n%sUsage: 86box [options] [cfg-file]\n\n"
"\nUsage: 86box [options] [cfg-file]\n\n"
"Valid options are:\n\n"
"-? or --help\t\t\t- show this information\n"
"-A or --assetpath path\t\t- set 'path' to be asset path\n"
@@ -737,16 +737,12 @@ pc_show_usage(char *s)
"-Y or --donothing\t\t- do not show any UI or run the emulation\n"
#endif
"-Z or --lastvmpath\t\t- the last param. is VM path rather than config\n"
"\nA config file can be specified. If none is, the default file will be used.\n",
s);
"\nA config file can be specified. If none is, the default file will be used.\n");
#ifdef _WIN32
ui_msgbox(MBX_ANSI | ((s == NULL) ? MBX_INFO : MBX_WARNING), p);
ui_msgbox(MBX_ANSI | MBX_INFO, p);
#else
if (s == NULL)
always_log("%s", p);
else
ui_msgbox(MBX_ANSI | MBX_WARNING, p);
always_log("%s", p);
#endif
}
@@ -846,7 +842,7 @@ usage:
}
}
pc_show_usage("");
pc_show_usage();
return 0;
} else if (!strcasecmp(argv[c], "--lastvmpath") || !strcasecmp(argv[c], "-Z")) {
lvmp = 1;
@@ -1709,6 +1705,8 @@ pc_reset_hard_init(void)
ide_hard_reset();
lpt_ports_reset();
/* Initialize the actual machine and its basic modules. */
machine_init();

4
src/chipset/ali1435.c
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@@ -98,7 +98,7 @@ ali1435_update_irqs(ali1435_t *dev, int set)
}
static void
ali1435_pci_write(int func, int addr, uint8_t val, void *priv)
ali1435_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1435_t *dev = (ali1435_t *) priv;
int irq;
@@ -163,7 +163,7 @@ ali1435_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali1435_pci_read(int func, int addr, void *priv)
ali1435_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
const ali1435_t *dev = (ali1435_t *) priv;
uint8_t ret;

4
src/chipset/ali1489.c
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@@ -411,7 +411,7 @@ ali1489_read(uint16_t addr, void *priv)
}
static void
ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ali1489_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1489_t *dev = (ali1489_t *) priv;
@@ -434,7 +434,7 @@ ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
ali1489_pci_read(UNUSED(int func), int addr, void *priv)
ali1489_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const ali1489_t *dev = (ali1489_t *) priv;
uint8_t ret = 0xff;

18
src/chipset/ali1531.c
View File

@@ -132,7 +132,7 @@ ali1531_shadow_recalc(UNUSED(int cur_reg), ali1531_t *dev)
}
static void
ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ali1531_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1531_t *dev = (ali1531_t *) priv;
@@ -298,7 +298,7 @@ ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
ali1531_read(UNUSED(int func), int addr, void *priv)
ali1531_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const ali1531_t *dev = (ali1531_t *) priv;
uint8_t ret = 0xff;
@@ -341,18 +341,18 @@ ali1531_reset(void *priv)
dev->pci_conf[0x5a] = 0x20;
dev->pci_conf[0x70] = 0x22;
ali1531_write(0, 0x42, 0x00, dev);
ali1531_write(0, 0x43, 0x00, dev);
ali1531_write(0, 0x42, 1, 0x00, dev);
ali1531_write(0, 0x43, 1, 0x00, dev);
ali1531_write(0, 0x47, 0x00, dev);
ali1531_write(0, 0x48, 0x00, dev);
ali1531_write(0, 0x47, 1, 0x00, dev);
ali1531_write(0, 0x48, 1, 0x00, dev);
for (uint8_t i = 0; i < 4; i++)
ali1531_write(0, 0x4c + i, 0x00, dev);
ali1531_write(0, 0x4c + i, 1, 0x00, dev);
for (uint8_t i = 0; i < 16; i += 2) {
ali1531_write(0, 0x60 + i, 0x08, dev);
ali1531_write(0, 0x61 + i, 0x40, dev);
ali1531_write(0, 0x60 + i, 1, 0x08, dev);
ali1531_write(0, 0x61 + i, 1, 0x40, dev);
}
}

20
src/chipset/ali1541.c
View File

@@ -177,7 +177,7 @@ ali1541_mask_bar(ali1541_t *dev)
}
static void
ali1541_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ali1541_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1541_t *dev = (ali1541_t *) priv;
@@ -562,7 +562,7 @@ ali1541_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
ali1541_read(UNUSED(int func), int addr, void *priv)
ali1541_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const ali1541_t *dev = (ali1541_t *) priv;
uint8_t ret = 0xff;
@@ -613,20 +613,20 @@ ali1541_reset(void *priv)
dev->pci_conf[0xe0] = 0x01;
cpu_cache_int_enabled = 1;
ali1541_write(0, 0x42, 0x00, dev);
ali1541_write(0, 0x42, 1, 0x00, dev);
ali1541_write(0, 0x54, 0x00, dev);
ali1541_write(0, 0x55, 0x00, dev);
ali1541_write(0, 0x54, 1, 0x00, dev);
ali1541_write(0, 0x55, 1, 0x00, dev);
for (uint8_t i = 0; i < 4; i++)
ali1541_write(0, 0x56 + i, 0x00, dev);
ali1541_write(0, 0x56 + i, 1, 0x00, dev);
ali1541_write(0, 0x60, 0x07, dev);
ali1541_write(0, 0x61, 0x40, dev);
ali1541_write(0, 0x60, 1, 0x07, dev);
ali1541_write(0, 0x61, 1, 0x40, dev);
for (uint8_t i = 0; i < 14; i += 2) {
ali1541_write(0, 0x62 + i, 0x00, dev);
ali1541_write(0, 0x63 + i, 0x00, dev);
ali1541_write(0, 0x62 + i, 1, 0x00, dev);
ali1541_write(0, 0x63 + i, 1, 0x00, dev);
}
}

130
src/chipset/ali1543.c
View File

@@ -112,13 +112,13 @@ ali1533_ddma_handler(UNUSED(ali1543_t *dev))
static void ali5229_ide_handler(ali1543_t *dev);
static void ali5229_ide_irq_handler(ali1543_t *dev);
static void ali5229_write(int func, int addr, uint8_t val, void *priv);
static void ali5229_write(int func, int addr, int len, uint8_t val, void *priv);
static void ali7101_write(int func, int addr, uint8_t val, void *priv);
static uint8_t ali7101_read(int func, int addr, void *priv);
static void ali7101_write(int func, int addr, int len, uint8_t val, void *priv);
static uint8_t ali7101_read(int func, int addr, int len, void *priv);
static void
ali1533_write(int func, int addr, uint8_t val, void *priv)
ali1533_write(int func, int addr, int len, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M1533: dev->pci_conf[%02x] = %02x\n", addr, val);
@@ -453,7 +453,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x7c ... 0xff:
if ((dev->type == 1) && !dev->pmu_dev_enable) {
dev->pmu_dev_enable = 1;
ali7101_write(func, addr, val, priv);
ali7101_write(func, addr, len, val, priv);
dev->pmu_dev_enable = 0;
}
break;
@@ -464,7 +464,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali1533_read(int func, int addr, void *priv)
ali1533_read(int func, int addr, int len, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
@@ -478,7 +478,7 @@ ali1533_read(int func, int addr, void *priv)
ret = (ret & 0xbf) | (dev->ide_dev_enable ? 0x40 : 0x00);
else if ((dev->type == 1) && ((addr >= 0x7c) && (addr <= 0xff)) && !dev->pmu_dev_enable) {
dev->pmu_dev_enable = 1;
ret = ali7101_read(func, addr, priv);
ret = ali7101_read(func, addr, len, priv);
dev->pmu_dev_enable = 0;
}
}
@@ -690,23 +690,23 @@ ali5229_chip_reset(ali1543_t *dev)
dev->ide_conf[0x4f] = 0x1a;
}
ali5229_write(0, 0x04, 0x05, dev);
ali5229_write(0, 0x10, 0xf1, dev);
ali5229_write(0, 0x11, 0x01, dev);
ali5229_write(0, 0x14, 0xf5, dev);
ali5229_write(0, 0x15, 0x03, dev);
ali5229_write(0, 0x18, 0x71, dev);
ali5229_write(0, 0x19, 0x01, dev);
ali5229_write(0, 0x1a, 0x75, dev);
ali5229_write(0, 0x1b, 0x03, dev);
ali5229_write(0, 0x20, 0x01, dev);
ali5229_write(0, 0x21, 0xf0, dev);
ali5229_write(0, 0x4d, 0x00, dev);
ali5229_write(0, 0x04, 1, 0x05, dev);
ali5229_write(0, 0x10, 1, 0xf1, dev);
ali5229_write(0, 0x11, 1, 0x01, dev);
ali5229_write(0, 0x14, 1, 0xf5, dev);
ali5229_write(0, 0x15, 1, 0x03, dev);
ali5229_write(0, 0x18, 1, 0x71, dev);
ali5229_write(0, 0x19, 1, 0x01, dev);
ali5229_write(0, 0x1a, 1, 0x75, dev);
ali5229_write(0, 0x1b, 1, 0x03, dev);
ali5229_write(0, 0x20, 1, 0x01, dev);
ali5229_write(0, 0x21, 1, 0xf0, dev);
ali5229_write(0, 0x4d, 1, 0x00, dev);
dev->ide_conf[0x09] = 0xfa;
ali5229_write(0, 0x09, 0xfa, dev);
ali5229_write(0, 0x52, 0x00, dev);
ali5229_write(0, 0x09, 1, 0xfa, dev);
ali5229_write(0, 0x52, 1, 0x00, dev);
ali5229_write(0, 0x50, 0x02, dev);
ali5229_write(0, 0x50, 1, 0x02, dev);
sff_set_slot(dev->ide_controller[0], dev->ide_slot);
sff_set_slot(dev->ide_controller[1], dev->ide_slot);
@@ -716,7 +716,7 @@ ali5229_chip_reset(ali1543_t *dev)
}
static void
ali5229_write(int func, int addr, uint8_t val, void *priv)
ali5229_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M5229: [W] dev->ide_conf[%02x] = %02x\n", addr, val);
@@ -885,7 +885,7 @@ ali5229_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali5229_read(int func, int addr, void *priv)
ali5229_read(int func, int addr, UNUSED(int len), void *priv)
{
const ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
@@ -908,7 +908,7 @@ ali5229_read(int func, int addr, void *priv)
}
static void
ali5237_write(int func, int addr, uint8_t val, void *priv)
ali5237_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M5237: dev->usb_conf[%02x] = %02x\n", addr, val);
@@ -975,7 +975,7 @@ ali5237_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali5237_read(int func, int addr, void *priv)
ali5237_read(int func, int addr, UNUSED(int len), void *priv)
{
const ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
@@ -987,7 +987,7 @@ ali5237_read(int func, int addr, void *priv)
}
static void
ali7101_write(int func, int addr, uint8_t val, void *priv)
ali7101_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M7101: [W] dev->pmu_conf[%02x] = %02x\n", addr, val);
@@ -1408,7 +1408,7 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali7101_read(int func, int addr, void *priv)
ali7101_read(int func, int addr, UNUSED(int len), void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
@@ -1516,11 +1516,11 @@ ali1543_reset(void *priv)
dev->usb_conf[0x0b] = 0x0c;
dev->usb_conf[0x3d] = 0x01;
ali5237_write(0, 0x04, 0x00, dev);
ali5237_write(0, 0x10, 0x00, dev);
ali5237_write(0, 0x11, 0x00, dev);
ali5237_write(0, 0x12, 0x00, dev);
ali5237_write(0, 0x13, 0x00, dev);
ali5237_write(0, 0x04, 1, 0x00, dev);
ali5237_write(0, 0x10, 1, 0x00, dev);
ali5237_write(0, 0x11, 1, 0x00, dev);
ali5237_write(0, 0x12, 1, 0x00, dev);
ali5237_write(0, 0x13, 1, 0x00, dev);
/* M7101 */
memset(dev->pmu_conf, 0x00, sizeof(dev->pmu_conf));
@@ -1536,26 +1536,26 @@ ali1543_reset(void *priv)
acpi_set_slot(dev->acpi, dev->pmu_slot);
acpi_set_nvr(dev->acpi, dev->nvr);
ali7101_write(0, 0x04, 0x0f, dev);
ali7101_write(0, 0x10, 0x01, dev);
ali7101_write(0, 0x11, 0x00, dev);
ali7101_write(0, 0x12, 0x00, dev);
ali7101_write(0, 0x13, 0x00, dev);
ali7101_write(0, 0x14, 0x01, dev);
ali7101_write(0, 0x15, 0x00, dev);
ali7101_write(0, 0x16, 0x00, dev);
ali7101_write(0, 0x17, 0x00, dev);
ali7101_write(0, 0x40, 0x00, dev);
ali7101_write(0, 0x41, 0x00, dev);
ali7101_write(0, 0x42, 0x00, dev);
ali7101_write(0, 0x43, 0x00, dev);
ali7101_write(0, 0x77, 0x00, dev);
ali7101_write(0, 0xbd, 0x00, dev);
ali7101_write(0, 0xc0, 0x00, dev);
ali7101_write(0, 0xc1, 0x00, dev);
ali7101_write(0, 0xc2, 0x00, dev);
ali7101_write(0, 0xc3, 0x00, dev);
ali7101_write(0, 0xe0, 0x00, dev);
ali7101_write(0, 0x04, 1, 0x0f, dev);
ali7101_write(0, 0x10, 1, 0x01, dev);
ali7101_write(0, 0x11, 1, 0x00, dev);
ali7101_write(0, 0x12, 1, 0x00, dev);
ali7101_write(0, 0x13, 1, 0x00, dev);
ali7101_write(0, 0x14, 1, 0x01, dev);
ali7101_write(0, 0x15, 1, 0x00, dev);
ali7101_write(0, 0x16, 1, 0x00, dev);
ali7101_write(0, 0x17, 1, 0x00, dev);
ali7101_write(0, 0x40, 1, 0x00, dev);
ali7101_write(0, 0x41, 1, 0x00, dev);
ali7101_write(0, 0x42, 1, 0x00, dev);
ali7101_write(0, 0x43, 1, 0x00, dev);
ali7101_write(0, 0x77, 1, 0x00, dev);
ali7101_write(0, 0xbd, 1, 0x00, dev);
ali7101_write(0, 0xc0, 1, 0x00, dev);
ali7101_write(0, 0xc1, 1, 0x00, dev);
ali7101_write(0, 0xc2, 1, 0x00, dev);
ali7101_write(0, 0xc3, 1, 0x00, dev);
ali7101_write(0, 0xe0, 1, 0x00, dev);
/* Do the bridge last due to device deactivations. */
/* M1533 */
@@ -1570,19 +1570,19 @@ ali1543_reset(void *priv)
dev->pci_conf[0x0a] = 0x01;
dev->pci_conf[0x0b] = 0x06;
ali1533_write(0, 0x41, 0x00, dev); /* Disables the keyboard and mouse IRQ latch. */
ali1533_write(0, 0x48, 0x00, dev); /* Disables all IRQ's. */
ali1533_write(0, 0x44, 0x00, dev);
ali1533_write(0, 0x4d, 0x00, dev);
ali1533_write(0, 0x53, 0x00, dev);
ali1533_write(0, 0x58, 0x00, dev);
ali1533_write(0, 0x5f, 0x00, dev);
ali1533_write(0, 0x72, 0x00, dev);
ali1533_write(0, 0x74, 0x00, dev);
ali1533_write(0, 0x75, 0x00, dev);
ali1533_write(0, 0x76, 0x00, dev);
ali1533_write(0, 0x41, 1, 0x00, dev); /* Disables the keyboard and mouse IRQ latch. */
ali1533_write(0, 0x48, 1, 0x00, dev); /* Disables all IRQ's. */
ali1533_write(0, 0x44, 1, 0x00, dev);
ali1533_write(0, 0x4d, 1, 0x00, dev);
ali1533_write(0, 0x53, 1, 0x00, dev);
ali1533_write(0, 0x58, 1, 0x00, dev);
ali1533_write(0, 0x5f, 1, 0x00, dev);
ali1533_write(0, 0x72, 1, 0x00, dev);
ali1533_write(0, 0x74, 1, 0x00, dev);
ali1533_write(0, 0x75, 1, 0x00, dev);
ali1533_write(0, 0x76, 1, 0x00, dev);
if (dev->type == 1)
ali1533_write(0, 0x78, 0x00, dev);
ali1533_write(0, 0x78, 1, 0x00, dev);
unmask_a20_in_smm = 1;
}

8
src/chipset/ali1621.c
View File

@@ -255,7 +255,7 @@ ali1621_mask_bar(ali1621_t *dev)
}
static void
ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ali1621_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1621_t *dev = (ali1621_t *) priv;
@@ -581,7 +581,7 @@ ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
ali1621_read(UNUSED(int func), int addr, void *priv)
ali1621_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const ali1621_t *dev = (ali1621_t *) priv;
uint8_t ret = 0xff;
@@ -647,10 +647,10 @@ ali1621_reset(void *priv)
dev->pci_conf[0xf2] = dev->pci_conf[0xf6] = dev->pci_conf[0xfa] = dev->pci_conf[0xfe] = 0x21;
dev->pci_conf[0xf3] = dev->pci_conf[0xf7] = dev->pci_conf[0xfb] = dev->pci_conf[0xff] = 0x43;
ali1621_write(0, 0x83, 0x08, dev);
ali1621_write(0, 0x83, 1, 0x08, dev);
for (uint8_t i = 0; i < 4; i++)
ali1621_write(0, 0x84 + i, 0x00, dev);
ali1621_write(0, 0x84 + i, 1, 0x00, dev);
}
static void

4
src/chipset/ims8848.c
View File

@@ -292,7 +292,7 @@ ims8848_read(uint16_t addr, void *priv)
}
static void
ims8849_pci_write(int func, int addr, uint8_t val, void *priv)
ims8849_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ims8848_t *dev = (ims8848_t *) priv;
@@ -326,7 +326,7 @@ ims8849_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ims8849_pci_read(int func, int addr, void *priv)
ims8849_pci_read(int func, UNUSED(int len), int addr, void *priv)
{
const ims8848_t *dev = (ims8848_t *) priv;
uint8_t ret = 0xff;

26
src/chipset/intel_420ex.c
View File

@@ -183,7 +183,7 @@ i420ex_drb_recalc(i420ex_t *dev)
static void
i420ex_write(int func, int addr, uint8_t val, void *priv)
i420ex_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
@@ -397,7 +397,7 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
i420ex_read(int func, int addr, void *priv)
i420ex_read(int func, int addr, UNUSED(int len), void *priv)
{
const i420ex_t *dev = (i420ex_t *) priv;
uint8_t ret;
@@ -472,31 +472,31 @@ i420ex_reset(void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
i420ex_write(0, 0x48, 0x00, priv);
i420ex_write(0, 0x48, 1, 0x00, priv);
/* Disable the PIC mouse latch. */
i420ex_write(0, 0x4e, 0x03, priv);
i420ex_write(0, 0x4e, 1, 0x03, priv);
for (uint8_t i = 0; i < 7; i++)
i420ex_write(0, 0x59 + i, 0x00, priv);
i420ex_write(0, 0x59 + i, 1, 0x00, priv);
for (uint8_t i = 0; i <= 4; i++)
dev->regs[0x60 + i] = 0x01;
dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */
dev->smram_locked = 0;
i420ex_write(0, 0x70, 0x00, priv);
i420ex_write(0, 0x70, 1, 0x00, priv);
mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
i420ex_write(0, 0xa0, 0x08, priv);
i420ex_write(0, 0xa2, 0x00, priv);
i420ex_write(0, 0xa4, 0x00, priv);
i420ex_write(0, 0xa5, 0x00, priv);
i420ex_write(0, 0xa6, 0x00, priv);
i420ex_write(0, 0xa7, 0x00, priv);
i420ex_write(0, 0xa8, 0x0f, priv);
i420ex_write(0, 0xa0, 1, 0x08, priv);
i420ex_write(0, 0xa2, 1, 0x00, priv);
i420ex_write(0, 0xa4, 1, 0x00, priv);
i420ex_write(0, 0xa5, 1, 0x00, priv);
i420ex_write(0, 0xa6, 1, 0x00, priv);
i420ex_write(0, 0xa7, 1, 0x00, priv);
i420ex_write(0, 0xa8, 1, 0x0f, priv);
}
static void

40
src/chipset/intel_4x0.c
View File

@@ -243,7 +243,7 @@ pm2_cntrl_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
}
static void
i4x0_write(int func, int addr, uint8_t val, void *priv)
i4x0_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
uint8_t *regs = (uint8_t *) dev->regs;
@@ -1535,7 +1535,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
i4x0_read(int func, int addr, void *priv)
i4x0_read(int func, int addr, UNUSED(int len), void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
uint8_t ret = 0xff;
@@ -1563,12 +1563,12 @@ i4x0_reset(void *priv)
memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x59, 0x00, priv);
i4x0_write(0, 0x59, 1, 0x00, priv);
else
i4x0_write(0, 0x59, 0x0f, priv);
i4x0_write(0, 0x59, 1, 0x0f, priv);
for (uint8_t i = 0; i < 6; i++)
i4x0_write(0, 0x5a + i, 0x00, priv);
i4x0_write(0, 0x5a + i, 1, 0x00, priv);
for (uint8_t i = 0; i <= dev->max_drb; i++)
dev->regs[0x60 + i] = dev->drb_default;
@@ -1582,18 +1582,18 @@ i4x0_reset(void *priv)
if (dev->type >= INTEL_430FX) {
dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x02, priv);
i4x0_write(0, 0x72, 1, 0x02, priv);
} else if (dev->type >= INTEL_430LX) {
dev->regs[0x72] &= 0xf7; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x00, priv);
i4x0_write(0, 0x72, 1, 0x00, priv);
} else {
dev->regs[0x57] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x57, 0x02, priv);
i4x0_write(0, 0x57, 1, 0x02, priv);
}
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv);
1, (dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv);
}
}
@@ -1932,24 +1932,24 @@ i4x0_init(const device_t *info)
else if (dev->type >= INTEL_440LX)
cpu_set_agp_speed(cpu_busspeed);
i4x0_write(regs[0x59], 0x59, 0x00, dev);
i4x0_write(regs[0x5a], 0x5a, 0x00, dev);
i4x0_write(regs[0x5b], 0x5b, 0x00, dev);
i4x0_write(regs[0x5c], 0x5c, 0x00, dev);
i4x0_write(regs[0x5d], 0x5d, 0x00, dev);
i4x0_write(regs[0x5e], 0x5e, 0x00, dev);
i4x0_write(regs[0x5f], 0x5f, 0x00, dev);
i4x0_write(regs[0x59], 0x59, 1, 0x00, dev);
i4x0_write(regs[0x5a], 0x5a, 1, 0x00, dev);
i4x0_write(regs[0x5b], 0x5b, 1, 0x00, dev);
i4x0_write(regs[0x5c], 0x5c, 1, 0x00, dev);
i4x0_write(regs[0x5d], 0x5d, 1, 0x00, dev);
i4x0_write(regs[0x5e], 0x5e, 1, 0x00, dev);
i4x0_write(regs[0x5f], 0x5f, 1, 0x00, dev);
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x72, 0x02, dev);
i4x0_write(0, 0x72, 1, 0x02, dev);
else if (dev->type >= INTEL_430LX)
i4x0_write(0, 0x72, 0x00, dev);
i4x0_write(0, 0x72, 1, 0x00, dev);
else
i4x0_write(0, 0x57, 0x02, dev);
i4x0_write(0, 0x57, 1, 0x02, dev);
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev);
1, (dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev);
}
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev, &dev->pci_slot);

16
src/chipset/intel_i450kx.c
View File

@@ -126,7 +126,7 @@ i450kx_vid_buf_recalc(i450kx_t *dev, int bus)
}
static void
pb_write(int func, int addr, uint8_t val, void *priv)
pb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
i450kx_t *dev = (i450kx_t *) priv;
@@ -371,7 +371,7 @@ pb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
pb_read(int func, int addr, void *priv)
pb_read(int func, int addr, UNUSED(int len), void *priv)
{
const i450kx_t *dev = (i450kx_t *) priv;
uint8_t ret = 0xff;
@@ -400,7 +400,7 @@ mc_fill_drbs(i450kx_t *dev)
}
static void
mc_write(int func, int addr, uint8_t val, void *priv)
mc_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
i450kx_t *dev = (i450kx_t *) priv;
@@ -601,7 +601,7 @@ mc_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
mc_read(int func, int addr, void *priv)
mc_read(int func, int addr, UNUSED(int len), void *priv)
{
const i450kx_t *dev = (i450kx_t *) priv;
uint8_t ret = 0xff;
@@ -707,9 +707,9 @@ i450kx_reset(void *priv)
#endif
i450kx_smram_recalc(dev, 1);
i450kx_vid_buf_recalc(dev, 1);
pb_write(0, 0x59, 0x30, dev);
pb_write(0, 0x59, 1, 0x30, dev);
for (i = 0x5a; i <= 0x5f; i++)
pb_write(0, i, 0x33, dev);
pb_write(0, i, 1, 0x33, dev);
/* Defaults MC */
dev->mc_pci_conf[0x00] = 0x86;
@@ -779,9 +779,9 @@ i450kx_reset(void *priv)
i450kx_smram_recalc(dev, 0);
i450kx_vid_buf_recalc(dev, 0);
mc_write(0, 0x59, 0x03, dev);
mc_write(0, 0x59, 1, 0x03, dev);
for (i = 0x5a; i <= 0x5f; i++)
mc_write(0, i, 0x00, dev);
mc_write(0, i, 1, 0x00, dev);
for (i = 0x60; i <= 0x6f; i++)
dev->mc_pci_conf[i] = 0x01;
}

96
src/chipset/intel_piix.c
View File

@@ -464,7 +464,7 @@ piix_trap_update(void *priv)
}
static void
piix_write(int func, int addr, uint8_t val, void *priv)
piix_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
piix_t *dev = (piix_t *) priv;
uint8_t *fregs;
@@ -1192,7 +1192,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
piix_read(int func, int addr, void *priv)
piix_read(int func, int addr, UNUSED(int len), void *priv)
{
piix_t *dev = (piix_t *) priv;
uint8_t ret = 0xff;
@@ -1447,68 +1447,68 @@ piix_reset(void *priv)
const piix_t *dev = (piix_t *) priv;
if (dev->type > 3) {
piix_write(3, 0x04, 0x00, priv);
piix_write(3, 0x5b, 0x00, priv);
piix_write(3, 0x04, 1, 0x00, priv);
piix_write(3, 0x5b, 1, 0x00, priv);
} else {
piix_write(0, 0xa0, 0x08, priv);
piix_write(0, 0xa2, 0x00, priv);
piix_write(0, 0xa4, 0x00, priv);
piix_write(0, 0xa5, 0x00, priv);
piix_write(0, 0xa6, 0x00, priv);
piix_write(0, 0xa7, 0x00, priv);
piix_write(0, 0xa8, 0x0f, priv);
piix_write(0, 0xa0, 1, 0x08, priv);
piix_write(0, 0xa2, 1, 0x00, priv);
piix_write(0, 0xa4, 1, 0x00, priv);
piix_write(0, 0xa5, 1, 0x00, priv);
piix_write(0, 0xa6, 1, 0x00, priv);
piix_write(0, 0xa7, 1, 0x00, priv);
piix_write(0, 0xa8, 1, 0x0f, priv);
}
/* Disable the PIC mouse latch. */
piix_write(0, 0x4e, 0x03, priv);
piix_write(0, 0x4e, 1, 0x03, priv);
if (dev->type == 5)
piix_write(0, 0xe1, 0x40, priv);
piix_write(1, 0x04, 0x00, priv);
piix_write(0, 0xe1, 1, 0x40, priv);
piix_write(1, 0x04, 1, 0x00, priv);
if (dev->type == 5) {
piix_write(1, 0x09, 0x8a, priv);
piix_write(1, 0x10, 0xf1, priv);
piix_write(1, 0x11, 0x01, priv);
piix_write(1, 0x14, 0xf5, priv);
piix_write(1, 0x15, 0x03, priv);
piix_write(1, 0x18, 0x71, priv);
piix_write(1, 0x19, 0x01, priv);
piix_write(1, 0x1c, 0x75, priv);
piix_write(1, 0x1d, 0x03, priv);
piix_write(1, 0x09, 1, 0x8a, priv);
piix_write(1, 0x10, 1, 0xf1, priv);
piix_write(1, 0x11, 1, 0x01, priv);
piix_write(1, 0x14, 1, 0xf5, priv);
piix_write(1, 0x15, 1, 0x03, priv);
piix_write(1, 0x18, 1, 0x71, priv);
piix_write(1, 0x19, 1, 0x01, priv);
piix_write(1, 0x1c, 1, 0x75, priv);
piix_write(1, 0x1d, 1, 0x03, priv);
} else
piix_write(1, 0x09, 0x80, priv);
piix_write(1, 0x20, 0x01, priv);
piix_write(1, 0x21, 0x00, priv);
piix_write(1, 0x41, 0x00, priv);
piix_write(1, 0x43, 0x00, priv);
piix_write(1, 0x09, 1, 0x80, priv);
piix_write(1, 0x20, 1, 0x01, priv);
piix_write(1, 0x21, 1, 0x00, priv);
piix_write(1, 0x41, 1, 0x00, priv);
piix_write(1, 0x43, 1, 0x00, priv);
ide_pri_disable();
ide_sec_disable();
if (dev->type >= 3) {
piix_write(2, 0x04, 0x00, priv);
piix_write(2, 0x04, 1, 0x00, priv);
if (dev->type == 5) {
piix_write(2, 0x10, 0x00, priv);
piix_write(2, 0x11, 0x00, priv);
piix_write(2, 0x12, 0x00, priv);
piix_write(2, 0x13, 0x00, priv);
piix_write(2, 0x10, 1, 0x00, priv);
piix_write(2, 0x11, 1, 0x00, priv);
piix_write(2, 0x12, 1, 0x00, priv);
piix_write(2, 0x13, 1, 0x00, priv);
} else {
piix_write(2, 0x20, 0x01, priv);
piix_write(2, 0x21, 0x00, priv);
piix_write(2, 0x22, 0x00, priv);
piix_write(2, 0x23, 0x00, priv);
piix_write(2, 0x20, 1, 0x01, priv);
piix_write(2, 0x21, 1, 0x00, priv);
piix_write(2, 0x22, 1, 0x00, priv);
piix_write(2, 0x23, 1, 0x00, priv);
}
}
if (dev->type >= 4) {
piix_write(0, 0xb0, is_pentium ? 0x00 : 0x04, priv);
piix_write(3, 0x40, 0x01, priv);
piix_write(3, 0x41, 0x00, priv);
piix_write(3, 0x5b, 0x00, priv);
piix_write(3, 0x80, 0x00, priv);
piix_write(3, 0x90, 0x01, priv);
piix_write(3, 0x91, 0x00, priv);
piix_write(3, 0xd2, 0x00, priv);
piix_write(0, 0xb0, 1, is_pentium ? 0x00 : 0x04, priv);
piix_write(3, 0x40, 1, 0x01, priv);
piix_write(3, 0x41, 1, 0x00, priv);
piix_write(3, 0x5b, 1, 0x00, priv);
piix_write(3, 0x80, 1, 0x00, priv);
piix_write(3, 0x90, 1, 0x01, priv);
piix_write(3, 0x91, 1, 0x00, priv);
piix_write(3, 0xd2, 1, 0x00, priv);
}
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);
@@ -1554,7 +1554,7 @@ piix_init(const device_t *info)
dev->rev = (info->local >> 4) & 0x0f;
dev->func_shift = (info->local >> 8) & 0x0f;
dev->no_mirq0 = (info->local >> 12) & 0x0f;
dev->func0_id = info->local >> 16;
dev->func0_id = (info->local >> 16) & 0xffff;
pci_add_card(PCI_ADD_SOUTHBRIDGE, piix_read, piix_write, dev, &dev->pci_slot);
piix_log("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot);
@@ -1580,7 +1580,9 @@ piix_init(const device_t *info)
dev->usb = device_add(&usb_device);
if (dev->type > 3) {
if (!strcmp(machine_get_internal_name(), "ms5156"))
if (info->local & PIIX4_NVR_AMI_1995J)
dev->nvr = device_add(&piix4_ami_1995j_nvr_device);
else if (info->local & PIIX4_NVR_AMI_1995)
dev->nvr = device_add(&piix4_ami_1995_nvr_device);
else
dev->nvr = device_add(&piix4_nvr_device);

22
src/chipset/intel_sio.c
View File

@@ -135,7 +135,7 @@ sio_timer_readw(uint16_t addr, void *priv)
}
static void
sio_write(int func, int addr, uint8_t val, void *priv)
sio_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
sio_t *dev = (sio_t *) priv;
uint8_t old;
@@ -324,7 +324,7 @@ sio_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sio_read(int func, int addr, void *priv)
sio_read(int func, int addr, UNUSED(int len), void *priv)
{
const sio_t *dev = (sio_t *) priv;
uint8_t ret;
@@ -473,20 +473,20 @@ sio_reset(void *priv)
const sio_t *dev = (sio_t *) priv;
/* Disable the PIC mouse latch. */
sio_write(0, 0x4d, 0x40, priv);
sio_write(0, 0x4d, 1, 0x40, priv);
sio_write(0, 0x57, 0x04, priv);
sio_write(0, 0x57, 1, 0x04, priv);
dma_set_params(1, 0xffffffff);
if (dev->id == 0x03) {
sio_write(0, 0xa0, 0x08, priv);
sio_write(0, 0xa2, 0x00, priv);
sio_write(0, 0xa4, 0x00, priv);
sio_write(0, 0xa5, 0x00, priv);
sio_write(0, 0xa6, 0x00, priv);
sio_write(0, 0xa7, 0x00, priv);
sio_write(0, 0xa8, 0x0f, priv);
sio_write(0, 0xa0, 1, 0x08, priv);
sio_write(0, 0xa2, 1, 0x00, priv);
sio_write(0, 0xa4, 1, 0x00, priv);
sio_write(0, 0xa5, 1, 0x00, priv);
sio_write(0, 0xa6, 1, 0x00, priv);
sio_write(0, 0xa7, 1, 0x00, priv);
sio_write(0, 0xa8, 1, 0x0f, priv);
}
}

31
src/chipset/laserxt.c
View File

@@ -296,6 +296,37 @@ lxt_init(const device_t *info)
}
static const device_config_t laserxt_config[] = {
{
.name = "bios",
.description = "BIOS Version",
.type = CONFIG_BIOS,
.default_string = "laserxt_126",
.default_int = 0,
.file_filter = NULL,
.spinner = { 0 },
.selection = { { 0 } },
.bios = {
{
.name = "1.08",
.internal_name = "laserxt_108",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 8192,
.files = { "roms/machines/ltxt/ltxt-v1.08.bin", "" }
},
{
.name = "1.26",
.internal_name = "laserxt_126",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 8192,
.files = { "roms/machines/ltxt/27c64.bin", "" }
},
{ .files_no = 0 }
}
},
{
.name = "ems_1_base",
.description = "EMS 1 Address",

5
src/chipset/opti822.c
View File

@@ -48,7 +48,6 @@ typedef struct opti822_t {
uint8_t pci_regs[256];
} opti822_t;
// #define ENABLE_OPTI822_LOG 1
#ifdef ENABLE_OPTI822_LOG
int opti822_do_log = ENABLE_OPTI822_LOG;
@@ -131,7 +130,7 @@ opti822_update_irqs(opti822_t *dev, int set)
}
static void
opti822_pci_write(int func, int addr, uint8_t val, void *priv)
opti822_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
opti822_t *dev = (opti822_t *) priv;
int irq;
@@ -336,7 +335,7 @@ opti822_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
opti822_pci_read(int func, int addr, void *priv)
opti822_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
const opti822_t *dev = (opti822_t *) priv;
uint8_t ret;

8
src/chipset/sis_5511.c
View File

@@ -76,7 +76,7 @@ typedef struct sis_5511_t {
} sis_5511_t;
static void
sis_5511_write(int func, int addr, uint8_t val, void *priv)
sis_5511_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
@@ -87,7 +87,7 @@ sis_5511_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5511_read(int func, int addr, void *priv)
sis_5511_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
uint8_t ret = 0xff;
@@ -101,7 +101,7 @@ sis_5511_read(int func, int addr, void *priv)
}
static void
sis_5513_write(int func, int addr, uint8_t val, void *priv)
sis_5513_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
@@ -114,7 +114,7 @@ sis_5513_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5513_read(int func, int addr, void *priv)
sis_5513_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
uint8_t ret = 0xff;

8
src/chipset/sis_5571.c
View File

@@ -75,7 +75,7 @@ typedef struct sis_5571_t {
} sis_5571_t;
static void
sis_5571_write(int func, int addr, uint8_t val, void *priv)
sis_5571_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
@@ -86,7 +86,7 @@ sis_5571_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5571_read(int func, int addr, void *priv)
sis_5571_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
uint8_t ret = 0xff;
@@ -100,7 +100,7 @@ sis_5571_read(int func, int addr, void *priv)
}
static void
sis_5572_write(int func, int addr, uint8_t val, void *priv)
sis_5572_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
@@ -120,7 +120,7 @@ sis_5572_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5572_read(int func, int addr, void *priv)
sis_5572_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
uint8_t ret = 0xff;

8
src/chipset/sis_5581.c
View File

@@ -75,7 +75,7 @@ typedef struct sis_5581_t {
} sis_5581_t;
static void
sis_5581_write(int func, int addr, uint8_t val, void *priv)
sis_5581_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
@@ -86,7 +86,7 @@ sis_5581_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5581_read(int func, int addr, void *priv)
sis_5581_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
uint8_t ret = 0xff;
@@ -100,7 +100,7 @@ sis_5581_read(int func, int addr, void *priv)
}
static void
sis_5582_write(int func, int addr, uint8_t val, void *priv)
sis_5582_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
@@ -120,7 +120,7 @@ sis_5582_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5582_read(int func, int addr, void *priv)
sis_5582_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
uint8_t ret = 0xff;

8
src/chipset/sis_5591.c
View File

@@ -76,7 +76,7 @@ typedef struct sis_5591_t {
} sis_5591_t;
static void
sis_5591_write(int func, int addr, uint8_t val, void *priv)
sis_5591_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
@@ -89,7 +89,7 @@ sis_5591_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5591_read(int func, int addr, void *priv)
sis_5591_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
uint8_t ret = 0xff;
@@ -105,7 +105,7 @@ sis_5591_read(int func, int addr, void *priv)
}
static void
sis_5595_write(int func, int addr, uint8_t val, void *priv)
sis_5595_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
@@ -125,7 +125,7 @@ sis_5595_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5595_read(int func, int addr, void *priv)
sis_5595_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
uint8_t ret = 0xff;

8
src/chipset/sis_5600.c
View File

@@ -76,7 +76,7 @@ typedef struct sis_5600_t {
} sis_5600_t;
static void
sis_5600_write(int func, int addr, uint8_t val, void *priv)
sis_5600_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
@@ -89,7 +89,7 @@ sis_5600_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5600_read(int func, int addr, void *priv)
sis_5600_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
uint8_t ret = 0xff;
@@ -105,7 +105,7 @@ sis_5600_read(int func, int addr, void *priv)
}
static void
sis_5595_write(int func, int addr, uint8_t val, void *priv)
sis_5595_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
@@ -125,7 +125,7 @@ sis_5595_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5595_read(int func, int addr, void *priv)
sis_5595_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
uint8_t ret = 0xff;

52
src/chipset/sis_85c496.c
View File

@@ -216,7 +216,7 @@ sis_85c496_drb_recalc(sis_85c496_t *dev)
/* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */
static void
sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
sis_85c49x_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t old;
@@ -507,7 +507,7 @@ sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
sis_85c49x_pci_read(UNUSED(int func), int addr, void *priv)
sis_85c49x_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t ret = dev->pci_conf[addr];
@@ -577,35 +577,35 @@ sis_85c496_reset(void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
sis_85c49x_pci_write(0, 0x44, 0x00, dev);
sis_85c49x_pci_write(0, 0x45, 0x00, dev);
sis_85c49x_pci_write(0, 0x58, 0x00, dev);
sis_85c49x_pci_write(0, 0x59, 0x00, dev);
sis_85c49x_pci_write(0, 0x5a, 0x00, dev);
// sis_85c49x_pci_write(0, 0x5a, 0x06, dev);
sis_85c49x_pci_write(0, 0x44, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x45, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x58, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x59, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x5a, 1, 0x00, dev);
// sis_85c49x_pci_write(0, 0x5a, 1, 0x06, dev);
for (uint8_t i = 0; i < 8; i++)
dev->pci_conf[0x48 + i] = 0x02;
sis_85c49x_pci_write(0, 0x80, 0x00, dev);
sis_85c49x_pci_write(0, 0x81, 0x00, dev);
sis_85c49x_pci_write(0, 0x9e, 0x00, dev);
sis_85c49x_pci_write(0, 0x8d, 0x00, dev);
sis_85c49x_pci_write(0, 0xa0, 0xff, dev);
sis_85c49x_pci_write(0, 0xa1, 0xff, dev);
sis_85c49x_pci_write(0, 0xc0, 0x00, dev);
sis_85c49x_pci_write(0, 0xc1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc2, 0x00, dev);
sis_85c49x_pci_write(0, 0xc3, 0x00, dev);
sis_85c49x_pci_write(0, 0xc8, 0x00, dev);
sis_85c49x_pci_write(0, 0xc9, 0x00, dev);
sis_85c49x_pci_write(0, 0xca, 0x00, dev);
sis_85c49x_pci_write(0, 0xcb, 0x00, dev);
sis_85c49x_pci_write(0, 0x80, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x81, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x9e, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x8d, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xa0, 1, 0xff, dev);
sis_85c49x_pci_write(0, 0xa1, 1, 0xff, dev);
sis_85c49x_pci_write(0, 0xc0, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc1, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc2, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc3, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc8, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc9, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xca, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xcb, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xd0, 0x79, dev);
sis_85c49x_pci_write(0, 0xd1, 0xff, dev);
sis_85c49x_pci_write(0, 0xd0, 0x78, dev);
sis_85c49x_pci_write(0, 0xd4, 0x00, dev);
sis_85c49x_pci_write(0, 0xd0, 1, 0x79, dev);
sis_85c49x_pci_write(0, 0xd1, 1, 0xff, dev);
sis_85c49x_pci_write(0, 0xd0, 1, 0x78, dev);
sis_85c49x_pci_write(0, 0xd4, 1, 0x00, dev);
dev->pci_conf[0x67] = 0x00;
dev->pci_conf[0xc6] = 0x00;

38
src/chipset/sis_85c50x.c
View File

@@ -199,7 +199,7 @@ sis_85c50x_smm_recalc(sis_85c50x_t *dev)
}
static void
sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
sis_85c50x_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
@@ -311,7 +311,7 @@ sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_85c50x_read(int func, int addr, void *priv)
sis_85c50x_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_85c50x_t *dev = (sis_85c50x_t *) priv;
uint8_t ret = 0xff;
@@ -344,7 +344,7 @@ sis_85c50x_ide_recalc(sis_85c50x_t *dev)
}
static void
sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
sis_85c50x_sb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
@@ -393,7 +393,7 @@ sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_85c50x_sb_read(int func, int addr, void *priv)
sis_85c50x_sb_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_85c50x_t *dev = (sis_85c50x_t *) priv;
uint8_t ret = 0xff;
@@ -553,17 +553,17 @@ sis_85c50x_reset(void *priv)
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
sis_85c50x_write(0, 0x51, 0x00, dev);
sis_85c50x_write(0, 0x53, 0x00, dev);
sis_85c50x_write(0, 0x54, 0x00, dev);
sis_85c50x_write(0, 0x55, 0x00, dev);
sis_85c50x_write(0, 0x56, 0x00, dev);
sis_85c50x_write(0, 0x5b, 0x00, dev);
sis_85c50x_write(0, 0x60, 0x00, dev);
sis_85c50x_write(0, 0x64, 0x00, dev);
sis_85c50x_write(0, 0x65, 0x00, dev);
sis_85c50x_write(0, 0x68, 0x00, dev);
sis_85c50x_write(0, 0x69, 0xff, dev);
sis_85c50x_write(0, 0x51, 1, 0x00, dev);
sis_85c50x_write(0, 0x53, 1, 0x00, dev);
sis_85c50x_write(0, 0x54, 1, 0x00, dev);
sis_85c50x_write(0, 0x55, 1, 0x00, dev);
sis_85c50x_write(0, 0x56, 1, 0x00, dev);
sis_85c50x_write(0, 0x5b, 1, 0x00, dev);
sis_85c50x_write(0, 0x60, 1, 0x00, dev);
sis_85c50x_write(0, 0x64, 1, 0x00, dev);
sis_85c50x_write(0, 0x65, 1, 0x00, dev);
sis_85c50x_write(0, 0x68, 1, 0x00, dev);
sis_85c50x_write(0, 0x69, 1, 0xff, dev);
if (dev->type & 1) {
for (uint8_t i = 0; i < 8; i++)
@@ -586,10 +586,10 @@ sis_85c50x_reset(void *priv)
dev->pci_conf_sb[0x0b] = 0x06;
if (dev->type & 2)
dev->pci_conf_sb[0x0e] = 0x80;
sis_85c50x_sb_write(0, 0x41, 0x80, dev);
sis_85c50x_sb_write(0, 0x42, 0x80, dev);
sis_85c50x_sb_write(0, 0x43, 0x80, dev);
sis_85c50x_sb_write(0, 0x44, 0x80, dev);
sis_85c50x_sb_write(0, 0x41, 1, 0x80, dev);
sis_85c50x_sb_write(0, 0x42, 1, 0x80, dev);
sis_85c50x_sb_write(0, 0x43, 1, 0x80, dev);
sis_85c50x_sb_write(0, 0x44, 1, 0x80, dev);
if (dev->type & 2) {
/* IDE (SiS 5503) */

20
src/chipset/stpc.c
View File

@@ -213,7 +213,7 @@ stpc_localbus_read(uint16_t addr, void *priv)
}
static void
stpc_nb_write(int func, int addr, uint8_t val, void *priv)
stpc_nb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
@@ -260,7 +260,7 @@ stpc_nb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
stpc_nb_read(int func, int addr, void *priv)
stpc_nb_read(int func, int addr, UNUSED(int len), void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
@@ -337,7 +337,7 @@ stpc_ide_bm_handlers(stpc_t *dev)
}
static void
stpc_ide_write(int func, int addr, uint8_t val, void *priv)
stpc_ide_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
@@ -445,7 +445,7 @@ stpc_ide_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
stpc_ide_read(int func, int addr, void *priv)
stpc_ide_read(int func, int addr, UNUSED(int len), void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
@@ -466,12 +466,12 @@ stpc_ide_read(int func, int addr, void *priv)
}
static void
stpc_isab_write(int func, int addr, uint8_t val, void *priv)
stpc_isab_write(int func, int addr, int len, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
if ((func == 1) && (dev->local != STPC_ATLAS)) {
stpc_ide_write(0, addr, val, priv);
stpc_ide_write(0, addr, len, val, priv);
return;
}
@@ -507,13 +507,13 @@ stpc_isab_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
stpc_isab_read(int func, int addr, void *priv)
stpc_isab_read(int func, int addr, int len, void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if ((func == 1) && (dev->local != STPC_ATLAS))
ret = stpc_ide_read(0, addr, priv);
ret = stpc_ide_read(0, addr, len, priv);
else if (func > 0)
ret = 0xff;
else
@@ -524,7 +524,7 @@ stpc_isab_read(int func, int addr, void *priv)
}
static void
stpc_usb_write(int func, int addr, uint8_t val, void *priv)
stpc_usb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
@@ -571,7 +571,7 @@ stpc_usb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
stpc_usb_read(int func, int addr, void *priv)
stpc_usb_read(int func, int addr, UNUSED(int len), void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;

5
src/chipset/umc_8886.c
View File

@@ -84,6 +84,7 @@
#include <86box/machine.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -187,7 +188,7 @@ umc_8886_irq_recalc(umc_8886_t *dev)
}
static void
umc_8886_write(int func, int addr, uint8_t val, void *priv)
umc_8886_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
umc_8886_t *dev = (umc_8886_t *) priv;
@@ -293,7 +294,7 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
umc_8886_read(int func, int addr, void *priv)
umc_8886_read(int func, int addr, UNUSED(int len), void *priv)
{
const umc_8886_t *dev = (umc_8886_t *) priv;
uint8_t ret = 0xff;

4
src/chipset/umc_8890.c
View File

@@ -119,7 +119,7 @@ um8890_smram(umc_8890_t *dev)
}
static void
um8890_write(int func, int addr, uint8_t val, void *priv)
um8890_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
@@ -158,7 +158,7 @@ um8890_write(int func, int addr, uint8_t val, void *priv)
static uint8_t
um8890_read(int func, int addr, void *priv)
um8890_read(int func, int addr, UNUSED(int len), void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
uint8_t ret = 0xff;

4
src/chipset/umc_hb4.c
View File

@@ -275,7 +275,7 @@ hb4_smram(hb4_t *dev)
}
static void
hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv)
hb4_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
hb4_t *dev = (hb4_t *) priv;
@@ -336,7 +336,7 @@ hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
hb4_read(int func, int addr, void *priv)
hb4_read(int func, int addr, UNUSED(int len), void *priv)
{
const hb4_t *dev = (hb4_t *) priv;
uint8_t ret = 0xff;

15
src/chipset/via_apollo.c
View File

@@ -29,6 +29,7 @@
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
#include <86box/spd.h>
#include <86box/agpgart.h>
@@ -225,7 +226,7 @@ via_apollo_setup(via_apollo_t *dev)
}
static void
via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
via_apollo_host_bridge_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
via_apollo_t *dev = (via_apollo_t *) priv;
if (func)
@@ -684,7 +685,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
via_apollo_read(int func, int addr, void *priv)
via_apollo_read(int func, int addr, UNUSED(int len), void *priv)
{
const via_apollo_t *dev = (via_apollo_t *) priv;
uint8_t ret = 0xff;
@@ -701,11 +702,11 @@ via_apollo_read(int func, int addr, void *priv)
}
static void
via_apollo_write(int func, int addr, uint8_t val, void *priv)
via_apollo_write(int func, int addr, int len, uint8_t val, void *priv)
{
switch (func) {
case 0:
via_apollo_host_bridge_write(func, addr, val, priv);
via_apollo_host_bridge_write(func, addr, len, val, priv);
break;
default:
break;
@@ -715,9 +716,9 @@ via_apollo_write(int func, int addr, uint8_t val, void *priv)
static void
via_apollo_reset(void *priv)
{
via_apollo_write(0, 0x61, 0x00, priv);
via_apollo_write(0, 0x62, 0x00, priv);
via_apollo_write(0, 0x63, 0x00, priv);
via_apollo_write(0, 0x61, 1, 0x00, priv);
via_apollo_write(0, 0x62, 1, 0x00, priv);
via_apollo_write(0, 0x63, 1, 0x00, priv);
}
static void *

46
src/chipset/via_pipc.c
View File

@@ -170,8 +170,8 @@ pipc_log(const char *fmt, ...)
static void pipc_sgd_handlers(pipc_t *dev, uint8_t modem);
static void pipc_codec_handlers(pipc_t *dev, uint8_t modem);
static void pipc_sb_handlers(pipc_t *dev, uint8_t modem);
static uint8_t pipc_read(int func, int addr, void *priv);
static void pipc_write(int func, int addr, uint8_t val, void *priv);
static uint8_t pipc_read(int func, int addr, int len, void *priv);
static void pipc_write(int func, int addr, int len, uint8_t val, void *priv);
static void
pipc_io_trap_pact(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
@@ -930,7 +930,7 @@ pipc_sb_get_buffer(int32_t *buffer, int len, void *priv)
}
static uint8_t
pipc_read(int func, int addr, void *priv)
pipc_read(int func, int addr, UNUSED(int len), void *priv)
{
pipc_t *dev = (pipc_t *) priv;
uint8_t ret = 0xff;
@@ -1026,7 +1026,7 @@ pipc_ddma_update(pipc_t *dev, int addr)
}
static void
pipc_write(int func, int addr, uint8_t val, void *priv)
pipc_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
pipc_t *dev = (pipc_t *) priv;
int c;
@@ -1661,34 +1661,34 @@ pipc_reset(void *priv)
pipc_t *dev = (pipc_t *) priv;
uint8_t pm_func = dev->usb[1] ? 4 : 3;
pipc_write(pm_func, 0x41, 0x00, priv);
pipc_write(pm_func, 0x48, 0x01, priv);
pipc_write(pm_func, 0x49, 0x00, priv);
pipc_write(pm_func, 0x41, 1, 0x00, priv);
pipc_write(pm_func, 0x48, 1, 0x01, priv);
pipc_write(pm_func, 0x49, 1, 0x00, priv);
dev->power_regs[0x42] = ((dev->local >> 16) == VIA_PIPC_586) ? 0x00 : 0x50;
acpi_set_irq_line(dev->acpi, 0x00);
pipc_write(1, 0x04, 0x80, priv);
pipc_write(1, 0x09, 0x85, priv);
pipc_write(1, 0x10, 0xf1, priv);
pipc_write(1, 0x11, 0x01, priv);
pipc_write(1, 0x14, 0xf5, priv);
pipc_write(1, 0x15, 0x03, priv);
pipc_write(1, 0x18, 0x71, priv);
pipc_write(1, 0x19, 0x01, priv);
pipc_write(1, 0x1c, 0x75, priv);
pipc_write(1, 0x1d, 0x03, priv);
pipc_write(1, 0x20, 0x01, priv);
pipc_write(1, 0x21, 0xcc, priv);
pipc_write(1, 0x04, 1, 0x80, priv);
pipc_write(1, 0x09, 1, 0x85, priv);
pipc_write(1, 0x10, 1, 0xf1, priv);
pipc_write(1, 0x11, 1, 0x01, priv);
pipc_write(1, 0x14, 1, 0xf5, priv);
pipc_write(1, 0x15, 1, 0x03, priv);
pipc_write(1, 0x18, 1, 0x71, priv);
pipc_write(1, 0x19, 1, 0x01, priv);
pipc_write(1, 0x1c, 1, 0x75, priv);
pipc_write(1, 0x1d, 1, 0x03, priv);
pipc_write(1, 0x20, 1, 0x01, priv);
pipc_write(1, 0x21, 1, 0xcc, priv);
if (dev->local <= VIA_PIPC_586B)
pipc_write(1, 0x40, 0x04, priv);
pipc_write(1, 0x40, 1, 0x04, priv);
else
pipc_write(1, 0x40, 0x00, priv);
pipc_write(1, 0x40, 1, 0x00, priv);
if (dev->local < VIA_PIPC_586B)
pipc_write(0, 0x44, 0x00, priv);
pipc_write(0, 0x44, 1, 0x00, priv);
pipc_write(0, 0x77, 0x00, priv);
pipc_write(0, 0x77, 1, 0x00, priv);
sff_set_slot(dev->bm[0], dev->pci_slot);
sff_set_slot(dev->bm[1], dev->pci_slot);

16
src/chipset/via_vt82c505.c
View File

@@ -38,7 +38,7 @@ typedef struct vt82c505_t {
} vt82c505_t;
static void
vt82c505_write(int func, int addr, uint8_t val, void *priv)
vt82c505_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t irq;
@@ -126,7 +126,7 @@ vt82c505_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
vt82c505_read(int func, int addr, void *priv)
vt82c505_read(int func, int addr, UNUSED(int len), void *priv)
{
const vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t ret = 0xff;
@@ -147,7 +147,7 @@ vt82c505_out(uint16_t addr, uint8_t val, void *priv)
if (addr == 0xa8)
dev->index = val;
else if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
vt82c505_write(0, dev->index, val, priv);
vt82c505_write(0, dev->index, 1, val, priv);
}
static uint8_t
@@ -157,7 +157,7 @@ vt82c505_in(uint16_t addr, void *priv)
uint8_t ret = 0xff;
if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
ret = vt82c505_read(0, dev->index, priv);
ret = vt82c505_read(0, dev->index, 1, priv);
return ret;
}
@@ -173,16 +173,16 @@ vt82c505_reset(void *priv)
for (uint8_t i = 0x80; i <= 0x9f; i++) {
switch (i) {
case 0x81:
vt82c505_write(0, i, 0x01, priv);
vt82c505_write(0, i, 1, 0x01, priv);
break;
case 0x84:
vt82c505_write(0, i, 0x03, priv);
vt82c505_write(0, i, 1, 0x03, priv);
break;
case 0x93:
vt82c505_write(0, i, 0x40, priv);
vt82c505_write(0, i, 1, 0x40, priv);
break;
default:
vt82c505_write(0, i, 0x00, priv);
vt82c505_write(0, i, 1, 0x00, priv);
break;
}
}

6
src/chipset/vl82c480.c
View File

@@ -154,13 +154,10 @@ vl82c480_write(uint16_t addr, uint8_t val, void *priv)
}
break;
/* TODO: This is actually Fast A20 disable. */
#if 0
case 0xee:
mem_a20_alt = 0x00;
mem_a20_recalc();
break;
#endif
default:
break;
@@ -184,13 +181,10 @@ vl82c480_read(uint16_t addr, void *priv)
ret = dev->regs[dev->idx];
break;
/* TODO: This is actually Fast A20 enable. */
#if 0
case 0xee:
mem_a20_alt = 0x02;
mem_a20_recalc();
break;
#endif
case 0xef:
softresetx86();

8
src/chipset/vl82c59x.c
View File

@@ -208,7 +208,7 @@ vl82c59x_set_pm_io(void *priv)
}
static void
vl82c59x_write(int func, int addr, uint8_t val, void *priv)
vl82c59x_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
@@ -275,7 +275,7 @@ vl82c59x_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
vl82c59x_read(int func, int addr, void *priv)
vl82c59x_read(int func, int addr, UNUSED(int len), void *priv)
{
const vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t ret = 0xff;
@@ -292,7 +292,7 @@ vl82c59x_read(int func, int addr, void *priv)
}
static void
vl82c59x_sb_write(int func, int addr, uint8_t val, void *priv)
vl82c59x_sb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t irq;
@@ -380,7 +380,7 @@ vl82c59x_sb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
vl82c59x_sb_read(int func, int addr, void *priv)
vl82c59x_sb_read(int func, int addr, UNUSED(int len), void *priv)
{
const vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t ret = 0xff;

566
src/cpu/808x.c
View File

@@ -51,7 +51,8 @@ uint32_t custom_nmi_vector = 0x00000000;
static uint8_t pfq[6];
/* Variables to aid with the prefetch queue operation. */
static int biu_cycles = 0, pfq_pos = 0;
static int biu_cycles = 0;
int pfq_pos = 0;
/* The IP equivalent of the current prefetch queue position. */
static uint16_t pfq_ip;
@@ -66,7 +67,7 @@ static int cpu_alu_op, pfq_size;
static uint32_t cpu_src = 0, cpu_dest = 0;
static uint32_t cpu_data = 0;
static uint16_t last_addr = 0x0000;
uint16_t last_addr = 0x0000;
static uint32_t *ovr_seg = NULL;
static int prefetching = 1, completed = 1;
@@ -204,67 +205,12 @@ prefetch_queue_get_size(void)
}
static void set_if(int cond);
void
sync_from_i8080(void)
{
AL = emulated_processor.a;
BH = emulated_processor.h;
BL = emulated_processor.l;
CH = emulated_processor.b;
CL = emulated_processor.c;
DH = emulated_processor.d;
DL = emulated_processor.e;
BP = emulated_processor.sp;
cpu_state.pc = emulated_processor.pc;
cpu_state.flags &= 0xFF00;
cpu_state.flags |= emulated_processor.sf << 7;
cpu_state.flags |= emulated_processor.zf << 6;
cpu_state.flags |= emulated_processor.hf << 4;
cpu_state.flags |= emulated_processor.pf << 2;
cpu_state.flags |= 1 << 1;
cpu_state.flags |= emulated_processor.cf << 0;
set_if(emulated_processor.iff);
}
void
sync_to_i8080(void)
{
if (!is_nec)
return;
emulated_processor.a = AL;
emulated_processor.h = BH;
emulated_processor.l = BL;
emulated_processor.b = CH;
emulated_processor.c = CL;
emulated_processor.d = DH;
emulated_processor.e = DL;
emulated_processor.sp = BP;
emulated_processor.pc = cpu_state.pc;
emulated_processor.iff = !!(cpu_state.flags & I_FLAG);
emulated_processor.sf = (cpu_state.flags >> 7) & 1;
emulated_processor.zf = (cpu_state.flags >> 6) & 1;
emulated_processor.hf = (cpu_state.flags >> 4) & 1;
emulated_processor.pf = (cpu_state.flags >> 2) & 1;
emulated_processor.cf = (cpu_state.flags >> 0) & 1;
emulated_processor.interrupt_delay = noint;
}
uint16_t
get_last_addr(void)
{
return last_addr;
}
static void
clock_start(void)
{
cycdiff = cycles;
}
static void
clock_end(void)
{
@@ -293,7 +239,7 @@ fetch_and_bus(int c, int bus)
pfq_add(c, !bus);
if (bus < 2) {
clock_end();
clock_start();
cycdiff = cycles;
}
}
@@ -412,7 +358,7 @@ readmemw(uint32_t s, uint16_t a)
else {
wait_cycs(4, 1);
ret = read_mem_b(s + a);
ret |= read_mem_b(s + ((is186 && !is_nec) ? (a + 1) : (a + 1) & 0xffff)) << 8;
ret |= read_mem_b(s + (is186 ? (a + 1) : (a + 1) & 0xffff)) << 8;
}
return ret;
@@ -484,7 +430,7 @@ writememw(uint32_t s, uint32_t a, uint16_t v)
else {
write_mem_b(addr, v & 0xff);
wait_cycs(4, 1);
addr = s + ((is186 && !is_nec) ? (a + 1) : ((a + 1) & 0xffff));
addr = s + (is186 ? (a + 1) : ((a + 1) & 0xffff));
write_mem_b(addr, v >> 8);
}
@@ -693,8 +639,6 @@ reset_808x(int hard)
load_cs(0xFFFF);
cpu_state.pc = 0;
if (is_nec)
cpu_state.flags |= MD_FLAG;
rammask = 0xfffff;
prefetching = 1;
@@ -929,7 +873,7 @@ seteaq(uint64_t val)
static void
push(uint16_t *val)
{
if ((is186 && !is_nec) && (SP == 1)) {
if (is186 && (SP == 1)) {
writememw(ss - 1, 0, *val);
SP = cpu_state.eaaddr = 0xFFFF;
return;
@@ -1085,11 +1029,6 @@ interrupt(uint16_t addr)
uint16_t new_cs, new_ip;
uint16_t tempf;
if (!(cpu_state.flags & MD_FLAG) && is_nec) {
sync_from_i8080();
x808x_log("CALLN/INT#/NMI#\n");
}
addr <<= 2;
cpu_state.eaaddr = addr;
old_cs = CS;
@@ -1103,11 +1042,9 @@ interrupt(uint16_t addr)
pfq_clear();
ovr_seg = NULL;
access(39, 16);
tempf = cpu_state.flags & (is_nec ? 0x8fd7 : 0x0fd7);
tempf = cpu_state.flags & 0x0fd7;
push(&tempf);
cpu_state.flags &= ~(I_FLAG | T_FLAG);
if (is_nec)
cpu_state.flags |= MD_FLAG;
access(40, 16);
push(&old_cs);
old_ip = cpu_state.pc;
@@ -1118,71 +1055,6 @@ interrupt(uint16_t addr)
push(&old_ip);
}
/* Ditto, but for breaking into emulation mode. */
static void
interrupt_brkem(uint16_t addr)
{
uint16_t old_cs, old_ip;
uint16_t new_cs, new_ip;
uint16_t tempf;
addr <<= 2;
cpu_state.eaaddr = addr;
old_cs = CS;
access(5, 16);
new_ip = readmemw(0, cpu_state.eaaddr);
wait_cycs(1, 0);
cpu_state.eaaddr = (cpu_state.eaaddr + 2) & 0xffff;
access(6, 16);
new_cs = readmemw(0, cpu_state.eaaddr);
prefetching = 0;
pfq_clear();
ovr_seg = NULL;
access(39, 16);
tempf = cpu_state.flags & (is_nec ? 0x8fd7 : 0x0fd7);
push(&tempf);
cpu_state.flags &= ~(MD_FLAG);
cpu_md_write_disable = 0;
access(40, 16);
push(&old_cs);
old_ip = cpu_state.pc;
load_cs(new_cs);
access(68, 16);
set_ip(new_ip);
access(41, 16);
push(&old_ip);
sync_to_i8080();
x808x_log("BRKEM mode\n");
}
void
retem_i8080(void)
{
sync_from_i8080();
prefetching = 0;
pfq_clear();
set_ip(pop());
load_cs(pop());
cpu_state.flags = pop();
emulated_processor.iff = !!(cpu_state.flags & I_FLAG);
cpu_md_write_disable = 1;
noint = 1;
nmi_enable = 1;
x808x_log("RETEM mode\n");
}
void
interrupt_808x(uint16_t addr)
{
interrupt(addr);
}
static void
custom_nmi(void)
{
@@ -1190,11 +1062,6 @@ custom_nmi(void)
uint16_t new_cs, new_ip;
uint16_t tempf;
if (!(cpu_state.flags & MD_FLAG) && is_nec) {
sync_from_i8080();
pclog("NMI# (CUTSOM)\n");
}
cpu_state.eaaddr = 0x0002;
old_cs = CS;
access(5, 16);
@@ -1209,11 +1076,9 @@ custom_nmi(void)
pfq_clear();
ovr_seg = NULL;
access(39, 16);
tempf = cpu_state.flags & (is_nec ? 0x8fd7 : 0x0fd7);
tempf = cpu_state.flags & 0x0fd7;
push(&tempf);
cpu_state.flags &= ~(I_FLAG | T_FLAG);
if (is_nec)
cpu_state.flags |= MD_FLAG;
access(40, 16);
push(&old_cs);
old_ip = cpu_state.pc;
@@ -1225,10 +1090,10 @@ custom_nmi(void)
}
static int
irq_pending(int nec_hlt)
irq_pending(void)
{
uint8_t temp;
int i_flag = (cpu_state.flags & I_FLAG) || nec_hlt;
int i_flag = (cpu_state.flags & I_FLAG);
temp = (nmi && nmi_enable && nmi_mask) || ((cpu_state.flags & T_FLAG) && !noint) || (i_flag && pic.int_pending && !noint);
@@ -1236,12 +1101,12 @@ irq_pending(int nec_hlt)
}
static void
check_interrupts(int nec_hlt)
check_interrupts(void)
{
int temp;
int i_flag = (cpu_state.flags & I_FLAG) || nec_hlt;
int i_flag = (cpu_state.flags & I_FLAG);
if (irq_pending(nec_hlt)) {
if (irq_pending()) {
if ((cpu_state.flags & T_FLAG) && !(noint & 1)) {
interrupt(1);
return;
@@ -1290,13 +1155,10 @@ rep_action(int bits)
return 0;
wait_cycs(2, 0);
t = CX;
if (irq_pending(0) && (repeating != 0)) {
if (irq_pending() && (repeating != 0)) {
access(71, bits);
pfq_clear();
if (is_nec && (ovr_seg != NULL))
set_ip(cpu_state.pc - 3);
else
set_ip(cpu_state.pc - 2);
set_ip(cpu_state.pc - 2);
t = 0;
}
if (t == 0) {
@@ -1919,32 +1781,16 @@ void
execx86(int cycs)
{
uint8_t temp = 0, temp2, old_af, nests;
uint8_t temp_val, temp_al, bit, handled = 0;
uint8_t odd, zero, nibbles_count, destcmp;
uint8_t destbyte, srcbyte, nibble_result, bit_length;
uint8_t bit_offset;
int8_t nibble_result_s;
uint16_t addr, tempw, new_cs, new_ip;
uint16_t addr, tempw, new_cs, new_ip, handled = 0;
uint16_t tempw_int, size, tempbp, lowbound;
uint16_t highbound, regval, orig_sp, wordtopush;
uint16_t immediate, old_flags;
uint16_t highbound, regval, orig_sp, wordtopush, immediate;
int bits;
uint32_t dest_seg, i, carry, nibble;
uint32_t srcseg, byteaddr;
uint32_t dest_seg;
cycles += cycs;
while (cycles > 0) {
clock_start();
if (is_nec && !(cpu_state.flags & MD_FLAG)) {
i8080_step(&emulated_processor);
set_if(emulated_processor.iff);
cycles -= emulated_processor.cyc;
emulated_processor.cyc = 0;
completed = 1;
goto exec_completed;
}
cycdiff = cycles;
if (!repeating) {
cpu_state.oldpc = cpu_state.pc;
@@ -2004,18 +1850,6 @@ execx86(int cycs)
handled = 1;
break;
case 0x64:
case 0x65:
if (is_nec) {
/* REPC/REPNC */
wait_cycs(1, 0);
in_rep = (opcode == 0x64 ? 1 : 2);
rep_c_flag = 1;
completed = 0;
handled = 1;
}
break;
case 0x68:
wordtopush = pfq_fetchw();
wait_cycs(1, 0);
@@ -2111,7 +1945,6 @@ execx86(int cycs)
tempw_int = 0;
size = pfq_fetchw();
nests = pfq_fetchb();
i = 0;
push(&BP);
tempw_int = SP;
@@ -2141,8 +1974,7 @@ execx86(int cycs)
wait_cycs((cpu_mod != 3) ? 9 : 6, 0);
if (!is_nec)
cpu_src &= 0x1F;
cpu_src &= 0x1F;
while (cpu_src != 0) {
cpu_dest = cpu_data;
oldc = cpu_state.flags & C_FLAG;
@@ -2239,299 +2071,6 @@ execx86(int cycs)
case 0x0F:
case 0x17:
case 0x1F: /* POP seg */
if (is_nec && (opcode == 0x0F)) {
uint8_t orig_opcode = opcode;
opcode = pfq_fetchb();
switch (opcode) {
case 0x28: /* ROL4 r/m */
do_mod_rm();
wait_cycs(21, 0);
temp_val = geteab();
temp_al = AL;
temp_al &= 0xF;
temp_al |= (temp_val & 0xF0);
temp_val = (temp_al & 0xF) | ((temp_val & 0xF) << 4);
temp_al >>= 4;
temp_al &= 0xF;
seteab(temp_val);
AL = temp_al;
handled = 1;
break;
case 0x2a: /* ROR4 r/m */
do_mod_rm();
wait_cycs(21, 0);
temp_val = geteab();
temp_al = AL;
AL = temp_val & 0xF;
temp_val = (temp_val >> 4) | ((temp_al & 0xF) << 4);
seteab(temp_val);
handled = 1;
break;
case 0x10: /* TEST1 r8/m8, CL*/
case 0x11: /* TEST1 r16/m16, CL*/
case 0x18: /* TEST1 r8/m8, imm3 */
case 0x19: /* TEST1 r16/m16, imm4 */
bits = 8 << (opcode & 0x1);
do_mod_rm();
wait_cycs(3, 0);
bit = (opcode & 0x8) ? (pfq_fetchb()) : (CL);
bit &= ((1 << (3 + (opcode & 0x1))) - 1);
read_ea(0, bits);
set_zf_ex(!(cpu_data & (1 << bit)));
cpu_state.flags &= ~(V_FLAG | C_FLAG);
handled = 1;
break;
case 0x16: /* NOT1 r8/m8, CL*/
case 0x17: /* NOT1 r16/m16, CL*/
case 0x1e: /* NOT1 r8/m8, imm3 */
case 0x1f: /* NOT1 r16/m16, imm4 */
bits = 8 << (opcode & 0x1);
do_mod_rm();
wait_cycs(3, 0);
bit = (opcode & 0x8) ? (pfq_fetchb()) : (CL);
bit &= ((1 << (3 + (opcode & 0x1))) - 1);
read_ea(0, bits);
if (bits == 8)
seteab((cpu_data & 0xFF) ^ (1 << bit));
else
seteaw((cpu_data & 0xFFFF) ^ (1 << bit));
handled = 1;
break;
case 0x14: /* SET1 r8/m8, CL*/
case 0x15: /* SET1 r16/m16, CL*/
case 0x1c: /* SET1 r8/m8, imm3 */
case 0x1d: /* SET1 r16/m16, imm4 */
bits = 8 << (opcode & 0x1);
do_mod_rm();
wait_cycs(3, 0);
bit = (opcode & 0x8) ? (pfq_fetchb()) : (CL);
bit &= ((1 << (3 + (opcode & 0x1))) - 1);
read_ea(0, bits);
if (bits == 8)
seteab((cpu_data & 0xFF) | (1 << bit));
else
seteaw((cpu_data & 0xFFFF) | (1 << bit));
handled = 1;
break;
case 0x12: /* CLR1 r8/m8, CL*/
case 0x13: /* CLR1 r16/m16, CL*/
case 0x1a: /* CLR1 r8/m8, imm3 */
case 0x1b: /* CLR1 r16/m16, imm4 */
bits = 8 << (opcode & 0x1);
do_mod_rm();
wait_cycs(3, 0);
bit = (opcode & 0x8) ? (pfq_fetchb()) : (CL);
bit &= ((1 << (3 + (opcode & 0x1))) - 1);
read_ea(0, bits);
if (bits == 8)
seteab((cpu_data & 0xFF) & ~(1 << bit));
else
seteaw((cpu_data & 0xFFFF) & ~(1 << bit));
handled = 1;
break;
case 0x20: /* ADD4S */
odd = !!(CL % 2);
zero = 1;
nibbles_count = CL - odd;
i = 0;
carry = 0;
nibble = 0;
srcseg = ovr_seg ? *ovr_seg : ds;
wait_cycs(5, 0);
for (i = 0; i < ((nibbles_count / 2) + odd); i++) {
wait_cycs(19, 0);
destcmp = read_mem_b((es) + DI + i);
for (nibble = 0; nibble < 2; nibble++) {
destbyte = destcmp >> (nibble ? 4 : 0);
srcbyte = read_mem_b(srcseg + SI + i) >> (nibble ? 4 : 0);
destbyte &= 0xF;
srcbyte &= 0xF;
nibble_result = (i == (nibbles_count / 2) && nibble == 1) ? (destbyte + carry) : ((uint8_t) (destbyte)) + ((uint8_t) (srcbyte)) + ((uint32_t) carry);
carry = 0;
while (nibble_result >= 10) {
nibble_result -= 10;
carry++;
}
if (zero != 0 || (i == (nibbles_count / 2) && nibble == 1))
zero = (nibble_result == 0);
destcmp = ((destcmp & (nibble ? 0x0F : 0xF0)) | (nibble_result << (4 * nibble)));
}
write_mem_b(es + DI + i, destcmp);
}
set_cf(!!carry);
set_zf(!!zero);
handled = 1;
break;
case 0x22: /* SUB4S */
odd = !!(CL % 2);
zero = 1;
nibbles_count = CL - odd;
i = 0;
carry = 0;
nibble = 0;
srcseg = ovr_seg ? *ovr_seg : ds;
wait_cycs(5, 0);
for (i = 0; i < ((nibbles_count / 2) + odd); i++) {
wait_cycs(19, 0);
destcmp = read_mem_b((es) + DI + i);
for (nibble = 0; nibble < 2; nibble++) {
destbyte = destcmp >> (nibble ? 4 : 0);
srcbyte = read_mem_b(srcseg + SI + i) >> (nibble ? 4 : 0);
destbyte &= 0xF;
srcbyte &= 0xF;
nibble_result_s = (i == (nibbles_count / 2) && nibble == 1) ? ((int8_t) destbyte - (int8_t) carry) : ((int8_t) (destbyte)) - ((int8_t) (srcbyte)) - ((int8_t) carry);
carry = 0;
while (nibble_result_s < 0) {
nibble_result_s += 10;
carry++;
}
if (zero != 0 || (i == (nibbles_count / 2) && nibble == 1))
zero = (nibble_result_s == 0);
destcmp = ((destcmp & (nibble ? 0x0F : 0xF0)) | (nibble_result_s << (4 * nibble)));
}
write_mem_b(es + DI + i, destcmp);
}
set_cf(!!carry);
set_zf(!!zero);
handled = 1;
break;
case 0x26: /* CMP4S */
odd = !!(CL % 2);
zero = 1;
nibbles_count = CL - odd;
i = 0;
carry = 0;
nibble = 0;
srcseg = ovr_seg ? *ovr_seg : ds;
wait_cycs(5, 0);
for (i = 0; i < ((nibbles_count / 2) + odd); i++) {
wait_cycs(19, 0);
destcmp = read_mem_b((es) + DI + i);
for (nibble = 0; nibble < 2; nibble++) {
destbyte = destcmp >> (nibble ? 4 : 0);
srcbyte = read_mem_b(srcseg + SI + i) >> (nibble ? 4 : 0);
destbyte &= 0xF;
srcbyte &= 0xF;
nibble_result_s = ((int8_t) (destbyte)) - ((int8_t) (srcbyte)) - ((int8_t) carry);
carry = 0;
while (nibble_result_s < 0) {
nibble_result_s += 10;
carry++;
}
if (zero != 0 || (i == (nibbles_count / 2) && nibble == 1))
zero = (nibble_result_s == 0);
destcmp = ((destcmp & (nibble ? 0x0F : 0xF0)) | (nibble_result_s << (4 * nibble)));
}
}
set_cf(!!carry);
set_zf(!!zero);
handled = 1;
break;
case 0x31: /* INS reg1, reg2 */
case 0x39: /* INS reg8, imm4 */
do_mod_rm();
wait_cycs(1, 0);
bit_length = ((opcode & 0x8) ? (pfq_fetchb() & 0xF) : (getr8(cpu_reg) & 0xF)) + 1;
bit_offset = getr8(cpu_rm) & 0xF;
byteaddr = (es) + DI;
i = 0;
if (bit_offset >= 8) {
DI++;
byteaddr++;
bit_offset -= 8;
}
for (i = 0; i < bit_length; i++) {
byteaddr = (es) + DI;
writememb(es, DI, (read_mem_b(byteaddr) & ~(1 << (bit_offset))) | ((!!(AX & (1 << i))) << bit_offset));
bit_offset++;
if (bit_offset == 8) {
DI++;
bit_offset = 0;
}
}
setr8(cpu_rm, bit_offset);
handled = 1;
break;
case 0x33: /* EXT reg1, reg2 */
case 0x3b: /* EXT reg8, imm4 */
do_mod_rm();
wait_cycs(1, 0);
bit_length = ((opcode & 0x8) ? (pfq_fetchb() & 0xF) : (getr8(cpu_reg) & 0xF)) + 1;
bit_offset = getr8(cpu_rm) & 0xF;
byteaddr = (ds) + SI;
i = 0;
if (bit_offset >= 8) {
SI++;
byteaddr++;
bit_offset -= 8;
}
AX = 0;
for (i = 0; i < bit_length; i++) {
byteaddr = (ds) + SI;
AX |= (!!(readmemb(byteaddr) & (1 << bit_offset))) << i;
bit_offset++;
if (bit_offset == 8) {
SI++;
bit_offset = 0;
}
}
setr8(cpu_rm, bit_offset);
handled = 1;
break;
case 0xFF: /* BRKEM */
interrupt_brkem(pfq_fetchb());
handled = 1;
break;
default:
opcode = orig_opcode;
cpu_state.pc--;
break;
}
} else
handled = 0;
if (handled)
break;
access(22, 16);
if (opcode == 0x0F) {
load_cs(pop());
@@ -3019,28 +2558,21 @@ execx86(int cycs)
}
#else
wait_cycs(7, 0);
check_interrupts(0);
check_interrupts();
#endif
break;
case 0x9C: /*PUSHF*/
access(33, 16);
if (is_nec)
tempw = (cpu_state.flags & 0x8fd7) | 0x7000;
else
tempw = (cpu_state.flags & 0x0fd7) | 0xf000;
tempw = (cpu_state.flags & 0x0fd7) | 0xf000;
push(&tempw);
break;
case 0x9D: { /*POPF*/
uint16_t old_flags = cpu_state.flags;
access(25, 16);
if (is_nec && cpu_md_write_disable)
cpu_state.flags = pop() | 0x8002;
else
cpu_state.flags = pop() | 0x0002;
cpu_state.flags = pop() | 0x0002;
wait_cycs(1, 0);
if ((old_flags ^ cpu_state.flags) & T_FLAG)
noint = 1;
sync_to_i8080();
break;
} case 0x9E: /*SAHF*/
wait_cycs(1, 0);
@@ -3306,15 +2838,10 @@ execx86(int cycs)
access(62, 8);
set_ip(new_ip);
access(45, 8);
if (is_nec && cpu_md_write_disable)
cpu_state.flags = pop() | 0x8002;
else
cpu_state.flags = pop() | 0x0002;
cpu_state.flags = pop() | 0x0002;
wait_cycs(5, 0);
noint = 2;
nmi_enable = 1;
if (is_nec && !(cpu_state.flags & MD_FLAG))
sync_to_i8080();
break;
case 0xD0:
@@ -3335,7 +2862,7 @@ execx86(int cycs)
cpu_src = CL;
wait_cycs((cpu_mod != 3) ? 9 : 6, 0);
}
if (is186 && !is_nec)
if (is186)
cpu_src &= 0x1F;
while (cpu_src != 0) {
cpu_dest = cpu_data;
@@ -3414,15 +2941,7 @@ execx86(int cycs)
case 0xD4: /*AAM*/
wait_cycs(1, 0);
#ifdef NO_VARIANT_ON_NEC
if (is_nec) {
(void) pfq_fetchb();
cpu_src = 10;
} else
cpu_src = pfq_fetchb();
#else
cpu_src = pfq_fetchb();
#endif
if (x86_div(AL, 0)) {
cpu_data = AL;
set_pzs(8);
@@ -3430,11 +2949,7 @@ execx86(int cycs)
break;
case 0xD5: /*AAD*/
wait_cycs(1, 0);
if (is_nec) {
(void) pfq_fetchb();
mul(10, AH);
} else
mul(pfq_fetchb(), AH);
mul(pfq_fetchb(), AH);
cpu_dest = AL;
cpu_src = cpu_data;
add(8);
@@ -3443,13 +2958,10 @@ execx86(int cycs)
set_pzs(8);
break;
case 0xD6: /*SALC*/
if (!is_nec) {
wait_cycs(1, 0);
AL = (cpu_state.flags & C_FLAG) ? 0xff : 0x00;
wait_cycs(1, 0);
break;
}
fallthrough;
wait_cycs(1, 0);
AL = (cpu_state.flags & C_FLAG) ? 0xff : 0x00;
wait_cycs(1, 0);
break;
case 0xD7: /*XLATB*/
cpu_state.eaaddr = (BX + AL) & 0xffff;
access(4, 8);
@@ -3651,9 +3163,9 @@ execx86(int cycs)
pfq_clear();
}
wait_cycs(1, 0);
if (irq_pending(is_nec)) {
if (irq_pending()) {
wait_cycs(cycles & 1, 0);
check_interrupts(is_nec);
check_interrupts();
} else {
repeating = 1;
completed = 0;
@@ -3699,7 +3211,6 @@ execx86(int cycs)
break;
case 0x20: /* MUL */
case 0x28: /* IMUL */
old_flags = cpu_state.flags;
wait_cycs(1, 0);
mul(get_accum(bits), cpu_data);
if (opcode & 1) {
@@ -3711,17 +3222,12 @@ execx86(int cycs)
AL = (uint8_t) cpu_data;
AH = (uint8_t) cpu_dest;
set_co_mul(bits, AH != ((AL & 0x80) == 0 || (rmdat & 0x38) == 0x20 ? 0 : 0xff));
if (!is_nec)
cpu_data = AH;
cpu_data = AH;
}
set_sf(bits);
set_pf();
if (cpu_mod != 3)
wait_cycs(1, 0);
/* NOTE: When implementing the V20, care should be taken to not change
the zero flag. */
if (is_nec)
cpu_state.flags = (cpu_state.flags & ~Z_FLAG) | (old_flags & Z_FLAG);
break;
case 0x30: /* DIV */
case 0x38: /* IDIV */
@@ -3843,7 +3349,7 @@ execx86(int cycs)
break;
}
}
exec_completed:
if (completed) {
repeating = 0;
ovr_seg = NULL;
@@ -3852,7 +3358,7 @@ exec_completed:
if (in_lock)
clear_lock = 1;
clock_end();
check_interrupts(0);
check_interrupts();
if (noint)
noint = 0;

2
src/cpu/CMakeLists.txt
View File

@@ -20,6 +20,8 @@ add_library(cpu OBJECT
cpu_table.c
fpu.c x86.c
808x.c
vx0.c
vx0_biu.c
386.c
386_common.c
386_dynarec.c

4
src/cpu/cpu.c
View File

@@ -1865,6 +1865,8 @@ cpu_set(void)
cpu_exec = exec386_2386;
} else if (cpu_s->cpu_type >= CPU_286)
cpu_exec = exec386_2386;
else if (is_nec)
cpu_exec = execvx0;
else
cpu_exec = execx86;
mmx_init();
@@ -1897,7 +1899,7 @@ cpu_set_pci_speed(int speed)
{
if (speed)
cpu_pci_speed = speed;
else if (cpu_busspeed < 42500000)
else if (cpu_busspeed < 40000000)
cpu_pci_speed = cpu_busspeed;
else if (cpu_busspeed < 84000000)
cpu_pci_speed = cpu_busspeed / 2;

3
src/cpu/cpu.h
View File

@@ -718,6 +718,7 @@ extern void codegen_reset(void);
extern void cpu_set_edx(void);
extern int divl(uint32_t val);
extern void execx86(int32_t cycs);
extern void execvx0(int32_t cycs);
extern void enter_smm(int in_hlt);
extern void enter_smm_check(int in_hlt);
extern void leave_smm(void);
@@ -809,6 +810,8 @@ extern void SF_FPU_reset(void);
extern void reset_808x(int hard);
extern void interrupt_808x(uint16_t addr);
extern void reset_vx0(int hard);
extern void cpu_register_fast_off_handler(void *timer);
extern void cpu_fast_off_advance(void);
extern void cpu_fast_off_period_set(uint16_t vla, double period);

4783
src/cpu/vx0.c Normal file
View File

File diff suppressed because it is too large Load Diff

1152
src/cpu/vx0_biu.c Normal file
View File

File diff suppressed because it is too large Load Diff

116
src/cpu/vx0_biu.h Normal file
View File

@@ -0,0 +1,116 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 808x BIU emulation header.
*
* Authors: Andrew Jenner, <https://www.reenigne.org>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2015-2020 Andrew Jenner.
* Copyright 2016-2020 Miran Grca.
*/
#ifndef EMU_808X_BIU_H
#define EMU_808X_BIU_H
#define DEBUG_SEG 0xf000
// #define DEBUG_SEG 0x0f3c
// #define DEBUG_SEG 0x1e1f
// #define DEBUG_SEG 0xf000
// #define DEBUG_SEG 0xc800
// #define DEBUG_SEG 0x0070
// #define DEBUG_SEG 0x0291
// #define DEBUG_SEG 0xefff
// #define DEBUG_SEG 0x15a2
// #define DEBUG_OFF_L 0x2c3b
// #define DEBUG_OFF_L 0xe182
// #define DEBUG_OFF_L 0xf000
// #define DEBUG_OFF_H 0xefff
// #define DEBUG_OFF_L 0x0000
// #define DEBUG_OFF_H 0xffff
#define DEBUG_OFF_L 0xf300
#define DEBUG_OFF_H 0xf3ff
#define BUS_OUT 1
#define BUS_HIGH 2
#define BUS_WIDE 4
#define BUS_CODE 8
#define BUS_IO 16
#define BUS_MEM 32
#define BUS_PIC 64
#define BUS_ACCESS_TYPE (BUS_CODE | BUS_IO | BUS_MEM | BUS_PIC)
#undef readmemb
#undef readmemw
#undef readmeml
#undef readmemq
enum {
BUS_T1 = 0,
BUS_T2,
BUS_T3,
BUS_T4
};
enum {
BIU_STATE_IDLE,
BIU_STATE_SUSP,
BIU_STATE_DELAY,
BIU_STATE_RESUME,
BIU_STATE_WAIT,
BIU_STATE_PF,
BIU_STATE_EU
};
enum {
DMA_STATE_IDLE,
DMA_STATE_TIMER,
DMA_STATE_DREQ,
DMA_STATE_HRQ,
DMA_STATE_HLDA,
DMA_STATE_OPERATING
};
/* Temporary BIU externs - move to 808x_biu.h. */
extern void biu_resume_on_queue_read(void);
extern void wait(int c);
extern void biu_reset(void);
extern void cpu_io_vx0(int bits, int out, uint16_t port);
extern void biu_state_set_eu(void);
extern uint8_t readmemb_vx0(uint32_t s, uint16_t a);
extern uint16_t readmemw_vx0(uint32_t s, uint16_t a);
extern uint16_t readmem_vx0(uint32_t s);
extern uint32_t readmeml_vx0(uint32_t s, uint16_t a);
extern uint64_t readmemq_vx0(uint32_t s, uint16_t a);
extern void writememb_vx0(uint32_t s, uint32_t a, uint8_t v);
extern void writememw_vx0(uint32_t s, uint32_t a, uint16_t v);
extern void writemem_vx0(uint32_t s, uint16_t v);
extern void writememl_vx0(uint32_t s, uint32_t a, uint32_t v);
extern void writememq_vx0(uint32_t s, uint32_t a, uint64_t v);
extern uint8_t biu_pfq_read(void);
extern uint8_t biu_pfq_fetchb_common(void);
extern uint8_t biu_pfq_fetchb(void);
extern uint16_t biu_pfq_fetchw(void);
extern uint16_t biu_pfq_fetch(void);
extern void biu_update_pc(void);
extern void biu_queue_flush(void);
extern void biu_suspend_fetch(void);
extern void biu_begin_eu(void);
extern void biu_wait_for_read_finish(void);
extern uint8_t biu_preload_byte;
extern int nx;
extern int schedule_fetch;
extern int in_lock;
extern int bus_request_type;
extern int pic_data;
extern int biu_queue_preload;
#endif /*EMU_808X_BIU_H*/

8
src/cpu/x86.c
View File

@@ -367,8 +367,12 @@ reset_common(int hard)
} else
device_reset_all(DEVICE_SOFTRESET);
if (!is286)
reset_808x(hard);
if (!is286) {
if (is_nec)
reset_vx0(hard);
else
reset_808x(hard);
}
in_lock = 0;

2
src/cpu/x86.h
View File

@@ -37,6 +37,7 @@ extern uint8_t opcode;
extern uint8_t flags_p;
extern uint8_t znptable8[256];
extern uint16_t last_addr;
extern uint16_t zero;
extern uint16_t oldcs;
extern uint16_t lastcs;
@@ -44,6 +45,7 @@ extern uint16_t lastpc;
extern uint16_t *mod1add[2][8];
extern uint16_t znptable16[65536];
extern int pfq_pos;
extern int x86_was_reset;
extern int trap;
extern int codegen_flat_ss;

4
src/cpu/x87_ops.h
View File

@@ -551,7 +551,11 @@ static int
FPU_ILLEGAL_a16(UNUSED(uint32_t fetchdat))
{
geteaw();
#ifdef FPU_NEC
do_cycles(timing_rr);
#else
wait_cycs(timing_rr, 0);
#endif
return 0;
}
#else

4
src/cpu/x87_ops_misc.h
View File

@@ -7,7 +7,11 @@ opFI(uint32_t fetchdat)
cpu_state.npxc &= ~0x80;
if (rmdat == 0xe1)
cpu_state.npxc |= 0x80;
#ifdef FPU_NEC
do_cycles(3);
#else
wait_cycs(3, 0);
#endif
return 0;
}
#else

4
src/cpu/x87_ops_sf.h
View File

@@ -354,7 +354,11 @@ sf_FI(uint32_t fetchdat)
fpu_state.cwd &= ~FPU_SW_Summary;
if (rmdat == 0xe1)
fpu_state.cwd |= FPU_SW_Summary;
#ifdef FPU_NEC
do_cycles(3);
#else
wait_cycs(3, 0);
#endif
return 0;
}
#else

32
src/device/hasp.c
View File

@@ -302,13 +302,13 @@ hasp_read_status(void *priv)
}
static void *
hasp_init(void *lpt, int type)
hasp_init(const device_t *info, int type)
{
hasp_t *dev = calloc(1, sizeof(hasp_t));
hasp_log("HASP: init(%d)\n", type);
dev->lpt = lpt;
dev->lpt = lpt_attach(hasp_write_data, NULL, NULL, hasp_read_status, NULL, NULL, NULL, dev);
dev->type = &hasp_types[type];
dev->status = 0x80;
@@ -317,9 +317,9 @@ hasp_init(void *lpt, int type)
}
static void *
hasp_init_savquest(void *lpt)
hasp_init_savquest(const device_t *info)
{
return hasp_init(lpt, HASP_TYPE_SAVQUEST);
return hasp_init(info, HASP_TYPE_SAVQUEST);
}
static void
@@ -332,16 +332,16 @@ hasp_close(void *priv)
free(dev);
}
const lpt_device_t lpt_hasp_savquest_device = {
.name = "Protection Dongle for Savage Quest",
.internal_name = "dongle_savquest",
.init = hasp_init_savquest,
.close = hasp_close,
.write_data = hasp_write_data,
.write_ctrl = NULL,
.strobe = NULL,
.read_status = hasp_read_status,
.read_ctrl = NULL,
.epp_write_data = NULL,
.epp_request_read = NULL
const device_t lpt_hasp_savquest_device = {
.name = "Protection Dongle for Savage Quest",
.internal_name = "dongle_savquest",
.flags = DEVICE_LPT,
.local = 0,
.init = hasp_init_savquest,
.close = hasp_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

113
src/device/lpt.c
View File

@@ -34,19 +34,22 @@ lpt_port_t lpt_ports[PARALLEL_MAX];
lpt_device_t lpt_devs[PARALLEL_MAX];
const lpt_device_t lpt_none_device = {
const device_t lpt_none_device = {
.name = "None",
.internal_name = "none",
.flags = DEVICE_LPT,
.local = 0,
.init = NULL,
.close = NULL,
.write_data = NULL,
.write_ctrl = NULL,
.read_status = NULL,
.read_ctrl = NULL
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static const struct {
const lpt_device_t *device;
const device_t *device;
} lpt_devices[] = {
// clang-format off
{ &lpt_none_device },
@@ -56,9 +59,7 @@ static const struct {
{ &lpt_prt_text_device },
{ &lpt_prt_escp_device },
{ &lpt_prt_ps_device },
#ifdef USE_PCL
{ &lpt_prt_pcl_device },
#endif
{ &lpt_plip_device },
{ &lpt_hasp_savquest_device },
{ NULL }
@@ -83,50 +84,41 @@ lpt_log(const char *fmt, ...)
# define lpt_log(fmt, ...)
#endif
int
lpt_device_available(int id)
{
if (lpt_devices[id].device)
return device_available(lpt_devices[id].device);
return 1;
}
const device_t *
lpt_device_getdevice(const int id)
{
return (device_t *) lpt_devices[id].device->cfgdevice;
return lpt_devices[id].device;
}
int
lpt_device_has_config(const int id)
{
int c = 0;
const device_t *dev = (device_t *) lpt_devices[id].device->cfgdevice;
const device_config_t *config;
if (dev == NULL)
if (lpt_devices[id].device == NULL)
return 0;
if (dev->config == NULL)
return 0;
config = dev->config;
while (config->type != CONFIG_END) {
c++;
config++;
}
return (c > 0) ? 1 : 0;
return device_has_config(lpt_devices[id].device);
}
const char *
lpt_device_get_name(const int id)
{
if (lpt_devices[id].device == NULL)
return NULL;
return 0;
return lpt_devices[id].device->name;
}
const char *
lpt_device_get_internal_name(const int id)
{
if (lpt_devices[id].device == NULL)
return NULL;
return lpt_devices[id].device->internal_name;
return device_get_internal_name(lpt_devices[id].device);
}
int
@@ -147,29 +139,43 @@ void
lpt_devices_init(void)
{
for (uint8_t i = 0; i < PARALLEL_MAX; i++) {
lpt_t *dev = lpt_devs[i].lpt;
memset(&(lpt_devs[i]), 0x00, sizeof(lpt_device_t));
if (lpt_devices[lpt_ports[i].device].device != NULL) {
memcpy(&(lpt_devs[i]), (lpt_device_t *) lpt_devices[lpt_ports[i].device].device, sizeof(lpt_device_t));
if (lpt_devs[i].init)
lpt_devs[i].priv = lpt_devs[i].init(dev);
} else
memset(&(lpt_devs[i]), 0x00, sizeof(lpt_device_t));
lpt_devs[i].lpt = dev;
if ((lpt_devices[lpt_ports[i].device].device != NULL) &&
(lpt_devices[lpt_ports[i].device].device != &lpt_none_device))
device_add_inst((device_t *) lpt_devices[lpt_ports[i].device].device, i + 1);
}
}
void *
lpt_attach(void (*write_data)(uint8_t val, void *priv),
void (*write_ctrl)(uint8_t val, void *priv),
void (*strobe)(uint8_t old, uint8_t val,void *priv),
uint8_t (*read_status)(void *priv),
uint8_t (*read_ctrl)(void *priv),
void (*epp_write_data)(uint8_t is_addr, uint8_t val, void *priv),
void (*epp_request_read)(uint8_t is_addr, void *priv),
void *priv)
{
int port = device_get_instance() - 1;
lpt_devs[port].write_data = write_data;
lpt_devs[port].write_ctrl = write_ctrl;
lpt_devs[port].strobe = strobe;
lpt_devs[port].read_status = read_status;
lpt_devs[port].read_ctrl = read_ctrl;
lpt_devs[port].epp_write_data = epp_write_data;
lpt_devs[port].epp_request_read = epp_request_read;
lpt_devs[port].priv = priv;
return lpt_ports[port].lpt;
}
void
lpt_devices_close(void)
{
for (uint8_t i = 0; i < PARALLEL_MAX; i++) {
if (lpt_devs[i].close)
lpt_devs[i].close(lpt_devs[i].priv);
for (uint8_t i = 0; i < PARALLEL_MAX; i++)
memset(&(lpt_devs[i]), 0x00, sizeof(lpt_device_t));
}
}
static uint8_t
@@ -954,10 +960,10 @@ lpt_init(const device_t *info)
if (lpt_ports[next_inst].enabled || (info->local & 0xFFF00000)) {
lpt_log("Adding parallel port %i...\n", next_inst);
dev->dt = &(lpt_devs[next_inst]);
dev->dt->lpt = dev;
dev->dt = &(lpt_devs[next_inst]);
lpt_ports[next_inst].lpt = dev;
dev->fifo = NULL;
dev->fifo = NULL;
memset(&dev->fifo_out_timer, 0x00, sizeof(pc_timer_t));
lpt_port_zero(dev);
@@ -1033,7 +1039,14 @@ lpt_standalone_init(void)
{
while (next_inst < (PARALLEL_MAX - 1))
device_add_inst(&lpt_port_device, next_inst + 1);
};
}
void
lpt_ports_reset(void)
{
for (int i = 0; i < PARALLEL_MAX; i++)
lpt_ports[i].lpt = NULL;
}
const device_t lpt_port_device = {
.name = "Parallel Port",

5
src/device/pci_bridge.c
View File

@@ -28,6 +28,7 @@
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#define PCI_BRIDGE_DEC_21150 0x10110022
#define PCI_BRIDGE_DEC_21152 0x10110024
@@ -93,7 +94,7 @@ pci_bridge_get_bus_index(void *priv)
}
static void
pci_bridge_write(int func, int addr, uint8_t val, void *priv)
pci_bridge_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
pci_bridge_t *dev = (pci_bridge_t *) priv;
@@ -391,7 +392,7 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
pci_bridge_read(int func, int addr, void *priv)
pci_bridge_read(int func, int addr, UNUSED(int len), void *priv)
{
const pci_bridge_t *dev = (pci_bridge_t *) priv;
uint8_t ret;

102
src/device/vfio.c
View File

@@ -246,12 +246,12 @@ vfio_log(const char *fmt, ...)
#endif
static uint8_t vfio_bar_gettype(vfio_device_t *dev, vfio_region_t *bar);
static uint8_t vfio_config_readb(int func, int addr, void *priv);
static uint16_t vfio_config_readw(int func, int addr, void *priv);
static uint32_t vfio_config_readl(int func, int addr, void *priv);
static void vfio_config_writeb(int func, int addr, uint8_t val, void *priv);
static void vfio_config_writew(int func, int addr, uint16_t val, void *priv);
static void vfio_config_writel(int func, int addr, uint32_t val, void *priv);
static uint8_t vfio_config_readb(int func, int addr, int len, void *priv);
static uint16_t vfio_config_readw(int func, int addr, int len, void *priv);
static uint32_t vfio_config_readl(int func, int addr, int len, void *priv);
static void vfio_config_writeb(int func, int addr, int len, uint8_t val, void *priv);
static void vfio_config_writew(int func, int addr, int len, uint16_t val, void *priv);
static void vfio_config_writel(int func, int addr, int len, uint32_t val, void *priv);
static void vfio_irq_intx_setpin(vfio_device_t *dev);
static void vfio_irq_msi_disable(vfio_device_t *dev);
static void vfio_irq_msix_disable(vfio_device_t *dev);
@@ -371,7 +371,7 @@ vfio_quirk_configmirror_readb(uint32_t addr, void *priv)
vfio_mem_readb_fd(addr, bar);
/* Read configuration register. */
uint8_t ret = vfio_config_readb(0, addr - bar->quirks.configmirror.offset, dev);
uint8_t ret = vfio_config_readb(0, addr - bar->quirks.configmirror.offset, 1, dev);
vfio_log_op("VFIO %s: Config mirror: Read %02X from index %02X\n",
dev->name, ret, addr - bar->quirks.configmirror.offset);
@@ -388,7 +388,7 @@ vfio_quirk_configmirror_readw(uint32_t addr, void *priv)
vfio_mem_readw_fd(addr, bar);
/* Read configuration register. */
uint16_t ret = vfio_config_readw(0, addr - bar->quirks.configmirror.offset, dev);
uint16_t ret = vfio_config_readw(0, addr - bar->quirks.configmirror.offset, 2, dev);
vfio_log_op("VFIO %s: Config mirror: Read %04X from index %02X\n",
dev->name, ret, addr - bar->quirks.configmirror.offset);
@@ -405,7 +405,7 @@ vfio_quirk_configmirror_readl(uint32_t addr, void *priv)
vfio_mem_readl_fd(addr, bar);
/* Read configuration register. */
uint32_t ret = vfio_config_readl(0, addr - bar->quirks.configmirror.offset, dev);
uint32_t ret = vfio_config_readl(0, addr - bar->quirks.configmirror.offset, 4, dev);
vfio_log_op("VFIO %s: Config mirror: Read %08X from index %02X\n",
dev->name, ret, addr - bar->quirks.configmirror.offset);
@@ -421,7 +421,7 @@ vfio_quirk_configmirror_writeb(uint32_t addr, uint8_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: Config mirror: Write %02X to index %02X\n",
dev->name, val, addr - bar->quirks.configmirror.offset);
vfio_config_writeb(0, addr - bar->quirks.configmirror.offset, val, dev);
vfio_config_writeb(0, addr - bar->quirks.configmirror.offset, 1, val, dev);
}
static void
@@ -433,7 +433,7 @@ vfio_quirk_configmirror_writew(uint32_t addr, uint16_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: Config mirror: Write %04X to index %02X\n",
dev->name, val, addr - bar->quirks.configmirror.offset);
vfio_config_writew(0, addr - bar->quirks.configmirror.offset, val, dev);
vfio_config_writew(0, addr - bar->quirks.configmirror.offset, 2, val, dev);
}
static void
@@ -445,7 +445,7 @@ vfio_quirk_configmirror_writel(uint32_t addr, uint32_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: Config mirror: Write %08X to index %02X\n",
dev->name, val, addr - bar->quirks.configmirror.offset);
vfio_config_writel(0, addr - bar->quirks.configmirror.offset, val, dev);
vfio_config_writel(0, addr - bar->quirks.configmirror.offset, 4, val, dev);
}
static void
@@ -541,11 +541,11 @@ vfio_quirk_configwindow_data_readb(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
uint32_t index = bar->quirks.configwindow.index;
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[0].start, dev);
ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[0].start, 1, dev);
vfio_log_op("VFIO %s: Config window: Read %02X from primary index %08X\n",
dev->name, ret, index);
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[1].start, dev);
ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[1].start, 1, dev);
vfio_log_op("VFIO %s: Config window: Read %02X from secondary index %08X\n",
dev->name, ret, index);
}
@@ -565,11 +565,11 @@ vfio_quirk_configwindow_data_readw(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
uint32_t index = bar->quirks.configwindow.index;
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[0].start, dev);
ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[0].start, 2, dev);
vfio_log_op("VFIO %s: Config window: Read %04X from primary index %08X\n",
dev->name, ret, index);
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[1].start, dev);
ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[1].start, 2, dev);
vfio_log_op("VFIO %s: Config window: Read %04X from secondary index %08X\n",
dev->name, ret, index);
}
@@ -589,11 +589,11 @@ vfio_quirk_configwindow_data_readl(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
uint32_t index = bar->quirks.configwindow.index;
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[0].start, dev);
ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[0].start, 4, dev);
vfio_log_op("VFIO %s: Config window: Read %08X from primary index %08X\n",
dev->name, ret, index);
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[1].start, dev);
ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[1].start, 4, dev);
vfio_log_op("VFIO %s: Config window: Read %08X from secondary index %08X\n",
dev->name, ret, index);
}
@@ -612,12 +612,12 @@ vfio_quirk_configwindow_data_writeb(uint16_t addr, uint8_t val, void *priv)
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
vfio_log_op("VFIO %s: Config window: Write %02X to primary index %08X\n",
dev->name, val, index);
vfio_config_writeb(0, index - bar->quirks.configwindow.offset[0].start, val, dev);
vfio_config_writeb(0, index - bar->quirks.configwindow.offset[0].start, 1, val, dev);
return;
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
vfio_log_op("VFIO %s: Config window: Write %02X to secondary index %08X\n",
dev->name, val, index);
vfio_config_writeb(0, index - bar->quirks.configwindow.offset[1].start, val, dev);
vfio_config_writeb(0, index - bar->quirks.configwindow.offset[1].start, 1, val, dev);
return;
}
@@ -636,12 +636,12 @@ vfio_quirk_configwindow_data_writew(uint16_t addr, uint16_t val, void *priv)
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
vfio_log_op("VFIO %s: Config window: Write %04X to primary index %08X\n",
dev->name, val, index);
vfio_config_writew(0, index - bar->quirks.configwindow.offset[0].start, val, dev);
vfio_config_writew(0, index - bar->quirks.configwindow.offset[0].start, 2, val, dev);
return;
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
vfio_log_op("VFIO %s: Config window: Write %04X to secondary index %08X\n",
dev->name, val, index);
vfio_config_writew(0, index - bar->quirks.configwindow.offset[1].start, val, dev);
vfio_config_writew(0, index - bar->quirks.configwindow.offset[1].start, 2, val, dev);
return;
}
@@ -660,12 +660,12 @@ vfio_quirk_configwindow_data_writel(uint16_t addr, uint32_t val, void *priv)
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
vfio_log_op("VFIO %s: Config window: Write %08X to primary index %08X\n",
dev->name, val, index);
vfio_config_writel(0, index - bar->quirks.configwindow.offset[0].start, val, dev);
vfio_config_writel(0, index - bar->quirks.configwindow.offset[0].start, 4, val, dev);
return;
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
vfio_log_op("VFIO %s: Config window: Write %08X to secondary index %08X\n",
dev->name, val, index);
vfio_config_writel(0, index - bar->quirks.configwindow.offset[1].start, val, dev);
vfio_config_writel(0, index - bar->quirks.configwindow.offset[1].start, 4, val, dev);
return;
}
@@ -1037,7 +1037,7 @@ vfio_quirk_nvidia3d0_data_readb(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
if ((prev_state == NVIDIA_3D0_READ) && (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000))) {
ret = vfio_config_readb(0, dev->quirks.nvidia3d0.index, dev);
ret = vfio_config_readb(0, dev->quirks.nvidia3d0.index, 1, dev);
vfio_log_op("VFIO %s: NVIDIA 3D0: Read %02X from index %08X\n", dev->name,
ret, dev->quirks.nvidia3d0.index);
}
@@ -1057,7 +1057,7 @@ vfio_quirk_nvidia3d0_data_readw(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
if ((prev_state == NVIDIA_3D0_READ) && (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000))) {
ret = vfio_config_readw(0, dev->quirks.nvidia3d0.index, dev);
ret = vfio_config_readw(0, dev->quirks.nvidia3d0.index, 2, dev);
vfio_log_op("VFIO %s: NVIDIA 3D0: Read %04X from index %08X\n", dev->name,
ret, dev->quirks.nvidia3d0.index);
}
@@ -1077,7 +1077,7 @@ vfio_quirk_nvidia3d0_data_readl(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
if ((prev_state == NVIDIA_3D0_READ) && (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000))) {
ret = vfio_config_readl(0, dev->quirks.nvidia3d0.index, dev);
ret = vfio_config_readl(0, dev->quirks.nvidia3d0.index, 4, dev);
vfio_log_op("VFIO %s: NVIDIA 3D0: Read %08X from index %08X\n", dev->name,
ret, dev->quirks.nvidia3d0.index);
}
@@ -1104,7 +1104,7 @@ vfio_quirk_nvidia3d0_data_writeb(uint16_t addr, uint8_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: NVIDIA 3D0: Write %02X to index %08X\n", dev->name,
val, dev->quirks.nvidia3d0.index);
vfio_config_writeb(0, dev->quirks.nvidia3d0.index, val, dev);
vfio_config_writeb(0, dev->quirks.nvidia3d0.index, val, 1, dev);
return;
}
}
@@ -1131,7 +1131,7 @@ vfio_quirk_nvidia3d0_data_writew(uint16_t addr, uint16_t val, void *priv)
if (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000)) {
vfio_log_op("VFIO %s: NVIDIA 3D0: Write %04X to index %08X\n", dev->name,
val, dev->quirks.nvidia3d0.index);
vfio_config_writew(0, dev->quirks.nvidia3d0.index, val, dev);
vfio_config_writew(0, dev->quirks.nvidia3d0.index, val, 2, dev);
return;
}
}
@@ -1159,7 +1159,7 @@ vfio_quirk_nvidia3d0_data_writel(uint16_t addr, uint32_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: NVIDIA 3D0: Write %08X to index %08X\n", dev->name,
val, dev->quirks.nvidia3d0.index);
vfio_config_writel(0, dev->quirks.nvidia3d0.index, val, dev);
vfio_config_writel(0, dev->quirks.nvidia3d0.index, val, 4, dev);
return;
}
}
@@ -1198,7 +1198,7 @@ vfio_quirk_remap(vfio_device_t *dev, vfio_region_t *bar, uint8_t enable)
/* BAR 2 configuration space mirror, and BAR 1/4 configuration space window. */
if (j && !i) {
/* QEMU only enables the mirror here if BAR 2 is 64-bit capable. */
if ((bar->bar_id == 2) && ((vfio_config_readb(0, 0x18, dev) & 0x07) == 0x04))
if ((bar->bar_id == 2) && ((vfio_config_readb(0, 0x18, 1, dev) & 0x07) == 0x04))
vfio_quirk_configmirror(dev, bar, 0x4000, 0, enable);
else if (bar->bar_id == 4)
vfio_quirk_configwindow(dev, bar, 0x00, 4, 0x04, 4, 0x4000, 0x4000, enable);
@@ -1479,7 +1479,7 @@ ceilpow2(uint32_t size)
}
static uint8_t
vfio_config_readb(int func, int addr, void *priv)
vfio_config_readb(int func, int addr, UNUSED(int len), void *priv)
{
vfio_device_t *dev = (vfio_device_t *) priv;
if (func)
@@ -1602,19 +1602,19 @@ end:
}
static uint16_t
vfio_config_readw(int func, int addr, void *priv)
vfio_config_readw(int func, int addr, UNUSED(int len), void *priv)
{
return vfio_config_readb(func, addr, priv) | (vfio_config_readb(func, addr + 1, priv) << 8);
return vfio_config_readb(func, addr, 2, priv) | (vfio_config_readb(func, addr + 1, 2, priv) << 8);
}
static uint32_t
vfio_config_readl(int func, int addr, void *priv)
vfio_config_readl(int func, int addr, UNUSED(int len), void *priv)
{
return vfio_config_readb(func, addr, priv) | (vfio_config_readb(func, addr + 1, priv) << 8) | (vfio_config_readb(func, addr + 2, priv) << 16) | (vfio_config_readb(func, addr + 3, priv) << 24);
return vfio_config_readb(func, addr, 4, priv) | (vfio_config_readb(func, addr + 1, 4, priv) << 8) | (vfio_config_readb(func, addr + 2, 4, priv) << 16) | (vfio_config_readb(func, addr + 3, 4, priv) << 24);
}
static void
vfio_config_writeb(int func, int addr, uint8_t val, void *priv)
vfio_config_writeb(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
vfio_device_t *dev = (vfio_device_t *) priv;
if (func)
@@ -1850,19 +1850,19 @@ end:
}
static void
vfio_config_writew(int func, int addr, uint16_t val, void *priv)
vfio_config_writew(int func, int addr, UNUSED(int len), uint16_t val, void *priv)
{
vfio_config_writeb(func, addr, val, priv);
vfio_config_writeb(func, addr | 1, val >> 8, priv);
vfio_config_writeb(func, addr, 2, val, priv);
vfio_config_writeb(func, addr | 1, 2, val >> 8, priv);
}
static void
vfio_config_writel(int func, int addr, uint32_t val, void *priv)
vfio_config_writel(int func, int addr, UNUSED(int len), uint32_t val, void *priv)
{
vfio_config_writeb(func, addr, val, priv);
vfio_config_writeb(func, addr | 1, val >> 8, priv);
vfio_config_writeb(func, addr | 2, val >> 16, priv);
vfio_config_writeb(func, addr | 3, val >> 24, priv);
vfio_config_writeb(func, addr, 4, val, priv);
vfio_config_writeb(func, addr | 1, 4, val >> 8, priv);
vfio_config_writeb(func, addr | 2, 4, val >> 16, priv);
vfio_config_writeb(func, addr | 3, 4, val >> 24, priv);
}
static void
@@ -2549,13 +2549,13 @@ vfio_dev_prereset(vfio_device_t *dev)
/* Extra steps for devices with power management capability. */
if (dev->pm_cap) {
/* Make sure the device is in D0 state. */
uint8_t pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, dev),
uint8_t pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, 1, dev),
state = pm_ctrl & 0x03;
if (state) {
pm_ctrl &= ~0x03;
vfio_config_writeb(0, dev->pm_cap + 4, pm_ctrl, dev);
vfio_config_writeb(0, dev->pm_cap + 4, pm_ctrl, 1, dev);
pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, dev);
pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, 1, dev);
state = pm_ctrl & 0x03;
if (state)
vfio_log("VFIO %s: Device stuck in D%d state\n", dev->name, state);
@@ -2566,10 +2566,10 @@ vfio_dev_prereset(vfio_device_t *dev)
}
/* Enable function-level reset if supported. */
dev->can_flr_reset = (dev->pcie_cap && (vfio_config_readb(0, dev->pcie_cap + 7, dev) & 0x10)) || (dev->af_cap && (vfio_config_readb(0, dev->af_cap + 3, dev) & 0x02));
dev->can_flr_reset = (dev->pcie_cap && (vfio_config_readb(0, dev->pcie_cap + 7, 1, dev) & 0x10)) || (dev->af_cap && (vfio_config_readb(0, dev->af_cap + 3, 1, dev) & 0x02));
/* Disable bus master, BARs, expansion ROM and VGA regions; also enable INTx. */
vfio_config_writew(0, 0x04, vfio_config_readw(0, 0x04, dev) & ~0x0407, dev);
vfio_config_writew(0, 0x04, 2, vfio_config_readw(0, 0x04, 2, dev) & ~0x0407, dev);
}
static void
@@ -2664,7 +2664,7 @@ vfio_dev_init(vfio_device_t *dev)
vfio_region_init(dev, &reg, &dev->vga_mem); /* memory [A0000:BFFFF] */
/* Inform that a PCI VGA video card is attached if no video card is emulated. */
if (gfxcard == VID_NONE)
if (gfxcard[0] == VID_NONE)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_default);
break;

30
src/disk/hdc_ide.c
View File

@@ -1603,10 +1603,12 @@ ide_writeb(uint16_t addr, uint8_t val, void *priv)
int ch;
int bad = 0;
int reset = 0;
int prev;
ch = dev->cur_dev;
ide = ide_drives[ch];
ide_other = ide_drives[ch ^ 1];
prev = ide->command;
ide_log("[%04X:%08X] ide_writeb(%04X, %02X, %08X)\n", CS, cpu_state.pc, addr, val, priv);
@@ -1649,37 +1651,31 @@ ide_writeb(uint16_t addr, uint8_t val, void *priv)
break;
case 0x4: /* Cylinder low */
if (ide->type & IDE_SHADOW)
break;
if (!(ide->tf->atastat & (BSY_STAT | DRQ_STAT))) {
if (!(ide->type & IDE_SHADOW) && !(ide->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide->tf->cylinder = (ide->tf->cylinder & 0xff00) | val;
ide->lba_addr = (ide->lba_addr & 0xfff00ff) | (val << 8);
}
if (!(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT))) {
if (!(ide_other->type & IDE_SHADOW) && !(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide_other->tf->cylinder = (ide_other->tf->cylinder & 0xff00) | val;
ide_other->lba_addr = (ide_other->lba_addr & 0xfff00ff) | (val << 8);
}
break;
case 0x5: /* Cylinder high */
if (ide->type & IDE_SHADOW)
break;
if (!(ide->tf->atastat & (BSY_STAT | DRQ_STAT))) {
if (!(ide->type & IDE_SHADOW) && !(ide->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide->tf->cylinder = (ide->tf->cylinder & 0xff) | (val << 8);
ide->lba_addr = (ide->lba_addr & 0xf00ffff) | (val << 16);
}
if (!(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT))) {
if (!(ide_other->type & IDE_SHADOW) && !(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide_other->tf->cylinder = (ide_other->tf->cylinder & 0xff) | (val << 8);
ide_other->lba_addr = (ide_other->lba_addr & 0xf00ffff) | (val << 16);
}
break;
case 0x6: /* Drive/Head */
if (ch != ((val >> 4) & 1) + (ide->board << 1)) {
if (ch != (((val >> 4) & 1) + (ide->board << 1))) {
if (!ide->reset && !ide_other->reset && ide->irqstat) {
ide_irq_lower(ide);
ide->irqstat = 1;
@@ -1721,7 +1717,8 @@ ide_writeb(uint16_t addr, uint8_t val, void *priv)
case 0x7: /* Command register */
if ((ide->tf->atastat & (BSY_STAT | DRQ_STAT)) &&
((val != WIN_SRST) || (ide->type != IDE_ATAPI)))
((val != WIN_SRST) || (ide->type != IDE_ATAPI)) &&
((val != WIN_VERIFY) || (prev != WIN_IDENTIFY)))
break;
if ((ide->type == IDE_NONE) || ((ide->type & IDE_SHADOW) && (val != WIN_DRIVE_DIAGNOSTICS)))
@@ -1786,7 +1783,13 @@ ide_writeb(uint16_t addr, uint8_t val, void *priv)
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus_type, 1);
uint32_t sec_count;
double wait_time;
if ((val == WIN_READ_DMA) || (val == WIN_READ_DMA_ALT)) {
if ((val == WIN_READ) && (prev == WIN_SETIDLE1)) {
/* Do the callback instantly - this happens on the Intel Monsoon. */
(void) hdd_timing_read(&hdd[ide->hdd_num], ide_get_sector(ide), 1);
ide->do_initial_read = 1;
ide_callback(ide);
break;
} else if ((val == WIN_READ_DMA) || (val == WIN_READ_DMA_ALT)) {
/* TODO: Make DMA timing more accurate. */
sec_count = ide->tf->secount ? ide->tf->secount : 256;
double seek_time = hdd_timing_read(&hdd[ide->hdd_num],
@@ -2346,6 +2349,7 @@ ide_callback(void *priv)
case WIN_READ:
case WIN_READ_NORETRY:
ide_log("IDE(%d) read(%d,%d,%d)\n", ide->channel, ide->tf->cylinder, ide->tf->head, ide->tf->sector);
if (ide->type == IDE_ATAPI) {
ide_set_signature(ide);
err = ABRT_ERR;

5
src/disk/hdc_ide_cmd640.c
View File

@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -289,7 +290,7 @@ cmd640_vlb_readl(uint16_t addr, void *priv)
}
static void
cmd640_pci_write(int func, int addr, uint8_t val, void *priv)
cmd640_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
@@ -367,7 +368,7 @@ cmd640_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
cmd640_pci_read(int func, int addr, void *priv)
cmd640_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
uint8_t ret = 0xff;

5
src/disk/hdc_ide_cmd646.c
View File

@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -296,7 +297,7 @@ cmd646_bios_handler(cmd646_t *dev)
}
static void
cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
cmd646_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
int reg50 = dev->regs[0x50];
@@ -481,7 +482,7 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
cmd646_pci_read(int func, int addr, void *priv)
cmd646_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
uint8_t ret = 0xff;

5
src/disk/hdc_ide_rz1000.c
View File

@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -108,7 +109,7 @@ rz1000_ide_handlers(rz1000_t *dev)
}
static void
rz1000_pci_write(int func, int addr, uint8_t val, void *priv)
rz1000_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
rz1000_t *dev = (rz1000_t *) priv;
@@ -138,7 +139,7 @@ rz1000_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
rz1000_pci_read(int func, int addr, void *priv)
rz1000_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
rz1000_t *dev = (rz1000_t *) priv;
uint8_t ret = 0xff;

5
src/disk/hdc_ide_w83769f.c
View File

@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -233,7 +234,7 @@ w83769f_vlb_readl(uint16_t addr, void *priv)
}
static void
w83769f_pci_write(int func, int addr, uint8_t val, void *priv)
w83769f_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
@@ -252,7 +253,7 @@ w83769f_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
w83769f_pci_read(int func, int addr, void *priv)
w83769f_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
uint8_t ret = 0xff;

3
src/include/86box/chipset.h
View File

@@ -105,6 +105,9 @@ extern const device_t i450kx_device;
extern const device_t sio_device;
extern const device_t sio_zb_device;
#define PIIX4_NVR_AMI_1995 0x0000000100000000
#define PIIX4_NVR_AMI_1995J 0x0000000200000000
extern const device_t piix_device;
extern const device_t piix_no_mirq_device;
extern const device_t piix_old_device;

58
src/include/86box/lpt.h
View File

@@ -18,11 +18,6 @@
#endif
typedef struct lpt_device_s {
const char *name;
const char *internal_name;
void *(*init)(void *lpt);
void (*close)(void *priv);
void (*write_data)(uint8_t val, void *priv);
void (*write_ctrl)(uint8_t val, void *priv);
void (*strobe)(uint8_t old, uint8_t val,void *priv);
@@ -31,13 +26,7 @@ typedef struct lpt_device_s {
void (*epp_write_data)(uint8_t is_addr, uint8_t val, void *priv);
void (*epp_request_read)(uint8_t is_addr, void *priv);
void *priv;
struct lpt_t *lpt;
//#ifdef EMU_DEVICE_H
// struct device_t *cfgdevice;
//#else
void *cfgdevice;
//#endif
void * priv;
} lpt_device_t;
#ifdef _TIMER_H_
@@ -86,6 +75,8 @@ typedef struct lpt_port_s {
uint8_t enabled;
int device;
lpt_t *lpt;
} lpt_port_t;
extern lpt_port_t lpt_ports[PARALLEL_MAX];
@@ -96,6 +87,22 @@ typedef enum {
LPT_STATE_WRITE_FIFO
} lpt_state_t;
extern const device_t lpt_dac_device;
extern const device_t lpt_dac_stereo_device;
extern const device_t dss_device;
extern const device_t lpt_hasp_savquest_device;
extern int lpt_device_available(int id);
#ifdef EMU_DEVICE_H
extern const device_t *lpt_device_getdevice(const int id);
#endif
extern int lpt_device_has_config(const int id);
extern const char *lpt_device_get_name(int id);
extern const char *lpt_device_get_internal_name(int id);
extern int lpt_device_get_from_internal_name(const char *str);
extern void lpt_write(uint16_t port, uint8_t val, void *priv);
extern void lpt_write_to_fifo(void *priv, uint8_t val);
@@ -109,24 +116,6 @@ extern uint8_t lpt_read_ecp_mode(lpt_t *dev);
extern void lpt_irq(void *priv, int raise);
extern int lpt_device_get_from_internal_name(const char *str);
extern const char *lpt_device_get_name(int id);
extern const char *lpt_device_get_internal_name(int id);
#ifdef EMU_DEVICE_H
extern const device_t *lpt_device_getdevice(const int id);
#endif
extern int lpt_device_has_config(const int id);
extern const lpt_device_t lpt_dac_device;
extern const lpt_device_t lpt_dac_stereo_device;
extern const lpt_device_t dss_device;
extern const lpt_device_t lpt_hasp_savquest_device;
extern void lpt_set_ext(lpt_t *dev, uint8_t ext);
extern void lpt_set_ecp(lpt_t *dev, uint8_t ecp);
extern void lpt_set_epp(lpt_t *dev, uint8_t epp);
@@ -143,12 +132,21 @@ extern void lpt_port_remove(lpt_t *dev);
extern void lpt1_remove_ams(lpt_t *dev);
extern void lpt_devices_init(void);
extern void * lpt_attach(void (*write_data)(uint8_t val, void *priv),
void (*write_ctrl)(uint8_t val, void *priv),
void (*strobe)(uint8_t old, uint8_t val,void *priv),
uint8_t (*read_status)(void *priv),
uint8_t (*read_ctrl)(void *priv),
void (*epp_write_data)(uint8_t is_addr, uint8_t val, void *priv),
void (*epp_request_read)(uint8_t is_addr, void *priv),
void *priv);
extern void lpt_devices_close(void);
extern void lpt_set_next_inst(int ni);
extern void lpt_set_3bc_used(int is_3bc_used);
extern void lpt_standalone_init(void);
extern void lpt_ports_reset(void);
extern const device_t lpt_port_device;

10
src/include/86box/machine.h
View File

@@ -1097,6 +1097,10 @@ extern const device_t an430tx_device;
extern int machine_at_an430tx_init(const machine_t *);
extern int machine_at_ym430tx_init(const machine_t *);
extern int machine_at_thunderbolt_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t ms5156_device;
#endif
extern int machine_at_ms5156_init(const machine_t *);
extern int machine_at_ma23c_init(const machine_t *);
extern int machine_at_mb540n_init(const machine_t *);
extern int machine_at_56a5_init(const machine_t *);
@@ -1404,6 +1408,9 @@ extern const device_t tandy_1000sl_video_device;
extern int machine_tandy1000sl2_init(const machine_t *);
/* m_v86p.c */
#ifdef EMU_DEVICE_H
extern const device_t v86p_device;
#endif
extern int machine_v86p_init(const machine_t *);
/* m_xt.c */
@@ -1475,6 +1482,9 @@ extern int machine_xt_to16_init(const machine_t *);
extern const device_t vendex_device;
#endif
extern int machine_xt_vendex_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t laserxt_device;
#endif
extern int machine_xt_laserxt_init(const machine_t *);
extern int machine_xt_znic_init(const machine_t *);
extern int machine_xt_z151_init(const machine_t *);

6
src/include/86box/network.h
View File

@@ -244,10 +244,8 @@ extern const device_t pcnet_am79c973_onboard_device;
extern const device_t modem_device;
/* PLIP */
#ifdef EMU_LPT_H
extern const lpt_device_t lpt_plip_device;
#endif
extern const device_t plip_device;
extern const device_t lpt_plip_device;
extern const device_t plip_device;
/* Realtek RTL8139C+ */
extern const device_t rtl8139c_plus_device;

79
src/include/86box/nmc93cxx.h
View File

@@ -1,25 +1,72 @@
#include <86box/vid_ati_eeprom.h>
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Header of the emulation of the National Semiconductors NMC93Cxx EEPROMs
* (16 bits or 8 bits).
*
* Authors: Cacodemon345
*
* Copyright 2023 Cacodemon345
*/
#pragma once
typedef struct nmc93cxx_eeprom_t {
ati_eeprom_t dev;
uint8_t addrbits;
uint16_t size;
char filename[1024];
} nmc93cxx_eeprom_t;
/* Forward declaration to hide internal device state from users. */
typedef struct nmc93cxx_eeprom_t nmc93cxx_eeprom_t;
/* EEPROM device type used to specify the size of data array. */
typedef enum nmc93cxx_eeprom_type {
/*
* Standard 93CX6 class of 16-bit EEPROMs.
*
* Type / Bits per cell / Number of cells
*/
NMC_93C06_x16_16,
NMC_93C46_x16_64,
NMC_93C56_x16_128,
NMC_93C57_x16_128,
NMC_93C66_x16_256,
NMC_93C76_x16_512,
NMC_93C86_x16_1024,
/*
* Some manufacturers use pin 6 as an "ORG" pin which,
* when pulled low, configures memory for 8-bit accesses.
*
* Type / Bits per cell / Number of cells
*/
NMC_93C46_x8_128,
NMC_93C56_x8_256,
NMC_93C57_x8_256,
NMC_93C66_x8_512,
NMC_93C76_x8_1024,
NMC_93C86_x8_2048,
} nmc93cxx_eeprom_type;
/* EEPROM device parameters. */
typedef struct nmc93cxx_eeprom_params_t {
uint16_t nwords;
char *filename;
uint16_t *default_content;
/* Device type */
nmc93cxx_eeprom_type type;
/* Name of EEPROM image file */
const char *filename;
/*
* Optional pointer to the default data buffer.
* The buffer size should match the size of EEPROM data array specified by nmc93cxx_eeprom_type.
*/
const void *default_content;
} nmc93cxx_eeprom_params_t;
/* Read from the EEPROM. */
uint16_t nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *eeprom);
/* Read the state of the data output (DO) line. */
bool nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *dev);
/* Write to the EEPROM. */
void nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *eeprom, int eecs, int eesk, int eedi);
/* Set the state of the input lines. */
void nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *dev, bool eecs, bool eesk, bool eedi);
/* Get EEPROM data array. */
uint16_t *nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *eeprom);
/* Returns pointer to the current EEPROM data array. */
const uint16_t *nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *dev);
extern const device_t nmc93cxx_device;

1
src/include/86box/nvr.h
View File

@@ -96,6 +96,7 @@ extern const device_t ami_1994_nvr_device;
extern const device_t ami_1995_nvr_device;
extern const device_t via_nvr_device;
extern const device_t piix4_ami_1995_nvr_device;
extern const device_t piix4_ami_1995j_nvr_device;
extern const device_t p6rp4_nvr_device;
extern const device_t martin_nvr_device;
extern const device_t elt_nvr_device;

8
src/include/86box/pci.h
View File

@@ -266,12 +266,12 @@ extern void pci_remap_bus(uint8_t bus_index, uint8_t bus_number);
extern void pci_register_bus_slot(int bus, int card, int type, int inta, int intb, int intc, int intd);
/* Add a PCI card. */
extern void pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot);
extern void pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, int len, void *priv),
void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot);
/* Add an instance of the PCI bridge. */
extern void pci_add_bridge(uint8_t agp, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv,
extern void pci_add_bridge(uint8_t agp, uint8_t (*read)(int func, int addr, int len, void *priv),
void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv,
uint8_t *slot);
/* Register the cards that have been added into slots. */

14
src/include/86box/prt_devs.h
View File

@@ -1,15 +1,9 @@
#ifndef EMU_PRT_DEVS_H
#define EMU_PRT_DEVS_H
extern const lpt_device_t lpt_prt_text_device;
extern const device_t prt_text_device;
extern const lpt_device_t lpt_prt_escp_device;
extern const device_t prt_escp_device;
extern const lpt_device_t lpt_prt_ps_device;
extern const device_t prt_ps_device;
#ifdef USE_PCL
extern const lpt_device_t lpt_prt_pcl_device;
extern const device_t prt_pcl_device;
#endif
extern const device_t lpt_prt_text_device;
extern const device_t lpt_prt_escp_device;
extern const device_t lpt_prt_ps_device;
extern const device_t lpt_prt_pcl_device;
#endif /*EMU_PRT_DEVS_H*/

3
src/include/86box/vid_8514a.h
View File

@@ -164,8 +164,11 @@ typedef struct ibm8514_t {
int y_count;
int input;
int input2;
int input3;
int output;
int output2;
int output3;
int init_cx;
int ssv_len;
int ssv_len_back;

17
src/machine/m_at_slot1.c
View File

@@ -1431,20 +1431,20 @@ static const device_config_t vei8_config[] = {
.name = "bios",
.description = "BIOS Version",
.type = CONFIG_BIOS,
.default_string = "vei8",
.default_string = "6110zu",
.default_int = 0,
.file_filter = NULL,
.spinner = { 0 },
.selection = { { 0 } },
.bios = {
{
.name = "Award Modular BIOS v6.00PG - Revision QHW.10.01 (HP Sherwood-B)",
.internal_name = "vei8",
.name = "Award Modular BIOS v6.00PG - Revision 61100003 (beta)",
.internal_name = "6110zu0003",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 262144,
.files = { "roms/machines/vei8/QHW1001.BIN", "" }
.files = { "roms/machines/vei8/61100003.BIN", "" }
},
{
.name = "Award Modular BIOS v6.00PG - Revision R804",
@@ -1455,6 +1455,15 @@ static const device_config_t vei8_config[] = {
.size = 262144,
.files = { "roms/machines/vei8/r804.bin", "" }
},
{
.name = "Award Modular BIOS v6.00PG - Revision QHW.10.01 (HP Sherwood-B)",
.internal_name = "vei8",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 262144,
.files = { "roms/machines/vei8/QHW1001.BIN", "" }
},
{ .files_no = 0 }
}
},

27
src/machine/m_at_socket370.c
View File

@@ -493,24 +493,6 @@ static const device_config_t ms6318_config[] = {
.size = 262144,
.files = { "roms/machines/ms6318/w6318vms.120", "" }
},
{
.name = "Award Modular BIOS v6.00PG - Revision 7.1B5E (Elonex OEM)",
.internal_name = "ms6318_715",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 262144,
.files = { "roms/machines/ms6318/w6318ve1.715", "" }
},
{
.name = "Award Modular BIOS v6.00PG - Revision 1.0B9 (Fujitsu-Siemens OEM)",
.internal_name = "ms6318_109",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 262144,
.files = { "roms/machines/ms6318/ms-6318-ver5.bin", "" }
},
{
.name = "Award Modular BIOS v6.00PG - Revision 1.8 (HP Pavilion A7xx)",
.internal_name = "ms6318_180",
@@ -547,15 +529,6 @@ static const device_config_t ms6318_config[] = {
.size = 262144,
.files = { "roms/machines/ms6318/ms6318.bin", "" }
},
{
.name = "Award Modular BIOS v6.00PG - Revision 7.51 (Medion MD6318)",
.internal_name = "ms6318_751",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 262144,
.files = { "roms/machines/ms6318/bios.rom", "" }
},
{ .files_no = 0 }
}
},

125
src/machine/m_at_socket7.c
View File

@@ -1548,6 +1548,131 @@ machine_at_thunderbolt_init(const machine_t *model)
return ret;
}
static const device_config_t ms5156_config[] = {
// clang-format off
{
.name = "bios",
.description = "BIOS Version",
.type = CONFIG_BIOS,
.default_string = "ms5156w",
.default_int = 0,
.file_filter = NULL,
.spinner = { 0 },
.selection = { { 0 } },
.bios = {
{
.name = "AMIBIOS 6 (071595) - Revision 1.0",
.internal_name = "ms5156a",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 131072,
.files = { "roms/machines/ms5156/A556MS10.ROM", "" }
},
{
.name = "AMIBIOS 6 (071595) - Revision 1.0 (Japanese)",
.internal_name = "ms5156aj",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 131072,
.files = { "roms/machines/ms5156/A556J110.ROM", "" }
},
{
.name = "AMIBIOS 6 (071595) - Revision 1.0 (Traditional Chinese)",
.internal_name = "ms5156atc",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 131072,
.files = { "roms/machines/ms5156/A556C410.ROM", "" }
},
{
.name = "AMIBIOS 6 (071595) - Revision 1.3 (Simplified Chinese)",
.internal_name = "ms5156asc",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 131072,
.files = { "roms/machines/ms5156/A556C313.ROM", "" }
},
{
.name = "Award Modular BIOS v4.51PG - Revision 1.5",
.internal_name = "ms5156w",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 131072,
.files = { "roms/machines/ms5156/W556MS15.BIN", "" }
},
{
.name = "Award Modular BIOS v4.51PG - Revision 1.6B1 (ACPI Beta)",
.internal_name = "ms5156wab",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 131072,
.files = { "roms/machines/ms5156/W556MS16.001", "" }
},
{ .files_no = 0 }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t ms5156_device = {
.name = "MSI MS-5156",
.internal_name = "ms5156",
.flags = 0,
.local = 0,
.init = NULL,
.close = NULL,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = ms5156_config
};
int
machine_at_ms5156_init(const machine_t *model)
{
int ret;
const char *fn;
device_context(model->device);
int is_english = !strcmp(device_get_config_bios("bios"), "ms5156a");
int is_award = !strcmp(device_get_config_bios("bios"), "ms5156w") || !strcmp(device_get_config_bios("bios"), "ms5156wab");
fn = device_get_bios_file(machine_get_device(machine), device_get_config_bios("bios"), 0);
ret = bios_load_linear(fn, 0x000e0000, 131072, 0);
device_context_restore();
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4); /* PIIX4 */
device_add(&i430tx_device);
if (is_award)
device_add(&piix4_device);
else if (is_english)
device_add_params(&piix4_device, (void *) PIIX4_NVR_AMI_1995);
else
device_add_params(&piix4_device, (void *) PIIX4_NVR_AMI_1995J);
device_add_params(&w83977_device, (void *) (W83977TF | W83977_AMI | W83977_NO_NVR));
device_add(&sst_flash_29ee010_device); /* assumed */
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
int
machine_at_ma23c_init(const machine_t *model)
{

104
src/machine/m_v86p.c
View File

@@ -48,35 +48,101 @@
#include <86box/sio.h>
#include <86box/video.h>
static const device_config_t v86p_config[] = {
// clang-format off
{
.name = "bios",
.description = "BIOS Version",
.type = CONFIG_BIOS,
.default_string = "v86p_122089",
.default_int = 0,
.file_filter = NULL,
.spinner = { 0 },
.selection = { { 0 } },
.bios = {
{
.name = "12/20/89",
.internal_name = "v86p_122089",
.bios_type = BIOS_NORMAL,
.files_no = 2,
.local = 0,
.size = 65536,
.files = { "roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_122089_Even.rom",
"roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_122089_Odd.rom",
"" }
},
{
.name = "09/04/89",
.internal_name = "v86p_090489",
.bios_type = BIOS_NORMAL,
.files_no = 2,
.local = 0,
.size = 65536,
.files = { "roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_090489_Even.rom",
"roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_090489_Odd.rom",
"" }
},
{
.name = "09/04/89 (Alt)",
.internal_name = "v86p_jvernet",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 1,
.size = 65536,
.files = { "roms/machines/v86p/V86P.ROM",
"" }
},
{ .files_no = 0 }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t v86p_device = {
.name = "Victor V86P",
.internal_name = "v86p_device",
.flags = 0,
.local = 0,
.init = NULL,
.close = NULL,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = v86p_config
};
int
machine_v86p_init(const machine_t *model)
{
int ret;
int rom_id = 0;
int ret = 0;
int files_no = 0;
int local = 0;
const char *fn1, *fn2;
ret = bios_load_interleavedr("roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_122089_Even.rom",
"roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_122089_Odd.rom",
0x000f8000, 65536, 0);
/* No ROMs available. */
if (!device_available(model->device))
return ret;
if (!ret) {
/* Try an older version of the BIOS. */
rom_id = 1;
ret = bios_load_interleavedr("roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_090489_Even.rom",
"roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_090489_Odd.rom",
0x000f8000, 65536, 0);
}
if (!ret) {
/* Try JVERNET's BIOS. */
rom_id = 2;
ret = bios_load_linear("roms/machines/v86p/V86P.ROM",
0x000f0000, 65536, 0);
device_context(model->device);
files_no = device_get_bios_num_files(model->device, device_get_config_bios("bios"));
local = device_get_bios_local(model->device, device_get_config_bios("bios"));
fn1 = device_get_bios_file(model->device, device_get_config_bios("bios"), 0);
if (files_no > 1)
{
fn2 = device_get_bios_file(model->device, device_get_config_bios("bios"), 1);
ret = bios_load_interleavedr(fn1, fn2, 0x000f8000, 65536, 0);
}
else
ret = bios_load_linear(fn1, 0x000f0000, 65536, 0);
device_context_restore();
if (bios_only || !ret)
return ret;
if (rom_id == 2)
if (local > 0)
video_load_font("roms/machines/v86p/V86P.FON", FONT_FORMAT_PC1512_T1000, LOAD_FONT_NO_OFFSET);
else
video_load_font("roms/machines/v86p/v86pfont.rom", FONT_FORMAT_PC1512_T1000, LOAD_FONT_NO_OFFSET);

13
src/machine/m_xt.c
View File

@@ -1884,10 +1884,17 @@ machine_xt_laserxt_common_init(const machine_t *model, int is_lxt3)
int
machine_xt_laserxt_init(const machine_t *model)
{
int ret;
int ret = 0;
const char *fn;
ret = bios_load_linear("roms/machines/ltxt/27c64.bin",
0x000fe000, 8192, 0);
/* No ROMs available. */
if (!device_available(model->device))
return ret;
device_context(model->device);
fn = device_get_bios_file(model->device, device_get_config_bios("bios"), 0);
ret = bios_load_linear(fn, 0x000fe000, 8192, 0);
device_context_restore();
if (bios_only || !ret)
return ret;

139
src/machine/machine_table.c
View File

@@ -2982,7 +2982,7 @@ const machine_t machines[] = {
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.device = &v86p_device,
.kbd_device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
@@ -15904,51 +15904,6 @@ const machine_t machines[] = {
.snd_device = NULL,
.net_device = NULL
},
/* Has a National Semiconductor PC87307 Super I/O with on-chip KBC, which has one of these
firmwares: AMI '5' MegaKey, Phoenix MultiKey/42 1.37, or Phoenix MultiKey/42i 4.16. */
{
.name = "[i430TX] ASUS TX97-XV (HP OEM)",
.internal_name = "tx97xv",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_tx97xv_init,
.p1_handler = machine_generic_p1_handler,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 75000000,
.min_voltage = 2100,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB | MACHINE_VIDEO,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.jumpered_ecp_dma = 0,
.default_jumpered_ecp_dma = -1,
.kbc_device = &kbc_at_device,
.kbc_params = KBC_VEN_AMI | 0x00004600,
.kbc_p1 = 0x00000cf0,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.kbd_device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &mach64vt3_onboard_device,
.snd_device = NULL,
.net_device = NULL
},
/* This has the AMIKey KBC firmware, which is type 'F' (YM430TX is based on the TX97). */
{
.name = "[i430TX] ASUS TX97",
@@ -16091,6 +16046,51 @@ const machine_t machines[] = {
.snd_device = &cs4236b_onboard_device,
.net_device = &pcnet_am79c973_onboard_device
},
/* Has a National Semiconductor PC87307 Super I/O with on-chip KBC, which has one of these
firmwares: AMI '5' MegaKey, Phoenix MultiKey/42 1.37, or Phoenix MultiKey/42i 4.16. */
{
.name = "[i430TX] HP Pavilion 81xx (ASUS TX97-XV)",
.internal_name = "tx97xv",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_tx97xv_init,
.p1_handler = machine_generic_p1_handler,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 75000000,
.min_voltage = 2100,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB | MACHINE_VIDEO,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.jumpered_ecp_dma = 0,
.default_jumpered_ecp_dma = -1,
.kbc_device = &kbc_at_device,
.kbc_params = KBC_VEN_AMI | 0x00004600,
.kbc_p1 = 0x00000cf0,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.kbd_device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &mach64vt3_onboard_device,
.snd_device = NULL,
.net_device = NULL
},
/* This has the Phoenix MultiKey KBC firmware on the NSC Super I/O chip. */
{
.name = "[i430TX] Intel AN430TX (Anchorage)",
@@ -16232,6 +16232,51 @@ const machine_t machines[] = {
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i430TX] MSI MS-5156",
.internal_name = "ms5156",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_ms5156_init,
.p1_handler = machine_generic_p1_handler,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 55000000,
.max_bus = 75000000,
.min_voltage = 2700,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 4096,
.max = 262144,
.step = 4096
},
.nvrmask = 255,
.jumpered_ecp_dma = 0,
.default_jumpered_ecp_dma = -1,
.kbc_device = NULL,
.kbc_params = 0x00000000,
.kbc_p1 = 0x00000cf0,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = &ms5156_device,
.kbd_device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C67x Super I/O chip with on-chip KBC with Phoenix or
AMI MEGAKEY '5' KBC firmware. */
{
@@ -18288,7 +18333,7 @@ const machine_t machines[] = {
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432, /* Manual thinks the maximum memory is 1024MB (256x4MB), but there is no 4th memory slot */
.max = 786432, /* Manual mistakenly says 1 GB with 256 MB in each slot, even though it only has three slots */
.step = 8192
},
.nvrmask = 255,

6
src/mem/catalyst_flash.c
View File

@@ -177,16 +177,16 @@ catalyst_flash_add_mappings(flash_t *dev)
mem_mapping_add(&dev->mapping, 0xe0000, 0x20000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS | MEM_MAPPING_ROM_WS, (void *) dev);
mem_mapping_add(&(dev->mapping_h[0]), 0xfffc0000, 0x20000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS | MEM_MAPPING_ROM_WS, (void *) dev);
mem_mapping_add(&(dev->mapping_h[1]), 0xfffe0000, 0x20000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS | MEM_MAPPING_ROM_WS, (void *) dev);
}
static void

6
src/mem/intel_flash.c
View File

@@ -320,16 +320,16 @@ intel_flash_add_mappings(flash_t *dev)
mem_mapping_add(&(dev->mapping[i]), base, 0x10000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS | MEM_MAPPING_ROM_WS, (void *) dev);
}
mem_mapping_add(&(dev->mapping_h[i]), (base | 0xfff00000) - sub, 0x10000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS | MEM_MAPPING_ROM_WS, (void *) dev);
mem_mapping_add(&(dev->mapping_h[i + max]), (base | 0xfff00000), 0x10000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS | MEM_MAPPING_ROM_WS, (void *) dev);
}
}

767
src/mem/nmc93cxx.c
View File

@@ -6,269 +6,676 @@
*
* This file is part of the 86Box distribution.
*
* Emulation of National Semiconductors NMC93Cxx EEPROMs.
* Emulation of National Semiconductors NMC93Cxx EEPROMs (16 bits or 8 bits).
*
* Authors: Cacodemon345
*
* Copyright 2023 Cacodemon345
*/
/* Ported over from QEMU */
/* Ported over from the MAME eepromser.cpp implementation. Copyright 2013 Aaron Giles */
#ifdef ENABLE_NMC93CXX_EEPROM_LOG
#include <stdarg.h>
#endif
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <stddef.h>
#include <wchar.h>
#include <time.h>
#define HAVE_STDARG_H
#include <assert.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/log.h>
#include <86box/nmc93cxx.h>
#include <86box/plat_unused.h>
#define WRITE_TIME_US 1750
#define WRITE_ALL_TIME_US 8000
#define ERASE_TIME_US 1000
#define ERASE_ALL_TIME_US 8000
typedef enum EepromCommand {
COMMAND_INVALID,
COMMAND_READ,
COMMAND_WRITE,
COMMAND_ERASE,
COMMAND_LOCK,
COMMAND_UNLOCK,
COMMAND_WRITEALL,
COMMAND_ERASEALL,
COMMAND_COPY_EEPROM_TO_RAM,
COMMAND_COPY_RAM_TO_EEPROM
} EepromCommand;
typedef enum EepromState {
STATE_IN_RESET,
STATE_WAIT_FOR_START_BIT,
STATE_WAIT_FOR_COMMAND,
STATE_READING_DATA,
STATE_WAIT_FOR_DATA,
STATE_WAIT_FOR_COMPLETION
} EepromState;
typedef enum EepromEvent {
EVENT_CS_RISING_EDGE = 1 << 0,
EVENT_CS_FALLING_EDGE = 1 << 1,
EVENT_CLK_RISING_EDGE = 1 << 2,
EVENT_CLK_FALLING_EDGE = 1 << 3
} EepromEvent;
struct nmc93cxx_eeprom_t {
/* Command completion timer */
pc_timer_t cmd_complete_timer;
/* Write tick */
uint32_t write_tick;
/* State of the CS line */
bool cs_state;
/* State of the CLK line */
bool clk_state;
/* State of the DI line */
bool di_state;
/* READY/BUSY status during a programming operation */
bool is_busy;
/* Internal device state */
EepromState state;
/* Accumulator of command+address bits */
uint32_t command_address_accum;
/* Current address extracted from command */
uint32_t address;
/* Holds data coming in/going out */
uint32_t shift_register;
/* Number of bits accumulated */
uint32_t bits_accum;
/* Current command */
EepromCommand command;
/* Number of memory cells */
uint16_t cells;
/* Number of bits per cell */
uint16_t data_bits;
/* Number of address bits in a command */
uint8_t command_address_bits;
/* Number of address bits in an address */
uint8_t address_bits;
/* Are we locked against writes? */
bool is_locked;
/* Tick of the last CS rising edge */
uint32_t last_cs_rising_edge_tick;
/* Device logging */
void *log;
/* Name of EEPROM image file */
char filename[1024];
/* EEPROM image words, must be the last structure member */
uint16_t array_data[];
};
#ifdef ENABLE_NMC93CXX_EEPROM_LOG
int nmc93cxx_eeprom_do_log = ENABLE_NMC93CXX_EEPROM_LOG;
static void
nmc93cxx_eeprom_log(int lvl, const char *fmt, ...)
nmc93cxx_eeprom_log(nmc93cxx_eeprom_t *dev, int lvl, const char *fmt, ...)
{
va_list ap;
if (nmc93cxx_eeprom_do_log >= lvl) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
log_out(dev->log, fmt, ap);
va_end(ap);
}
}
#define MAKE_CASE(x) case x: return #x;
static char*
nmc93cxx_eeprom_state_to_name(EepromState state)
{
switch (state) {
MAKE_CASE(STATE_IN_RESET);
MAKE_CASE(STATE_WAIT_FOR_START_BIT);
MAKE_CASE(STATE_WAIT_FOR_COMMAND);
MAKE_CASE(STATE_READING_DATA);
MAKE_CASE(STATE_WAIT_FOR_DATA);
MAKE_CASE(STATE_WAIT_FOR_COMPLETION);
default: return "<UNK>";
}
}
static char *
nmc93cxx_eeprom_cmd_to_name(EepromCommand command)
{
switch (command) {
MAKE_CASE(COMMAND_INVALID);
MAKE_CASE(COMMAND_READ);
MAKE_CASE(COMMAND_WRITE);
MAKE_CASE(COMMAND_ERASE);
MAKE_CASE(COMMAND_LOCK);
MAKE_CASE(COMMAND_UNLOCK);
MAKE_CASE(COMMAND_WRITEALL);
MAKE_CASE(COMMAND_ERASEALL);
MAKE_CASE(COMMAND_COPY_EEPROM_TO_RAM);
MAKE_CASE(COMMAND_COPY_RAM_TO_EEPROM);
default: return "<UNK>";
}
}
#undef MAKE_CASE
#else
# define nmc93cxx_eeprom_log(lvl, fmt, ...)
# define nmc93cxx_eeprom_log(dev, lvl, fmt, ...)
#endif
static void
nmc93cxx_eeprom_set_state(nmc93cxx_eeprom_t *dev, EepromState state)
{
if (dev->state != state) {
nmc93cxx_eeprom_log(dev, 2, "EEPROM: New state %s\n", nmc93cxx_eeprom_state_to_name(state));
}
dev->state = state;
}
static void
nmc93cxx_eeprom_cmd_complete_timer_callback(void *priv)
{
nmc93cxx_eeprom_t *dev = priv;
dev->is_busy = false;
}
static void
nmc93cxx_eeprom_start_cmd_timer(nmc93cxx_eeprom_t *dev, double period)
{
dev->is_busy = true;
timer_on_auto(&dev->cmd_complete_timer, period);
}
static void *
nmc93cxx_eeprom_init(const device_t *info)
{
uint16_t nwords = 64;
uint8_t addrbits = 6;
uint8_t filldefault = 1;
nmc93cxx_eeprom_params_t *params_details = (nmc93cxx_eeprom_params_t *) info->local;
nmc93cxx_eeprom_t *eeprom = NULL;
if (info->local == 0)
return NULL;
nmc93cxx_eeprom_t *dev;
bool fill_default = true;
uint16_t cells, nwords, data_bits;
uint8_t addrbits;
nwords = params_details->nwords;
/* Check for mandatory parameters */
assert(params_details != NULL);
assert(params_details->filename != NULL);
switch (nwords) {
case 16:
case 64:
switch (params_details->type) {
/* 16-bit EEPROMs */
case NMC_93C06_x16_16:
cells = 16;
addrbits = 6;
data_bits = 16;
break;
case 128:
case 256:
case NMC_93C46_x16_64:
cells = 64;
addrbits = 6;
data_bits = 16;
break;
case NMC_93C56_x16_128:
cells = 128;
addrbits = 8;
data_bits = 16;
break;
case NMC_93C57_x16_128:
cells = 128;
addrbits = 7;
data_bits = 16;
break;
case NMC_93C66_x16_256:
cells = 256;
addrbits = 8;
data_bits = 16;
break;
case NMC_93C76_x16_512:
cells = 512;
addrbits = 10;
data_bits = 16;
break;
case NMC_93C86_x16_1024:
cells = 1024;
addrbits = 10;
data_bits = 16;
break;
/* 8-bit EEPROMs */
case NMC_93C46_x8_128:
cells = 128;
addrbits = 7;
data_bits = 8;
break;
case NMC_93C56_x8_256:
cells = 256;
addrbits = 9;
data_bits = 8;
break;
case NMC_93C57_x8_256:
cells = 256;
addrbits = 8;
data_bits = 8;
break;
case NMC_93C66_x8_512:
cells = 512;
addrbits = 9;
data_bits = 8;
break;
case NMC_93C76_x8_1024:
cells = 1024;
addrbits = 11;
data_bits = 8;
break;
case NMC_93C86_x8_2048:
cells = 1024;
addrbits = 11;
data_bits = 8;
break;
default:
nwords = 64;
addrbits = 6;
/* Invalid parameter passed to the device */
assert(false);
break;
}
eeprom = calloc(1, sizeof(nmc93cxx_eeprom_t) + ((nwords + 1) * 2));
if (!eeprom)
/* The "ORG" pin can select the x8 or x16 memory organization */
if (data_bits == 16) {
nwords = cells;
} else {
nwords = cells / 2;
assert(data_bits == 8);
}
dev = calloc(1, offsetof(nmc93cxx_eeprom_t, array_data[nwords]));
if (!dev)
return NULL;
eeprom->size = nwords;
eeprom->addrbits = addrbits;
/* Output DO is tristate, read results in 1. */
eeprom->dev.out = 1;
dev->cells = cells;
dev->command_address_bits = addrbits;
dev->data_bits = data_bits;
dev->is_locked = true;
dev->command = COMMAND_INVALID;
dev->log = log_open("nmc93cxx");
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
if (params_details->filename) {
FILE *fp = nvr_fopen(params_details->filename, "rb");
strncpy(eeprom->filename, params_details->filename, sizeof(eeprom->filename) - 1);
if (fp) {
filldefault = !fread(eeprom->dev.data, sizeof(uint16_t), nwords, fp);
fclose(fp);
}
/* Load the EEPROM image */
snprintf(dev->filename, sizeof(dev->filename), "%s", params_details->filename);
FILE *fp = nvr_fopen(dev->filename, "rb");
if (fp) {
fill_default = !fread(dev->array_data, (size_t) dev->data_bits / 8, dev->cells, fp);
fclose(fp);
}
if (fill_default && params_details->default_content) {
memcpy(dev->array_data, params_details->default_content, (size_t) dev->cells * ((size_t) dev->data_bits / 8));
}
if (filldefault) {
memcpy(eeprom->dev.data, params_details->default_content, nwords * sizeof(uint16_t));
/* Compute address bits */
uint32_t count = dev->cells - 1;
dev->address_bits = 0;
while (count != 0) {
count >>= 1;
dev->address_bits++;
}
return eeprom;
timer_add(&dev->cmd_complete_timer, nmc93cxx_eeprom_cmd_complete_timer_callback, dev, 0);
return dev;
}
static uint32_t
nmc93cxx_eeprom_cell_read(nmc93cxx_eeprom_t *dev, uint32_t address)
{
if (dev->data_bits == 16) {
return dev->array_data[address];
} else {
return *((uint8_t *)dev->array_data + address);
}
}
static void
nmc93cxx_eeprom_save(nmc93cxx_eeprom_t *eeprom)
nmc93cxx_eeprom_cell_write(nmc93cxx_eeprom_t *dev, uint32_t address, uint32_t data)
{
FILE *fp = nvr_fopen(eeprom->filename, "wb");
if (!fp)
return;
fwrite(eeprom->dev.data, 2, eeprom->size, fp);
fclose(fp);
if (dev->data_bits == 16) {
dev->array_data[address] = data;
} else {
*((uint8_t *)dev->array_data + address) = data;
}
}
static void
nmc93cxx_eeprom_handle_cmd_write(nmc93cxx_eeprom_t *dev, uint32_t address, uint32_t data)
{
nmc93cxx_eeprom_log(dev, 1, "EEPROM: WR %08lX <-- %X\n", address, data);
nmc93cxx_eeprom_cell_write(dev, address, data);
nmc93cxx_eeprom_start_cmd_timer(dev, WRITE_TIME_US);
}
static void
nmc93cxx_eeprom_handle_cmd_write_all(nmc93cxx_eeprom_t *dev, uint32_t data)
{
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Write all operation %X\n", data);
for (uint32_t address = 0; address < (1 << dev->address_bits); ++address) {
nmc93cxx_eeprom_cell_write(dev, address, nmc93cxx_eeprom_cell_read(dev, address) & data);
}
nmc93cxx_eeprom_start_cmd_timer(dev, WRITE_ALL_TIME_US);
}
static void
nmc93cxx_eeprom_handle_cmd_erase(nmc93cxx_eeprom_t *dev, uint32_t address)
{
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Erase data at %08lx\n", address);
nmc93cxx_eeprom_cell_write(dev, address, ~0);
nmc93cxx_eeprom_start_cmd_timer(dev, ERASE_TIME_US);
}
static void
nmc93cxx_eeprom_handle_cmd_erase_all(nmc93cxx_eeprom_t *dev)
{
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Erase all operation\n");
for (uint32_t address = 0; address < (1 << dev->address_bits); ++address) {
nmc93cxx_eeprom_cell_write(dev, address, ~0);
}
nmc93cxx_eeprom_start_cmd_timer(dev, ERASE_ALL_TIME_US);
}
static void
nmc93cxx_eeprom_parse_command_and_address(nmc93cxx_eeprom_t *dev)
{
dev->address = dev->command_address_accum & ((1 << dev->command_address_bits) - 1);
/* Extract the command portion and handle it */
switch (dev->command_address_accum >> dev->command_address_bits) {
/* Opcode 0 needs two more bits to decode the operation */
case 0:
switch (dev->address >> (dev->command_address_bits - 2)) {
case 0: dev->command = COMMAND_LOCK; break;
case 1: dev->command = COMMAND_WRITEALL; break;
case 2: dev->command = COMMAND_ERASEALL; break;
case 3: dev->command = COMMAND_UNLOCK; break;
}
dev->address = 0;
break;
case 1: dev->command = COMMAND_WRITE; break;
case 2: dev->command = COMMAND_READ; break;
case 3: dev->command = COMMAND_ERASE; break;
default:
dev->command = COMMAND_INVALID;
break;
}
if (dev->address >= (1 << dev->address_bits)) {
nmc93cxx_eeprom_log(dev, 1, "EEPROM: out-of-range address 0x%X provided (maximum should be 0x%X)\n", dev->address, (1 << dev->address_bits) - 1);
}
}
static void
nmc93cxx_eeprom_execute_command(nmc93cxx_eeprom_t *dev)
{
/* Parse into a generic command and reset the accumulator count */
nmc93cxx_eeprom_parse_command_and_address(dev);
dev->bits_accum = 0;
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Execute command %s\n", nmc93cxx_eeprom_cmd_to_name(dev->command));
switch (dev->command) {
/*
* Advance to the READING_DATA state; data is fetched after first CLK
* reset the shift register to 0 to simulate the dummy 0 bit that happens prior
* to the first clock
*/
case COMMAND_READ:
dev->shift_register = 0;
nmc93cxx_eeprom_set_state(dev, STATE_READING_DATA);
break;
/* Reset the shift register and wait for enough data to be clocked through */
case COMMAND_WRITE:
case COMMAND_WRITEALL:
dev->shift_register = 0;
nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_DATA);
break;
/* Erase the parsed address (unless locked) and wait for it to complete */
case COMMAND_ERASE:
if (dev->is_locked) {
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Attempt to erase while locked\n");
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
break;
}
nmc93cxx_eeprom_handle_cmd_erase(dev, dev->address);
nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMPLETION);
break;
/* Lock the chip; return to IN_RESET state */
case COMMAND_LOCK:
dev->is_locked = true;
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
break;
/* Unlock the chip; return to IN_RESET state */
case COMMAND_UNLOCK:
dev->is_locked = false;
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
break;
/* Erase the entire chip (unless locked) and wait for it to complete */
case COMMAND_ERASEALL:
if (dev->is_locked) {
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Attempt to erase all while locked\n");
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
break;
}
nmc93cxx_eeprom_handle_cmd_erase_all(dev);
nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMPLETION);
break;
default:
nmc93cxx_eeprom_log(dev, 1, "execute_command called with invalid command %d\n", dev->command);
assert(false);
break;
}
}
static void
nmc93cxx_eeprom_execute_write_command(nmc93cxx_eeprom_t *dev)
{
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Execute write command %s\n", nmc93cxx_eeprom_cmd_to_name(dev->command));
switch (dev->command) {
/* Reset the shift register and wait for enough data to be clocked through */
case COMMAND_WRITE:
if (dev->is_locked) {
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Attempt to write to address 0x%X while locked\n", dev->address);
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
break;
}
nmc93cxx_eeprom_handle_cmd_write(dev, dev->address, dev->shift_register);
nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMPLETION);
break;
/*
* Write the entire EEPROM with the same data; ERASEALL is required before so we
* AND against the already-present data
*/
case COMMAND_WRITEALL:
if (dev->is_locked) {
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Attempt to write all while locked\n");
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
break;
}
nmc93cxx_eeprom_handle_cmd_write_all(dev, dev->shift_register);
nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMPLETION);
break;
default:
nmc93cxx_eeprom_log(dev, 1, "execute_command called with invalid command %d\n", dev->command);
assert(false);
break;
}
}
static void
nmc93cxx_eeprom_handle_event(nmc93cxx_eeprom_t *dev, EepromEvent event)
{
switch (dev->state) {
/* CS is not asserted; wait for a rising CS to move us forward, ignoring all clocks */
case STATE_IN_RESET:
if (event == EVENT_CS_RISING_EDGE)
nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_START_BIT);
break;
/*
* CS is asserted; wait for rising clock with a 1 start bit; falling CS will reset us
* note that because each bit is written independently, it is possible for us to receive
* a false rising CLK edge at the exact same time as a rising CS edge; it appears we
* should ignore these edges (makes sense really)
*/
case STATE_WAIT_FOR_START_BIT:
if ((event == EVENT_CLK_RISING_EDGE) && dev->di_state && !dev->is_busy && (dev->write_tick != dev->last_cs_rising_edge_tick)) {
dev->command_address_accum = 0;
dev->bits_accum = 0;
nmc93cxx_eeprom_set_state(dev, STATE_WAIT_FOR_COMMAND);
} else if (event == EVENT_CS_FALLING_EDGE)
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
break;
/* CS is asserted; wait for a command to come through; falling CS will reset us */
case STATE_WAIT_FOR_COMMAND:
if (event == EVENT_CLK_RISING_EDGE) {
/* If we have enough bits for a command + address, check it out */
dev->command_address_accum = (dev->command_address_accum << 1) | dev->di_state;
if (++dev->bits_accum == 2 + dev->command_address_bits)
nmc93cxx_eeprom_execute_command(dev);
} else if (event == EVENT_CS_FALLING_EDGE)
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
break;
/* CS is asserted; reading data, clock the shift register; falling CS will reset us */
case STATE_READING_DATA:
if (event == EVENT_CLK_RISING_EDGE) {
uint32_t bit_index = dev->bits_accum++;
/* Wrapping the address on multi-read */
if (((bit_index % dev->data_bits) == 0) && (bit_index == 0))
{
uint32_t addr = (dev->address + dev->bits_accum / dev->data_bits) & ((1 << dev->address_bits) - 1);
uint32_t data = nmc93cxx_eeprom_cell_read(dev, addr);
nmc93cxx_eeprom_log(dev, 1, "EEPROM: RD %08lX --> %X\n", addr, data);
dev->shift_register = data << (32 - dev->data_bits);
} else {
dev->shift_register = (dev->shift_register << 1) | 1;
}
} else if (event == EVENT_CS_FALLING_EDGE) {
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
if (dev->bits_accum > (dev->data_bits + 1))
nmc93cxx_eeprom_log(dev, 1, "EEPROM: Overclocked read by %d bits\n", dev->bits_accum - dev->data_bits);
else if (dev->bits_accum < dev->data_bits)
nmc93cxx_eeprom_log(dev, 1, "EEPROM: CS deasserted in READING_DATA after %d bits\n", dev->bits_accum);
}
break;
/* CS is asserted; waiting for data; clock data through until we accumulate enough; falling CS will reset us */
case STATE_WAIT_FOR_DATA:
if (event == EVENT_CLK_RISING_EDGE) {
dev->shift_register = (dev->shift_register << 1) | dev->di_state;
if (++dev->bits_accum == dev->data_bits)
nmc93cxx_eeprom_execute_write_command(dev);
} else if (event == EVENT_CS_FALLING_EDGE) {
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
nmc93cxx_eeprom_log(dev, 1, "EEPROM: CS deasserted in STATE_WAIT_FOR_DATA after %d bits\n", dev->bits_accum);
}
break;
/* CS is asserted; waiting for completion; watch for CS falling */
case STATE_WAIT_FOR_COMPLETION:
if (event == EVENT_CS_FALLING_EDGE)
nmc93cxx_eeprom_set_state(dev, STATE_IN_RESET);
break;
default:
break;
}
}
void
nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *eeprom, int eecs, int eesk, int eedi)
nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *dev, bool eecs, bool eesk, bool eedi)
{
uint8_t tick = eeprom->dev.count;
uint8_t eedo = eeprom->dev.out;
uint16_t address = eeprom->dev.address;
uint8_t command = eeprom->dev.opcode;
assert(dev != NULL);
nmc93cxx_eeprom_log(1, "CS=%u SK=%u DI=%u DO=%u, tick = %u\n",
eecs, eesk, eedi, eedo, tick);
dev->write_tick++;
if (!eeprom->dev.oldena && eecs) {
/* Start chip select cycle. */
nmc93cxx_eeprom_log(1, "Cycle start, waiting for 1st start bit (0)\n");
tick = 0;
command = 0x0;
address = 0x0;
} else if (eeprom->dev.oldena && !eecs) {
/* End chip select cycle. This triggers write / erase. */
if (!eeprom->dev.wp) {
uint8_t subcommand = address >> (eeprom->addrbits - 2);
if (command == 0 && subcommand == 2) {
/* Erase all. */
for (address = 0; address < eeprom->size; address++)
eeprom->dev.data[address] = 0xffff;
nmc93cxx_eeprom_log(dev, 3, "EEPROM: CS=%u SK=%u DI=%u DO=%u, tick = %u\n",
eecs, eesk, eedi, nmc93cxx_eeprom_read(dev), dev->write_tick);
nmc93cxx_eeprom_save(eeprom);
} else if (command == 3) {
/* Erase word. */
eeprom->dev.data[address] = 0xffff;
nmc93cxx_eeprom_save(eeprom);
} else if (tick >= (2 + 2 + eeprom->addrbits + 16)) {
if (command == 1) {
/* Write word. */
eeprom->dev.data[address] &= eeprom->dev.dat;
nmc93cxx_eeprom_save(eeprom);
} else if (command == 0 && subcommand == 1) {
/* Write all. */
for (address = 0; address < eeprom->size; address++)
eeprom->dev.data[address] &= eeprom->dev.dat;
if (dev->cs_state != eecs) {
dev->cs_state = eecs;
nmc93cxx_eeprom_save(eeprom);
}
}
/* Remember the rising edge tick so we don't process CLK signals at the same time */
if (eecs) {
dev->last_cs_rising_edge_tick = dev->write_tick;
}
/* Output DO is tristate, read results in 1. */
eedo = 1;
} else if (eecs && !eeprom->dev.oldclk && eesk) {
/* Raising edge of clock shifts data in. */
if (tick == 0) {
/* Wait for 1st start bit. */
if (eedi == 0) {
nmc93cxx_eeprom_log(1, "Got correct 1st start bit, waiting for 2nd start bit (1)\n");
tick++;
} else {
nmc93cxx_eeprom_log(1, "wrong 1st start bit (is 1, should be 0)\n");
tick = 2;
#if 0
~ assert(!"wrong start bit");
#endif
}
} else if (tick == 1) {
/* Wait for 2nd start bit. */
if (eedi != 0) {
nmc93cxx_eeprom_log(1, "Got correct 2nd start bit, getting command + address\n");
tick++;
} else {
nmc93cxx_eeprom_log(1, "1st start bit is longer than needed\n");
}
} else if (tick < 2 + 2) {
/* Got 2 start bits, transfer 2 opcode bits. */
tick++;
command <<= 1;
if (eedi) {
command += 1;
}
} else if (tick < 2 + 2 + eeprom->addrbits) {
/* Got 2 start bits and 2 opcode bits, transfer all address bits. */
tick++;
address = ((address << 1) | eedi);
if (tick == 2 + 2 + eeprom->addrbits) {
nmc93cxx_eeprom_log(1, "Address = 0x%02x (value 0x%04x)\n",
address, eeprom->dev.data[address]);
if (command == 2) {
eedo = 0;
}
address = address % eeprom->size;
if (command == 0) {
/* Command code in upper 2 bits of address. */
switch (address >> (eeprom->addrbits - 2)) {
case 0:
nmc93cxx_eeprom_log(1, "write disable command\n");
eeprom->dev.wp = 1;
break;
case 1:
nmc93cxx_eeprom_log(1, "write all command\n");
break;
case 2:
nmc93cxx_eeprom_log(1, "erase all command\n");
break;
case 3:
nmc93cxx_eeprom_log(1, "write enable command\n");
eeprom->dev.wp = 0;
break;
default:
break;
}
} else {
/* Read, write or erase word. */
eeprom->dev.dat = eeprom->dev.data[address];
}
}
} else if (tick < 2 + 2 + eeprom->addrbits + 16) {
/* Transfer 16 data bits. */
tick++;
if (command == 2) {
/* Read word. */
eedo = ((eeprom->dev.dat & 0x8000) != 0);
}
eeprom->dev.dat <<= 1;
eeprom->dev.dat += eedi;
} else {
nmc93cxx_eeprom_log(1, "additional unneeded tick, not processed\n");
}
nmc93cxx_eeprom_handle_event(dev, eecs ? EVENT_CS_RISING_EDGE : EVENT_CS_FALLING_EDGE);
}
dev->di_state = eedi;
if (dev->clk_state != eesk) {
dev->clk_state = eesk;
nmc93cxx_eeprom_handle_event(dev, eesk ? EVENT_CLK_RISING_EDGE : EVENT_CLK_FALLING_EDGE);
}
/* Save status of EEPROM. */
eeprom->dev.count = tick;
eeprom->dev.oldena = eecs;
eeprom->dev.oldclk = eesk;
eeprom->dev.out = eedo;
eeprom->dev.address = address;
eeprom->dev.opcode = command;
}
uint16_t
nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *eeprom)
bool
nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *dev)
{
/* Return status of pin DO (0 or 1). */
return eeprom->dev.out;
assert(dev != NULL);
if (dev->state == STATE_WAIT_FOR_START_BIT) {
/* Read the state of the READY/BUSY line */
return !dev->is_busy;
} else if (dev->state == STATE_READING_DATA) {
/* Read the current output bit */
return ((dev->shift_register & 0x80000000) != 0);
}
/* The DO pin is tristated */
return true;
}
static void
nmc93cxx_eeprom_close(void *priv)
{
nmc93cxx_eeprom_t *eeprom = (nmc93cxx_eeprom_t *) priv;
FILE *fp = nvr_fopen(eeprom->filename, "wb");
nmc93cxx_eeprom_t *dev = priv;
FILE *fp = nvr_fopen(dev->filename, "wb");
if (fp) {
fwrite(eeprom->dev.data, 2, eeprom->size, fp);
fwrite(dev->array_data, dev->data_bits / 8, dev->cells, fp);
fclose(fp);
}
free(priv);
log_close(dev->log);
free(dev);
}
uint16_t *
nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *eeprom)
const uint16_t *
nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *dev)
{
if (UNLIKELY(eeprom == NULL))
return NULL;
assert(dev != NULL);
/* Get EEPROM data array. */
return &eeprom->dev.data[0];
return &dev->array_data[0];
}
const device_t nmc93cxx_device = {

6
src/mem/sst_flash.c
View File

@@ -485,18 +485,18 @@ sst_add_mappings(sst_t *dev)
mem_mapping_add(&(dev->mapping[i]), base, 0x10000,
sst_read, sst_readw, sst_readl,
sst_write, NULL, NULL,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS | MEM_MAPPING_ROM_WS, (void *) dev);
}
if (is6117) {
mem_mapping_add(&(dev->mapping_h[i]), (base | 0x3f00000), 0x10000,
sst_read, sst_readw, sst_readl,
sst_write, NULL, NULL,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS | MEM_MAPPING_ROM_WS, (void *) dev);
} else {
mem_mapping_add(&(dev->mapping_h[i]), (base | (cpu_16bitbus ? 0xf00000 : 0xfff00000)), 0x10000,
sst_read, sst_readw, sst_readl,
sst_write, NULL, NULL,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS | MEM_MAPPING_ROM_WS, (void *) dev);
}
}
}

21
src/network/net_ne2000.c
View File

@@ -182,7 +182,7 @@ nic_config_reset(void *priv)
{
nic_t *dev = (nic_t *) priv;
uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom);
const uint8_t *data = (const uint8_t *) nmc93cxx_eeprom_data(dev->eeprom);
dev->config1 = (data[0x00] & 0x7f) | 0x80;
dev->config2 = (data[0x01] & 0xdf);
@@ -425,7 +425,7 @@ page3_read(nic_t *dev, uint32_t off, UNUSED(unsigned int len))
case 0xd: /* CONFIG4 */
if (dev->board == NE2K_RTL8019AS_PNP) {
uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom);
const uint8_t *data = (const uint8_t *) nmc93cxx_eeprom_data(dev->eeprom);
ret = data[0x03];
}
break;
@@ -464,7 +464,7 @@ page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len))
if ((val & 0xc0) == 0x80)
nmc93cxx_eeprom_write(dev->eeprom, !!(val & 0x08), !!(val & 0x04), !!(val & 0x02));
else if ((val & 0xc0) == 0x40) {
uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom);
const uint8_t *data = (const uint8_t *) nmc93cxx_eeprom_data(dev->eeprom);
dev->config1 = (data[0x00] & 0x7f) | 0x80;
dev->config2 = (data[0x01] & 0xdf);
@@ -799,7 +799,7 @@ nic_update_bios(nic_t *dev)
}
static uint8_t
nic_pci_read(UNUSED(int func), int addr, void *priv)
nic_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const nic_t *dev = (nic_t *) priv;
uint8_t ret = 0x00;
@@ -894,7 +894,7 @@ nic_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
nic_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
nic_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
nic_t *dev = (nic_t *) priv;
uint8_t valxor;
@@ -1391,18 +1391,15 @@ nic_init(const device_t *info)
nmc93cxx_eeprom_params_t params;
char filename[1024] = { 0 };
params.nwords = 64;
params.default_content = (uint16_t *) dev->eeprom_data;
params.type = NMC_93C46_x16_64;
params.default_content = dev->eeprom_data;
params.filename = filename;
int inst = device_get_instance();
snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, inst);
dev->eeprom = device_add_inst_params(&nmc93cxx_device, inst, &params);
if (dev->eeprom == NULL) {
free(dev);
return NULL;
}
if (info->local == NE2K_RTL8019AS_PNP) {
uint8_t *data = (uint8_t *) nmc93cxx_eeprom_data(dev->eeprom);
const uint8_t *data = (const uint8_t *) nmc93cxx_eeprom_data(dev->eeprom);
dev->config1 = (data[0x00] & 0x7f) | 0x80;
dev->config2 = (data[0x01] & 0xdf);

21
src/network/net_pcap.c
View File

@@ -235,7 +235,8 @@ net_pcap_rx_handler(uint8_t *user, const struct pcap_pkthdr *h, const uint8_t *b
net_pcap_t *pcap = (net_pcap_t *) user;
memcpy(pcap->pkt.data, bytes, h->caplen);
pcap->pkt.len = h->caplen;
network_rx_put_pkt(pcap->card, &pcap->pkt);
if (!(net_cards_conf[pcap->card->card_num].link_state & NET_LINK_DOWN))
network_rx_put_pkt(pcap->card, &pcap->pkt);
}
/* Send a packet to the Pcap interface. */
@@ -282,12 +283,14 @@ net_pcap_thread(void *priv)
case NET_EVENT_TX:
net_event_clear(&pcap->tx_event);
int packets = network_tx_popv(pcap->card, pcap->pktv, PCAP_PKT_BATCH);
for (int i = 0; i < packets; i++) {
h.caplen = pcap->pktv[i].len;
f_pcap_sendqueue_queue(pcap->pcap_queue, &h, pcap->pktv[i].data);
if (!(net_cards_conf[pcap->card->card_num].link_state & NET_LINK_DOWN)) {
int packets = network_tx_popv(pcap->card, pcap->pktv, PCAP_PKT_BATCH);
for (int i = 0; i < packets; i++) {
h.caplen = pcap->pktv[i].len;
f_pcap_sendqueue_queue(pcap->pcap_queue, &h, pcap->pktv[i].data);
}
f_pcap_sendqueue_transmit(pcap->pcap, pcap->pcap_queue, 0);
}
f_pcap_sendqueue_transmit(pcap->pcap, pcap->pcap_queue, 0);
pcap->pcap_queue->len = 0;
break;
@@ -333,8 +336,10 @@ net_pcap_thread(void *priv)
net_event_clear(&pcap->tx_event);
int packets = network_tx_popv(pcap->card, pcap->pktv, PCAP_PKT_BATCH);
for (int i = 0; i < packets; i++) {
net_pcap_in(pcap->pcap, pcap->pktv[i].data, pcap->pktv[i].len);
if (!(net_cards_conf[pcap->card->card_num].link_state & NET_LINK_DOWN)) {
for (int i = 0; i < packets; i++) {
net_pcap_in(pcap->pcap, pcap->pktv[i].data, pcap->pktv[i].len);
}
}
}

4
src/network/net_pcnet.c
View File

@@ -2588,7 +2588,7 @@ pcnet_ioset(nic_t *dev, uint16_t addr, int len)
}
static void
pcnet_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
pcnet_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
nic_t *dev = (nic_t *) priv;
uint8_t valxor;
@@ -2671,7 +2671,7 @@ pcnet_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
pcnet_pci_read(UNUSED(int func), int addr, void *priv)
pcnet_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const nic_t *dev = (nic_t *) priv;

33
src/network/net_plip.c
View File

@@ -441,13 +441,14 @@ plip_rx(void *priv, uint8_t *buf, int io_len)
}
static void *
plip_lpt_init(void *lpt)
plip_lpt_init(const device_t *info)
{
plip_t *dev = (plip_t *) calloc(1, sizeof(plip_t));
plip_log(1, "PLIP: lpt_init()\n");
dev->lpt = lpt;
dev->lpt = lpt_attach(plip_write_data, plip_write_ctrl, NULL, plip_read_status, NULL, NULL, NULL, dev);
memset(dev->mac, 0xfc, 6); /* static MAC used by Linux; just a placeholder */
dev->status = 0x80;
@@ -485,24 +486,22 @@ plip_close(void *priv)
free(priv);
}
const lpt_device_t lpt_plip_device = {
.name = "Parallel Line Internet Protocol",
.internal_name = "plip",
.init = plip_lpt_init,
.close = plip_close,
.write_data = plip_write_data,
.write_ctrl = plip_write_ctrl,
.strobe = NULL,
.read_status = plip_read_status,
.read_ctrl = NULL,
.epp_write_data = NULL,
.epp_request_read = NULL,
.priv = NULL,
.lpt = NULL
const device_t lpt_plip_device = {
.name = "Parallel Line Internet Protocol (LPT)",
.internal_name = "plip",
.flags = DEVICE_LPT,
.local = 0,
.init = plip_lpt_init,
.close = plip_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t plip_device = {
.name = "Parallel Line Internet Protocol",
.name = "Parallel Line Internet Protocol (Network)",
.internal_name = "plip",
.flags = DEVICE_LPT,
.local = 0,

12
src/network/net_rtl8139.c
View File

@@ -3100,7 +3100,7 @@ rtl8139_timer(void *priv)
}
static uint8_t
rtl8139_pci_read(UNUSED(int func), int addr, void *priv)
rtl8139_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const RTL8139State *s = (RTL8139State *) priv;
@@ -3157,7 +3157,7 @@ rtl8139_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
rtl8139_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
rtl8139_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
RTL8139State *s = (RTL8139State *) priv;
@@ -3286,15 +3286,11 @@ nic_init(const device_t *info)
for (uint32_t i = 0; i < 6; i++)
s->phys[MAC0 + i] = mac_bytes[i];
params.nwords = 64;
params.default_content = (uint16_t *) s->eeprom_data;
params.type = NMC_93C46_x16_64;
params.default_content = s->eeprom_data;
params.filename = filename;
snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, s->inst);
s->eeprom = device_add_inst_params(&nmc93cxx_device, s->inst, &params);
if (s->eeprom == NULL) {
free(s);
return NULL;
}
s->nic = network_attach(s, (uint8_t *) &s->phys[MAC0], rtl8139_do_receive, rtl8139_set_link_status);
timer_add(&s->timer, rtl8139_timer, s, 0);

31
src/network/net_slirp.c
View File

@@ -193,11 +193,14 @@ net_slirp_send_packet(const void *qp, size_t pkt_len, void *opaque)
memcpy(slirp->pkt.data, (uint8_t *) qp, pkt_len);
slirp->pkt.len = pkt_len;
if (slirp->during_tx) {
network_rx_on_tx_put_pkt(slirp->card, &slirp->pkt);
slirp->recv_on_tx = 1;
} else
network_rx_put_pkt(slirp->card, &slirp->pkt);
if (!(net_cards_conf[slirp->card->card_num].link_state & NET_LINK_DOWN)) {
if (slirp->during_tx) {
network_rx_on_tx_put_pkt(slirp->card, &slirp->pkt);
slirp->recv_on_tx = 1;
} else
network_rx_put_pkt(slirp->card, &slirp->pkt);
}
return pkt_len;
}
@@ -362,8 +365,10 @@ net_slirp_rx_deferred_packets(net_slirp_t *slirp)
if (slirp->recv_on_tx) {
do {
packets = network_rx_on_tx_popv(slirp->card, slirp->pkt_tx_v, SLIRP_PKT_BATCH);
for (int i = 0; i < packets; i++)
network_rx_put_pkt(slirp->card, &(slirp->pkt_tx_v[i]));
if (!(net_cards_conf[slirp->card->card_num].link_state & NET_LINK_DOWN)) {
for (int i = 0; i < packets; i++)
network_rx_put_pkt(slirp->card, &(slirp->pkt_tx_v[i]));
}
} while (packets > 0);
slirp->recv_on_tx = 0;
}
@@ -403,8 +408,10 @@ net_slirp_thread(void *priv)
{
slirp->during_tx = 1;
int packets = network_tx_popv(slirp->card, slirp->pkt_tx_v, SLIRP_PKT_BATCH);
for (int i = 0; i < packets; i++)
net_slirp_in(slirp, slirp->pkt_tx_v[i].data, slirp->pkt_tx_v[i].len);
if (!(net_cards_conf[slirp->card->card_num].link_state & NET_LINK_DOWN)) {
for (int i = 0; i < packets; i++)
net_slirp_in(slirp, slirp->pkt_tx_v[i].data, slirp->pkt_tx_v[i].len);
}
slirp->during_tx = 0;
net_slirp_rx_deferred_packets(slirp);
@@ -456,8 +463,10 @@ net_slirp_thread(void *priv)
slirp->during_tx = 1;
int packets = network_tx_popv(slirp->card, slirp->pkt_tx_v, SLIRP_PKT_BATCH);
for (int i = 0; i < packets; i++)
net_slirp_in(slirp, slirp->pkt_tx_v[i].data, slirp->pkt_tx_v[i].len);
if (!(net_cards_conf[slirp->card->card_num].link_state & NET_LINK_DOWN)) {
for (int i = 0; i < packets; i++)
net_slirp_in(slirp, slirp->pkt_tx_v[i].data, slirp->pkt_tx_v[i].len);
}
slirp->during_tx = 0;
net_slirp_rx_deferred_packets(slirp);

28
src/network/net_switch.c
View File

@@ -372,25 +372,29 @@ net_switch_thread(void *priv)
net_event_clear(&netswitch->tx_event);
netswitch->during_tx = 1;
packets = network_tx_popv(netswitch->card, netswitch->pkt_tx_v, SWITCH_PKT_BATCH);
for (int i = 0; i < packets; i++) {
if (!(net_cards_conf[netswitch->card->card_num].link_state & NET_LINK_DOWN)) {
for (int i = 0; i < packets; i++) {
#define MAC_FORMAT "(%02X:%02X:%02X:%02X:%02X:%02X -> %02X:%02X:%02X:%02X:%02X:%02X)"
#define MAC_FORMAT_ARGS(p) (p)[6], (p)[7], (p)[8], (p)[9], (p)[10], (p)[11], (p)[0], (p)[1], (p)[2], (p)[3], (p)[4], (p)[5]
netswitch_log("Network Switch: sending %d-byte packet " MAC_FORMAT "\n",
netswitch->pkt_tx_v[i].len, MAC_FORMAT_ARGS(netswitch->pkt_tx_v[i].data));
netswitch_log("Network Switch: sending %d-byte packet " MAC_FORMAT "\n",
netswitch->pkt_tx_v[i].len, MAC_FORMAT_ARGS(netswitch->pkt_tx_v[i].data));
/* Send through all known host interfaces. */
for (net_switch_hostaddr_t *hostaddr = netswitch->hostaddrs; hostaddr; hostaddr = hostaddr->next)
sendto(hostaddr->socket_tx,
(char *) netswitch->pkt_tx_v[i].data, netswitch->pkt_tx_v[i].len, 0,
&hostaddr->addr_tx.sa, sizeof(hostaddr->addr_tx.sa));
/* Send through all known host interfaces. */
for (net_switch_hostaddr_t *hostaddr = netswitch->hostaddrs; hostaddr; hostaddr = hostaddr->next)
sendto(hostaddr->socket_tx,
(char *) netswitch->pkt_tx_v[i].data, netswitch->pkt_tx_v[i].len, 0,
&hostaddr->addr_tx.sa, sizeof(hostaddr->addr_tx.sa));
}
}
netswitch->during_tx = 0;
if (netswitch->recv_on_tx) {
do {
packets = network_rx_on_tx_popv(netswitch->card, netswitch->pkt_tx_v, SWITCH_PKT_BATCH);
for (int i = 0; i < packets; i++)
network_rx_put_pkt(netswitch->card, &(netswitch->pkt_tx_v[i]));
if (!(net_cards_conf[netswitch->card->card_num].link_state & NET_LINK_DOWN)) {
for (int i = 0; i < packets; i++)
network_rx_put_pkt(netswitch->card, &(netswitch->pkt_tx_v[i]));
}
} while (packets > 0);
netswitch->recv_on_tx = 0;
}
@@ -407,9 +411,9 @@ net_switch_thread(void *priv)
netswitch_log("Network Switch: recv error (%d)\n", len);
} else if ((AS_U64(netswitch->pkt.data[6]) & le64_to_cpu(0xffffffffffffULL)) == netswitch->mac_addr_u64) {
/* A packet we've sent has looped back, drop it. */
} else if (netswitch->promisc || /* promiscuous mode? */
} else if (!(net_cards_conf[netswitch->card->card_num].link_state & NET_LINK_DOWN) && (netswitch->promisc || /* promiscuous mode? */
(netswitch->pkt.data[0] & 1) || /* broadcast packet? */
((AS_U64(netswitch->pkt.data[0]) & le64_to_cpu(0xffffffffffffULL)) == netswitch->mac_addr_u64)) { /* packet for me? */
((AS_U64(netswitch->pkt.data[0]) & le64_to_cpu(0xffffffffffffULL)) == netswitch->mac_addr_u64))) { /* packet for me? */
netswitch_log("Network Switch: receiving %d-byte packet " MAC_FORMAT "\n",
len, MAC_FORMAT_ARGS(netswitch->pkt.data));
netswitch->pkt.len = len;

16
src/network/net_tulip.c
View File

@@ -733,7 +733,9 @@ tulip_tx(TULIPState *s, struct tulip_descriptor *desc)
if ((s->csr[6] >> CSR6_OM_SHIFT) & CSR6_OM_MASK) {
/* Internal or external Loopback */
tulip_receive(s, s->tx_frame, s->tx_frame_len);
} else if (s->tx_frame_len <= sizeof(s->tx_frame)) {
} else if (net_cards_conf[s->nic->card_num].link_state & NET_LINK_DOWN)
desc->status |= (TDES0_ES | TDES0_NC);
else if (s->tx_frame_len <= sizeof(s->tx_frame)) {
//pclog("Transmit!.\n");
network_tx(s->nic, s->tx_frame, s->tx_frame_len);
}
@@ -1180,7 +1182,7 @@ tulip_srom_crc(uint8_t *eeprom)
}
static uint8_t
tulip_pci_read(UNUSED(int func), int addr, void *priv)
tulip_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const TULIPState *s = (TULIPState *) priv;
uint8_t ret = 0;
@@ -1299,7 +1301,7 @@ tulip_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
tulip_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
tulip_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
TULIPState *s = (TULIPState *) priv;
@@ -1640,16 +1642,12 @@ nic_init(const device_t *info)
}
if (info->local != 3) {
params.nwords = 64;
params.default_content = (uint16_t *) s->eeprom_data;
params.type = NMC_93C46_x16_64;
params.default_content = s->eeprom_data;
params.filename = filename;
int inst = device_get_instance();
snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, inst);
s->eeprom = device_add_inst_params(&nmc93cxx_device, inst, &params);
if (s->eeprom == NULL) {
free(s);
return NULL;
}
}
s->tulip_pci_bar[0].addr_regs[0] = 1;

13
src/network/net_vde.c
View File

@@ -151,10 +151,12 @@ static void net_vde_thread(void *priv) {
if (pfd[NET_EVENT_TX].revents & POLLIN) {
net_event_clear(&vde->tx_event);
int packets = network_tx_popv(vde->card, vde->pktv, VDE_PKT_BATCH);
for (int i=0; i<packets; i++) {
int nc = f_vde_send(vde->vdeconn, vde->pktv[i].data,vde->pktv[i].len, 0 );
if (nc == 0) {
vde_log("VDE: Problem, no bytes sent.\n");
if (!(net_cards_conf[vde->card->card_num].link_state & NET_LINK_DOWN)) {
for (int i=0; i<packets; i++) {
int nc = f_vde_send(vde->vdeconn, vde->pktv[i].data,vde->pktv[i].len, 0 );
if (nc == 0) {
vde_log("VDE: Problem, no bytes sent.\n");
}
}
}
}
@@ -163,7 +165,8 @@ static void net_vde_thread(void *priv) {
if (pfd[NET_EVENT_RX].revents & POLLIN) {
int nc = f_vde_recv(vde->vdeconn, vde->pkt.data, NET_MAX_FRAME, 0);
vde->pkt.len = nc;
network_rx_put_pkt(vde->card, &vde->pkt);
if (!(net_cards_conf[vde->card->card_num].link_state & NET_LINK_DOWN))
network_rx_put_pkt(vde->card, &vde->pkt);
}
// We have been told to close

106
src/nvr_at.c
View File

@@ -289,21 +289,22 @@
#define RTC_REGS 14 /* number of registers */
#define FLAG_NO_NMI 0x01
#define FLAG_AMI_1992_HACK 0x02
#define FLAG_AMI_1994_HACK 0x04
#define FLAG_AMI_1995_HACK 0x08
#define FLAG_P6RP4_HACK 0x10
#define FLAG_PIIX4 0x20
#define FLAG_MULTI_BANK 0x40
#define FLAG_MARTIN_HACK 0x80
#define FLAG_NO_NMI 0x001
#define FLAG_AMI_1992_HACK 0x002
#define FLAG_AMI_1994_HACK 0x004
#define FLAG_AMI_1995_HACK 0x008
#define FLAG_AMI_1999_HACK 0x010
#define FLAG_AMI_1999J_HACK 0x020
#define FLAG_P6RP4_HACK 0x040
#define FLAG_PIIX4 0x080
#define FLAG_MULTI_BANK 0x100
#define FLAG_MARTIN_HACK 0x200
typedef struct local_t {
int8_t stat;
uint8_t cent;
uint8_t def;
uint8_t flags;
uint8_t read_addr;
uint8_t wp_0d;
uint8_t wp_32;
@@ -317,6 +318,8 @@ typedef struct local_t {
int16_t count;
int16_t state;
uint16_t flags;
uint16_t addr[8];
int32_t smi_enable;
@@ -576,6 +579,10 @@ nvr_reg_common_write(uint16_t reg, uint8_t val, nvr_t *nvr, local_t *local)
nvr->is_new = 0;
if ((reg == 0x52) && (local->flags & FLAG_AMI_1995_HACK))
nvr->is_new = 0;
if ((reg == 0x54) && (local->flags & FLAG_AMI_1999_HACK))
nvr->is_new = 0;
if ((reg == 0x55) && (local->flags & FLAG_AMI_1999J_HACK))
nvr->is_new = 0;
if ((reg >= 0x38) && (reg <= 0x3f) && local->wp[0])
return;
if ((reg >= 0xb8) && (reg <= 0xbf) && local->wp[1])
@@ -825,6 +832,34 @@ nvr_read(uint16_t addr, void *priv)
ret = checksum >> 8;
else
ret = checksum & 0xff;
} else if (!nvr->is_new && (local->flags & FLAG_AMI_1999_HACK)) {
/* The checksum at 3E-3F is for 37-3D and 40-73. */
for (i = 0x37; i <= 0x3d; i++)
checksum += nvr->regs[i];
for (i = 0x40; i <= 0x73; i++) {
if (i == 0x54)
checksum += (nvr->regs[i] & 0x3f);
else
checksum += nvr->regs[i];
}
if (local->addr[addr_id] == 0x3e)
ret = checksum >> 8;
else
ret = checksum & 0xff;
} else if (!nvr->is_new && (local->flags & FLAG_AMI_1999J_HACK)) {
/* The checksum at 3E-3F is for 37-3D and 40-73. */
for (i = 0x37; i <= 0x3d; i++)
checksum += nvr->regs[i];
for (i = 0x40; i <= 0x73; i++) {
if (i == 0x55)
checksum += (nvr->regs[i] & 0xfc);
else
checksum += nvr->regs[i];
}
if (local->addr[addr_id] == 0x3e)
ret = checksum >> 8;
else
ret = checksum & 0xff;
} else if (!nvr->is_new && (local->flags & FLAG_P6RP4_HACK)) {
/* The checksum at 3E-3F is for 37-3D and 40-51. */
for (i = 0x37; i <= 0x3d; i++)
@@ -857,6 +892,20 @@ nvr_read(uint16_t addr, void *priv)
ret = nvr->regs[local->addr[addr_id]];
break;
case 0x54:
if (!nvr->is_new && (local->flags & FLAG_AMI_1999_HACK))
ret = nvr->regs[local->addr[addr_id]] & 0x3f;
else
ret = nvr->regs[local->addr[addr_id]];
break;
case 0x55:
if (!nvr->is_new && (local->flags & FLAG_AMI_1999J_HACK))
ret = nvr->regs[local->addr[addr_id]] & 0xfc;
else
ret = nvr->regs[local->addr[addr_id]];
break;
default:
if (!(local->lock[local->addr[addr_id]] & 0x02))
ret = nvr->regs[local->addr[addr_id]];
@@ -1173,15 +1222,20 @@ nvr_at_init(const device_t *info)
local->cent = RTC_CENTURY_VIA;
break;
case 8: /* Epson Equity LT */
if ((info->local & 0x1f) == 0x18) {
local->flags |= (FLAG_PIIX4 | FLAG_AMI_1995_HACK);
local->def = 0x00;
nvr->irq = 8;
local->cent = RTC_CENTURY_AT;
} else {
nvr->irq = -1;
local->cent = RTC_CENTURY_ELT;
}
nvr->irq = -1;
local->cent = RTC_CENTURY_ELT;
break;
case 9: /* Intel PIIX4 + AMI 1999 hack */
local->flags |= (FLAG_PIIX4 | FLAG_AMI_1999_HACK);
local->def = 0x00;
nvr->irq = 8;
local->cent = RTC_CENTURY_AT;
break;
case 0x0a: /* Intel PIIX4 + AMI 1999J hack */
local->flags |= (FLAG_PIIX4 | FLAG_AMI_1999J_HACK);
local->def = 0x00;
nvr->irq = 8;
local->cent = RTC_CENTURY_AT;
break;
default:
@@ -1460,7 +1514,21 @@ const device_t piix4_ami_1995_nvr_device = {
.name = "Intel PIIX4 AMI WinBIOS 1995 PC/AT NVRAM",
.internal_name = "piix4_ami_1995_nvr",
.flags = DEVICE_ISA16,
.local = 0x10 | 8,
.local = 0x10 | 9,
.init = nvr_at_init,
.close = nvr_at_close,
.reset = nvr_at_reset,
.available = NULL,
.speed_changed = nvr_at_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t piix4_ami_1995j_nvr_device = {
.name = "Intel PIIX4 AMI WinBIOS 1995J PC/AT NVRAM",
.internal_name = "piix4_ami_1995j_nvr",
.flags = DEVICE_ISA16,
.local = 0x10 | 10,
.init = nvr_at_init,
.close = nvr_at_close,
.reset = nvr_at_reset,

52
src/pci.c
View File

@@ -40,15 +40,15 @@ typedef struct pci_card_t {
uint8_t irq_routing[PCI_INT_PINS_NUM];
void * priv;
void (*write)(int func, int addr, uint8_t val, void *priv);
uint8_t (*read)(int func, int addr, void *priv);
void (*write)(int func, int addr, int len, uint8_t val, void *priv);
uint8_t (*read)(int func, int addr, int len, void *priv);
} pci_card_t;
typedef struct pci_card_desc_t {
uint8_t type;
void * priv;
void (*write)(int func, int addr, uint8_t val, void *priv);
uint8_t (*read)(int func, int addr, void *priv);
void (*write)(int func, int addr, int len, uint8_t val, void *priv);
uint8_t (*read)(int func, int addr, int len, void *priv);
uint8_t *slot;
} pci_card_desc_t;
@@ -91,6 +91,7 @@ static int pci_card;
static int pci_bus;
static int pci_key;
static int pci_trc_reg = 0;
static int pci_access_len = 0;
static uint32_t pci_enable = 0x00000000;
static void pci_reset_regs(void);
@@ -174,7 +175,7 @@ pci_irq(uint8_t slot, uint8_t pci_int, int level, int set, uint8_t *irq_state)
return;
if (pci_flags & FLAG_NO_IRQ_STEERING)
irq_line = pci_cards[slot].read(0, 0x3c, pci_cards[slot].priv);
irq_line = pci_cards[slot].read(0, 0x3c, 1, pci_cards[slot].priv);
else {
irq_routing = pci_cards[slot].irq_routing[pci_int_index];
@@ -349,12 +350,12 @@ pci_reg_write(uint16_t port, uint8_t val)
slot = pci_card_to_slot_mapping[pci_bus_number_to_index_mapping[pci_bus]][pci_card];
if (slot != PCI_CARD_INVALID) {
if (pci_cards[slot].write)
pci_cards[slot].write(pci_func, pci_index | (port & 0x03), val, pci_cards[slot].priv);
pci_cards[slot].write(pci_func, pci_index | (port & 0x03), pci_access_len, val, pci_cards[slot].priv);
}
pci_log("PCI: [WB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X = %02X\n",
pci_log("PCI: [WB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X, length %I = %02X\n",
(port >= 0xc000) ? 2 : 1, slot,
(slot == PCI_CARD_INVALID) ? "non-existent" : (pci_cards[slot].write ? "used" : "unused"),
pci_card, pci_bus, pci_func, pci_index | (port & 0x03), val);
pci_card, pci_bus, pci_func, pci_index | (port & 0x03), pci_access_len, val);
}
static void
@@ -364,6 +365,8 @@ pci_reset_regs(void)
pci_enable = 0x00000000;
pci_flags &= ~(FLAG_CONFIG_IO_ON | FLAG_CONFIG_M1_IO_ON);
pci_access_len = 1;
}
void
@@ -496,16 +499,24 @@ pci_writew(uint16_t port, uint16_t val, UNUSED(void *priv))
{
if (port & 0x0001) {
/* Non-aligned access, split into two byte accesses. */
if (pci_access_len == 1)
pci_access_len = 2;
pci_write(port, val & 0xff, priv);
pci_write(port + 1, val >> 8, priv);
if (pci_access_len == 2)
pci_access_len = 1;
} else {
/* Aligned access, still split because we cheat. */
switch (port) {
case 0xcfc:
case 0xcfe:
case 0xc000 ... 0xcffe:
if (pci_access_len == 1)
pci_access_len = 2;
pci_write(port, val & 0xff, priv);
pci_write(port + 1, val >> 8, priv);
if (pci_access_len == 2)
pci_access_len = 1;
break;
default:
@@ -519,8 +530,10 @@ pci_writel(uint16_t port, uint32_t val, UNUSED(void *priv))
{
if (port & 0x0003) {
/* Non-aligned access, split into two word accesses. */
pci_access_len = 4;
pci_writew(port, val & 0xffff, priv);
pci_writew(port + 2, val >> 16, priv);
pci_access_len = 1;
} else {
/* Aligned access. */
switch (port) {
@@ -545,8 +558,10 @@ pci_writel(uint16_t port, uint32_t val, UNUSED(void *priv))
case 0xcfc:
case 0xc000 ... 0xcffc:
/* Still split because we cheat. */
pci_access_len = 4;
pci_writew(port, val & 0xffff, priv);
pci_writew(port + 2, val >> 16, priv);
pci_access_len = 1;
break;
default:
@@ -569,12 +584,12 @@ pci_reg_read(uint16_t port)
slot = pci_card_to_slot_mapping[pci_bus_number_to_index_mapping[pci_bus]][pci_card];
if (slot != PCI_CARD_INVALID) {
if (pci_cards[slot].read)
ret = pci_cards[slot].read(pci_func, pci_index | (port & 0x03), pci_cards[slot].priv);
ret = pci_cards[slot].read(pci_func, pci_index | (port & 0x03), pci_access_len, pci_cards[slot].priv);
}
pci_log("PCI: [RB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X = %02X\n",
pci_log("PCI: [RB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X, length %i = %02X\n",
(port >= 0xc000) ? 2 : 1, slot,
(slot == PCI_CARD_INVALID) ? "non-existent" : (pci_cards[slot].read ? "used" : "unused"),
pci_card, pci_bus, pci_func, pci_index | (port & 0x03), ret);
pci_card, pci_bus, pci_access_len, pci_index | (port & 0x03), pci_func, ret);
return ret;
}
@@ -643,8 +658,12 @@ pci_readw(uint16_t port, UNUSED(void *priv))
case 0xcfc:
case 0xcfe:
case 0xc000 ... 0xcffe:
if (pci_access_len == 1)
pci_access_len = 2;
ret = pci_read(port, priv);
ret |= ((uint16_t) pci_read(port + 1, priv)) << 8;
if (pci_access_len == 2)
pci_access_len = 1;
break;
default:
@@ -662,8 +681,10 @@ pci_readl(uint16_t port, UNUSED(void *priv))
if (port & 0x0003) {
/* Non-aligned access, split into two word accesses. */
pci_access_len = 4;
ret = pci_readw(port, priv);
ret |= ((uint32_t) pci_readw(port + 2, priv)) << 16;
pci_access_len = 1;
} else {
/* Aligned access. */
switch (port) {
@@ -682,8 +703,10 @@ pci_readl(uint16_t port, UNUSED(void *priv))
case 0xcfc:
case 0xc000 ... 0xcffc:
/* Still split because we cheat. */
pci_access_len = 4;
ret = pci_readw(port, priv);
ret |= ((uint32_t) pci_readw(port + 2, priv)) << 16;
pci_access_len = 1;
break;
}
}
@@ -781,8 +804,8 @@ pci_find_slot(uint8_t add_type, uint8_t ignore_slot)
/* Add a PCI card. */
void
pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot)
pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, int len, void *priv),
void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot)
{
pci_card_desc_t *dev;
@@ -853,7 +876,8 @@ pci_register_card(int pci_card)
/* Add an instance of the PCI bridge. */
void
pci_add_bridge(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot)
pci_add_bridge(uint8_t add_type, uint8_t (*read)(int func, int addr, int len, void *priv),
void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot)
{
pci_card_t *card;
uint8_t bridge_slot = (add_type == PCI_ADD_NORMAL) ? last_normal_pci_card_id : pci_find_slot(add_type, 0xff);

4
src/pci_dummy.c
View File

@@ -38,7 +38,7 @@ pci_dummy_interrupt(int set, pci_dummy_t *dev)
}
static uint8_t
pci_dummy_read(uint16_t port, void *priv)
pci_dummy_read(uint16_t port, UNUSED(int len), void *priv)
{
pci_dummy_t *dev = (pci_dummy_t *) priv;
uint8_t ret = 0xff;
@@ -90,7 +90,7 @@ pci_dummy_readl(uint16_t port, void *priv)
}
static void
pci_dummy_write(uint16_t port, UNUSED(uint8_t val), void *priv)
pci_dummy_write(uint16_t port, UNUSED(uint8_t val), UNUSED(int len), void *priv)
{
pci_dummy_t *dev = (pci_dummy_t *) priv;

4
src/printer/CMakeLists.txt
View File

@@ -23,10 +23,6 @@ add_library(print OBJECT
prt_ps.c
)
if(PCL)
target_compile_definitions(print PRIVATE USE_PCL)
endif()
if(APPLE)
find_library(GHOSTSCRIPT_LIB gs)
if (NOT GHOSTSCRIPT_LIB)

28
src/printer/prt_escp.c
View File

@@ -1979,7 +1979,7 @@ read_status(void *priv)
}
static void *
escp_init(void *lpt)
escp_init(const device_t *info)
{
escp_t *dev = NULL;
@@ -1995,7 +1995,8 @@ escp_init(void *lpt)
/* Initialize a device instance. */
dev = (escp_t *) calloc(1, sizeof(escp_t));
dev->ctrl = 0x04;
dev->lpt = lpt;
dev->lpt = lpt_attach(write_data, write_ctrl, strobe, read_status, read_ctrl, NULL, NULL, dev);
rom_get_full_path(dev->fontpath, "roms/printer/fonts/");
@@ -2109,13 +2110,13 @@ static const device_config_t lpt_prt_escp_config[] = {
#endif
// clang-format on
const device_t prt_escp_device = {
const device_t lpt_prt_escp_device = {
.name = "Generic ESC/P 2 Dot-Matrix Printer",
.internal_name = "dot_matrix",
.flags = DEVICE_LPT,
.local = 0,
.init = NULL,
.close = NULL,
.init = escp_init,
.close = escp_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
@@ -2126,20 +2127,3 @@ const device_t prt_escp_device = {
.config = NULL
#endif
};
const lpt_device_t lpt_prt_escp_device = {
.name = "Generic ESC/P 2 Dot-Matrix Printer",
.internal_name = "dot_matrix",
.init = escp_init,
.close = escp_close,
.write_data = write_data,
.write_ctrl = write_ctrl,
.strobe = strobe,
.read_status = read_status,
.read_ctrl = read_ctrl,
.epp_write_data = NULL,
.epp_request_read = NULL,
.priv = NULL,
.lpt = NULL,
.cfgdevice = (device_t *) &prt_escp_device
};

448
src/printer/prt_ps.c
View File

@@ -61,40 +61,55 @@
#define POSTSCRIPT_BUFFER_LENGTH 65536
enum {
LANG_RAW = 0,
LANG_PS,
LANG_PCL_5E,
LANG_PCL_5C,
LANG_HP_RTL,
LANG_PCL_6
};
typedef struct ps_t {
const char *name;
void *lpt;
void * lpt;
pc_timer_t pulse_timer;
pc_timer_t timeout_timer;
pc_timer_t pulse_timer;
pc_timer_t timeout_timer;
char data;
bool ack;
bool select;
bool busy;
bool int_pending;
bool error;
bool autofeed;
bool pcl;
bool pending;
bool pjl;
bool pjl_command;
uint8_t ctrl;
uint8_t pcl_escape;
uint16_t pjl_command_start;
bool ack;
bool select;
bool busy;
bool int_pending;
bool error;
bool autofeed;
bool pcl;
bool pending;
bool pjl;
bool pjl_command;
char printer_path[260];
char data;
char filename[260];
char printer_path[260];
char filename[260];
char buffer[POSTSCRIPT_BUFFER_LENGTH];
size_t buffer_pos;
char buffer[POSTSCRIPT_BUFFER_LENGTH];
uint8_t ctrl;
uint8_t pcl_escape;
uint16_t pjl_command_start;
int lang;
size_t buffer_pos;
} ps_t;
typedef struct gsapi_revision_s {
const char *product;
const char *copyright;
long revision;
long revisiondate;
} gsapi_revision_t;
@@ -155,8 +170,23 @@ convert_to_pdf(ps_t *dev)
gsargv[arg++] = "-dSAFER";
gsargv[arg++] = "-sDEVICE=pdfwrite";
if (dev->pcl) {
gsargv[arg++] = "-LPCL";
gsargv[arg++] = "-lPCL5E";
if (dev->lang == LANG_PCL_6)
gsargv[arg++] = "-LPCLXL";
else {
gsargv[arg++] = "-LPCL";
switch (dev->lang) {
default:
case LANG_PCL_5E:
gsargv[arg++] = "-lPCL5E";
break;
case LANG_PCL_5C:
gsargv[arg++] = "-lPCL5C";
break;
case LANG_HP_RTL:
gsargv[arg++] = "-lRTL";
break;
}
}
}
gsargv[arg++] = "-q";
gsargv[arg++] = "-o";
@@ -196,7 +226,7 @@ reset_ps(ps_t *dev)
dev->ack = false;
if (dev->pending) {
if (ghostscript_handle != NULL)
if ((dev->lang != LANG_RAW) && (ghostscript_handle != NULL))
convert_to_pdf(dev);
dev->filename[0] = 0;
@@ -220,8 +250,14 @@ write_buffer(ps_t *dev, bool finish)
if (dev->buffer_pos == 0)
return;
if (dev->filename[0] == 0)
plat_tempfile(dev->filename, NULL, dev->pcl ? ".pcl" : ".ps");
if (dev->filename[0] == 0) {
if (dev->lang == LANG_RAW)
plat_tempfile(dev->filename, NULL, ".raw");
else if (dev->pcl)
plat_tempfile(dev->filename, NULL, (dev->lang == LANG_PCL_6) ? ".pxl" : ".pcl");
else
plat_tempfile(dev->filename, NULL, ".ps");
}
strcpy(path, dev->printer_path);
path_slash(path);
@@ -244,7 +280,7 @@ write_buffer(ps_t *dev, bool finish)
dev->buffer_pos = 0;
if (finish) {
if (ghostscript_handle != NULL)
if ((dev->lang != LANG_RAW) && (ghostscript_handle != NULL))
convert_to_pdf(dev);
dev->filename[0] = 0;
@@ -262,7 +298,7 @@ timeout_timer(void *priv)
if (dev->buffer_pos != 0)
write_buffer(dev, true);
else if (dev->pending) {
if (ghostscript_handle != NULL)
if ((dev->lang != LANG_RAW) && (ghostscript_handle != NULL))
convert_to_pdf(dev);
dev->filename[0] = 0;
@@ -284,92 +320,115 @@ ps_write_data(uint8_t val, void *priv)
dev->data = (char) val;
}
static int
process_escape(ps_t *dev, int do_pjl)
{
int ret = 0;
if (dev->data == 0x1b)
dev->pcl_escape = 1;
else switch (dev->pcl_escape) {
case 1:
dev->pcl_escape = (dev->data == 0x25) ? 2 : 0;
break;
case 2:
dev->pcl_escape = (dev->data == 0x2d) ? 3 : 0;
break;
case 3:
dev->pcl_escape = (dev->data == 0x31) ? 4 : 0;
break;
case 4:
dev->pcl_escape = (dev->data == 0x32) ? 5 : 0;
break;
case 5:
dev->pcl_escape = (dev->data == 0x33) ? 6 : 0;
break;
case 6:
dev->pcl_escape = (dev->data == 0x34) ? 7 : 0;
break;
case 7:
dev->pcl_escape = (dev->data == 0x35) ? 8 : 0;
break;
case 8:
dev->pcl_escape = 0;
if (dev->data == 0x58) {
if (do_pjl)
dev->pjl = true;
dev->buffer[dev->buffer_pos++] = dev->data;
dev->buffer[dev->buffer_pos] = 0;
/* Wipe the slate clean so that there won't be a bogus empty page output to PDF. */
dev->pending = false;
ret = 1;
}
break;
}
return ret;
}
static void
process_data(ps_t *dev)
{
/* On PCL, check for escape sequences. */
if (dev->pcl) {
if (dev->pjl) {
dev->buffer[dev->buffer_pos++] = dev->data;
/* Filter out any PJL commands. */
if (dev->pjl_command && (dev->data == '\n')) {
dev->pjl_command = false;
if (!memcmp(&(dev->buffer[dev->pjl_command_start]), "@PJL ENTER LANGUAGE=PCL", 0x17))
dev->pjl = false;
else if (!memcmp(&(dev->buffer[dev->pjl_command_start]), "@PJL ENTER LANGUAGE=POSTSCRIPT", 0x1e))
fatal("Printing PostScript using the PCL printer is not (yet) supported!\n");
dev->buffer_pos = dev->pjl_command_start;
} else if (!dev->pjl_command && (dev->buffer_pos >= 0x05) && !memcmp(&(dev->buffer[dev->buffer_pos - 0x5]), "@PJL ", 0x05)) {
dev->pjl_command = true;
dev->pjl_command_start = dev->buffer_pos - 0x05;
}
dev->buffer[dev->buffer_pos] = 0;
return;
} else if (dev->data == 0x1b)
dev->pcl_escape = 1;
else switch (dev->pcl_escape) {
case 1:
dev->pcl_escape = (dev->data == 0x25) ? 2 : 0;
if (dev->data == 0x0e) {
dev->buffer[dev->buffer_pos++] = dev->data;
dev->buffer[dev->buffer_pos] = 0;
if (dev->buffer_pos > 2)
write_buffer(dev, true);
return;
}
break;
case 2:
dev->pcl_escape = (dev->data == 0x2d) ? 3 : 0;
break;
case 3:
dev->pcl_escape = (dev->data == 0x31) ? 4 : 0;
break;
case 4:
dev->pcl_escape = (dev->data == 0x32) ? 5 : 0;
break;
case 5:
dev->pcl_escape = (dev->data == 0x33) ? 6 : 0;
break;
case 6:
dev->pcl_escape = (dev->data == 0x34) ? 7 : 0;
break;
case 7:
dev->pcl_escape = (dev->data == 0x35) ? 8 : 0;
break;
case 8:
dev->pcl_escape = 0;
if (dev->data == 0x58)
dev->pjl = true;
break;
if (dev->lang == LANG_RAW) {
if ((dev->data == 0x1b) || (dev->pcl_escape > 0)) {
if (process_escape(dev, 0))
return;
}
} else if ((dev->data < 0x20) || (dev->data == 0x7f)) {
/* On PostScript, check for non-printable characters. */
switch (dev->data) {
/* The following characters are considered white-space
by the PostScript specification */
case '\t':
case '\n':
case '\f':
case '\r':
break;
} else {
/* On PCL, check for escape sequences. */
if (dev->pcl) {
if (dev->pjl) {
dev->buffer[dev->buffer_pos++] = dev->data;
/* Same with NUL, except we better change it to a space first */
case '\0':
dev->data = ' ';
break;
/* Filter out any PJL commands. */
if (dev->pjl_command && (dev->data == '\n')) {
dev->pjl_command = false;
if (!memcmp(&(dev->buffer[dev->pjl_command_start]), "@PJL ENTER LANGUAGE=PCL", 0x17))
dev->pjl = false;
else if (!memcmp(&(dev->buffer[dev->pjl_command_start]), "@PJL ENTER LANGUAGE=POSTSCRIPT", 0x1e))
fatal("Printing PostScript using the PCL printer is not (yet) supported!\n");
dev->buffer[dev->buffer_pos] = 0x00;
dev->buffer_pos = dev->pjl_command_start;
} else if (!dev->pjl_command && (dev->buffer_pos >= 0x05) && !memcmp(&(dev->buffer[dev->buffer_pos - 0x5]), "@PJL ", 0x05)) {
dev->pjl_command = true;
dev->pjl_command_start = dev->buffer_pos - 0x05;
} else if (!dev->pjl_command && (dev->data == 0x1b))
/* The universal exit code is also valid in PJL. */
dev->pcl_escape = 1;
/* Ctrl+D (0x04) marks the end of the document */
case '\4':
write_buffer(dev, true);
dev->buffer[dev->buffer_pos] = 0;
return;
} else if ((dev->data == 0x1b) || (dev->pcl_escape > 0)) {
if (process_escape(dev, 1))
return;
}
} else if ((dev->data < 0x20) || (dev->data == 0x7f)) {
/* On PostScript, check for non-printable characters. */
switch (dev->data) {
/* The following characters are considered white-space
by the PostScript specification */
case '\t':
case '\n':
case '\f':
case '\r':
break;
/* Don't bother with the others */
default:
return;
/* Same with NUL, except we better change it to a space first */
case '\0':
dev->data = ' ';
break;
/* Ctrl+D (0x04) marks the end of the document */
case '\4':
write_buffer(dev, true);
return;
/* Don't bother with the others */
default:
return;
}
}
}
@@ -460,34 +519,39 @@ ps_read_status(void *priv)
}
static void *
ps_init(void *lpt)
ps_init(const device_t *info)
{
ps_t *dev = (ps_t *) calloc(1, sizeof(ps_t));
gsapi_revision_t rev;
dev->ctrl = 0x04;
dev->lpt = lpt;
dev->pcl = false;
/* Try loading the DLL. */
ghostscript_handle = dynld_module(PATH_GHOSTSCRIPT_DLL, ghostscript_imports);
dev->lpt = lpt_attach(ps_write_data, ps_write_ctrl, ps_strobe, ps_read_status, NULL, NULL, NULL, dev);
dev->lang = device_get_config_int("language");
if (dev->lang != LANG_RAW) {
/* Try loading the DLL. */
ghostscript_handle = dynld_module(PATH_GHOSTSCRIPT_DLL, ghostscript_imports);
#ifdef PATH_GHOSTSCRIPT_DLL_ALT1
if (ghostscript_handle == NULL) {
ghostscript_handle = dynld_module(PATH_GHOSTSCRIPT_DLL_ALT1, ghostscript_imports);
if (ghostscript_handle == NULL) {
ghostscript_handle = dynld_module(PATH_GHOSTSCRIPT_DLL_ALT1, ghostscript_imports);
# ifdef PATH_GHOSTSCRIPT_DLL_ALT2
if (ghostscript_handle == NULL)
ghostscript_handle = dynld_module(PATH_GHOSTSCRIPT_DLL_ALT2, ghostscript_imports);
if (ghostscript_handle == NULL)
ghostscript_handle = dynld_module(PATH_GHOSTSCRIPT_DLL_ALT2, ghostscript_imports);
# endif
}
}
#endif
if (ghostscript_handle == NULL) {
ui_msgbox_header(MBX_ERROR, plat_get_string(STRING_GHOSTSCRIPT_ERROR_TITLE), plat_get_string(STRING_GHOSTSCRIPT_ERROR_DESC));
} else {
if (gsapi_revision(&rev, sizeof(rev)) == 0) {
pclog("Loaded %s, rev %ld (%ld)\n", rev.product, rev.revision, rev.revisiondate);
} else {
dynld_close(ghostscript_handle);
ghostscript_handle = NULL;
if (ghostscript_handle == NULL) {
ui_msgbox_header(MBX_ERROR, plat_get_string(STRING_GHOSTSCRIPT_ERROR_TITLE), plat_get_string(STRING_GHOSTSCRIPT_ERROR_DESC));
} else {
if (gsapi_revision(&rev, sizeof(rev)) == 0) {
pclog("Loaded %s, rev %ld (%ld)\n", rev.product, rev.revision, rev.revisiondate);
} else {
dynld_close(ghostscript_handle);
ghostscript_handle = NULL;
}
}
}
@@ -506,36 +570,40 @@ ps_init(void *lpt)
return dev;
}
#ifdef USE_PCL
static void *
pcl_init(void *lpt)
pcl_init(const device_t *info)
{
ps_t *dev = (ps_t *) calloc(1, sizeof(ps_t));
gsapi_revision_t rev;
dev->ctrl = 0x04;
dev->lpt = lpt;
dev->pcl = true;
/* Try loading the DLL. */
ghostscript_handle = dynld_module(PATH_GHOSTPCL_DLL, ghostscript_imports);
dev->lpt = lpt_attach(ps_write_data, ps_write_ctrl, ps_strobe, ps_read_status, NULL, NULL, NULL, dev);
dev->lang = device_get_config_int("language");
if (dev->lang != LANG_RAW) {
/* Try loading the DLL. */
ghostscript_handle = dynld_module(PATH_GHOSTPCL_DLL, ghostscript_imports);
#ifdef PATH_GHOSTPCL_DLL_ALT1
if (ghostscript_handle == NULL) {
ghostscript_handle = dynld_module(PATH_GHOSTPCL_DLL_ALT1, ghostscript_imports);
if (ghostscript_handle == NULL) {
ghostscript_handle = dynld_module(PATH_GHOSTPCL_DLL_ALT1, ghostscript_imports);
# ifdef PATH_GHOSTPCL_DLL_ALT2
if (ghostscript_handle == NULL)
ghostscript_handle = dynld_module(PATH_GHOSTPCL_DLL_ALT2, ghostscript_imports);
if (ghostscript_handle == NULL)
ghostscript_handle = dynld_module(PATH_GHOSTPCL_DLL_ALT2, ghostscript_imports);
# endif
}
}
#endif
if (ghostscript_handle == NULL) {
ui_msgbox_header(MBX_ERROR, plat_get_string(STRING_GHOSTPCL_ERROR_TITLE), plat_get_string(STRING_GHOSTPCL_ERROR_DESC));
} else {
if (gsapi_revision(&rev, sizeof(rev)) == 0) {
pclog("Loaded %s, rev %ld (%ld)\n", rev.product, rev.revision, rev.revisiondate);
if (ghostscript_handle == NULL) {
ui_msgbox_header(MBX_ERROR, plat_get_string(STRING_GHOSTPCL_ERROR_TITLE), plat_get_string(STRING_GHOSTPCL_ERROR_DESC));
} else {
dynld_close(ghostscript_handle);
ghostscript_handle = NULL;
if (gsapi_revision(&rev, sizeof(rev)) == 0) {
pclog("Loaded %s, rev %ld (%ld)\n", rev.product, rev.revision, rev.revisiondate);
} else {
dynld_close(ghostscript_handle);
ghostscript_handle = NULL;
}
}
}
@@ -553,7 +621,6 @@ pcl_init(void *lpt)
return dev;
}
#endif
static void
ps_close(void *priv)
@@ -574,36 +641,75 @@ ps_close(void *priv)
free(dev);
}
const lpt_device_t lpt_prt_ps_device = {
.name = "Generic PostScript Printer",
.internal_name = "postscript",
.init = ps_init,
.close = ps_close,
.write_data = ps_write_data,
.write_ctrl = ps_write_ctrl,
.strobe = ps_strobe,
.read_status = ps_read_status,
.read_ctrl = NULL,
.epp_write_data = NULL,
.epp_request_read = NULL,
.priv = NULL,
.lpt = NULL
// clang-format off
static const device_config_t lpt_prt_ps_config[] = {
{
.name = "language",
.description = "Language",
.type = CONFIG_SELECTION,
.default_string = NULL,
.default_int = LANG_PS,
.file_filter = NULL,
.spinner = { 0 },
.selection = {
{ .description = "Raw", .value = LANG_RAW },
{ .description = "PDF (PostScript)", .value = LANG_PS },
{ .description = "" }
},
.bios = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
// clang-format off
static const device_config_t lpt_prt_pcl_config[] = {
{
.name = "language",
.description = "Language",
.type = CONFIG_SELECTION,
.default_string = NULL,
.default_int = LANG_PCL_5E,
.file_filter = NULL,
.spinner = { 0 },
.selection = {
{ .description = "Raw", .value = LANG_RAW },
{ .description = "PDF (PCL 5e)", .value = LANG_PCL_5E },
{ .description = "PDF (PCL 5c)", .value = LANG_PCL_5C },
{ .description = "PDF (HP-RTL)", .value = LANG_HP_RTL },
{ .description = "PDF (PCL 6)", .value = LANG_PCL_6 },
{ .description = "" }
},
.bios = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t lpt_prt_ps_device = {
.name = "Generic PostScript Printer",
.internal_name = "postscript",
.flags = DEVICE_LPT,
.local = 0,
.init = ps_init,
.close = ps_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = lpt_prt_ps_config
};
#ifdef USE_PCL
const lpt_device_t lpt_prt_pcl_device = {
.name = "Generic PCL5e Printer",
.internal_name = "pcl",
.init = pcl_init,
.close = ps_close,
.write_data = ps_write_data,
.write_ctrl = ps_write_ctrl,
.strobe = ps_strobe,
.read_status = ps_read_status,
.read_ctrl = NULL,
.epp_write_data = NULL,
.epp_request_read = NULL,
.priv = NULL,
.lpt = NULL
const device_t lpt_prt_pcl_device = {
.name = "Generic PCL Printer",
.internal_name = "pcl",
.flags = DEVICE_LPT,
.local = 0,
.init = pcl_init,
.close = ps_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = lpt_prt_pcl_config
};
#endif

27
src/printer/prt_text.c
View File

@@ -455,13 +455,13 @@ read_status(void *priv)
}
static void *
prnt_init(void *lpt)
prnt_init(const device_t *info)
{
/* Initialize a device instance. */
prnt_t *dev = (prnt_t *) calloc(1, sizeof(prnt_t));
dev->ctrl = 0x04;
dev->lpt = lpt;
dev->lpt = lpt_attach(write_data, write_ctrl, strobe, read_status, NULL, NULL, NULL, dev);
/* Initialize parameters. */
reset_printer(dev);
@@ -523,13 +523,13 @@ static const device_config_t lpt_prt_text_config[] = {
#endif
// clang-format on
const device_t prt_text_device = {
const device_t lpt_prt_text_device = {
.name = "Generic Text Printer",
.internal_name = "text_prt",
.flags = DEVICE_LPT,
.local = 0,
.init = NULL,
.close = NULL,
.init = prnt_init,
.close = prnt_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
@@ -540,20 +540,3 @@ const device_t prt_text_device = {
.config = NULL
#endif
};
const lpt_device_t lpt_prt_text_device = {
.name = "Generic Text Printer",
.internal_name = "text_prt",
.init = prnt_init,
.close = prnt_close,
.write_data = write_data,
.write_ctrl = write_ctrl,
.strobe = strobe,
.read_status = read_status,
.read_ctrl = NULL,
.epp_write_data = NULL,
.epp_request_read = NULL,
.priv = NULL,
.lpt = NULL,
.cfgdevice = (device_t *) &prt_text_device
};

3
src/qt/languages/86box.pot
View File

@@ -3017,3 +3017,6 @@ msgstr ""
msgid "To change the system directory, stop all running machines."
msgstr ""
msgid "Raw"
msgstr ""

9
src/qt/languages/ca-ES.po
View File

@@ -3016,10 +3016,13 @@ msgid "&Allow recompilation"
msgstr "&Permetre recompilació"
msgid "&Fast forward"
msgstr ""
msgstr "&Avançar ràpidament"
msgid "Fast forward"
msgstr ""
msgstr "Avançar ràpidament"
msgid "To change the system directory, stop all running machines."
msgstr ""
msgstr "Per canviar el directori del sistema, atureu totes les màquines en funcionament."
msgid "Raw"
msgstr "En brut"

11
src/qt/languages/cs-CZ.po
View File

@@ -1,6 +1,6 @@
msgid ""
msgstr ""
"PO-Revision-Date: 2026-01-02 21:56+0000\n"
"PO-Revision-Date: 2026-01-21 07:40+0000\n"
"Last-Translator: David Hrdlička <hrdlickadavid@outlook.com>\n"
"Language-Team: Czech <https://weblate.86box.net/projects/86box/86box/cs/>\n"
"Language: cs-CZ\n"
@@ -3016,10 +3016,13 @@ msgid "&Allow recompilation"
msgstr "&Povolit rekompilaci"
msgid "&Fast forward"
msgstr ""
msgstr "&Zrychlit"
msgid "Fast forward"
msgstr ""
msgstr "Zrychlit"
msgid "To change the system directory, stop all running machines."
msgstr ""
msgstr "Před změnou systémového adresáře nejprve zastavte všechny běžící počítače."
msgid "Raw"
msgstr "Surový"

9
src/qt/languages/de-DE.po
View File

@@ -3016,10 +3016,13 @@ msgid "&Allow recompilation"
msgstr "Recompilierung &zulassen"
msgid "&Fast forward"
msgstr ""
msgstr "&Schnellvorlauf"
msgid "Fast forward"
msgstr ""
msgstr "Schnellvorlauf"
msgid "To change the system directory, stop all running machines."
msgstr ""
msgstr "Um das Systemverzeichnis zu ändern, stoppen Sie alle laufenden Maschinen."
msgid "Raw"
msgstr "Roh"

71
src/qt/languages/el-GR.po
View File

@@ -1,6 +1,6 @@
msgid ""
msgstr ""
"PO-Revision-Date: 2026-01-10 12:56+0000\n"
"PO-Revision-Date: 2026-01-26 17:57+0000\n"
"Last-Translator: DimMan88 <dimman88@hotmail.com>\n"
"Language-Team: Greek <https://weblate.86box.net/projects/86box/86box/el/>\n"
"Language: el-GR\n"
@@ -2919,24 +2919,26 @@ msgstr "Επιτυχής διαγραφή των περιεχομένων NVRAM
msgid "An error occurred trying to wipe the NVRAM contents of the virtual machine \"%1\""
msgstr ""
"Ένα σφάλμα προέκυψε κατά την εκκαθάριση των περιεχομένων της NVRAM της "
"εικονικής μηχανής \"%1\""
msgid "%1 VM Manager"
msgstr ""
msgstr "%1 VM Manager"
msgid "%n disk(s)"
msgstr ""
msgstr "%n δίσκος(οι)"
msgid "Unknown Status"
msgstr ""
msgstr "Άγνωστη Κατάσταση"
msgid "No Machines Found!"
msgstr ""
msgstr "Δεν βρέθηκαν μηχανές!"
msgid "Check for updates on startup"
msgstr "Έλεγχος για ενημερώσεις κατα την εκκίνηση"
msgid "Unable to determine release information"
msgstr ""
msgstr "Αδυναμία προσδιορισμού πληροφοριών έκδοσης"
msgid "There was an error checking for updates:\n\n%1\n\nPlease try again later."
msgstr ""
@@ -2947,82 +2949,84 @@ msgstr ""
"Παρακαλώ προσπαθήστε ξανά αργότερα."
msgid "Update check complete"
msgstr ""
msgstr "Ο έλεγχος ενημερώσεων ολοκληρώθηκε"
msgid "stable"
msgstr ""
msgstr "σταθερή"
msgid "beta"
msgstr ""
msgstr "δοκιμαστική"
msgid "You are running the latest %1 version of 86Box: %2"
msgstr ""
msgstr "Τρέχετε την τελευταία %1 έκδοση του 86Box: %2"
msgid "version"
msgstr ""
msgstr "έκδοση"
msgid "build"
msgstr ""
msgstr "build"
msgid "You are currently running version <b>%1</b>."
msgstr ""
msgstr "Τρέχετε την έκδοση <b>%1</b>."
msgid "<b>Version %1</b> is now available."
msgstr ""
msgstr "<b>Έκδοση %1</b> είναι διαθέσιμη."
msgid "You are currently running build <b>%1</b>."
msgstr ""
msgstr "Τρέχετε το build <b>%1</b>."
msgid "<b>Build %1</b> is now available."
msgstr ""
msgstr "<b>Build %1</b> είναι τώρα διαθέσιμο."
msgid "Would you like to visit the download page?"
msgstr ""
msgstr "Επιθυμείτε να επισκεφθείτε την σελίδα λήψεων;"
msgid "Visit download page"
msgstr ""
msgstr "Επίσκεψη σελίδας λήψεων"
msgid "Update check"
msgstr ""
msgstr "Έλεγχος ενημερώσεων"
msgid "Checking for updates…"
msgstr "Έλεγχος για ενημερώσεις…"
msgid "86Box Update"
msgstr ""
msgstr "Ενημέρωση 86Box"
msgid "Release notes:"
msgstr ""
msgstr "Σημειώσεις έκδοσης:"
msgid "%1 Hz"
msgstr ""
msgstr "%1 Hz"
msgid "Virtual machine crash"
msgstr ""
msgstr "Σφάλμα εικονικής μηχανής"
msgid "The virtual machine \"%1\"'s process has unexpectedly terminated with exit code %2."
msgstr ""
"Η διεργασία της εικονικής μηχανής \"%1\" τερματίστηκε απροσδόκητα με κωδικό "
"εξόδου %2."
msgid "The system will not be added."
msgstr ""
msgstr "Το σύστημα δεν θα προστεθεί."
msgid "&Update mouse every CPU frame"
msgstr "&Ανανέωση ποντικιού ανα καρέ CPU"
msgid "Hue"
msgstr ""
msgstr "Απόχρωση"
msgid "Saturation"
msgstr ""
msgstr "Κορεσμός"
msgid "Contrast"
msgstr ""
msgstr "Αντίθεση"
msgid "Brightness"
msgstr ""
msgstr "Φωτεινότητα"
msgid "Sharpness"
msgstr ""
msgstr "Οξύτητα"
msgid "&CGA composite settings…"
msgstr "Ρυθμίσεις &CGA composite…"
@@ -3073,10 +3077,13 @@ msgid "&Allow recompilation"
msgstr "&Να επιτρέπεται ανασύνταξη"
msgid "&Fast forward"
msgstr ""
msgstr "&Γρήγορα μπροστά"
msgid "Fast forward"
msgstr ""
msgstr "Γρήγορα μπροστά"
msgid "To change the system directory, stop all running machines."
msgstr ""
msgstr "Για να αλλάξετε τον κατάλογο συστήματος, σταματήστε πρώτα όλες τις μηχανές σε λειτουργία."
msgid "Raw"
msgstr "Αρχικος"

9
src/qt/languages/es-ES.po
View File

@@ -3016,10 +3016,13 @@ msgid "&Allow recompilation"
msgstr "&Permitir recompilación"
msgid "&Fast forward"
msgstr ""
msgstr "&Avance rápido"
msgid "Fast forward"
msgstr ""
msgstr "Avance rápido"
msgid "To change the system directory, stop all running machines."
msgstr ""
msgstr "Para cambiar el directorio del sistema, detenga todas las máquinas en funcionamiento."
msgid "Raw"
msgstr "Plano"

9
src/qt/languages/fi-FI.po
View File

@@ -3016,10 +3016,13 @@ msgid "&Allow recompilation"
msgstr "&Salli uudelleenkääntäminen"
msgid "&Fast forward"
msgstr ""
msgstr "&Nopea eteneminen"
msgid "Fast forward"
msgstr ""
msgstr "Nopea eteneminen"
msgid "To change the system directory, stop all running machines."
msgstr ""
msgstr "Järjestelmähakemiston muuttamiseksi pysäytä kaikki käynnissä olevat koneet."
msgid "Raw"
msgstr "Raaka"

9
src/qt/languages/fr-FR.po
View File

@@ -3016,10 +3016,13 @@ msgid "&Allow recompilation"
msgstr "&Permettre la recompilation"
msgid "&Fast forward"
msgstr ""
msgstr "&Avance rapide"
msgid "Fast forward"
msgstr ""
msgstr "Avance rapide"
msgid "To change the system directory, stop all running machines."
msgstr ""
msgstr "Pour modifier le répertoire système, arrêtez toutes les machines en cours d'exécution."
msgid "Raw"
msgstr "Brut"

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