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Amazingly, if I make a 32-bit write to SVGA, it probably shouldn't write to four different CRTC registers.....

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This commit is contained in:
starfrost013
2025-07-17 19:16:39 +01:00
parent 0adba2cabe
commit 5fc903fb48
3 changed files with 15 additions and 9 deletions
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16
src/video/nv/nv3/nv3_core.c
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@@ -197,7 +197,9 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv)
nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
nv3_svga_write(real_address, val & 0xFF, nv3);
nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3);
if (val > 0xFF)
nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3);
return;
}
@@ -225,9 +227,15 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv)
nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
nv3_svga_write(real_address, val & 0xFF, nv3);
nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3);
nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3);
nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3);
if (val > 0xFF)
nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3);
if (val > 0xFFFF)
nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3);
if (val > 0xFFFFFF)
nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3);
return;
}

5
src/video/nv/nv3/render/nv3_render_core.c
View File

@@ -454,8 +454,7 @@ void nv3_render_write_pixel_to_buffer(nv3_coord_16_t position, uint32_t color, n
return;
}
// convert to 16bpp
// forcing it to render in 15bpp fixes it,
// convert to 15bpp or 16bpp based on if we are in 16bpp mode
rop_dst = vram_16[pixel_addr_vram];
@@ -497,8 +496,6 @@ void nv3_render_write_pixel(nv3_coord_16_t position, uint32_t color, nv3_grobj_t
nv3_render_write_pixel_to_buffer(position, color, grobj, 2);
if (dst_buffer & (pgraph_dest_buffer3))
nv3_render_write_pixel_to_buffer(position, color, grobj, 3);
}
/* Ensure the correct monitor size */

3
src/video/nv/nv3/subsystems/nv3_pfifo.c
View File

@@ -742,7 +742,7 @@ void nv3_pfifo_cache0_pull(void)
// Tell the CPU if we found a software method and turn off cache pulling
if (!(current_context & 0x800000))
{
nv_log("The object in CACHE0 is a software object\n");
nv_log_verbose_only("The object in CACHE0 is a software object\n");
nv3->pfifo.cache0_settings.pull0 |= NV3_PFIFO_CACHE0_PULL0_SOFTWARE_METHOD;
nv3->pfifo.cache0_settings.pull0 &= ~NV3_PFIFO_CACHE0_PULL0_ENABLED;
@@ -923,6 +923,7 @@ void nv3_pfifo_cache1_pull(void)
return; // interrupt was fired, and we went to ramro
}
// should this be obtained from the grobj? Test on real nv3 h/w after drawrect.nvp works
uint32_t current_context = nv3->pfifo.cache1_settings.context[current_subchannel]; // get the current subchannel
uint8_t class_id = ((nv3_ramin_context_t*)&current_context)->class_id;