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Merge pull request #3428 from jriwanek-forks/sonarlint

Browse Source 
Next round of sonarlint cleanups
This commit is contained in:
Miran Grča
2023-06-27 01:34:57 +02:00
committed by GitHub
parent 2fe3bcd5d2 21adfd4d50
commit 5aa96a63d0
176 changed files with 2791 additions and 1377 deletions
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12
src/cdrom/cdrom.c
View File

@@ -422,6 +422,8 @@ cdrom_seek(cdrom_t *dev, uint32_t pos, uint8_t vendor_type)
case 0x80:
pos = bcd2bin((pos >> 24) & 0xff);
break;
default:
break;
}
dev->seek_pos = pos;
@@ -611,6 +613,8 @@ cdrom_audio_track_search(cdrom_t *dev, uint32_t pos, int type, uint8_t playbit)
}
dev->seek_pos = (pos >> 24) & 0xff;
break;
default:
break;
}
/* Unlike standard commands, if there's a data track on an Audio CD (mixed mode)
@@ -652,6 +656,8 @@ cdrom_audio_play_toshiba(cdrom_t *dev, uint32_t pos, int type)
}
dev->cd_end = pos;
break;
default:
break;
}
cdrom_log("Toshiba/NEC Play Audio: MSF = %06x, type = %02x, cdstatus = %02x\n", pos, type, dev->cd_status);
@@ -698,6 +704,8 @@ cdrom_audio_scan(cdrom_t *dev, uint32_t pos, int type)
case 0x80:
dev->seek_pos = (pos >> 24) & 0xff;
break;
default:
break;
}
/* Do this at this point, since it's at this point that we know the
@@ -1331,13 +1339,15 @@ cdrom_read_disc_info_toc(cdrom_t *dev, unsigned char *b, unsigned char track, in
b[2] = 0;
b[3] = 0;
break;
default:
break;
}
return 1;
}
static int
track_type_is_valid(uint8_t id, int type, int flags, int audio, int mode2)
track_type_is_valid(UNUSED(uint8_t id), int type, int flags, int audio, int mode2)
{
if (!(flags & 0x70) && (flags & 0xf8)) { /* 0x08/0x80/0x88 are illegal modes */
cdrom_log("CD-ROM %i: [Any Mode] 0x08/0x80/0x88 are illegal modes\n", id);

4
src/cdrom/cdrom_image_backend.c
View File

@@ -283,7 +283,7 @@ cdi_get_audio_track_pre(cd_img_t *cdi, int track)
/* This replaces both Info and EndInfo, they are specified by a variable. */
int
cdi_get_audio_track_info(cd_img_t *cdi, int end, int track, int *track_num, TMSF *start, uint8_t *attr)
cdi_get_audio_track_info(cd_img_t *cdi, UNUSED(int end), int track, int *track_num, TMSF *start, uint8_t *attr)
{
track_t *trk = &cdi->tracks[track - 1];
int pos = trk->start + 150;
@@ -302,7 +302,7 @@ cdi_get_audio_track_info(cd_img_t *cdi, int end, int track, int *track_num, TMSF
}
int
cdi_get_audio_track_info_lba(cd_img_t *cdi, int end, int track, int *track_num, uint32_t *start, uint8_t *attr)
cdi_get_audio_track_info_lba(cd_img_t *cdi, UNUSED(int end), int track, int *track_num, uint32_t *start, uint8_t *attr)
{
track_t *trk = &cdi->tracks[track - 1];

6
src/cdrom/cdrom_image_viso.c
View File

@@ -114,8 +114,10 @@ typedef struct _viso_entry_ {
} viso_entry_t;
typedef struct {
uint64_t vol_size_offsets[2], pt_meta_offsets[2];
int format, use_version_suffix : 1;
uint64_t vol_size_offsets[2];
uint64_t pt_meta_offsets[2];
int format;
int use_version_suffix : 1;
size_t metadata_sectors, all_sectors, entry_map_size, sector_size, file_fifo_pos;
uint8_t *metadata;

16
src/cdrom/cdrom_mitsumi.c
View File

@@ -242,9 +242,11 @@ mitsumi_cdrom_in(uint16_t port, void *priv)
ret |= FLAG_NOSTAT;
pclog("Read port 1: ret = %02x\n", ret | FLAG_UNK);
return ret | FLAG_UNK;
default:
break;
}
return (0xff);
return 0xff;
}
static void
@@ -283,6 +285,8 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
case 0x10:
dev->enable_irq = val;
break;
default:
break;
}
dev->cmdbuf[1] = 0;
dev->cmdbuf_count = 2;
@@ -297,6 +301,8 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
if (dev->conf == 1)
dev->cmdrd_count++;
break;
default:
break;
}
break;
case CMD_READ1X:
@@ -320,8 +326,12 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
case 3:
dev->readmsf |= CD_DCB(val) << ((dev->cmdrd_count - 3) << 3);
break;
default:
break;
}
break;
default:
break;
}
if (!dev->cmdrd_count)
dev->stat = cdrom.host_drive ? (STAT_READY | (dev->change ? STAT_CHANGE : 0)) : 0;
@@ -406,11 +416,13 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
case 1:
mitsumi_cdrom_reset(dev);
break;
default:
break;
}
}
static void *
mitsumi_cdrom_init(const device_t *info)
mitsumi_cdrom_init(UNUSED(const device_t *info))
{
mcd_t *dev;

3
src/chipset/82c100.c
View File

@@ -28,6 +28,7 @@
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/rom.h>
#include <86box/chipset.h>
@@ -349,7 +350,7 @@ ct_82c100_close(void *priv)
}
static void *
ct_82c100_init(const device_t *info)
ct_82c100_init(UNUSED(const device_t *info))
{
ct_82c100_t *dev;

5
src/chipset/acc2168.c
View File

@@ -30,6 +30,7 @@
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#define ENABLED_SHADOW (MEM_READ_INTERNAL | ((dev->regs[0x02] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL))
@@ -158,6 +159,8 @@ acc2168_write(uint16_t addr, uint8_t val, void *p)
break;
}
break;
default:
break;
}
}
@@ -178,7 +181,7 @@ acc2168_close(void *priv)
}
static void *
acc2168_init(const device_t *info)
acc2168_init(UNUSED(const device_t *info))
{
acc2168_t *dev = (acc2168_t *) malloc(sizeof(acc2168_t));
memset(dev, 0, sizeof(acc2168_t));

8
src/chipset/ali1429.c
View File

@@ -239,12 +239,16 @@ ali1429_write(uint16_t addr, uint8_t val, void *priv)
case 6:
cpu_set_isa_speed(cpu_busspeed / 12);
break;
default:
break;
}
break;
case 0x21 ... 0x27:
dev->regs[dev->index] = val;
break;
default:
break;
}
/* M1429G Only Registers */
@@ -260,10 +264,14 @@ ali1429_write(uint16_t addr, uint8_t val, void *priv)
case 0x57:
dev->reg_57h = val;
break;
default:
break;
}
}
}
break;
default:
break;
}
}

25
src/chipset/ali1435.c
View File

@@ -31,6 +31,7 @@
#include <86box/timer.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
@@ -188,11 +189,12 @@ ali1435_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x23:
/* #ifdef ENABLE_ALI1435_LOG
if (dev->index != 0x03)
ali1435_log("M1435: dev->regs[%02x] = %02x\n", dev->index, val);
#endif */
#if 0
#ifdef ENABLE_ALI1435_LOG
if (dev->index != 0x03)
ali1435_log("M1435: dev->regs[%02x] = %02x\n", dev->index, val);
#endif
#endif
if (dev->index == 0x03)
dev->cfg_locked = (val != 0x69);
@@ -216,9 +218,14 @@ ali1435_write(uint16_t addr, uint8_t val, void *priv)
case 0x07:
dev->regs[dev->index] = val;
break;
default:
break;
}
}
break;
default:
break;
}
}
@@ -277,7 +284,7 @@ ali1435_close(void *p)
}
static void *
ali1435_init(const device_t *info)
ali1435_init(UNUSED(const device_t *info))
{
ali1435_t *dev = (ali1435_t *) malloc(sizeof(ali1435_t));
memset(dev, 0, sizeof(ali1435_t));
@@ -294,10 +301,12 @@ ali1435_init(const device_t *info)
ali1435_reset(dev);
/* pci_set_irq_level(PCI_INTA, 0);
#if 0
pci_set_irq_level(PCI_INTA, 0);
pci_set_irq_level(PCI_INTB, 0);
pci_set_irq_level(PCI_INTC, 0);
pci_set_irq_level(PCI_INTD, 0); */
pci_set_irq_level(PCI_INTD, 0);
#endif
return dev;
}

26
src/chipset/ali1489.c
View File

@@ -35,6 +35,7 @@
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
@@ -126,6 +127,8 @@ ali1489_smram_recalc(ali1489_t *dev)
else
smram_enable(dev->smram, 0x38000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1);
break;
default:
break;
}
if ((dev->regs[0x19] & 0x31) == 0x11) {
@@ -320,6 +323,8 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
case 0x30:
picint(1 << 10);
break;
default:
break;
}
dev->regs[0x35] |= 0x0e;
} else if (!(val & 0x10))
@@ -381,6 +386,8 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
/* TODO: When doing the IRQ and PCI IRQ rewrite, bits 0 to 3 toggle edge/level output. */
dev->regs[dev->index] = val;
break;
default:
break;
}
if (dev->index != 0x03) {
@@ -390,6 +397,9 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[dev->index] = val;
break;
default:
break;
}
}
@@ -409,6 +419,8 @@ ali1489_read(uint16_t addr, void *priv)
else
ret = dev->regs[dev->index];
break;
default:
break;
}
ali1489_log("M1489: dev->regs[%02x] (%02x)\n", dev->index, ret);
@@ -417,7 +429,7 @@ ali1489_read(uint16_t addr, void *priv)
}
static void
ali1489_pci_write(int func, int addr, uint8_t val, void *priv)
ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
ali1489_t *dev = (ali1489_t *) priv;
@@ -433,11 +445,13 @@ ali1489_pci_write(int func, int addr, uint8_t val, void *priv)
case 0x07:
dev->pci_conf[0x07] &= ~(val & 0xb8);
break;
default:
break;
}
}
static uint8_t
ali1489_pci_read(int func, int addr, void *priv)
ali1489_pci_read(UNUSED(int func), int addr, void *priv)
{
ali1489_t *dev = (ali1489_t *) priv;
uint8_t ret = 0xff;
@@ -529,8 +543,12 @@ ali1489_ide_write(uint16_t addr, uint8_t val, void *priv)
dev->ide_regs[dev->ide_index] = val;
ali1489_ide_handler(dev);
break;
default:
break;
}
break;
default:
break;
}
}
@@ -548,6 +566,8 @@ ali1489_ide_read(uint16_t addr, void *priv)
ret = dev->ide_regs[dev->ide_index];
ali1489_log("M1489-IDE: dev->regs[%02x] (%02x)\n", dev->ide_index, ret);
break;
default:
break;
}
return ret;
@@ -576,7 +596,7 @@ ali1489_close(void *priv)
}
static void *
ali1489_init(const device_t *info)
ali1489_init(UNUSED(const device_t *info))
{
ali1489_t *dev = (ali1489_t *) malloc(sizeof(ali1489_t));
memset(dev, 0, sizeof(ali1489_t));

20
src/chipset/ali1531.c
View File

@@ -28,6 +28,7 @@
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/smram.h>
#include <86box/spd.h>
@@ -82,6 +83,8 @@ ali1531_smram_recalc(uint8_t val, ali1531_t *dev)
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
break;
default:
break;
}
}
@@ -89,7 +92,7 @@ ali1531_smram_recalc(uint8_t val, ali1531_t *dev)
}
static void
ali1531_shadow_recalc(int cur_reg, ali1531_t *dev)
ali1531_shadow_recalc(UNUSED(int cur_reg), ali1531_t *dev)
{
int bit;
int r_reg;
@@ -124,7 +127,7 @@ ali1531_shadow_recalc(int cur_reg, ali1531_t *dev)
}
static void
ali1531_write(int func, int addr, uint8_t val, void *priv)
ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
ali1531_t *dev = (ali1531_t *) priv;
@@ -228,8 +231,10 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
case 0x57: /* H2PO */
dev->pci_conf[addr] = val & 0x60;
/* Find where the Shut-down Special cycle is initiated. */
// if (!(val & 0x20))
// outb(0x92, 0x01);
#if 0
if (!(val & 0x20))
outb(0x92, 0x01);
#endif
break;
case 0x58:
@@ -288,11 +293,14 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
case 0x83:
dev->pci_conf[addr] = val & 0x10;
break;
default:
break;
}
}
static uint8_t
ali1531_read(int func, int addr, void *priv)
ali1531_read(UNUSED(int func), int addr, void *priv)
{
ali1531_t *dev = (ali1531_t *) priv;
uint8_t ret = 0xff;
@@ -361,7 +369,7 @@ ali1531_close(void *priv)
}
static void *
ali1531_init(const device_t *info)
ali1531_init(UNUSED(const device_t *info))
{
ali1531_t *dev = (ali1531_t *) malloc(sizeof(ali1531_t));
memset(dev, 0, sizeof(ali1531_t));

22
src/chipset/ali1541.c
View File

@@ -28,6 +28,7 @@
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/smram.h>
#include <86box/spd.h>
@@ -83,6 +84,8 @@ ali1541_smram_recalc(uint8_t val, ali1541_t *dev)
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
break;
default:
break;
}
}
@@ -90,7 +93,7 @@ ali1541_smram_recalc(uint8_t val, ali1541_t *dev)
}
static void
ali1541_shadow_recalc(int cur_reg, ali1541_t *dev)
ali1541_shadow_recalc(UNUSED(int cur_reg), ali1541_t *dev)
{
int bit;
int r_reg;
@@ -131,8 +134,8 @@ ali1541_mask_bar(ali1541_t *dev)
uint32_t mask;
switch (dev->pci_conf[0xbc] & 0x0f) {
case 0x00:
default:
case 0x00:
mask = 0x00000000;
break;
case 0x01:
@@ -170,7 +173,7 @@ ali1541_mask_bar(ali1541_t *dev)
}
static void
ali1541_write(int func, int addr, uint8_t val, void *priv)
ali1541_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
ali1541_t *dev = (ali1541_t *) priv;
@@ -367,8 +370,10 @@ ali1541_write(int func, int addr, uint8_t val, void *priv)
case 0x87: /* H2PO */
dev->pci_conf[addr] = val;
/* Find where the Shut-down Special cycle is initiated. */
// if (!(val & 0x20))
// outb(0x92, 0x01);
#if 0
if (!(val & 0x20))
outb(0x92, 0x01);
#endif
break;
case 0x88:
@@ -546,11 +551,14 @@ ali1541_write(int func, int addr, uint8_t val, void *priv)
case 0xf7:
dev->pci_conf[addr] = val & 0x43;
break;
default:
break;
}
}
static uint8_t
ali1541_read(int func, int addr, void *priv)
ali1541_read(UNUSED(int func), int addr, void *priv)
{
ali1541_t *dev = (ali1541_t *) priv;
uint8_t ret = 0xff;
@@ -628,7 +636,7 @@ ali1541_close(void *priv)
}
static void *
ali1541_init(const device_t *info)
ali1541_init(UNUSED(const device_t *info))
{
ali1541_t *dev = (ali1541_t *) malloc(sizeof(ali1541_t));
memset(dev, 0, sizeof(ali1541_t));

33
src/chipset/ali1543.c
View File

@@ -36,6 +36,7 @@
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/sio.h>
#include <86box/smbus.h>
@@ -95,7 +96,7 @@ ali1543_log(const char *fmt, ...)
#endif
static void
ali1533_ddma_handler(ali1543_t *dev)
ali1533_ddma_handler(UNUSED(ali1543_t *dev))
{
/* TODO: Find any documentation that actually explains the ALi southbridge DDMA mapping. */
}
@@ -168,6 +169,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 6:
cpu_set_isa_pci_div((val & 7) + 1);
break;
default:
break;
}
break;
@@ -227,8 +230,10 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val;
ali1543_log("SIRQI = IRQ %i; SIRQII = IRQ %i\n", ali1533_irq_routing[(val >> 4) & 0x0f], ali1533_irq_routing[val & 0x0f]);
// pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]);
// pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
#if 0
pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
#endif
}
break;
@@ -293,6 +298,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x30:
dev->ide_slot = 0x0d; /* A24 = slot 13 */
break;
default:
break;
}
pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_IDE, ((int) dev->ide_slot) + dev->offset);
ali1543_log("IDE slot = %02X (A%0i)\n", ((int) dev->ide_slot) + dev->offset, dev->ide_slot + 11);
@@ -364,6 +371,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x0c:
dev->pmu_slot = 0x04; /* A15 = slot 04 */
break;
default:
break;
}
pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_PMU, ((int) dev->pmu_slot) + dev->offset);
ali1543_log("PMU slot = %02X (A%0i)\n", ((int) dev->pmu_slot) + dev->offset, dev->pmu_slot + 11);
@@ -380,6 +389,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x03:
dev->usb_slot = 0x01; /* A12 = slot 01 */
break;
default:
break;
}
pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_USB, ((int) dev->usb_slot) + dev->offset);
ali1543_log("USB slot = %02X (A%0i)\n", ((int) dev->usb_slot) + dev->offset, dev->usb_slot + 11);
@@ -437,6 +448,9 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->pmu_dev_enable = 0;
}
break;
default:
break;
}
}
@@ -509,6 +523,8 @@ ali5229_ide_irq_handler(ali1543_t *dev)
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2);
break;
default:
break;
}
}
@@ -546,6 +562,8 @@ ali5229_ide_irq_handler(ali1543_t *dev)
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2);
break;
default:
break;
}
}
}
@@ -857,6 +875,9 @@ ali5229_write(int func, int addr, uint8_t val, void *priv)
case 0x5f:
dev->ide_conf[addr] = val & 0x7f;
break;
default:
break;
}
}
@@ -942,6 +963,9 @@ ali5237_write(int func, int addr, uint8_t val, void *priv)
if (!(dev->usb_conf[0x42] & 0x10))
dev->usb_conf[addr] = val;
break;
default:
break;
}
}
@@ -1426,6 +1450,9 @@ ali7101_read(int func, int addr, void *priv)
case 0x74:
dev->pmu_conf[addr] &= 0xcc;
break;
default:
break;
}
}
}

18
src/chipset/ali1621.c
View File

@@ -28,6 +28,7 @@
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/smram.h>
#include <86box/spd.h>
@@ -111,6 +112,8 @@ ali1621_smram_recalc(uint8_t val, ali1621_t *dev)
case 0x30: /* Protect. */
access_smm |= ACCESS_SMRAM_R;
break;
default:
break;
}
}
@@ -122,6 +125,8 @@ ali1621_smram_recalc(uint8_t val, ali1621_t *dev)
case 0x30: /* Protect. */
access_smm |= ACCESS_SMRAM_W;
break;
default:
break;
}
smram_enable(dev->smram[0], 0xa0000, 0xa0000, 0x20000, ((val & 0x30) == 0x10), (val & 0x30));
@@ -137,7 +142,7 @@ ali1621_smram_recalc(uint8_t val, ali1621_t *dev)
}
static void
ali1621_shadow_recalc(int cur_reg, ali1621_t *dev)
ali1621_shadow_recalc(UNUSED(int cur_reg), ali1621_t *dev)
{
int r_bit;
int w_bit;
@@ -207,8 +212,8 @@ ali1621_mask_bar(ali1621_t *dev)
uint32_t mask;
switch (dev->pci_conf[0xbc] & 0x0f) {
case 0x00:
default:
case 0x00:
mask = 0x00000000;
break;
case 0x01:
@@ -246,7 +251,7 @@ ali1621_mask_bar(ali1621_t *dev)
}
static void
ali1621_write(int func, int addr, uint8_t val, void *priv)
ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
ali1621_t *dev = (ali1621_t *) priv;
@@ -565,11 +570,14 @@ ali1621_write(int func, int addr, uint8_t val, void *priv)
case 0xf0 ... 0xff:
dev->pci_conf[addr] = val;
break;
default:
break;
}
}
static uint8_t
ali1621_read(int func, int addr, void *priv)
ali1621_read(UNUSED(int func), int addr, void *priv)
{
ali1621_t *dev = (ali1621_t *) priv;
uint8_t ret = 0xff;
@@ -653,7 +661,7 @@ ali1621_close(void *priv)
}
static void *
ali1621_init(const device_t *info)
ali1621_init(UNUSED(const device_t *info))
{
ali1621_t *dev = (ali1621_t *) malloc(sizeof(ali1621_t));
memset(dev, 0, sizeof(ali1621_t));

6
src/chipset/ali6117.c
View File

@@ -277,6 +277,9 @@ ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
case 0x7:
cpu_set_isa_speed(cpu_busspeed / 6);
break;
default:
break;
}
break;
@@ -372,6 +375,9 @@ ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
case 0x71:
val &= 0x1f;
break;
default:
break;
}
dev->regs[dev->reg_offset] = val;

8
src/chipset/contaq_82c59x.c
View File

@@ -82,6 +82,8 @@ contaq_82c59x_isa_speed_recalc(contaq_82c59x_t *dev)
case 0x03:
cpu_set_isa_speed(cpu_busspeed / 5);
break;
default:
break;
}
}
}
@@ -274,8 +276,14 @@ contaq_82c59x_write(uint16_t addr, uint8_t val, void *priv)
case 0x7c:
dev->regs[dev->index] = val;
break;
default:
break;
}
break;
default:
break;
}
}

9
src/chipset/cs4031.c
View File

@@ -27,6 +27,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -134,8 +135,14 @@ cs4031_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[dev->index] = val & 0xb3;
port_92_set_features(dev->port_92, val & 0x10, val & 0x20);
break;
default:
break;
}
break;
default:
break;
}
}
@@ -156,7 +163,7 @@ cs4031_close(void *priv)
}
static void *
cs4031_init(const device_t *info)
cs4031_init(UNUSED(const device_t *info))
{
cs4031_t *dev = (cs4031_t *) malloc(sizeof(cs4031_t));
memset(dev, 0, sizeof(cs4031_t));

9
src/chipset/cs8230.c
View File

@@ -25,6 +25,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/chipset.h>
@@ -51,6 +52,8 @@ shadow_control(uint32_t addr, uint32_t size, int state)
case 0x11:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
default:
break;
}
flushmmucache_nopc();
@@ -112,6 +115,8 @@ cs8230_read(uint16_t port, void *p)
case 0x2a:
ret = cs8230->regs[cs8230->idx];
break;
default:
break;
}
}
@@ -137,6 +142,8 @@ cs8230_write(uint16_t port, uint8_t val, void *p)
case 0x0f: /* Address maps */
rethink_shadow_mappings(cs8230);
break;
default:
break;
}
}
}
@@ -151,7 +158,7 @@ cs8230_close(void *priv)
static void
*
cs8230_init(const device_t *info)
cs8230_init(UNUSED(const device_t *info))
{
cs8230_t *cs8230 = (cs8230_t *) malloc(sizeof(cs8230_t));
memset(cs8230, 0, sizeof(cs8230_t));

9
src/chipset/et6000.c
View File

@@ -28,6 +28,7 @@
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -105,9 +106,15 @@ et6000_write(uint16_t addr, uint8_t val, void *priv)
et6000_shadow_control(0xe0000, 0x10000, val & 0x20, (val & 0x20) && (val & 0x10));
et6000_shadow_control(0xf0000, 0x10000, val & 0x40, !(val & 0x40));
break;
default:
break;
}
et6000_log("ET6000: dev->regs[%02x] = %02x\n", dev->index, dev->regs[dev->index]);
break;
default:
break;
}
}
@@ -128,7 +135,7 @@ et6000_close(void *priv)
}
static void *
et6000_init(const device_t *info)
et6000_init(UNUSED(const device_t *info))
{
et6000_t *dev = (et6000_t *) malloc(sizeof(et6000_t));
memset(dev, 0, sizeof(et6000_t));

8
src/chipset/gc100.c
View File

@@ -70,7 +70,7 @@ gc100_log(const char *fmt, ...)
static uint8_t
get_fdd_switch_settings(void)
{
int fdd_count = 0;
uint8_t fdd_count = 0;
for (uint8_t i = 0; i < FDD_NUM; i++) {
if (fdd_get_flags(i))
@@ -135,6 +135,9 @@ gc100_write(uint16_t port, uint8_t val, void *priv)
/* addr 0x6 */
/* addr 0x7 */
default:
break;
}
gc100_log("GC100: Write %02x at %02x\n", val, port);
@@ -187,6 +190,9 @@ gc100_read(uint16_t port, void *priv)
/* addr 0x6 */
/* addr 0x7 */
default:
break;
}
return ret;

3
src/chipset/headland.c
View File

@@ -34,6 +34,7 @@
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -205,7 +206,7 @@ hl_ems_update(headland_t *dev, uint8_t mar)
}
static void
set_global_EMS_state(headland_t *dev, int state)
set_global_EMS_state(headland_t *dev, UNUSED(int state))
{
for (uint8_t i = 0; i < 32; i++) {
hl_ems_update(dev, i | (((dev->cr[0] & 0x01) << 5) ^ 0x20));

14
src/chipset/ims8848.c
View File

@@ -31,6 +31,7 @@
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -244,10 +245,16 @@ ims8848_write(uint16_t addr, uint8_t val, void *priv)
/* Base Memory */
ims8848_base_memory(dev);
break;
default:
break;
}
dev->access_data = 0;
}
break;
default:
break;
}
}
@@ -276,6 +283,8 @@ ims8848_read(uint16_t addr, void *priv)
}
ims8848_log("[R] [%i] REG %02X = %02X\n", old_ad, dev->idx, ret);
break;
default:
break;
}
return ret;
@@ -309,6 +318,9 @@ ims8849_pci_write(int func, int addr, uint8_t val, void *priv)
case 0x52 ... 0x55:
dev->pci_conf[addr] = val;
break;
default:
break;
}
}
@@ -364,7 +376,7 @@ ims8848_close(void *priv)
}
static void *
ims8848_init(const device_t *info)
ims8848_init(UNUSED(const device_t *info))
{
ims8848_t *dev = (ims8848_t *) malloc(sizeof(ims8848_t));
memset(dev, 0, sizeof(ims8848_t));

13
src/chipset/intel_420ex.c
View File

@@ -34,6 +34,7 @@
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
@@ -97,6 +98,8 @@ i420ex_map(uint32_t addr, uint32_t size, int state)
case 3:
mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
default:
break;
}
flushmmucache_nopc();
}
@@ -118,9 +121,9 @@ i420ex_smram_handler_phase1(i420ex_t *dev)
uint32_t size = 0x00010000;
switch (regs[0x70] & 0x07) {
default:
case 0:
case 1:
default:
host_base = ram_base = 0x00000000;
size = 0x00000000;
break;
@@ -195,6 +198,8 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
ide_set_side(0, 0x0376);
ide_pri_enable();
break;
default:
break;
}
}
break;
@@ -356,6 +361,8 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
cpu_fast_off_count = val + 1;
cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
break;
default:
break;
}
}
@@ -411,9 +418,9 @@ i420ex_reset_hard(void *priv)
}
static void
i420ex_apm_out(uint16_t port, uint8_t val, void *p)
i420ex_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
{
i420ex_t *dev = (i420ex_t *) p;
i420ex_t *dev = (i420ex_t *) priv;
if (dev->apm->do_smi)
dev->regs[0xaa] |= 0x80;

133
src/chipset/intel_4x0.c
View File

@@ -28,6 +28,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#include <86box/spd.h>
#include <86box/machine.h>
@@ -165,8 +166,8 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
} else {
size[0] = 0x00010000;
switch (*reg & 0x03) {
case 0:
default:
case 0:
base[0] = (mem_size << 10) - size[0];
s = 1;
break;
@@ -222,17 +223,17 @@ i4x0_mask_bar(uint8_t *regs, void *agpgart)
}
static uint8_t
pm2_cntrl_read(uint16_t addr, void *p)
pm2_cntrl_read(UNUSED(uint16_t addr), void *priv)
{
i4x0_t *dev = (i4x0_t *) p;
i4x0_t *dev = (i4x0_t *) priv;
return dev->pm2_cntrl & 0x01;
}
static void
pm2_cntrl_write(uint16_t addr, uint8_t val, void *p)
pm2_cntrl_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
i4x0_t *dev = (i4x0_t *) p;
i4x0_t *dev = (i4x0_t *) priv;
dev->pm2_cntrl = val & 0x01;
}
@@ -251,6 +252,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (addr) {
case 0x04: /*Command register*/
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
@@ -258,7 +260,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
case INTEL_440GX:
case INTEL_440ZX:
default:
regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
break;
case INTEL_430FX:
@@ -291,16 +292,18 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440EX:
regs[0x05] = val & 0x01;
break;
default:
break;
}
break;
case 0x07:
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
case INTEL_430HX:
default:
regs[0x07] &= ~(val & 0x70);
break;
case INTEL_430FX:
@@ -343,6 +346,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430TX:
regs[0x0f] = (val & 0x40);
break;
default:
break;
}
break;
case 0x12:
@@ -355,6 +360,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x12] = (val & 0xc0);
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0x13:
@@ -367,6 +374,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x13] = val;
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0x2c:
@@ -382,6 +391,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs_l[addr] = 1;
}
break;
default:
break;
}
break;
@@ -396,14 +407,16 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430TX:
regs[0x4f] = (val & 0x80);
break;
default:
break;
}
break;
case 0x50:
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
default:
regs[0x50] = (val & 0xe5);
break;
case INTEL_430NX:
@@ -467,17 +480,19 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x51] = (regs[0x51] & 0xb0) | (val & 0x4f);
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0x52: /* Cache Control Register */
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430FX:
case INTEL_430VX:
case INTEL_430TX:
default:
regs[0x52] = (val & 0xfb);
break;
case INTEL_430NX:
@@ -515,6 +530,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
/* Not applicable to 440ZX as that does not support ECC. */
regs[0x53] = val;
break;
default:
break;
}
break;
case 0x54:
@@ -534,6 +551,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x54] = val & 0x82;
break;
default:
break;
}
break;
case 0x55:
@@ -553,6 +572,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440EX:
regs[0x55] = val;
break;
default:
break;
}
break;
case 0x56:
@@ -577,6 +598,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440EX:
regs[0x56] = val;
break;
default:
break;
}
break;
case 0x57:
@@ -628,10 +651,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x58:
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
default:
regs[0x58] = val & 0x01;
break;
case INTEL_430NX:
@@ -720,6 +743,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
@@ -731,7 +755,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
default:
regs[addr] = val;
break;
case INTEL_430FX:
@@ -768,6 +791,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430TX:
regs[addr] = val & 0x7f;
break;
default:
break;
}
break;
case 0x66:
@@ -786,6 +811,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440ZX:
regs[addr] = val;
break;
default:
break;
}
break;
case 0x67:
@@ -810,6 +837,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430TX:
regs[addr] = val & 0xb7;
break;
default:
break;
}
break;
case 0x68:
@@ -838,6 +867,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440ZX:
regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0);
break;
default:
break;
}
break;
case 0x69:
@@ -856,6 +887,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440ZX:
regs[0x69] = val & 0x3f;
break;
default:
break;
}
break;
case 0x6a:
@@ -880,6 +913,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
else
regs[addr] = val & 0x33;
break;
default:
break;
}
break;
case 0x6c:
@@ -899,6 +934,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
else if (addr == 0x6d)
regs[addr] = val & 0xcf;
break;
default:
break;
}
break;
case 0x6f:
@@ -909,6 +946,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440EX:
regs[addr] = val & 0xcf;
break;
default:
break;
}
break;
case 0x70:
@@ -930,6 +969,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440EX:
regs[addr] = val & 0xf8;
break;
default:
break;
}
break;
case 0x71:
@@ -953,6 +994,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440LX:
regs[addr] = val & 0x1f;
break;
default:
break;
}
break;
case 0x72: /* SMRAM */
@@ -998,6 +1041,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
i4x0_smram_handler_phase1(dev);
}
break;
default:
break;
}
break;
case 0x74:
@@ -1008,6 +1053,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0x74] = val;
break;
default:
break;
}
break;
case 0x75:
@@ -1018,6 +1065,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440ZX:
case INTEL_440GX:
regs[addr] = val;
default:
break;
}
break;
case 0x77:
@@ -1025,6 +1074,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
case INTEL_440ZX:
regs[0x77] = val & 0x03;
default:
break;
}
break;
case 0x78:
@@ -1039,6 +1090,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0x78] = val & 0x1f;
break;
default:
break;
}
break;
case 0x79:
@@ -1054,6 +1107,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0x79] = val;
break;
default:
break;
}
break;
case 0x7a:
@@ -1066,6 +1121,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
break;
default:
break;
}
break;
case 0x7c:
@@ -1081,6 +1138,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440ZX:
regs[0x7c] = val & 0x1f;
break;
default:
break;
}
break;
case 0x7d:
@@ -1091,6 +1150,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430NX:
regs[0x7d] = val & 0x32;
break;
default:
break;
}
break;
case 0x7e:
@@ -1102,6 +1163,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430NX:
regs[addr] = val;
break;
default:
break;
}
break;
case 0x80:
@@ -1111,6 +1174,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0x80] &= ~(val & 0x03);
break;
default:
break;
}
break;
case 0x90:
@@ -1132,6 +1197,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0x90] = val;
break;
default:
break;
}
break;
case 0x91:
@@ -1144,6 +1211,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
/* Not applicable on 82443EX and 82443ZX. */
regs[0x91] &= ~(val & 0x11);
break;
default:
break;
}
break;
case 0x92:
@@ -1157,6 +1226,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0x92] &= ~(val & 0x1f);
break;
default:
break;
}
break;
case 0x93:
@@ -1170,6 +1241,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x93] = (val & 0x0e);
trc_write(0x0093, val & 0x06, NULL);
break;
default:
break;
}
break;
case 0xa7:
@@ -1178,6 +1251,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440EX:
regs[0xa7] = val & 0x1f;
break;
default:
break;
}
break;
case 0xa8:
@@ -1190,6 +1265,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[addr] = (val & 0x03);
break;
default:
break;
}
break;
case 0xb0:
@@ -1201,6 +1278,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0xb0] = (val & 0x80);
break;
default:
break;
}
break;
case 0xb1:
@@ -1214,6 +1293,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0xb1] = (val & 0xa0);
break;
default:
break;
}
break;
case 0xb4:
@@ -1226,6 +1307,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0xb4] = (val & 0x3f);
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0xb9:
@@ -1238,6 +1321,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0xb9] = (val & 0xf0);
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
@@ -1252,6 +1337,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[addr] = val;
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
@@ -1261,6 +1348,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440EX:
regs[addr] = (val & 0xf8);
break;
default:
break;
}
break;
@@ -1270,6 +1359,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440EX:
regs[addr] = (val & 0xf8);
break;
default:
break;
}
break;
@@ -1287,6 +1378,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[addr] = val;
break;
default:
break;
}
break;
case 0xca:
@@ -1298,6 +1391,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440ZX:
regs[addr] = val & 0xe7;
break;
default:
break;
}
break;
case 0xcb:
@@ -1309,6 +1404,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440ZX:
regs[addr] = val & 0xa7;
break;
default:
break;
}
break;
case 0xcc:
@@ -1320,6 +1417,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440ZX:
regs[0xcc] = (val & 0x58);
break;
default:
break;
}
break;
case 0xe0:
@@ -1339,6 +1438,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
if (!regs_l[addr])
regs[addr] = val;
break;
default:
break;
}
break;
case 0xe5:
@@ -1350,6 +1451,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
if (!regs_l[addr])
regs[addr] = (val & 0x3f);
break;
default:
break;
}
break;
case 0xe7:
@@ -1364,6 +1467,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0xe7] |= (val & 0x7f);
}
break;
default:
break;
}
break;
case 0xf0:
@@ -1373,6 +1478,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0xf0] = (val & 0xc0);
break;
default:
break;
}
break;
case 0xf1:
@@ -1382,6 +1489,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440GX:
regs[0xf1] = (val & 0x03);
break;
default:
break;
}
break;
}
@@ -1746,6 +1855,8 @@ static void
dev->drb_unit = 8;
dev->drb_default = 0x01;
break;
default:
break;
}
regs[0x04] = 0x06;

10
src/chipset/intel_82335.c
View File

@@ -28,6 +28,7 @@
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
/* Shadow capabilities */
#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
@@ -109,7 +110,9 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv)
shadowbios_write = !!(dev->regs[0x22] & 0x01);
/* Base System 512/640KB set */
// mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB);
#if 0
mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB);
#endif
/* Video RAM shadow*/
mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW);
@@ -139,6 +142,9 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv)
}
break;
}
default:
break;
}
}
@@ -165,7 +171,7 @@ intel_82335_close(void *priv)
}
static void *
intel_82335_init(const device_t *info)
intel_82335_init(UNUSED(const device_t *info))
{
intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t));
memset(dev, 0, sizeof(intel_82335_t));

29
src/chipset/intel_i450kx.c
View File

@@ -35,6 +35,7 @@ i450GX is way more popular of an option but needs more stuff.
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/chipset.h>
@@ -112,7 +113,9 @@ i450kx_vid_buf_recalc(i450kx_t *dev, int bus)
{
uint8_t *regs = bus ? dev->pb_pci_conf : dev->mc_pci_conf;
#if 0
// int state = (regs[0x58] & 0x02) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_DISABLED | MEM_WRITE_DISABLED);
#endif
int state = (regs[0x58] & 0x02) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (bus)
@@ -167,8 +170,10 @@ pb_write(int func, int addr, uint8_t val, void *priv)
case 0x4a:
case 0x4b:
dev->pb_pci_conf[addr] = val;
// if (addr == 0x4a)
// pci_remap_bus(dev->bus_index, val);
#if 0
if (addr == 0x4a)
pci_remap_bus(dev->bus_index, val);
#endif
break;
case 0x4c:
@@ -366,6 +371,9 @@ pb_write(int func, int addr, uint8_t val, void *priv)
case 0xcb:
dev->pb_pci_conf[addr] = val;
break;
default:
break;
}
}
@@ -590,6 +598,9 @@ mc_write(int func, int addr, uint8_t val, void *priv)
case 0xcb:
dev->mc_pci_conf[addr] = val;
break;
default:
break;
}
}
@@ -613,7 +624,9 @@ i450kx_reset(void *priv)
i450kx_t *dev = (i450kx_t *) priv;
uint32_t i;
#if 0
// pclog("i450KX: i450kx_reset()\n");
#endif
/* Defaults PB */
dev->pb_pci_conf[0x00] = 0x86;
@@ -671,8 +684,10 @@ i450kx_reset(void *priv)
dev->pb_pci_conf[0xa6] = 0xfe;
dev->pb_pci_conf[0xa7] = 0x00;
/* Note: Do NOT reset these two registers on programmed (TRC) hard reset! */
// dev->pb_pci_conf[0xb0] = 0x00;
// dev->pb_pci_conf[0xb1] = 0x00;
#if 0
dev->pb_pci_conf[0xb0] = 0x00;
dev->pb_pci_conf[0xb1] = 0x00;
#endif
dev->pb_pci_conf[0xb4] = 0x00;
dev->pb_pci_conf[0xb5] = 0x00;
dev->pb_pci_conf[0xb8] = 0x05;
@@ -693,7 +708,9 @@ i450kx_reset(void *priv)
dev->pb_pci_conf[0xca] = 0x00;
dev->pb_pci_conf[0xcb] = 0x00;
// pci_remap_bus(dev->bus_index, 0x00);
#if 0
pci_remap_bus(dev->bus_index, 0x00);
#endif
i450kx_smram_recalc(dev, 1);
i450kx_vid_buf_recalc(dev, 1);
pb_write(0, 0x59, 0x30, dev);
@@ -786,7 +803,7 @@ i450kx_close(void *priv)
}
static void *
i450kx_init(const device_t *info)
i450kx_init(UNUSED(const device_t *info))
{
i450kx_t *dev = (i450kx_t *) malloc(sizeof(i450kx_t));
memset(dev, 0, sizeof(i450kx_t));

25
src/chipset/intel_piix.c
View File

@@ -40,6 +40,7 @@
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/plat.h>
#include <86box/port_92.h>
#include <86box/scsi_device.h>
#include <86box/hdc.h>
@@ -135,6 +136,8 @@ smsc_ide_irqs(piix_t *dev)
case 0x07:
irq_line = 15;
break;
default:
break;
}
sff_set_irq_line(dev->bm[0], irq_line);
@@ -203,7 +206,7 @@ piix_ide_bm_handlers(piix_t *dev)
}
static uint8_t
kbc_alias_reg_read(uint16_t addr, void *p)
kbc_alias_reg_read(UNUSED(uint16_t addr), UNUSED(void *priv))
{
uint8_t ret = inb(0x61);
@@ -211,7 +214,7 @@ kbc_alias_reg_read(uint16_t addr, void *p)
}
static void
kbc_alias_reg_write(uint16_t addr, uint8_t val, void *p)
kbc_alias_reg_write(UNUSED(uint16_t addr), uint8_t val, UNUSED(void *priv))
{
outb(0x61, val);
}
@@ -267,7 +270,7 @@ nvr_update_io_mapping(piix_t *dev)
}
static void
piix_trap_io(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
piix_trap_io(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
{
piix_io_trap_t *trap = (piix_io_trap_t *) priv;
@@ -555,8 +558,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x6a:
switch (dev->type) {
case 1:
default:
case 1:
fregs[0x6a] = (fregs[0x6a] & 0xfb) | (val & 0x04);
fregs[0x0e] = (val & 0x04) ? 0x80 : 0x00;
piix_log("PIIX: Write %02X\n", val);
@@ -791,6 +794,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
}
}
break;
default:
break;
}
else if (func == 1)
switch (addr) { /* IDE */
@@ -1012,6 +1017,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
nvr_read_addr_set(!!(val & 0x10), dev->nvr);
}
break;
default:
break;
}
else if (func == 3)
switch (addr) { /* Power Management */
@@ -1145,6 +1152,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
fregs[0x91] = val;
smbus_update_io_mapping(dev);
break;
default:
break;
}
}
@@ -1409,9 +1418,9 @@ piix_reset_hard(piix_t *dev)
}
static void
piix_apm_out(uint16_t port, uint8_t val, void *p)
piix_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
{
piix_t *dev = (piix_t *) p;
piix_t *dev = (piix_t *) priv;
if (dev->apm->do_smi) {
if (dev->type < 4)
@@ -1695,7 +1704,9 @@ piix_init(const device_t *info)
else
dev->board_config[1] |= 0x00;
// device_add(&i8254_sec_device);
#if 0
device_add(&i8254_sec_device);
#endif
return dev;
}

6
src/chipset/intel_sio.c
View File

@@ -315,6 +315,8 @@ sio_write(int func, int addr, uint8_t val, void *priv)
cpu_fast_off_count = val + 1;
cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
break;
default:
break;
}
}
@@ -542,7 +544,9 @@ sio_init(const device_t *info)
timer_add(&dev->timer, NULL, NULL, 0);
// device_add(&i8254_sec_device);
#if 0
device_add(&i8254_sec_device);
#endif
return dev;
}

11
src/chipset/neat.c
View File

@@ -30,6 +30,7 @@
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#define NEAT_DEBUG 0
@@ -340,6 +341,8 @@ ems_write(uint16_t port, uint8_t val, void *priv)
ems->page |= (val & 0x7f); /* add new bits */
ems_recalc(dev, ems);
break;
default:
break;
}
}
@@ -359,6 +362,8 @@ ems_read(uint16_t port, void *priv)
if (dev->ems[vpage].enabled)
ret |= 0x80;
break;
default:
break;
}
#if NEAT_DEBUG > 1
@@ -608,6 +613,8 @@ neat_write(uint16_t port, uint8_t val, void *priv)
case 7: /* 7 MB */
dev->ems_size = i << 10;
break;
default:
break;
}
dev->ems_pages = (dev->ems_size << 10) / EMS_PGSIZE;
if (dev->regs[REG_RB7] & RB7_EMSEN) {
@@ -622,6 +629,8 @@ neat_write(uint16_t port, uint8_t val, void *priv)
break;
}
break;
default:
break;
}
}
@@ -660,7 +669,7 @@ neat_close(void *priv)
}
static void *
neat_init(const device_t *info)
neat_init(UNUSED(const device_t *info))
{
neat_t *dev;
int i;

37
src/chipset/olivetti_eva.c
View File

@@ -32,6 +32,7 @@
#include <86box/chipset.h>
#include <86box/video.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
typedef struct
{
@@ -77,20 +78,24 @@ olivetti_eva_write(uint16_t addr, uint8_t val, void *priv)
* Unfortunately, if triggered, the BIOS remapping function fails causing
* a fatal error. Therefore, this code section is currently commented.
*/
// if (val & 1){
// /*
// * Set the register to 7 or above for the BIOS to trigger the
// * memory remapping function if shadowing is active.
// */
// dev->reg_069 = 0x7;
// }
// if (val & 8) {
// /*
// * Activate shadowing for region e0000-fffff
// */
// mem_remap_top(256);
// mem_set_mem_state_both(0xa0000, 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
// }
#if 0
if (val & 1) {
/*
* Set the register to 7 or above for the BIOS to trigger the
* memory remapping function if shadowing is active.
*/
dev->reg_069 = 0x7;
}
if (val & 8) {
/*
* Activate shadowing for region e0000-fffff
*/
mem_remap_top(256);
mem_set_mem_state_both(0xa0000, 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
#endif
break;
default:
break;
}
}
@@ -111,6 +116,8 @@ olivetti_eva_read(uint16_t addr, void *priv)
case 0x069:
ret = dev->reg_069;
break;
default:
break;
}
olivetti_eva_log("Olivetti EVA Gate Array: Read %02x at %02x\n", ret, addr);
return ret;
@@ -125,7 +132,7 @@ olivetti_eva_close(void *priv)
}
static void *
olivetti_eva_init(const device_t *info)
olivetti_eva_init(UNUSED(const device_t *info))
{
olivetti_eva_t *dev = (olivetti_eva_t *) malloc(sizeof(olivetti_eva_t));
memset(dev, 0, sizeof(olivetti_eva_t));

7
src/chipset/opti283.c
View File

@@ -29,6 +29,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#ifdef ENABLE_OPTI283_LOG
@@ -234,8 +235,12 @@ opti283_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[dev->index] = val;
opti283_shadow_recalc(dev);
break;
default:
break;
}
break;
default:
break;
}
}
@@ -260,7 +265,7 @@ opti283_close(void *priv)
}
static void *
opti283_init(const device_t *info)
opti283_init(UNUSED(const device_t *info))
{
opti283_t *dev = (opti283_t *) malloc(sizeof(opti283_t));
memset(dev, 0x00, sizeof(opti283_t));

7
src/chipset/opti291.c
View File

@@ -28,6 +28,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -107,8 +108,12 @@ opti291_write(uint16_t addr, uint8_t val, void *priv)
case 0x2c:
dev->regs[dev->index] = val;
break;
default:
break;
}
break;
default:
break;
}
}
@@ -129,7 +134,7 @@ opti291_close(void *priv)
}
static void *
opti291_init(const device_t *info)
opti291_init(UNUSED(const device_t *info))
{
opti291_t *dev = (opti291_t *) malloc(sizeof(opti291_t));
memset(dev, 0, sizeof(opti291_t));

7
src/chipset/opti391.c
View File

@@ -27,6 +27,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#ifdef ENABLE_OPTI391_LOG
@@ -164,8 +165,12 @@ opti391_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[dev->index] = val;
opti391_shadow_recalc(dev);
break;
default:
break;
}
break;
default:
break;
}
}
@@ -190,7 +195,7 @@ opti391_close(void *priv)
}
static void *
opti391_init(const device_t *info)
opti391_init(UNUSED(const device_t *info))
{
opti391_t *dev = (opti391_t *) malloc(sizeof(opti391_t));
memset(dev, 0x00, sizeof(opti391_t));

6
src/chipset/opti495.c
View File

@@ -141,6 +141,8 @@ opti495_write(uint16_t addr, uint8_t val, void *priv)
case 0x26:
opti495_recalc(dev);
break;
default:
break;
}
}
break;
@@ -149,6 +151,8 @@ opti495_write(uint16_t addr, uint8_t val, void *priv)
case 0xe2:
dev->scratch[~addr & 0x01] = val;
break;
default:
break;
}
}
@@ -172,6 +176,8 @@ opti495_read(uint16_t addr, void *priv)
case 0xe2:
ret = dev->scratch[~addr & 0x01];
break;
default:
break;
}
return ret;

9
src/chipset/opti499.c
View File

@@ -29,6 +29,7 @@
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
typedef struct
@@ -154,6 +155,8 @@ opti499_write(uint16_t addr, uint8_t val, void *priv)
case 0x2d:
opti499_recalc(dev);
break;
default:
break;
}
}
break;
@@ -162,6 +165,8 @@ opti499_write(uint16_t addr, uint8_t val, void *priv)
case 0xe2:
dev->scratch[~addr & 0x01] = val;
break;
default:
break;
}
}
@@ -188,6 +193,8 @@ opti499_read(uint16_t addr, void *priv)
case 0xe2:
ret = dev->scratch[~addr & 0x01];
break;
default:
break;
}
return ret;
@@ -230,7 +237,7 @@ opti499_close(void *priv)
}
static void *
opti499_init(const device_t *info)
opti499_init(UNUSED(const device_t *info))
{
opti499_t *dev = (opti499_t *) malloc(sizeof(opti499_t));
memset(dev, 0, sizeof(opti499_t));

4
src/chipset/opti5x7.c
View File

@@ -143,9 +143,13 @@ opti5x7_write(uint16_t addr, uint8_t val, void *priv)
case 0x11: /* Master Cycle Control Register */
dev->regs[dev->idx] = val;
break;
default:
break;
}
opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, dev->regs[dev->idx]);
break;
default:
break;
}
}

9
src/chipset/opti822.c
View File

@@ -33,6 +33,7 @@
#include <86box/timer.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
@@ -107,7 +108,9 @@ opti822_update_irqs(opti822_t *dev, int set)
int irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 };
pic_t *temp_pic;
// dev->irq_convert = (dev->pci_regs[0x53] & 0x08);
#if 0
dev->irq_convert = (dev->pci_regs[0x53] & 0x08);
#endif
dev->irq_convert = 1;
for (uint8_t i = 0; i < 16; i++) {
@@ -325,6 +328,8 @@ opti822_pci_write(int func, int addr, uint8_t val, void *priv)
}
opti822_update_irqs(dev, 1);
break;
default:
break;
}
}
@@ -383,7 +388,7 @@ opti822_close(void *p)
}
static void *
opti822_init(const device_t *info)
opti822_init(UNUSED(const device_t *info))
{
opti822_t *dev = (opti822_t *) malloc(sizeof(opti822_t));
memset(dev, 0, sizeof(opti822_t));

6
src/chipset/opti895.c
View File

@@ -185,6 +185,8 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
break;
}
break;
default:
break;
}
}
break;
@@ -193,6 +195,8 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
case 0xe2:
dev->scratch[addr - 0xe1] = val;
break;
default:
break;
}
}
@@ -218,6 +222,8 @@ opti895_read(uint16_t addr, void *priv)
case 0xe2:
ret = dev->scratch[addr - 0xe1];
break;
default:
break;
}
return ret;

19
src/chipset/scamp.c
View File

@@ -31,6 +31,7 @@
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -424,6 +425,8 @@ recalc_mappings(void *priv)
virt_base += (1 << 24);
dev->row_virt_shift[bank_nr] = 12;
break;
default:
break;
}
} else {
switch (rammap[cur_rammap].bank[bank_nr]) {
@@ -489,6 +492,8 @@ recalc_mappings(void *priv)
virt_base += (1 << 24);
dev->row_virt_shift[bank_nr] = 12;
break;
default:
break;
}
}
switch (rammap[cur_rammap].bank[bank_nr]) {
@@ -534,6 +539,8 @@ recalc_mappings(void *priv)
ram_mirrored_interleaved_write, NULL, NULL);
}
break;
default:
break;
}
}
}
@@ -644,6 +651,8 @@ shadow_control(uint32_t addr, uint32_t size, int state, int ems_enable)
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
default:
break;
}
flushmmucache_nopc();
@@ -756,6 +765,8 @@ scamp_write(uint16_t addr, uint8_t val, void *priv)
case CFG_FEAXS:
shadow_recalc(dev);
break;
default:
break;
}
}
break;
@@ -767,6 +778,8 @@ scamp_write(uint16_t addr, uint8_t val, void *priv)
mem_a20_recalc();
}
break;
default:
break;
}
}
@@ -809,6 +822,8 @@ scamp_read(uint16_t addr, void *priv)
softresetx86();
cpu_set_edx();
break;
default:
break;
}
return ret;
@@ -823,7 +838,7 @@ scamp_close(void *priv)
}
static void *
scamp_init(const device_t *info)
scamp_init(UNUSED(const device_t *info))
{
uint32_t addr;
int c;
@@ -924,6 +939,8 @@ scamp_init(const device_t *info)
dev->ibank_shift[c] = 23;
dev->ram_interleaved[c] = 1;
break;
default:
break;
}
}

4
src/chipset/scat.c
View File

@@ -1191,6 +1191,8 @@ scat_out(uint16_t port, uint8_t val, void *priv)
if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
dev->reg_2xA = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? val : val & 0xc3;
break;
default:
break;
}
}
@@ -1258,6 +1260,8 @@ scat_in(uint16_t port, void *priv)
if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
ret = dev->reg_2xA;
break;
default:
break;
}
return ret;

23
src/chipset/sis_5511.c
View File

@@ -32,6 +32,7 @@
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
@@ -121,6 +122,8 @@ sis_5511_smram_recalc(sis_5511_t *dev)
case 2:
smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1);
break;
default:
break;
}
flushmmucache();
@@ -153,7 +156,7 @@ sis_5513_bm_handler(sis_5511_t *dev)
}
static void
sis_5511_write(int func, int addr, uint8_t val, void *priv)
sis_5511_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
sis_5511_t *dev = (sis_5511_t *) priv;
@@ -331,12 +334,14 @@ sis_5511_write(int func, int addr, uint8_t val, void *priv)
case 0x93: /* 5512 General Purpose Register Index */
dev->pci_conf[addr] = val;
break;
default:
break;
}
sis_5511_log("SiS 5511: dev->pci_conf[%02x] = %02x POST: %02x\n", addr, dev->pci_conf[addr], inb(0x80));
}
static uint8_t
sis_5511_read(int func, int addr, void *priv)
sis_5511_read(UNUSED(int func), int addr, void *priv)
{
sis_5511_t *dev = (sis_5511_t *) priv;
sis_5511_log("SiS 5511: dev->pci_conf[%02x] (%02x) POST %02x\n", addr, dev->pci_conf[addr], inb(0x80));
@@ -428,6 +433,8 @@ sis_5513_pci_to_isa_write(int addr, uint8_t val, sis_5511_t *dev)
case 0x6a: /* GPIO Status Register */
dev->pci_conf_sb[0][addr] &= val & 0x15;
break;
default:
break;
}
}
@@ -514,6 +521,8 @@ sis_5513_ide_write(int addr, uint8_t val, sis_5511_t *dev)
case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */
dev->pci_conf_sb[1][addr] = val;
break;
default:
break;
}
}
@@ -528,6 +537,8 @@ sis_5513_write(int func, int addr, uint8_t val, void *priv)
case 1:
sis_5513_ide_write(addr, val, dev);
break;
default:
break;
}
sis_5511_log("SiS 5513: dev->pci_conf[%02x][%02x] = %02x POST: %02x\n", func, addr, dev->pci_conf_sb[func][addr], inb(0x80));
}
@@ -567,6 +578,8 @@ sis_5513_isa_write(uint16_t addr, uint8_t val, void *priv)
case 2:
cpu_set_isa_pci_div(3);
break;
default:
break;
}
break;
case 0x01:
@@ -587,9 +600,13 @@ sis_5513_isa_write(uint16_t addr, uint8_t val, void *priv)
case 0x0b:
dev->regs[dev->index] = val;
break;
default:
break;
}
sis_5511_log("SiS 5513-ISA: dev->regs[%02x] = %02x POST: %02x\n", dev->index + 0x50, dev->regs[dev->index], inb(0x80));
break;
default:
break;
}
}
@@ -700,7 +717,7 @@ sis_5511_close(void *priv)
}
static void *
sis_5511_init(const device_t *info)
sis_5511_init(UNUSED(const device_t *info))
{
sis_5511_t *dev = (sis_5511_t *) malloc(sizeof(sis_5511_t));
memset(dev, 0, sizeof(sis_5511_t));

21
src/chipset/sis_5571.c
View File

@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
@@ -117,6 +118,8 @@ sis_5571_smm_recalc(sis_5571_t *dev)
case 0x03:
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x10000, (dev->pci_conf[0xa3] & 0x10), 1);
break;
default:
break;
}
flushmmucache();
@@ -149,7 +152,7 @@ sis_5571_bm_handler(sis_5571_t *dev)
}
static void
memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
memory_pci_bridge_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
sis_5571_t *dev = (sis_5571_t *) priv;
@@ -324,12 +327,14 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0xd0;
sis_5571_smm_recalc(dev);
break;
default:
break;
}
sis_5571_log("SiS5571: dev->pci_conf[%02x] = %02x\n", addr, val);
}
static uint8_t
memory_pci_bridge_read(int func, int addr, void *priv)
memory_pci_bridge_read(UNUSED(int func), int addr, void *priv)
{
sis_5571_t *dev = (sis_5571_t *) priv;
sis_5571_log("SiS5571: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]);
@@ -375,6 +380,8 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
case 2:
cpu_set_isa_pci_div(3);
break;
default:
break;
}
break;
@@ -498,6 +505,8 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x77: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */
dev->pci_conf_sb[0][addr] = val;
break;
default:
break;
}
sis_5571_log("SiS5571-SB: dev->pci_conf[%02x] = %02x\n", addr, val);
break;
@@ -577,6 +586,8 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */
dev->pci_conf_sb[1][addr] = val;
break;
default:
break;
}
sis_5571_log("SiS5571-IDE: dev->pci_conf[%02x] = %02x\n", addr, val);
break;
@@ -615,6 +626,8 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x3c: /* Interrupt Line */
dev->pci_conf_sb[2][addr] = val;
break;
default:
break;
}
sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] = %02x\n", addr, val);
}
@@ -670,7 +683,7 @@ sis_5571_usb_update_interrupt(usb_t* usb, void* priv)
}
static uint8_t
sis_5571_usb_handle_smi(usb_t* usb, void* priv)
sis_5571_usb_handle_smi(UNUSED(usb_t* usb), UNUSED(void* priv))
{
/* Left unimplemented for now. */
return 1;
@@ -740,7 +753,7 @@ sis_5571_close(void *priv)
}
static void *
sis_5571_init(const device_t *info)
sis_5571_init(UNUSED(const device_t *info))
{
sis_5571_t *dev = (sis_5571_t *) malloc(sizeof(sis_5571_t));
memset(dev, 0x00, sizeof(sis_5571_t));

9
src/chipset/sis_85c310.c
View File

@@ -10,6 +10,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
typedef struct
@@ -64,6 +65,8 @@ rabbit_recalcmapping(rabbit_t *dev)
/* 128K at 0E0000-0FFFFF */
mem_set_mem_state(0x000e0000, 0x00020000, shflags);
break;
default:
break;
}
flushmmucache();
@@ -89,6 +92,8 @@ rabbit_write(uint16_t addr, uint8_t val, void *priv)
} else
dev->regs[dev->cur_reg] = val;
break;
default:
break;
}
}
@@ -106,6 +111,8 @@ rabbit_read(uint16_t addr, void *priv)
} else
ret = dev->regs[dev->cur_reg];
break;
default:
break;
}
return ret;
@@ -120,7 +127,7 @@ rabbit_close(void *priv)
}
static void *
rabbit_init(const device_t *info)
rabbit_init(UNUSED(const device_t *info))
{
rabbit_t *dev = (rabbit_t *) malloc(sizeof(rabbit_t));
memset(dev, 0, sizeof(rabbit_t));

21
src/chipset/sis_85c496.c
View File

@@ -32,6 +32,7 @@
#include <86box/dma.h>
#include <86box/nvr.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/machine.h>
@@ -98,6 +99,8 @@ sis_85c497_isa_write(uint16_t port, uint8_t val, void *priv)
dev->regs[dev->cur_reg] = val & 0xfc;
dma_set_mask((val & 0x80) ? 0xffffffff : 0x00ffffff);
break;
default:
break;
}
}
@@ -182,7 +185,7 @@ sis_85c496_ide_handler(sis_85c496_t *dev)
/* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */
static void
sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t old;
@@ -255,7 +258,9 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
case 0x4d:
case 0x4e:
case 0x4f:
// dev->pci_conf[addr] = val;
#if 0
dev->pci_conf[addr] = val;
#endif
spd_write_drbs(dev->pci_conf, 0x48, 0x4f, 1);
break;
case 0x50:
@@ -321,6 +326,8 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
host_base = 0x000e0000;
ram_base = 0x000b0000;
break;
default:
break;
}
smram_enable(dev->smram, host_base, ram_base, size,
@@ -459,11 +466,13 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0x6e;
nvr_bank_set(0, !!(val & 0x40), dev->nvr);
break;
default:
break;
}
}
static uint8_t
sis_85c49x_pci_read(int func, int addr, void *priv)
sis_85c49x_pci_read(UNUSED(int func), int addr, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t ret = dev->pci_conf[addr];
@@ -481,6 +490,8 @@ sis_85c49x_pci_read(int func, int addr, void *priv)
case 0x83: /*Port 70h Mirror*/
ret = inb(0x70);
break;
default:
break;
}
sis_85c496_log("[%04X:%08X] PCI Read %02X from %02X:%02X\n", CS, cpu_state.pc, ret, func, addr);
@@ -607,7 +618,9 @@ static void
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev);
// sis_85c497_isa_reset(dev);
#if 0
sis_85c497_isa_reset(dev);
#endif
dev->port_92 = device_add(&port_92_device);
port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);

9
src/chipset/sis_85c4xx.c
View File

@@ -28,6 +28,7 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/mem.h>
#include <86box/smram.h>
@@ -124,7 +125,7 @@ sis_85c4xx_recalcmapping(sis_85c4xx_t *dev)
}
static void
sis_85c4xx_sw_smi_out(uint16_t port, uint8_t val, void *priv)
sis_85c4xx_sw_smi_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
@@ -235,6 +236,8 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
port_92_add(dev->port_92);
}
break;
default:
break;
}
} else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00))
dev->reg_00 = val;
@@ -245,6 +248,8 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
case 0xe2:
dev->scratch[port - 0xe1] = val;
return;
default:
break;
}
}
@@ -273,6 +278,8 @@ sis_85c4xx_in(uint16_t port, void *priv)
case 0xe1:
case 0xe2:
ret = dev->scratch[port - 0xe1];
default:
break;
}
return ret;

17
src/chipset/sis_85c50x.c
View File

@@ -31,6 +31,7 @@
#include <86box/apm.h>
#include <86box/machine.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
@@ -133,6 +134,8 @@ sis_85c50x_smm_recalc(sis_85c50x_t *dev)
smram_enable(dev->smram[0], host_base, 0xb0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
smram_enable(dev->smram[1], host_base ^ 0x00100000, 0xa0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
default:
break;
}
}
@@ -213,7 +216,9 @@ sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = (val & 0x7f);
break;
case 0x69:
dev->pci_conf[addr] &= ~(val);
dev->pci_conf[addr] &= ~val;
break;
default:
break;
}
}
@@ -267,6 +272,8 @@ sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
dev->pci_conf_sb[addr] = val;
break;
default:
break;
}
}
@@ -314,8 +321,12 @@ sis_85c50x_isa_write(uint16_t addr, uint8_t val, void *priv)
case 0x85:
outb(0x70, val);
break;
default:
break;
}
break;
default:
break;
}
}
@@ -336,6 +347,8 @@ sis_85c50x_isa_read(uint16_t addr, void *priv)
else
ret = dev->regs[dev->index];
break;
default:
break;
}
sis_85c50x_log("85C503 ISA: [R] (%04X) = %02X\n", addr, ret);
@@ -401,7 +414,7 @@ sis_85c50x_close(void *priv)
}
static void *
sis_85c50x_init(const device_t *info)
sis_85c50x_init(UNUSED(const device_t *info))
{
sis_85c50x_t *dev = (sis_85c50x_t *) malloc(sizeof(sis_85c50x_t));
memset(dev, 0x00, sizeof(sis_85c50x_t));

18
src/chipset/stpc.c
View File

@@ -30,6 +30,7 @@
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/device.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/usb.h>
#include <86box/hdc_ide.h>
@@ -248,6 +249,8 @@ stpc_nb_write(int func, int addr, uint8_t val, void *priv)
case 0x52:
val &= 0x70;
break;
default:
break;
}
dev->pci_conf[0][addr] = val;
@@ -432,6 +435,8 @@ stpc_ide_write(int func, int addr, uint8_t val, void *priv)
sff_bus_master_set_irq(0x00, dev->bm[1]);
}
break;
default:
break;
}
}
@@ -489,6 +494,8 @@ stpc_isab_write(int func, int addr, uint8_t val, void *priv)
case 0x05:
val &= 0x01;
break;
default:
break;
}
dev->pci_conf[1][addr] = val;
@@ -551,6 +558,8 @@ stpc_usb_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[3][addr] = val;
ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
break;
default:
break;
}
dev->pci_conf[3][addr] = val;
@@ -720,6 +729,9 @@ stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
val &= 0xf1;
stpc_serial_handlers(val);
break;
default:
break;
}
dev->regs[dev->reg_offset] = val;
@@ -957,7 +969,7 @@ stpc_serial_close(void *priv)
}
static void *
stpc_serial_init(const device_t *info)
stpc_serial_init(UNUSED(const device_t *info))
{
stpc_log("STPC: serial_init()\n");
@@ -990,6 +1002,8 @@ stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val)
case 0x3:
lpt2_remove();
break;
default:
break;
}
switch (new_addr) {
@@ -1068,7 +1082,7 @@ stpc_lpt_close(void *priv)
}
static void *
stpc_lpt_init(const device_t *info)
stpc_lpt_init(UNUSED(const device_t *info))
{
stpc_log("STPC: lpt_init()\n");

10
src/chipset/umc_8886.c
View File

@@ -212,6 +212,8 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
case 2:
cpu_set_isa_pci_div(2);
break;
default:
break;
}
break;
@@ -250,6 +252,9 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
case 0xa5 ... 0xa8:
dev->pci_conf_sb[func][addr] = val;
break;
default:
break;
}
break;
@@ -271,8 +276,13 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
case 0x41:
dev->pci_conf_sb[func][addr] = val;
break;
default:
break;
}
break;
default:
break;
}
}

8
src/chipset/umc_hb4.c
View File

@@ -106,6 +106,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
@@ -261,7 +262,7 @@ hb4_smram(hb4_t *dev)
}
static void
hb4_write(int func, int addr, uint8_t val, void *priv)
hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
hb4_t *dev = (hb4_t *) priv;
@@ -322,6 +323,9 @@ hb4_write(int func, int addr, uint8_t val, void *priv)
case 0x61:
dev->pci_conf[addr] = val;
break;
default:
break;
}
}
@@ -383,7 +387,7 @@ hb4_close(void *priv)
}
static void *
hb4_init(const device_t *info)
hb4_init(UNUSED(const device_t *info))
{
hb4_t *dev = (hb4_t *) malloc(sizeof(hb4_t));
memset(dev, 0, sizeof(hb4_t));

15
src/chipset/via_apollo.c
View File

@@ -69,6 +69,8 @@ apollo_map(uint32_t addr, uint32_t size, int state)
case 3:
mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
default:
break;
}
flushmmucache_nopc();
@@ -392,8 +394,8 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
smram_disable_all();
if (dev->id >= VIA_691)
switch (val & 0x03) {
case 0x00:
default:
case 0x00:
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); /* Non-SMM: Code PCI, Data PCI */
break;
@@ -412,8 +414,8 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
}
else if (dev->id >= VIA_597)
switch (val & 0x03) {
case 0x00:
default:
case 0x00:
/* Disable SMI Address Redirection (default) */
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0);
@@ -458,6 +460,8 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3);
break;
default:
break;
}
break;
case 0x65:
@@ -673,6 +677,8 @@ via_apollo_read(int func, int addr, void *priv)
case 0:
ret = dev->pci_conf[addr];
break;
default:
break;
}
return ret;
@@ -685,6 +691,8 @@ via_apollo_write(int func, int addr, uint8_t val, void *priv)
case 0:
via_apollo_host_bridge_write(func, addr, val, priv);
break;
default:
break;
}
}
@@ -728,6 +736,9 @@ via_apollo_init(const device_t *info)
case VIA_694:
device_add(&via_mvp3_agp_device);
break;
default:
break;
}
if (dev->id >= VIA_597)

13
src/chipset/via_pipc.c
View File

@@ -41,6 +41,7 @@
#include <86box/ddma.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -162,7 +163,7 @@ static uint8_t pipc_read(int func, int addr, void *priv);
static void pipc_write(int func, int addr, uint8_t val, void *priv);
static void
pipc_io_trap_pact(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
pipc_io_trap_pact(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
{
pipc_io_trap_t *trap = (pipc_io_trap_t *) priv;
@@ -175,7 +176,7 @@ pipc_io_trap_pact(int size, uint16_t addr, uint8_t write, uint8_t val, void *pri
}
static void
pipc_io_trap_glb(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
pipc_io_trap_glb(UNUSED(int size), UNUSED(uint16_t addr), uint8_t write, UNUSED(uint8_t val), void *priv)
{
pipc_io_trap_t *trap = (pipc_io_trap_t *) priv;
@@ -332,6 +333,8 @@ pipc_reset_hard(void *priv)
case VIA_PIPC_8231:
dev->usb_regs[i][0x08] = 0x1e;
break;
default:
break;
}
dev->usb_regs[i][0x0a] = 0x03;
@@ -392,6 +395,9 @@ pipc_reset_hard(void *priv)
case VIA_PIPC_686B:
dev->power_regs[0x08] = 0x40;
break;
default:
break;
}
if (dev->local == VIA_PIPC_686B)
dev->power_regs[0x34] = 0x68;
@@ -453,6 +459,9 @@ pipc_reset_hard(void *priv)
case VIA_PIPC_8231:
dev->ac97_regs[i][0x08] = (i == 0) ? 0x40 : 0x20;
break;
default:
break;
}
if (i == 0) {

9
src/chipset/via_vt82c49x.c
View File

@@ -189,6 +189,8 @@ vt82c49x_recalc(vt82c49x_t *dev)
if (!shadow_bitmap)
mem_remap_top(384);
break;
default:
break;
}
}
@@ -280,8 +282,13 @@ vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
(val & 0x40) ? "second" : "prim");
}
break;
default:
break;
}
break;
default:
break;
}
}
@@ -303,6 +310,8 @@ vt82c49x_read(uint16_t addr, void *priv)
else if (dev->index < 0x80)
ret = dev->regs[dev->index];
break;
default:
break;
}
return ret;

5
src/chipset/via_vt82c505.c
View File

@@ -26,6 +26,7 @@
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/device.h>
#include <86box/chipset.h>
@@ -116,6 +117,8 @@ vt82c505_write(int func, int addr, uint8_t val, void *priv)
case 0x93:
dev->pci_conf[addr] = val & 0xe0;
break;
default:
break;
}
}
@@ -194,7 +197,7 @@ vt82c505_close(void *priv)
}
static void *
vt82c505_init(const device_t *info)
vt82c505_init(UNUSED(const device_t *info))
{
vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
memset(dev, 0, sizeof(vt82c505_t));

8
src/chipset/vl82c480.c
View File

@@ -40,8 +40,8 @@ vl82c480_shflags(uint8_t access)
int ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
switch (access) {
case 0x00:
default:
case 0x00:
ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
break;
case 0x01:
@@ -125,6 +125,9 @@ vl82c480_write(uint16_t addr, uint8_t val, void *p)
if (mem_a20_alt)
outb(0x92, inb(0x92) & ~2);
break;
default:
break;
}
}
@@ -152,6 +155,9 @@ vl82c480_read(uint16_t addr, void *p)
softresetx86();
cpu_set_edx();
break;
default:
break;
}
return ret;

13
src/chipset/wd76c10.c
View File

@@ -37,6 +37,7 @@
#include <86box/hdc_ide.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/chipset.h>
@@ -100,6 +101,8 @@ wd76c10_refresh_control(wd76c10_t *dev)
case 4:
serial_setup(dev->uart[1], 0x2e8, 3);
break;
default:
break;
}
serial_remove(dev->uart[0]);
@@ -117,6 +120,8 @@ wd76c10_refresh_control(wd76c10_t *dev)
case 4:
serial_setup(dev->uart[0], 0x2e8, 4);
break;
default:
break;
}
lpt1_remove();
@@ -153,6 +158,8 @@ wd76c10_split_addr(wd76c10_t *dev)
if (((dev->shadow_ram >> 8) & 3) == 3)
mem_remap_top(384);
break;
default:
break;
}
}
@@ -187,6 +194,8 @@ wd76c10_shadow_recalc(wd76c10_t *dev)
case 3:
mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | MEM_WRITE_DISABLED);
break;
default:
break;
}
switch ((dev->shadow_ram >> 8) & 3) {
@@ -203,6 +212,8 @@ wd76c10_shadow_recalc(wd76c10_t *dev)
case 3:
mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
break;
default:
break;
}
}
@@ -424,7 +435,7 @@ wd76c10_close(void *priv)
}
static void *
wd76c10_init(const device_t *info)
wd76c10_init(UNUSED(const device_t *info))
{
wd76c10_t *dev = (wd76c10_t *) malloc(sizeof(wd76c10_t));
memset(dev, 0, sizeof(wd76c10_t));

8
src/device/bugger.c
View File

@@ -266,7 +266,7 @@ bug_reset(void)
/* Handle a WRITE operation to one of our registers. */
static void
bug_write(uint16_t port, uint8_t val, void *priv)
bug_write(uint16_t port, uint8_t val, UNUSED(void *priv))
{
switch (port - BUGGER_ADDR) {
case BUG_CTRL: /* control register */
@@ -284,12 +284,14 @@ bug_write(uint16_t port, uint8_t val, void *priv)
bug_wdata(val);
}
break;
default:
break;
}
}
/* Handle a READ operation from one of our registers. */
static uint8_t
bug_read(uint16_t port, void *priv)
bug_read(uint16_t port, UNUSED(void *priv))
{
uint8_t ret = 0xff;
@@ -319,7 +321,7 @@ bug_read(uint16_t port, void *priv)
/* Initialize the ISA BusBugger emulator. */
static void *
bug_init(const device_t *info)
bug_init(UNUSED(const device_t *info))
{
bugger_log("%s, I/O=%04x\n", info->name, BUGGER_ADDR);

2
src/device/cartridge.c
View File

@@ -68,7 +68,7 @@ cart_read(uint32_t addr, void *priv)
}
static void
cart_load_error(int drive, char *fn)
cart_load_error(int drive, UNUSED(char *fn))
{
cartridge_log("Cartridge: could not load '%s'\n", fn);
memset(cart_fns[drive], 0, sizeof(cart_fns[drive]));

6
src/device/cassette.c
View File

@@ -544,7 +544,7 @@ pc_cas_set_out(pc_cassette_t *cas, unsigned char val)
}
void
pc_cas_print_state(const pc_cassette_t *cas)
pc_cas_print_state(UNUSED(const pc_cassette_t *cas))
{
cassette_log("%s %s %lu %s %lu\n", (cas->fname != NULL) ? cas->fname : "<none>", cas->pcm ? "pcm" : "cas", cas->srate, cas->save ? "save" : "load", cas->position);
}
@@ -642,7 +642,7 @@ pc_cas_advance(pc_cassette_t *cas)
}
static void
cassette_close(void *p)
cassette_close(UNUSED(void *priv))
{
if (cassette != NULL) {
free(cassette);
@@ -664,7 +664,7 @@ cassette_callback(void *p)
}
static void *
cassette_init(const device_t *info)
cassette_init(UNUSED(const device_t *info))
{
cassette = NULL;

7
src/device/clock_ics9xxx.c
View File

@@ -26,6 +26,7 @@
#include <86box/i2c.h>
#include "cpu.h"
#include <86box/clock.h>
#include <86box/plat_unused.h>
#ifdef ENABLE_ICS9xxx_LOG
int ics9xxx_do_log = ENABLE_ICS9xxx_LOG;
@@ -983,7 +984,7 @@ ics9xxx_detect(ics9xxx_t *dev)
#endif
static uint8_t
ics9xxx_start(void *bus, uint8_t addr, uint8_t read, void *priv)
ics9xxx_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
{
ics9xxx_t *dev = (ics9xxx_t *) priv;
@@ -995,7 +996,7 @@ ics9xxx_start(void *bus, uint8_t addr, uint8_t read, void *priv)
}
static uint8_t
ics9xxx_read(void *bus, uint8_t addr, void *priv)
ics9xxx_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
ics9xxx_t *dev = (ics9xxx_t *) priv;
uint8_t ret = 0xff;
@@ -1049,7 +1050,7 @@ ics9xxx_set(ics9xxx_t *dev, uint8_t val)
}
static uint8_t
ics9xxx_write(void *bus, uint8_t addr, uint8_t data, void *priv)
ics9xxx_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv)
{
ics9xxx_t *dev = (ics9xxx_t *) priv;

6
src/device/hasp.c
View File

@@ -131,6 +131,8 @@ hasp_write_data(uint8_t val, void *priv)
return;
}
break;
default:
break;
}
dev->status = 0;
@@ -163,6 +165,8 @@ hasp_write_data(uint8_t val, void *priv)
I guessed the implicit ones with a bit of trial and error */
dev->status = 0x20;
return;
default:
break;
}
}
@@ -199,6 +203,8 @@ hasp_write_data(uint8_t val, void *priv)
/* again, just the relevant bits instead of the true values */
dev->status = 0x20;
break;
default:
break;
}
} else if (dev->state == HASP_STATE_PASSWORD_END) {
if (val & 1) {

8
src/device/hwm_gl518sm.c
View File

@@ -27,6 +27,8 @@
#include <86box/io.h>
#include <86box/i2c.h>
#include <86box/hwm.h>
#include <86box/plat_unused.h>
#define CLAMP(a, min, max) (((a) < (min)) ? (min) : (((a) > (max)) ? (max) : (a)))
/* Formulas and factors derived from Linux's gl518sm.c driver. */
@@ -85,7 +87,7 @@ gl518sm_remap(gl518sm_t *dev, uint8_t addr)
}
static uint8_t
gl518sm_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
gl518sm_i2c_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
{
gl518sm_t *dev = (gl518sm_t *) priv;
@@ -95,7 +97,7 @@ gl518sm_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
}
static uint8_t
gl518sm_i2c_read(void *bus, uint8_t addr, void *priv)
gl518sm_i2c_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
gl518sm_t *dev = (gl518sm_t *) priv;
uint16_t read = gl518sm_read(dev, dev->addr_register);
@@ -159,7 +161,7 @@ gl518sm_read(gl518sm_t *dev, uint8_t reg)
}
static uint8_t
gl518sm_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
gl518sm_i2c_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv)
{
gl518sm_t *dev = (gl518sm_t *) priv;

9
src/device/hwm_lm75.c
View File

@@ -25,6 +25,7 @@
#include <86box/device.h>
#include <86box/i2c.h>
#include <86box/hwm.h>
#include <86box/plat_unused.h>
#define LM75_TEMP_TO_REG(t) ((t) << 8)
@@ -47,7 +48,7 @@ lm75_log(const char *fmt, ...)
#endif
static uint8_t
lm75_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
lm75_i2c_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
{
lm75_t *dev = (lm75_t *) priv;
@@ -74,7 +75,7 @@ lm75_read(lm75_t *dev, uint8_t reg)
}
static uint8_t
lm75_i2c_read(void *bus, uint8_t addr, void *priv)
lm75_i2c_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
lm75_t *dev = (lm75_t *) priv;
uint8_t ret = 0;
@@ -103,6 +104,8 @@ lm75_i2c_read(void *bus, uint8_t addr, void *priv)
case 0x3: /* Tos */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x5 : 0x6);
break;
default:
break;
}
}
@@ -128,7 +131,7 @@ lm75_write(lm75_t *dev, uint8_t reg, uint8_t val)
}
static uint8_t
lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
lm75_i2c_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv)
{
lm75_t *dev = (lm75_t *) priv;

35
src/device/hwm_lm78.c
View File

@@ -27,6 +27,7 @@
#include <86box/timer.h>
#include <86box/machine.h>
#include <86box/nvr.h>
#include <86box/plat_unused.h>
#include "cpu.h"
#include <86box/i2c.h>
#include <86box/hwm.h>
@@ -114,7 +115,7 @@ lm78_nvram(lm78_t *dev, uint8_t save)
}
static uint8_t
lm78_nvram_start(void *bus, uint8_t addr, uint8_t read, void *priv)
lm78_nvram_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
{
lm78_t *dev = (lm78_t *) priv;
@@ -124,7 +125,7 @@ lm78_nvram_start(void *bus, uint8_t addr, uint8_t read, void *priv)
}
static uint8_t
lm78_nvram_read(void *bus, uint8_t addr, void *priv)
lm78_nvram_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
lm78_t *dev = (lm78_t *) priv;
uint8_t ret = 0xff;
@@ -158,7 +159,7 @@ lm78_nvram_read(void *bus, uint8_t addr, void *priv)
}
static uint8_t
lm78_nvram_write(void *bus, uint8_t addr, uint8_t val, void *priv)
lm78_nvram_write(UNUSED(void *bus), uint8_t addr, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
@@ -195,7 +196,7 @@ lm78_nvram_write(void *bus, uint8_t addr, uint8_t val, void *priv)
}
static uint8_t
lm78_security_start(void *bus, uint8_t addr, uint8_t read, void *priv)
lm78_security_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
{
lm78_t *dev = (lm78_t *) priv;
@@ -205,7 +206,7 @@ lm78_security_start(void *bus, uint8_t addr, uint8_t read, void *priv)
}
static uint8_t
lm78_security_read(void *bus, uint8_t addr, void *priv)
lm78_security_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
lm78_t *dev = (lm78_t *) priv;
@@ -213,7 +214,7 @@ lm78_security_read(void *bus, uint8_t addr, void *priv)
}
static uint8_t
lm78_security_write(void *bus, uint8_t addr, uint8_t val, void *priv)
lm78_security_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
@@ -229,6 +230,8 @@ lm78_security_write(void *bus, uint8_t addr, uint8_t val, void *priv)
case 0xe7:
/* read-only registers */
return 1;
default:
break;
}
dev->as99127f.regs[2][dev->as99127f.security_addr_register++] = val;
@@ -316,7 +319,7 @@ lm78_reset(void *priv)
}
static uint8_t
lm78_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
lm78_i2c_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
{
lm78_t *dev = (lm78_t *) priv;
@@ -405,7 +408,7 @@ lm78_isa_read(uint16_t port, void *priv)
}
static uint8_t
lm78_i2c_read(void *bus, uint8_t addr, void *priv)
lm78_i2c_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
lm78_t *dev = (lm78_t *) priv;
@@ -446,6 +449,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
case 0x20:
val &= 0x7f;
break;
default:
break;
}
dev->as99127f.regs[0][reg] = val;
@@ -477,6 +482,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
case 0x5f:
/* read-only registers */
return 0;
default:
break;
}
dev->w83782d.regs[0][reg & 0x0f] = val;
@@ -497,6 +504,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
case 0x5f:
/* read-only registers */
return 0;
default:
break;
}
dev->w83782d.regs[1][reg & 0x0f] = val;
@@ -559,6 +568,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
if (!(dev->local & LM78_WINBOND))
return 0;
break;
default:
break;
}
if ((reg >= 0x60) && (reg <= 0x94)) /* write auto-increment value RAM registers to their non-auto-increment locations */
@@ -613,6 +624,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
i2c_sethandler(i2c_smbus, (val & 0xf8) >> 1, 4, lm78_nvram_start, lm78_nvram_read, lm78_nvram_write, NULL, dev);
}
break;
default:
break;
}
return 1;
@@ -644,7 +657,7 @@ lm78_isa_write(uint16_t port, uint8_t val, void *priv)
}
static uint8_t
lm78_i2c_write(void *bus, uint8_t addr, uint8_t val, void *priv)
lm78_i2c_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
@@ -694,13 +707,15 @@ lm78_as99127f_write(void *priv, uint8_t reg, uint8_t val)
resetx86();
}
break;
default:
break;
}
return 1;
}
static void
lm78_reset_timer(void *priv)
lm78_reset_timer(UNUSED(void *priv))
{
pc_reset_hard();
}

8
src/device/hwm_vt82c686.c
View File

@@ -25,6 +25,7 @@
#include <86box/device.h>
#include <86box/io.h>
#include <86box/hwm.h>
#include <86box/plat_unused.h>
#define CLAMP(a, min, max) (((a) < (min)) ? (min) : (((a) > (max)) ? (max) : (a)))
/* Formulas and factors derived from Linux's via686a.c driver. */
@@ -113,6 +114,8 @@ vt82c686_write(uint16_t port, uint8_t val, void *priv)
case 0x48:
val &= 0x7f;
break;
default:
break;
}
dev->regs[reg] = val;
@@ -143,6 +146,9 @@ vt82c686_hwm_write(uint8_t addr, uint8_t val, void *priv)
case 0x74:
dev->enable = val & 0x01;
break;
default:
break;
}
if (dev->enable && dev->io_base)
@@ -174,7 +180,7 @@ vt82c686_close(void *priv)
}
static void *
vt82c686_init(const device_t *info)
vt82c686_init(UNUSED(const device_t *info))
{
vt82c686_t *dev = (vt82c686_t *) malloc(sizeof(vt82c686_t));
memset(dev, 0, sizeof(vt82c686_t));

3
src/device/i2c_gpio.c
View File

@@ -136,6 +136,9 @@ i2c_gpio_set(void *dev_handle, uint8_t scl, uint8_t sda)
dev->slave_sda = !i2c_write(dev->i2c, dev->slave_addr, dev->byte);
i2c_gpio_log(2, "I2C GPIO %s: Write %02X %sACK\n", dev->bus_name, dev->byte, dev->slave_sda ? "N" : "");
break;
default:
break;
}
} else if (dev->pos == 9) {
switch (dev->slave_read) {

6
src/device/ibm_5161.c
View File

@@ -26,6 +26,7 @@
#include <86box/pci.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/machine.h>
@@ -76,6 +77,9 @@ ibm_5161_in(uint16_t port, void *priv)
0 =On */
ret = dev->regs[3] & 0x01;
break;
default:
break;
}
return ret;
@@ -90,7 +94,7 @@ ibm_5161_close(void *p)
}
static void *
ibm_5161_init(const device_t *info)
ibm_5161_init(UNUSED(const device_t *info))
{
ibm_5161_t *dev = (ibm_5161_t *) malloc(sizeof(ibm_5161_t));
memset(dev, 0, sizeof(ibm_5161_t));

11
src/device/isamem.c
View File

@@ -305,6 +305,9 @@ ems_read(uint16_t port, void *priv)
case 0x0001: /* W/O */
break;
default:
break;
}
#if ISAMEM_DEBUG
@@ -383,6 +386,9 @@ ems_write(uint16_t port, uint8_t val, void *priv)
if (val)
dev->flags |= FLAG_CONFIG;
break;
default:
break;
}
}
@@ -458,6 +464,9 @@ isamem_init(const device_t *info)
if (!!device_get_config_int("speed"))
dev->flags |= FLAG_FAST;
break;
default:
break;
}
/* Fix up the memory start address. */
@@ -471,6 +480,7 @@ isamem_init(const device_t *info)
isamem_log(", FAST");
if (dev->flags & FLAG_WIDE)
isamem_log(", 16BIT");
isamem_log(")\n");
/* Force (back to) 8-bit bus if needed. */
@@ -617,6 +627,7 @@ isamem_init(const device_t *info)
dev->base_addr, dev->ems_size, dev->ems_pages);
if (dev->frame_addr > 0)
isamem_log(", Frame=%05XH", dev->frame_addr);
isamem_log("\n");
/*

21
src/device/isapnp.c
View File

@@ -26,6 +26,7 @@
#include <86box/device.h>
#include <86box/io.h>
#include <86box/isapnp.h>
#include <86box/plat_unused.h>
#define CHECK_CURRENT_LD() \
if (!dev->current_ld) { \
@@ -245,14 +246,14 @@ isapnp_reset_ld_regs(isapnp_device_t *ld)
}
static uint8_t
isapnp_read_rangecheck(uint16_t addr, void *priv)
isapnp_read_rangecheck(UNUSED(uint16_t addr), void *priv)
{
isapnp_device_t *dev = (isapnp_device_t *) priv;
return (dev->regs[0x31] & 0x01) ? 0x55 : 0xaa;
}
static uint8_t
isapnp_read_data(uint16_t addr, void *priv)
isapnp_read_data(UNUSED(uint16_t addr), void *priv)
{
isapnp_t *dev = (isapnp_t *) priv;
uint8_t ret = 0xff;
@@ -418,7 +419,7 @@ isapnp_set_read_data(uint16_t addr, isapnp_t *dev)
}
static void
isapnp_write_addr(uint16_t addr, uint8_t val, void *priv)
isapnp_write_addr(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
isapnp_t *dev = (isapnp_t *) priv;
isapnp_card_t *card = dev->first_card;
@@ -449,7 +450,7 @@ isapnp_write_addr(uint16_t addr, uint8_t val, void *priv)
}
static void
isapnp_write_data(uint16_t addr, uint8_t val, void *priv)
isapnp_write_data(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
isapnp_t *dev = (isapnp_t *) priv;
isapnp_card_t *card;
@@ -681,6 +682,9 @@ isapnp_write_data(uint16_t addr, uint8_t val, void *priv)
val |= 0x02;
break;
default:
break;
}
dev->current_ld->regs[dev->reg] = val;
@@ -691,7 +695,7 @@ isapnp_write_data(uint16_t addr, uint8_t val, void *priv)
}
static void *
isapnp_init(const device_t *info)
isapnp_init(UNUSED(const device_t *info))
{
isapnp_t *dev = (isapnp_t *) malloc(sizeof(isapnp_t));
memset(dev, 0, sizeof(isapnp_t));
@@ -862,6 +866,9 @@ isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size)
default:
isapnp_log("ISAPnP: >%s%s Large resource %02X (length %d)\n", ldn ? ">" : "", in_df ? ">" : "", res, (card->rom[i + 2] << 8) | card->rom[i + 1]);
break;
#else
default:
break;
#endif
}
@@ -1022,11 +1029,11 @@ isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size)
card->rom_size = i + 2;
break;
#ifdef ENABLE_ISAPNP_LOG
default:
#ifdef ENABLE_ISAPNP_LOG
isapnp_log("ISAPnP: >%s%s Small resource %02X (length %d)\n", ldn ? ">" : "", in_df ? ">" : "", res, card->rom[i] & 0x07);
break;
#endif
break;
}
i++; /* header */

3
src/device/isartc.c
View File

@@ -427,7 +427,6 @@ mm67_write(uint16_t port, uint8_t val, void *priv)
{
rtcdev_t *dev = (rtcdev_t *) priv;
int reg = port - dev->base_addr;
int i;
#if ISARTC_DEBUG
isartc_log("ISARTC: write(%04x, %02x)\n", port - dev->base_addr, val);
@@ -452,7 +451,7 @@ mm67_write(uint16_t port, uint8_t val, void *priv)
case MM67_RSTRAM:
if (val == 0xff) {
for (i = MM67_AL_MSEC; i <= MM67_AL_MON; i++)
for (uint8_t i = MM67_AL_MSEC; i <= MM67_AL_MON; i++)
dev->nvr.regs[i] = RTC_BCD(0);
dev->nvr.regs[MM67_DOW] = RTC_BCD(1);
dev->nvr.regs[MM67_DOM] = RTC_BCD(1);

47
src/device/kbc_at.c
View File

@@ -29,6 +29,7 @@
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/ppi.h>
#include <86box/mem.h>
#include <86box/device.h>
@@ -279,6 +280,8 @@ kbc_translate(atkbc_t *dev, uint8_t val)
case 0x4d:
t3100e_notify_set(0x0f);
break; /* Right */
default:
break;
}
kbc_at_log("ATkbc: translate is %s, ", translate ? "on" : "off");
@@ -399,10 +402,14 @@ kbc_scan_kbd_at(atkbc_t *dev)
kbc_ibf_process(dev);
/* AT mode. */
} else {
// dev->t = dev->mem[0x28];
#if 0
dev->t = dev->mem[0x28];
#endif
if (dev->mem[0x2e] != 0x00) {
// if (!(dev->t & 0x02))
// return;
#if 0
if (!(dev->t & 0x02))
return;
#endif
dev->mem[0x2e] = 0x00;
}
dev->p2 &= 0xbf;
@@ -466,7 +473,9 @@ at_main_ibf:
/* Keyboard controller command want to output a single byte. */
kbc_at_log("ATkbc: %02X coming from channel %i with high status %02X\n", dev->val, dev->channel, dev->stat_hi);
kbc_send_to_ob(dev, dev->val, dev->channel, dev->stat_hi);
// dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
#if 0
dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
#endif
dev->state = STATE_MAIN_IBF;
dev->pending = 0;
goto at_main_ibf;
@@ -608,7 +617,9 @@ ps2_main_ibf:
/* Keyboard controller command want to output a single byte. */
kbc_at_log("ATkbc: %02X coming from channel %i with high status %02X\n", dev->val, dev->channel, dev->stat_hi);
kbc_send_to_ob(dev, dev->val, dev->channel, dev->stat_hi);
// dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
#if 0
dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
#endif
dev->state = STATE_MAIN_IBF;
dev->pending = 0;
goto ps2_main_ibf;
@@ -1041,6 +1052,9 @@ write60_ami(void *priv, uint8_t val)
kbc_at_do_poll = kbc_at_poll_at;
}
return 0;
default:
break;
}
return 1;
@@ -1244,13 +1258,16 @@ write64_ami(void *priv, uint8_t val)
case 0xef: /* ??? - sent by AMI486 */
kbc_at_log("ATkbc: ??? - sent by AMI486\n");
return 0;
default:
break;
}
return write64_generic(dev, val);
}
static uint8_t
write60_quadtel(void *priv, uint8_t val)
write60_quadtel(void *priv, UNUSED(uint8_t val))
{
atkbc_t *dev = (atkbc_t *) priv;
@@ -1258,6 +1275,8 @@ write60_quadtel(void *priv, uint8_t val)
case 0xcf: /*??? - sent by MegaPC BIOS*/
kbc_at_log("ATkbc: ??? - sent by MegaPC BIOS\n");
return 0;
default:
break;
}
return 1;
@@ -1280,6 +1299,8 @@ write64_olivetti(void *priv, uint8_t val)
kbc_delay_to_ob(dev, (0x0c | (is386 ? 0x00 : 0x80)) & 0xdf, 0, 0x00);
dev->p1 = ((dev->p1 + 1) & 3) | (dev->p1 & 0xfc);
return 0;
default:
break;
}
return write64_generic(dev, val);
@@ -1300,6 +1321,9 @@ write64_quadtel(void *priv, uint8_t val)
dev->wantdata = 1;
dev->state = STATE_KBC_PARAM;
return 0;
default:
break;
}
return write64_generic(dev, val);
@@ -1315,6 +1339,8 @@ write60_toshiba(void *priv, uint8_t val)
kbc_at_log("ATkbc: T3100e - set color/mono switch\n");
t3100e_mono_set(val);
return 0;
default:
break;
}
return 1;
@@ -1405,6 +1431,9 @@ write64_toshiba(void *priv, uint8_t val)
dev->p1 = (t3100e_mono_get() & 1) ? 0xff : 0xbf;
kbc_delay_to_ob(dev, dev->p1, 0, 0x00);
return 0;
default:
break;
}
return write64_generic(dev, val);
@@ -1726,6 +1755,9 @@ kbc_at_write(uint16_t port, uint8_t val, void *priv)
return;
}
break;
default:
break;
}
dev->ib = val;
@@ -1922,6 +1954,9 @@ kbc_at_init(const device_t *info)
dev->write60_ven = write60_toshiba;
dev->write64_ven = write64_toshiba;
break;
default:
break;
}
max_ports = ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) ? 2 : 1;

2
src/device/kbc_at_dev.c
View File

@@ -169,6 +169,8 @@ kbc_at_dev_poll(void *priv)
if (dev->cmd_queue_start == dev->cmd_queue_end)
dev->state = DEV_STATE_EXECUTE_BAT;
break;
default:
break;
}
}

8
src/device/keyboard.c
View File

@@ -167,6 +167,8 @@ keyboard_input(int down, uint16_t scan)
case 0x138: /* Right Alt */
shift |= 0x40;
break;
default:
break;
}
} else {
switch (scan & 0x1ff) {
@@ -197,13 +199,17 @@ keyboard_input(int down, uint16_t scan)
case 0x046:
scroll_lock ^= 1;
break;
default:
break;
}
}
}
/* NOTE: Shouldn't this be some sort of bit shift? An array of 8 unsigned 64-bit integers
should be enough. */
/* recv_key[scan >> 6] |= ((uint64_t) down << ((uint64_t) scan & 0x3fLL)); */
#if 0
recv_key[scan >> 6] |= ((uint64_t) down << ((uint64_t) scan & 0x3fLL));
#endif
/* pclog("Received scan code: %03X (%s)\n", scan & 0x1ff, down ? "down" : "up"); */
recv_key[scan & 0x1ff] = down;

2
src/device/keyboard_at.c
View File

@@ -491,8 +491,8 @@ static void
keyboard_at_set_scancode_set(void)
{
switch (keyboard_mode) {
case 0x01:
default:
case 0x01:
keyboard_set_table(scancode_set1);
break;

9
src/device/keyboard_xt.c
View File

@@ -454,6 +454,9 @@ kbd_adddata(uint16_t val)
case 0x54: /* SysRQ => toggle window */
t1000_syskey(0x00, 0x00, 0x08);
break;
default:
break;
}
} else
t1000_syskey(0x04, 0x00, 0x00); /* Reset 'Fn' indicator */
@@ -578,6 +581,9 @@ kbd_write(uint16_t port, uint8_t val, void *priv)
kbd->pravetz_flags = (kbd->pravetz_flags & ~(1 << bit)) | set;
}
break;
default:
break;
}
}
@@ -686,6 +692,9 @@ kbd_read(uint16_t port, void *priv)
ret = kbd->pravetz_flags;
kbd_log("XTkbd: Port %02X in : %02X\n", port, ret);
break;
default:
break;
}
return ret;

3
src/device/mouse.c
View File

@@ -30,6 +30,7 @@
#include <86box/timer.h>
#include <86box/gdbstub.h>
#include <86box/mouse.h>
#include <86box/plat_unused.h>
typedef struct {
const device_t *device;
@@ -152,7 +153,7 @@ mouse_close(void)
}
static void
mouse_timer_poll(void *priv)
mouse_timer_poll(UNUSED(void *priv))
{
/* Poll at 255 Hz, maximum supported by PS/2 mic. */
timer_on_auto(&mouse_timer, 1000000.0 / sample_rate);

13
src/device/mouse_bus.c
View File

@@ -80,6 +80,7 @@
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/mouse.h>
#include <86box/plat_unused.h>
#include <86box/random.h>
#define IRQ_MASK ((1 << 5) >> dev->irq)
@@ -216,6 +217,8 @@ lt_read(uint16_t port, void *priv)
else
return 0xff;
break;
default:
break;
}
bm_log("DEBUG: read from address 0x%04x, value = 0x%02x\n", port, value);
@@ -263,6 +266,8 @@ ms_read(uint16_t port, void *priv)
case INP_PORT_CONFIG:
bm_log("ERROR: Unsupported read from port 0x%04x\n", port);
break;
default:
break;
}
bm_log("DEBUG: read from address 0x%04x, value = 0x%02x\n", port, value);
@@ -355,6 +360,9 @@ lt_write(uint16_t port, uint8_t val, void *priv)
dev->control_val &= ~bit; /* Reset */
}
break;
default:
break;
}
}
@@ -444,12 +452,15 @@ ms_write(uint16_t port, uint8_t val, void *priv)
case INP_PORT_CONFIG:
bm_log("ERROR: Unsupported write to port 0x%04x (value = 0x%02x)\n", port, val);
break;
default:
break;
}
}
/* The emulator calls us with an update on the host mouse device. */
static int
bm_poll(int x, int y, int z, int b, double abs_x, double abs_y, void *priv)
bm_poll(int x, int y, UNUSED(int z), int b, UNUSED(double abs_x), UNUSED(double abs_y), void *priv)
{
mouse_t *dev = (mouse_t *) priv;
int xor ;

3
src/device/mouse_ps2.c
View File

@@ -23,6 +23,7 @@
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mouse.h>
#include <86box/plat_unused.h>
enum {
MODE_STREAM,
@@ -310,7 +311,7 @@ ps2_write(void *priv)
}
static int
ps2_poll(int x, int y, int z, int b, double abs_x, double abs_y, void *priv)
ps2_poll(int x, int y, int z, int b, UNUSED(double abs_x), UNUSED(double abs_y), void *priv)
{
atkbc_dev_t *dev = (atkbc_dev_t *) priv;
int packet_size = (dev->flags & FLAG_INTMODE) ? 4 : 3;

22
src/device/mouse_serial.c
View File

@@ -26,6 +26,7 @@
#include <86box/timer.h>
#include <86box/serial.h>
#include <86box/mouse.h>
#include <86box/plat_unused.h>
#define SERMOUSE_PORT 0 /* attach to Serial0 */
@@ -138,8 +139,8 @@ sermouse_transmit_period(mouse_t *dev, int bps, int rps)
case 5: /* MM Series format: 8 data, odd parity, 1 stop, 1 start */
word_len = 11;
break;
default:
case 7: /* Microsoft-compatible format: 7 data, no parity, 1 stop, 1 start */
default:
word_len = 9;
break;
}
@@ -158,7 +159,7 @@ sermouse_transmit_period(mouse_t *dev, int bps, int rps)
/* Callback from serial driver: RTS was toggled. */
static void
sermouse_callback(struct serial_s *serial, void *priv)
sermouse_callback(UNUSED(struct serial_s *serial), void *priv)
{
mouse_t *dev = (mouse_t *) priv;
@@ -332,6 +333,9 @@ sermouse_report(int x, int y, int z, int b, mouse_t *dev)
case 7:
len = sermouse_data_ms(dev, x, y, z, b);
break;
default:
break;
}
dev->data_len = len;
@@ -527,7 +531,7 @@ sermouse_command_timer(void *priv)
}
static int
sermouse_poll(int x, int y, int z, int b, double abs_x, double abs_y, void *priv)
sermouse_poll(int x, int y, int z, int b, UNUSED(double abs_x), UNUSED(double abs_y), void *priv)
{
mouse_t *dev = (mouse_t *) priv;
@@ -613,7 +617,7 @@ ltsermouse_switch_baud_rate(mouse_t *dev, int phase)
}
static void
ltsermouse_write(struct serial_s *serial, void *priv, uint8_t data)
ltsermouse_write(UNUSED(struct serial_s *serial), void *priv, uint8_t data)
{
mouse_t *dev = (mouse_t *) priv;
@@ -644,6 +648,8 @@ ltsermouse_write(struct serial_s *serial, void *priv, uint8_t data)
}
ltsermouse_switch_baud_rate(dev, PHASE_BAUD_RATE);
break;
default:
break;
}
else
switch (data) {
@@ -728,11 +734,13 @@ ltsermouse_write(struct serial_s *serial, void *priv, uint8_t data)
case 0x6B:
ltsermouse_command_phase(dev, PHASE_BUTTONS);
break;
default:
break;
}
}
static void
ltsermouse_transmit_period(serial_t *serial, void *priv, double transmit_period)
ltsermouse_transmit_period(UNUSED(serial_t *serial), void *priv, double transmit_period)
{
mouse_t *dev = (mouse_t *) priv;
@@ -796,8 +804,8 @@ sermouse_init(const device_t *info)
dev->id_len = 1;
dev->id[0] = 'M';
switch (dev->but) {
case 2:
default:
case 2:
dev->type = info->local ? MOUSE_TYPE_LOGITECH : MOUSE_TYPE_MICROSOFT;
break;
case 3:
@@ -846,7 +854,7 @@ sermouse_init(const device_t *info)
mouse_set_buttons((dev->flags & FLAG_3BTN) ? 3 : 2);
/* Return our private data to the I/O layer. */
return (dev);
return dev;
}
static const device_config_t mssermouse_config[] = {

16
src/device/mouse_wacom_tablet.c
View File

@@ -197,6 +197,9 @@ wacom_process_settings_dword(mouse_wacom_t *wacom, uint32_t dword)
case 3:
wacom->transmit_period = wacom_transmit_period(wacom, 19200, -1);
break;
default:
break;
}
mouse_mode = !wacom->settings_bits.coord_sys;
@@ -245,7 +248,7 @@ wacom_reset_artpad(mouse_wacom_t *wacom)
}
static void
wacom_callback(struct serial_s *serial, void *priv)
wacom_callback(UNUSED(struct serial_s *serial), void *priv)
{
mouse_wacom_t *wacom = (mouse_wacom_t *) priv;
@@ -265,13 +268,16 @@ wacom_callback(struct serial_s *serial, void *priv)
case 3:
wacom->transmit_period = wacom_transmit_period(wacom, 19200, -1);
break;
default:
break;
}
timer_stop(&wacom->report_timer);
timer_on_auto(&wacom->report_timer, wacom->transmit_period);
}
static void
wacom_write(struct serial_s *serial, void *priv, uint8_t data)
wacom_write(UNUSED(struct serial_s *serial), void *priv, uint8_t data)
{
mouse_wacom_t *wacom = (mouse_wacom_t *) priv;
static int special_command = 0;
@@ -295,6 +301,8 @@ wacom_write(struct serial_s *serial, void *priv, uint8_t data)
wacom->data_rec[wacom->data_rec_pos++] = data;
break;
}
default:
break;
}
special_command = 0;
return;
@@ -403,7 +411,7 @@ wacom_write(struct serial_s *serial, void *priv, uint8_t data)
}
static int
wacom_poll(int x, int y, int z, int b, double abs_x, double abs_y, void *priv)
wacom_poll(int x, int y, UNUSED(int z), int b, double abs_x, double abs_y, void *priv)
{
mouse_wacom_t *wacom = (mouse_wacom_t *) priv;
@@ -563,8 +571,8 @@ wacom_report_timer(void *priv)
return;
switch (wacom->mode) {
case WACOM_MODE_STREAM:
default:
case WACOM_MODE_STREAM:
break;
case WACOM_MODE_POINT:

6
src/device/pci_bridge.c
View File

@@ -352,6 +352,9 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
return;
}
break;
default:
break;
}
dev->regs[addr] = val;
@@ -434,6 +437,9 @@ pci_bridge_reset(void *priv)
dev->regs[0x06] = 0x20;
dev->regs[0x07] = 0x02;
break;
default:
break;
}
/* class */

5
src/device/phoenix_486_jumper.c
View File

@@ -28,6 +28,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
/*
Bit 7 = Super I/O chip: 1 = enabled, 0 = disabled;
@@ -64,7 +65,7 @@ phoenix_486_jumper_log(const char *fmt, ...)
#endif
static void
phoenix_486_jumper_write(uint16_t addr, uint8_t val, void *priv)
phoenix_486_jumper_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
phoenix_486_jumper_log("Phoenix 486 Jumper: Write %02x\n", val);
@@ -75,7 +76,7 @@ phoenix_486_jumper_write(uint16_t addr, uint8_t val, void *priv)
}
static uint8_t
phoenix_486_jumper_read(uint16_t addr, void *priv)
phoenix_486_jumper_read(UNUSED(uint16_t addr), void *priv)
{
phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
phoenix_486_jumper_log("Phoenix 486 Jumper: Read %02x\n", dev->jumper);

4
src/device/postcard.c
View File

@@ -86,7 +86,7 @@ postcard_reset(void)
}
static void
postcard_write(uint16_t port, uint8_t val, void *priv)
postcard_write(UNUSED(uint16_t port), uint8_t val, UNUSED(void *priv))
{
if (postcard_written && (val == postcard_code))
return;
@@ -100,7 +100,7 @@ postcard_write(uint16_t port, uint8_t val, void *priv)
}
static void *
postcard_init(const device_t *info)
postcard_init(UNUSED(const device_t *info))
{
postcard_reset();

22
src/device/serial.c
View File

@@ -154,7 +154,9 @@ serial_receive_timer(void *priv)
{
serial_t *dev = (serial_t *) priv;
// serial_log("serial_receive_timer()\n");
#if 0
serial_log("serial_receive_timer()\n");
#endif
timer_on_auto(&dev->receive_timer, /* dev->bits * */ dev->transmit_period);
@@ -174,7 +176,9 @@ serial_receive_timer(void *priv)
} else {
/* We can input data into the FIFO. */
dev->rcvr_fifo[dev->rcvr_fifo_end] = (uint8_t) (dev->out_new & 0xff);
// dev->rcvr_fifo_end = (dev->rcvr_fifo_end + 1) & 0x0f;
#if 0
dev->rcvr_fifo_end = (dev->rcvr_fifo_end + 1) & 0x0f;
#endif
/* Do not wrap around, makes sure it still triggers the interrupt
at 16 bytes. */
dev->rcvr_fifo_end++;
@@ -557,6 +561,8 @@ serial_write(uint16_t addr, uint8_t val, void *p)
case 3:
dev->rcvr_fifo_len = 14;
break;
default:
break;
}
dev->out_new = 0xffff;
serial_log("FIFO now %sabled, receive FIFO length = %i\n", dev->fifo_enabled ? "en" : "dis", dev->rcvr_fifo_len);
@@ -624,8 +630,10 @@ serial_write(uint16_t addr, uint8_t val, void *p)
serial_update_ints(dev);
break;
case 6:
// dev->msr = (val & 0xf0) | (dev->msr & 0x0f);
// dev->msr = val;
#if 0
dev->msr = (val & 0xf0) | (dev->msr & 0x0f);
dev->msr = val;
#endif
/* The actual condition bits of the MSR are read-only, but the delta bits are
undocumentedly writable, and the PCjr BIOS uses them to raise MSR interrupts. */
dev->msr = (dev->msr & 0xf0) | (val & 0x0f);
@@ -637,6 +645,8 @@ serial_write(uint16_t addr, uint8_t val, void *p)
if (dev->type >= SERIAL_16450)
dev->scratch = val;
break;
default:
break;
}
}
@@ -736,6 +746,8 @@ serial_read(uint16_t addr, void *p)
case 7:
ret = dev->scratch;
break;
default:
break;
}
// serial_log("UART: Read %02X from port %02X\n", ret, addr);
@@ -914,7 +926,7 @@ serial_set_next_inst(int ni)
void
serial_standalone_init(void)
{
for (; next_inst < SERIAL_MAX;)
while (next_inst < SERIAL_MAX)
device_add_inst(&ns8250_device, next_inst + 1);
};

37
src/device/serial_passthrough.c
View File

@@ -29,6 +29,7 @@
#include <86box/serial.h>
#include <86box/serial_passthrough.h>
#include <86box/plat_serial_passthrough.h>
#include <86box/plat_unused.h>
#define ENABLE_SERIAL_PASSTHROUGH_LOG 1
#ifdef ENABLE_SERIAL_PASSTHROUGH_LOG
@@ -61,7 +62,7 @@ serial_passthrough_init(void)
}
static void
serial_passthrough_write(serial_t *s, void *priv, uint8_t val)
serial_passthrough_write(UNUSED(serial_t *s), void *priv, uint8_t val)
{
plat_serpt_write(priv, val);
}
@@ -86,24 +87,32 @@ host_to_serial_cb(void *priv)
}
}
if (plat_serpt_read(dev, &byte)) {
// printf("got byte %02X\n", byte);
#if 0
printf("got byte %02X\n", byte);
#endif
serial_write_fifo(dev->serial, byte);
// serial_set_dsr(dev->serial, 1);
#if 0
serial_set_dsr(dev->serial, 1);
#endif
}
no_write_to_machine:
// serial_device_timeout(dev->serial);
#if 0
serial_device_timeout(dev->serial);
#endif
timer_on_auto(&dev->host_to_serial_timer, (1000000.0 / dev->baudrate) * (double) dev->bits);
}
static void
serial_passthrough_rcr_cb(struct serial_s *serial, void *priv)
serial_passthrough_rcr_cb(UNUSED(struct serial_s *serial), void *priv)
{
serial_passthrough_t *dev = (serial_passthrough_t *) priv;
timer_stop(&dev->host_to_serial_timer);
/* FIXME: do something to dev->baudrate */
timer_on_auto(&dev->host_to_serial_timer, (1000000.0 / dev->baudrate) * (double) dev->bits);
// serial_clear_fifo(dev->serial);
#if 0
serial_clear_fifo(dev->serial);
#endif
}
static void
@@ -114,7 +123,9 @@ serial_passthrough_speed_changed(void *priv)
timer_stop(&dev->host_to_serial_timer);
/* FIXME: do something to dev->baudrate */
timer_on_auto(&dev->host_to_serial_timer, (1000000.0 / dev->baudrate) * (double) dev->bits);
// serial_clear_fifo(dev->serial);
#if 0
serial_clear_fifo(dev->serial);
#endif
}
static void
@@ -131,28 +142,28 @@ serial_passthrough_dev_close(void *priv)
}
void
serial_passthrough_transmit_period(serial_t *serial, void *p, double transmit_period)
serial_passthrough_transmit_period(UNUSED(serial_t *serial), void *priv, double transmit_period)
{
serial_passthrough_t *dev = (serial_passthrough_t *) p;
serial_passthrough_t *dev = (serial_passthrough_t *) priv;
if (dev->mode != SERPT_MODE_HOSTSER)
return;
dev->baudrate = 1000000.0 / transmit_period;
serial_passthrough_speed_changed(p);
serial_passthrough_speed_changed(priv);
plat_serpt_set_params(dev);
}
void
serial_passthrough_lcr_callback(serial_t *serial, void *p, uint8_t lcr)
serial_passthrough_lcr_callback(serial_t *serial, void *priv, uint8_t lcr)
{
serial_passthrough_t *dev = (serial_passthrough_t *) p;
serial_passthrough_t *dev = (serial_passthrough_t *) priv;
if (dev->mode != SERPT_MODE_HOSTSER)
return;
dev->bits = serial->bits;
dev->data_bits = ((lcr & 0x03) + 5);
serial_passthrough_speed_changed(p);
serial_passthrough_speed_changed(priv);
plat_serpt_set_params(dev);
}

6
src/device/smbus_ali7101.c
View File

@@ -79,6 +79,9 @@ smbus_ali7101_read(uint16_t addr, void *priv)
case 0x07:
ret = dev->cmd;
break;
default:
break;
}
smbus_ali7101_log("SMBus ALI7101: read(%02X) = %02x\n", addr, ret);
@@ -223,6 +226,9 @@ smbus_ali7101_write(uint16_t addr, uint8_t val, void *priv)
case 0x07:
dev->cmd = val;
break;
default:
break;
}
if (dev->next_stat != 0x04) { /* schedule dispatch of any pending status register update */

6
src/device/smbus_piix4.c
View File

@@ -83,6 +83,9 @@ smbus_piix4_read(uint16_t addr, void *priv)
if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE)
dev->index = 0;
break;
default:
break;
}
smbus_piix4_log("SMBus PIIX4: read(%02X) = %02x\n", addr, ret);
@@ -309,6 +312,9 @@ unknown_protocol:
if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE)
dev->index = 0;
break;
default:
break;
}
if (dev->next_stat) { /* schedule dispatch of any pending status register update */

22
src/disk/hdc_esdi_at.c
View File

@@ -84,7 +84,11 @@ typedef struct {
typedef struct {
uint8_t status;
uint8_t error;
int secount, sector, cylinder, head, cylprecomp;
int secount;
int sector;
int cylinder;
int head;
int cylprecomp;
uint8_t command;
uint8_t fdisk;
int pos;
@@ -132,13 +136,13 @@ irq_raise(esdi_t *esdi)
}
static __inline void
irq_lower(esdi_t *esdi)
irq_lower(UNUSED(esdi_t *esdi))
{
picintc(1 << 14);
}
static __inline void
irq_update(esdi_t *esdi)
irq_update(UNUSED(esdi_t *esdi))
{
if (esdi->irqstat && !((pic2.irr | pic2.isr) & 0x40) && !(esdi->fdisk & 2))
picint(1 << 14);
@@ -159,7 +163,7 @@ esdi_set_callback(esdi_t *esdi, double callback)
}
double
esdi_get_xfer_time(esdi_t *esdi, int size)
esdi_get_xfer_time(UNUSED(esdi_t *esdi), int size)
{
/* 390.625 us per sector at 10 Mbit/s = 1280 kB/s. */
return (3125.0 / 8.0) * (double) size;
@@ -417,6 +421,9 @@ esdi_write(uint16_t port, uint8_t val, void *priv)
esdi->fdisk = val;
irq_update(esdi);
break;
default:
break;
}
}
@@ -498,6 +505,9 @@ esdi_read(uint16_t port, void *priv)
irq_lower(esdi);
temp = esdi->status;
break;
default:
break;
}
esdi_at_log("WD1007 read(%04x) = %02x\n", port, temp);
@@ -791,7 +801,7 @@ esdi_callback(void *priv)
}
static void
loadhd(esdi_t *esdi, int hdd_num, int d, const char *fn)
loadhd(esdi_t *esdi, int hdd_num, int d, UNUSED(const char *fn))
{
drive_t *drive = &esdi->drives[hdd_num];
@@ -822,7 +832,7 @@ esdi_rom_write(uint32_t addr, uint8_t val, void *p)
}
static void *
wd1007vse1_init(const device_t *info)
wd1007vse1_init(UNUSED(const device_t *info))
{
int c;

36
src/disk/hdc_esdi_mca.c
View File

@@ -82,6 +82,7 @@
#include <86box/ui.h>
#include <86box/hdc.h>
#include <86box/hdd.h>
#include <86box/plat_unused.h>
/* These are hardwired. */
#define ESDI_IOADDR_PRI 0x3510
@@ -117,8 +118,8 @@ typedef struct esdi_t {
uint16_t cmd_data[4];
int cmd_dev;
int status_pos,
status_len;
int status_pos;
int status_len;
uint16_t status_data[256];
@@ -221,7 +222,7 @@ set_irq(esdi_t *dev)
}
static __inline void
clear_irq(esdi_t *dev)
clear_irq(UNUSED(esdi_t *dev))
{
picintc(1 << 14);
}
@@ -241,7 +242,7 @@ esdi_mca_set_callback(esdi_t *dev, double callback)
}
static double
esdi_mca_get_xfer_time(esdi_t *esdi, int size)
esdi_mca_get_xfer_time(UNUSED(esdi_t *esdi), int size)
{
/* 390.625 us per sector at 10 Mbit/s = 1280 kB/s. */
return (3125.0 / 8.0) * (double) size;
@@ -440,6 +441,9 @@ esdi_callback(void *priv)
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
@@ -513,6 +517,9 @@ esdi_callback(void *priv)
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
@@ -546,6 +553,9 @@ esdi_callback(void *priv)
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
@@ -577,6 +587,9 @@ esdi_callback(void *priv)
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
@@ -695,7 +708,6 @@ esdi_callback(void *priv)
}
dev->data[dev->data_pos++] = val & 0xffff;
;
}
memcpy(dev->sector_buffer[dev->sector_pos++], dev->data, 512);
@@ -714,6 +726,9 @@ esdi_callback(void *priv)
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
default:
break;
}
break;
@@ -771,6 +786,9 @@ esdi_callback(void *priv)
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
default:
break;
}
break;
@@ -839,6 +857,9 @@ esdi_callback(void *priv)
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
@@ -1085,6 +1106,9 @@ esdi_mca_write(int port, uint8_t val, void *priv)
case 0x10:
dev->dma = 4;
break;
default:
break;
}
if (dev->pos_regs[2] & 1) {
@@ -1113,7 +1137,7 @@ esdi_mca_feedb(void *priv)
}
static void *
esdi_init(const device_t *info)
esdi_init(UNUSED(const device_t *info))
{
drive_t *drive;
esdi_t *dev;

32
src/disk/hdc_ide.c
View File

@@ -111,10 +111,14 @@
#define IDE_TIME 10.0
typedef struct {
int bit32, cur_dev,
irq, inited,
diag, force_ata3;
uint16_t base_main, side_main;
int bit32;
int cur_dev;
int irq;
int inited;
int diag;
int force_ata3;
uint16_t base_main;
uint16_t side_main;
pc_timer_t timer;
ide_t *ide[2];
} ide_board_t;
@@ -717,7 +721,7 @@ ide_next_sector(ide_t *ide)
}
static void
loadhd(ide_t *ide, int d, const char *fn)
loadhd(ide_t *ide, int d, UNUSED(const char *fn))
{
if (!hdd_image_load(d)) {
ide->type = IDE_NONE;
@@ -746,7 +750,9 @@ ide_set_signature(ide_t *ide)
ide->cylinder = ide->sc->request_length;
} else {
ide->secount = 1;
// ide->cylinder = ((ide->type == IDE_HDD) ? 0 : 0xFFFF);
#if 0
ide->cylinder = ((ide->type == IDE_HDD) ? 0 : 0xFFFF);
#endif
ide->cylinder = ((ide->type == IDE_HDD) ? 0 : 0x7F7F);
if (ide->type == IDE_HDD)
ide->drive = 0;
@@ -851,7 +857,7 @@ ide_set_sector(ide_t *ide, int64_t sector_num)
if (ide->lba) {
ide->head = (sector_num >> 24);
ide->cylinder = (sector_num >> 8);
ide->sector = (sector_num);
ide->sector = sector_num;
} else {
cyl = sector_num / (hdd[ide->hdd_num].hpc * hdd[ide->hdd_num].spt);
r = sector_num % (hdd[ide->hdd_num].hpc * hdd[ide->hdd_num].spt);
@@ -1334,7 +1340,7 @@ dev_reset(ide_t *ide)
}
void
ide_write_devctl(uint16_t addr, uint8_t val, void *priv)
ide_write_devctl(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
ide_board_t *dev = (ide_board_t *) priv;
@@ -2048,7 +2054,7 @@ ide_readb(uint16_t addr, void *priv)
}
uint8_t
ide_read_alt_status(uint16_t addr, void *priv)
ide_read_alt_status(UNUSED(uint16_t addr), void *priv)
{
uint8_t temp = 0xff;
@@ -2957,7 +2963,7 @@ ide_ter_init(const device_t *info)
/* Close a standalone IDE unit. */
static void
ide_ter_close(void *priv)
ide_ter_close(UNUSED(void *priv))
{
ide_board_close(2);
}
@@ -2988,7 +2994,7 @@ ide_qua_init(const device_t *info)
/* Close a standalone IDE unit. */
static void
ide_qua_close(void *priv)
ide_qua_close(UNUSED(void *priv))
{
ide_board_close(3);
}
@@ -3087,7 +3093,7 @@ ide_board_reset(int board)
/* Reset a standalone IDE unit. */
static void
ide_reset(void *p)
ide_reset(UNUSED(void *priv))
{
ide_log("Resetting IDE...\n");
@@ -3100,7 +3106,7 @@ ide_reset(void *p)
/* Close a standalone IDE unit. */
static void
ide_close(void *priv)
ide_close(UNUSED(void *priv))
{
ide_log("Closing IDE...\n");

30
src/disk/hdc_ide_cmd640.c
View File

@@ -37,14 +37,17 @@
#include <86box/zip.h>
#include <86box/mo.h>
typedef struct
{
uint8_t vlb_idx, id,
in_cfg, single_channel,
pci, regs[256];
typedef struct {
uint8_t vlb_idx;
uint8_t id;
uint8_t in_cfg;
uint8_t single_channel;
uint8_t pci, regs[256];
uint32_t local;
int slot, irq_mode[2],
irq_pin, irq_line;
int slot;
int irq_mode[2];
int irq_pin;
int irq_line;
} cmd640_t;
static int next_id = 0;
@@ -166,6 +169,9 @@ cmd640_common_write(int addr, uint8_t val, cmd640_t *dev)
case 0x5b: /* Undocumented register that Linux attempts to use! */
dev->regs[addr] = val;
break;
default:
break;
}
}
@@ -188,6 +194,9 @@ cmd640_vlb_write(uint16_t addr, uint8_t val, void *priv)
if (dev->regs[0x50] & 0x80)
dev->in_cfg = 0;
break;
default:
break;
}
}
@@ -227,6 +236,9 @@ cmd640_vlb_read(uint16_t addr, void *priv)
if (dev->regs[0x50] & 0x80)
dev->in_cfg = 0;
break;
default:
break;
}
return ret;
@@ -462,7 +474,9 @@ cmd640_init(const device_t *info)
ide_board_set_force_ata3(0, 1);
ide_board_set_force_ata3(1, 1);
// ide_pri_disable();
#if 0
ide_pri_disable();
#endif
} else if (info->flags & DEVICE_VLB) {
device_add(&ide_vlb_2ch_device);

19
src/disk/hdc_ide_cmd646.c
View File

@@ -37,13 +37,15 @@
#include <86box/zip.h>
#include <86box/mo.h>
typedef struct
{
uint8_t vlb_idx, single_channel,
in_cfg, regs[256];
uint32_t local;
int slot, irq_mode[2],
irq_pin;
typedef struct {
uint8_t vlb_idx;
uint8_t single_channel;
uint8_t in_cfg;
uint8_t regs[256];
uint32_t local;
int slot;
int irq_mode[2];
int irq_pin;
sff8038i_t *bm[2];
} cmd646_t;
@@ -262,6 +264,9 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
case 0x78 ... 0x7f:
sff_bus_master_write(addr & 0x0f, val, dev->bm[1]);
break;
default:
break;
}
}

13
src/disk/hdc_ide_opti611.c
View File

@@ -28,6 +28,7 @@
#include <86box/mem.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/plat_unused.h>
typedef struct
{
@@ -68,6 +69,9 @@ opti611_cfg_write(uint16_t addr, uint8_t val, void *priv)
case 0x0006:
dev->regs[0x06] = val;
break;
default:
break;
}
}
@@ -109,6 +113,9 @@ opti611_cfg_read(uint16_t addr, void *priv)
case 0x0006:
ret = dev->regs[addr];
break;
default:
break;
}
return ret;
@@ -153,7 +160,7 @@ opti611_ide_write(uint16_t addr, uint8_t val, void *priv)
}
static void
opti611_ide_writew(uint16_t addr, uint16_t val, void *priv)
opti611_ide_writew(uint16_t addr, UNUSED(uint16_t val), void *priv)
{
opti611_t *dev = (opti611_t *) priv;
@@ -169,7 +176,7 @@ opti611_ide_writew(uint16_t addr, uint16_t val, void *priv)
}
static void
opti611_ide_writel(uint16_t addr, uint32_t val, void *priv)
opti611_ide_writel(uint16_t addr, UNUSED(uint32_t val), void *priv)
{
opti611_t *dev = (opti611_t *) priv;
@@ -281,7 +288,7 @@ opti611_close(void *priv)
}
static void *
opti611_init(const device_t *info)
opti611_init(UNUSED(const device_t *info))
{
opti611_t *dev = (opti611_t *) malloc(sizeof(opti611_t));
memset(dev, 0, sizeof(opti611_t));

29
src/disk/hdc_ide_sff8038i.c
View File

@@ -42,6 +42,7 @@
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/mo.h>
#include <86box/plat_unused.h>
static int next_id = 0;
@@ -160,6 +161,9 @@ sff_bus_master_write(uint16_t port, uint8_t val, void *priv)
dev->ptr = (dev->ptr & 0x00fffffc) | (val << 24);
dev->ptr %= (mem_size * 1024);
break;
default:
break;
}
}
@@ -185,6 +189,9 @@ sff_bus_master_writew(uint16_t port, uint16_t val, void *priv)
dev->ptr = (dev->ptr & 0x0000fffc) | (val << 16);
dev->ptr %= (mem_size * 1024);
break;
default:
break;
}
}
@@ -206,6 +213,9 @@ sff_bus_master_writel(uint16_t port, uint32_t val, void *priv)
dev->ptr %= (mem_size * 1024);
dev->ptr0 = val & 0xff;
break;
default:
break;
}
}
@@ -238,6 +248,9 @@ sff_bus_master_read(uint16_t port, void *priv)
case 7:
ret = dev->ptr >> 24;
break;
default:
break;
}
sff_log("SFF-8038i Bus master BYTE read : %04X %02X\n", port, ret);
@@ -264,6 +277,9 @@ sff_bus_master_readw(uint16_t port, void *priv)
case 6:
ret = dev->ptr >> 16;
break;
default:
break;
}
sff_log("SFF-8038i Bus master WORD read : %04X %04X\n", port, ret);
@@ -287,6 +303,9 @@ sff_bus_master_readl(uint16_t port, void *priv)
case 4:
ret = dev->ptr0 | (dev->ptr & 0xffffff00);
break;
default:
break;
}
sff_log("sff Bus master DWORD read : %04X %08X\n", port, ret);
@@ -295,7 +314,7 @@ sff_bus_master_readl(uint16_t port, void *priv)
}
int
sff_bus_master_dma(int channel, uint8_t *data, int transfer_length, int out, void *priv)
sff_bus_master_dma(UNUSED(int channel), uint8_t *data, int transfer_length, int out, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
#ifdef ENABLE_SFF_LOG
@@ -379,8 +398,8 @@ sff_bus_master_set_irq(int channel, void *priv)
channel &= 0x01;
switch (dev->irq_mode[channel]) {
case 0:
default:
case 0:
/* Legacy IRQ mode. */
if (irq)
picint(1 << (14 + channel));
@@ -481,7 +500,7 @@ sff_set_irq_line(sff8038i_t *dev, int irq_line)
}
void
sff_set_irq_level(sff8038i_t *dev, int channel, int irq_level)
sff_set_irq_level(sff8038i_t *dev, int channel, UNUSED(int irq_level))
{
dev->irq_level[channel] = 0;
}
@@ -492,8 +511,8 @@ sff_set_irq_mode(sff8038i_t *dev, int channel, int irq_mode)
dev->irq_mode[channel] = irq_mode;
switch (dev->irq_mode[channel]) {
case 0:
default:
case 0:
/* Legacy IRQ mode. */
sff_log("[%08X] Setting channel %i to legacy IRQ %i\n", dev, channel, 14 + channel);
break;
@@ -537,7 +556,7 @@ sff_close(void *p)
static void
*
sff_init(const device_t *info)
sff_init(UNUSED(const device_t *info))
{
sff8038i_t *dev = (sff8038i_t *) malloc(sizeof(sff8038i_t));
memset(dev, 0, sizeof(sff8038i_t));

50
src/disk/hdc_st506_at.c
View File

@@ -75,35 +75,35 @@
#define CMD_SET_PARAMETERS 0x91
typedef struct {
int8_t present, /* drive is present */
hdd_num, /* drive number in system */
steprate, /* current servo step rate */
spt, /* physical #sectors per track */
hpc, /* physical #heads per cylinder */
pad;
int16_t tracks; /* physical #tracks per cylinder */
int8_t present; /* drive is present */
int8_t hdd_num; /* drive number in system */
int8_t steprate; /* current servo step rate */
int8_t spt; /* physical #sectors per track */
int8_t hpc; /* physical #heads per cylinder */
int8_t pad;
int16_t tracks; /* physical #tracks per cylinder */
int8_t cfg_spt, /* configured #sectors per track */
cfg_hpc; /* configured #heads per track */
int8_t cfg_spt; /* configured #sectors per track */
int8_t cfg_hpc; /* configured #heads per track */
int16_t curcyl; /* current track number */
int16_t curcyl; /* current track number */
} drive_t;
typedef struct {
uint8_t precomp, /* 1: precomp/error register */
error,
secount, /* 2: sector count register */
sector, /* 3: sector number */
head, /* 6: head number + drive select */
command, /* 7: command/status */
status,
fdisk; /* 8: control register */
uint8_t precomp; /* 1: precomp/error register */
uint8_t error;
uint8_t secount; /* 2: sector count register */
uint8_t sector; /* 3: sector number */
uint8_t head; /* 6: head number + drive select */
uint8_t command; /* 7: command/status */
uint8_t status;
uint8_t fdisk; /* 8: control register */
uint16_t cylinder; /* 4/5: cylinder LOW and HIGH */
int8_t reset, /* controller in reset */
irqstat, /* current IRQ status */
drvsel, /* current selected drive */
pad;
int8_t reset; /* controller in reset */
int8_t irqstat; /* current IRQ status */
int8_t drvsel; /* current selected drive */
int8_t pad;
int pos; /* offset within data buffer */
pc_timer_t callback_timer; /* callback delay timer */
@@ -144,7 +144,7 @@ irq_raise(mfm_t *mfm)
}
static inline void
irq_lower(mfm_t *mfm)
irq_lower(UNUSED(mfm_t *mfm))
{
picintc(1 << 14);
}
@@ -668,7 +668,7 @@ do_callback(void *priv)
}
static void
loadhd(mfm_t *mfm, int c, int d, const char *fn)
loadhd(mfm_t *mfm, int c, int d, UNUSED(const char *fn))
{
drive_t *drive = &mfm->drives[c];
@@ -686,7 +686,7 @@ loadhd(mfm_t *mfm, int c, int d, const char *fn)
}
static void *
mfm_init(const device_t *info)
mfm_init(UNUSED(const device_t *info))
{
mfm_t *mfm;
int c;

46
src/disk/hdc_st506_xt.c
View File

@@ -238,12 +238,12 @@ typedef struct {
uint16_t cylinder; /* current cylinder */
uint8_t spt, /* physical parameters */
hpc;
uint8_t spt; /* physical parameters */
uint8_t hpc;
uint16_t tracks;
uint8_t cfg_spt, /* configured parameters */
cfg_hpc;
uint8_t cfg_spt; /* configured parameters */
uint8_t cfg_hpc;
uint16_t cfg_cyl;
} drive_t;
@@ -253,15 +253,18 @@ typedef struct {
uint8_t spt; /* sectors-per-track for controller */
uint16_t base; /* controller configuration */
int8_t irq,
dma;
int8_t irq;
int8_t dma;
uint8_t switches;
uint8_t misc;
uint8_t nr_err, err_bv, cur_sec, pad;
uint32_t bios_addr,
bios_size,
bios_ram;
rom_t bios_rom;
uint8_t nr_err;
uint8_t err_bv;
uint8_t cur_sec;
uint8_t pad;
uint32_t bios_addr;
uint32_t bios_size;
uint32_t bios_ram;
rom_t bios_rom;
int state; /* operational data */
uint8_t irq_dma;
@@ -272,14 +275,14 @@ typedef struct {
uint8_t command[6]; /* current command request */
int drive_sel;
int sector,
head,
cylinder,
count;
int sector;
int head;
int cylinder;
int count;
uint8_t compl ; /* current request completion code */
int buff_pos, /* pointers to the RAM buffer */
buff_cnt;
int buff_pos; /* pointers to the RAM buffer */
int buff_cnt;
drive_t drives[MFM_NUM]; /* the attached drives */
uint8_t scratch[64]; /* ST-11 scratchpad RAM */
@@ -1362,9 +1365,10 @@ mem_read(uint32_t addr, void *priv)
case ST506_XT_TYPE_ST11R: /* ST-11R */
mask = 0x1fff; /* ST-11 decodes RAM on each 8K block */
break;
/* default:
break; */
#if 0
default:
break;
#endif
}
addr = addr & dev->bios_rom.mask;
@@ -1429,7 +1433,7 @@ loadrom(hdc_t *dev, const char *fn)
}
static void
loadhd(hdc_t *dev, int c, int d, const char *fn)
loadhd(hdc_t *dev, int c, int d, UNUSED(const char *fn))
{
drive_t *drive = &dev->drives[c];

46
src/disk/hdc_xta.c
View File

@@ -185,12 +185,12 @@ enum {
typedef struct {
uint8_t cmd; /* [7:5] class, [4:0] opcode */
uint8_t head : 5, /* [4:0] head number */
drvsel : 1, /* [5] drive select */
mbz : 2; /* [7:6] 00 */
uint8_t head : 5; /* [4:0] head number */
uint8_t drvsel : 1; /* [5] drive select */
uint8_t mbz : 2; /* [7:6] 00 */
uint8_t sector : 6, /* [5:0] sector number 0-63 */
cyl_high : 2; /* [7:6] cylinder [9:8] bits */
uint8_t sector : 6; /* [5:0] sector number 0-63 */
uint8_t cyl_high : 2; /* [7:6] cylinder [9:8] bits */
uint8_t cyl_low; /* [7:0] cylinder [7:0] bits */
@@ -216,19 +216,19 @@ typedef struct {
/* Define an attached drive. */
typedef struct {
int8_t id, /* drive ID on bus */
present, /* drive is present */
hdd_num, /* index to global disk table */
type; /* drive type ID */
int8_t id; /* drive ID on bus */
int8_t present; /* drive is present */
int8_t hdd_num; /* index to global disk table */
int8_t type; /* drive type ID */
uint16_t cur_cyl; /* last known position of heads */
uint8_t spt, /* active drive parameters */
hpc;
uint8_t spt; /* active drive parameters */
uint8_t hpc;
uint16_t tracks;
uint8_t cfg_spt, /* configured drive parameters */
cfg_hpc;
uint8_t cfg_spt; /* configured drive parameters */
uint8_t cfg_hpc;
uint16_t cfg_tracks;
} drive_t;
@@ -252,17 +252,17 @@ typedef struct {
pc_timer_t timer;
/* Data transfer. */
int16_t buf_idx, /* buffer index and pointer */
buf_len;
int16_t buf_idx; /* buffer index and pointer */
int16_t buf_len;
uint8_t *buf_ptr;
/* Current operation parameters. */
dcb_t dcb; /* device control block */
uint16_t track; /* requested track# */
uint8_t head, /* requested head# */
sector, /* requested sector# */
comp; /* operation completion byte */
int count; /* requested sector count */
dcb_t dcb; /* device control block */
uint16_t track; /* requested track# */
uint8_t head; /* requested head# */
uint8_t sector; /* requested sector# */
uint8_t comp; /* operation completion byte */
int count; /* requested sector count */
drive_t drives[XTA_NUM]; /* the attached drive(s) */
@@ -958,7 +958,9 @@ hdc_write(uint16_t port, uint8_t val, void *priv)
break;
case 3: /* DMA/IRQ intr register */
// xta_log("%s: WriteMASK(%02X)\n", dev->name, val);
#if 0
xta_log("%s: WriteMASK(%02X)\n", dev->name, val);
#endif
dev->intr = val;
break;
}

5
src/disk/hdc_xtide.c
View File

@@ -43,6 +43,7 @@
#include <86box/device.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/plat_unused.h>
#define ROM_PATH_XT "roms/hdd/xtide/ide_xt.bin"
#define ROM_PATH_XTP "roms/hdd/xtide/ide_xtp.bin"
@@ -193,7 +194,7 @@ xtide_at_386_available(void)
}
static void *
xtide_acculogic_init(const device_t *info)
xtide_acculogic_init(UNUSED(const device_t *info))
{
xtide_t *xtide = malloc(sizeof(xtide_t));
@@ -228,7 +229,7 @@ xtide_close(void *priv)
}
static void *
xtide_at_ps2_init(const device_t *info)
xtide_at_ps2_init(UNUSED(const device_t *info))
{
xtide_t *xtide = malloc(sizeof(xtide_t));

2
src/disk/hdd.c
View File

@@ -102,7 +102,7 @@ no_cdrom:
}
char *
hdd_bus_to_string(int bus, int cdrom)
hdd_bus_to_string(int bus, UNUSED(int cdrom))
{
char *s = "none";

5
src/disk/hdd_image.c
View File

@@ -45,7 +45,8 @@ typedef struct
FILE *file; /* Used for HDD_IMAGE_RAW, HDD_IMAGE_HDI, and HDD_IMAGE_HDX. */
MVHDMeta *vhd; /* Used for HDD_IMAGE_VHD. */
uint32_t base;
uint32_t pos, last_sector;
uint32_t pos;
uint32_t last_sector;
uint8_t type; /* HDD_IMAGE_RAW, HDD_IMAGE_HDI, HDD_IMAGE_HDX, or HDD_IMAGE_VHD */
uint8_t loaded;
} hdd_image_t;
@@ -637,7 +638,7 @@ hdd_image_get_type(uint8_t id)
}
void
hdd_image_unload(uint8_t id, int fn_preserve)
hdd_image_unload(uint8_t id, UNUSED(int fn_preserve))
{
if (strlen(hdd[id].fn) == 0)
return;

16
src/disk/mo.c
View File

@@ -793,7 +793,7 @@ mo_data_command_finish(mo_t *dev, int len, int block_len, int alloc_len, int dir
}
static void
mo_sense_clear(mo_t *dev, int command)
mo_sense_clear(mo_t *dev, UNUSED(int command))
{
mo_sense_key = mo_asc = mo_ascq = 0;
}
@@ -938,7 +938,7 @@ mo_invalid_field_pl(mo_t *dev)
}
static int
mo_blocks(mo_t *dev, int32_t *len, int first_batch, int out)
mo_blocks(mo_t *dev, int32_t *len, UNUSED(int first_batch), int out)
{
*len = 0;
@@ -1179,7 +1179,9 @@ mo_pre_execution_check(mo_t *dev, uint8_t *cdb)
static void
mo_seek(mo_t *dev, uint32_t pos)
{
/* mo_log("MO %i: Seek %08X\n", dev->id, pos); */
#if 0
mo_log("MO %i: Seek %08X\n", dev->id, pos);
#endif
dev->sector_pos = pos;
}
@@ -1687,7 +1689,9 @@ mo_command(scsi_common_t *sc, uint8_t *cdb)
dev->buffer[1] = 0x80; /*Removable*/
dev->buffer[2] = (dev->drv->bus_type == MO_BUS_SCSI) ? 0x02 : 0x00; /*SCSI-2 compliant*/
dev->buffer[3] = (dev->drv->bus_type == MO_BUS_SCSI) ? 0x02 : 0x21;
// dev->buffer[4] = 31;
#if 0
dev->buffer[4] = 31;
#endif
dev->buffer[4] = 0;
if (dev->drv->bus_type == MO_BUS_SCSI) {
dev->buffer[6] = 1; /* 16-bit transfers supported */
@@ -1830,7 +1834,9 @@ mo_command(scsi_common_t *sc, uint8_t *cdb)
break;
}
/* mo_log("MO %i: Phase: %02X, request length: %i\n", dev->id, dev->phase, dev->request_length); */
#if 0
mo_log("MO %i: Phase: %02X, request length: %i\n", dev->id, dev->phase, dev->request_length);
#endif
if (mo_atapi_phase_to_scsi(dev) == SCSI_PHASE_STATUS)
mo_buf_free(dev);

12
src/disk/zip.c
View File

@@ -1768,7 +1768,9 @@ zip_command(scsi_common_t *sc, uint8_t *cdb)
case 1: /* Start the disc and read the TOC. */
break;
case 2: /* Eject the disc if possible. */
/* zip_eject(dev->id); */
#if 0
zip_eject(dev->id);
#endif
break;
case 3: /* Load the disc (close tray). */
zip_reload(dev->id);
@@ -1850,7 +1852,9 @@ zip_command(scsi_common_t *sc, uint8_t *cdb)
dev->buffer[1] = 0x80; /*Removable*/
dev->buffer[2] = (dev->drv->bus_type == ZIP_BUS_SCSI) ? 0x02 : 0x00; /*SCSI-2 compliant*/
dev->buffer[3] = (dev->drv->bus_type == ZIP_BUS_SCSI) ? 0x02 : 0x21;
// dev->buffer[4] = 31;
#if 0
dev->buffer[4] = 31;
#endif
dev->buffer[4] = 0;
if (dev->drv->bus_type == ZIP_BUS_SCSI) {
dev->buffer[6] = 1; /* 16-bit transfers supported */
@@ -2010,7 +2014,9 @@ atapi_out:
break;
}
/* zip_log("ZIP %i: Phase: %02X, request length: %i\n", dev->id, dev->phase, dev->request_length); */
#if 0
zip_log("ZIP %i: Phase: %02X, request length: %i\n", dev->id, dev->phase, dev->request_length);
#endif
if (zip_atapi_phase_to_scsi(dev) == SCSI_PHASE_STATUS)
zip_buf_free(dev);

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