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Merge branch 'master' of https://github.com/86Box/86Box.git into EngiNerd

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EngiNerd89
2020-12-19 21:31:33 +01:00
parent 51009d8e28 66e2b9bc1b
commit 590003ab09
71 changed files with 1698 additions and 1196 deletions
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643
src/chipset/sis_85c50x.c
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@@ -6,405 +6,365 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 85c501/85c503 chip.
* Implementation of the SiS 85C50x Chipset.
*
*
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Authors: Tiseno100,
*
* Copyright 2019 Miran Grca.
* Copyright 2020 Tiseno100.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/apm.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct sis_85c501_t
#ifdef ENABLE_SIS_85C50X_LOG
int sis_85c50x_do_log = ENABLE_SIS_85C50X_LOG;
static void
sis_85c50x_log(const char *fmt, ...)
{
/* 85c501 */
uint8_t turbo_reg;
va_list ap;
/* 85c503 */
if (sis_85c50x_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define sis_85c50x_log(fmt, ...)
#endif
/* Registers */
uint8_t pci_conf[2][256];
/* 85c50x ISA */
uint8_t cur_reg,
regs[39];
typedef struct sis_85c50x_t
{
uint8_t index,
pci_conf[256], pci_conf_sb[256],
regs[256];
smram_t * smram;
port_92_t * port_92;
} sis_85c50x_t;
static void
sis_85c501_recalcmapping(sis_85c50x_t *dev)
sis_85c50x_shadow_recalc(sis_85c50x_t *dev)
{
int c, d;
uint32_t base;
uint32_t base, i, can_read, can_write;
for (c = 0; c < 1; c++) {
for (d = 0; d < 4; d++) {
base = 0xe0000 + (d << 14);
if (dev->pci_conf[0][0x54 + c] & (1 << (d + 4))) {
switch (dev->pci_conf[0][0x53] & 0x60) {
case 0x00:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x40:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x60:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
}
} else
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
can_read = (dev->pci_conf[0x53] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
can_write = (dev->pci_conf[0x53] & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
if (!can_read)
can_write = MEM_WRITE_EXTANY;
mem_set_mem_state_both(0xf0000, 0x10000, can_read | can_write);
shadowbios = 1;
shadowbios_write = 1;
for (i = 0; i < 4; i++) {
base = 0xe0000 + (i << 14);
mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x54] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
base = 0xd0000 + (i << 14);
mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x55] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
base = 0xc0000 + (i << 14);
mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x56] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
}
flushmmucache();
shadowbios = 1;
}
static void
sis_85c501_write(int func, int addr, uint8_t val, void *priv)
sis_85c50x_smm_recalc(sis_85c50x_t *dev)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
/* NOTE: Naming mismatch - what the datasheet calls "host address" is what we call ram_base. */
uint32_t ram_base = (dev->pci_conf[0x64] << 20) |
((dev->pci_conf[0x65] & 0x07) << 28);
if (func)
smram_disable(dev->smram);
if ((((dev->pci_conf[0x65] & 0xe0) >> 5) != 0x00) && (ram_base == 0x00000000))
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch ((dev->pci_conf[0x65] & 0xe0) >> 5) {
case 0x00:
if (!(dev->pci_conf[0x54] & 0xc0))
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x01:
smram_enable(dev->smram, 0xb0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x02:
smram_enable(dev->smram, 0xa0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x04:
smram_enable(dev->smram, 0xa0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x06:
smram_enable(dev->smram, 0xb0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
}
}
static void
sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
uint8_t valxor = (val ^ dev->pci_conf[addr]);
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x42;
val |= 0x04;
case 0x04: /* Command - low byte */
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xb4) | (val & 0x4b);
break;
case 0x05:
val &= 0x01;
case 0x07: /* Status - high byte */
dev->pci_conf[addr] = ((dev->pci_conf[addr] & 0xf9) & ~(val & 0xf8)) | (val & 0x06);
break;
case 0x50:
dev->pci_conf[addr] = val;
break;
case 0x51: /* Cache */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = (val & 0x40);
cpu_update_waitstates();
break;
case 0x52:
dev->pci_conf[addr] = val;
break;
case 0x53: /* Shadow RAM */
case 0x54:
case 0x55:
case 0x56:
dev->pci_conf[addr] = val;
sis_85c50x_shadow_recalc(dev);
if (addr == 0x54)
sis_85c50x_smm_recalc(dev);
break;
case 0x57: case 0x58: case 0x59: case 0x5a:
case 0x5c: case 0x5d: case 0x5e: case 0x61:
case 0x62: case 0x63: case 0x67: case 0x68:
case 0x6a: case 0x6b: case 0x6c: case 0x6d:
case 0x6e: case 0x6f:
dev->pci_conf[addr] = val;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x5b:
dev->pci_conf[addr] = val;
if (valxor & 0xc0)
port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80));
break;
case 0x60: /* SMI */
if ((dev->pci_conf[0x68] & 0x01) && !(dev->pci_conf[addr] & 0x02) && (val & 0x02)) {
dev->pci_conf[0x69] |= 0x01;
smi_line = 1;
}
dev->pci_conf[addr] = val & 0x3e;
break;
case 0x64: /* SMRAM */
case 0x65:
dev->pci_conf[addr] = val;
sis_85c50x_smm_recalc(dev);
break;
case 0x66:
dev->pci_conf[addr] = (val & 0x7f);
break;
case 0x69:
dev->pci_conf[addr] &= ~(val);
break;
}
sis_85c50x_log("85C501: dev->pci_conf[%02x] = %02x\n", addr, val);
}
static uint8_t
sis_85c50x_read(int func, int addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
sis_85c50x_log("85C501: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]);
return dev->pci_conf[addr];
}
static void
sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
switch (addr) {
case 0x04: /* Command */
dev->pci_conf_sb[addr] = val & 0x0f;
break;
case 0x07: /* Status */
dev->pci_conf_sb[addr] &= ~(val & 0x30);
break;
case 0x40: /* BIOS Control Register */
dev->pci_conf_sb[addr] = val & 0x3f;
break;
case 0x41: case 0x42: case 0x43: case 0x44:
/* INTA/B/C/D# Remapping Control Register */
dev->pci_conf_sb[addr] = val & 0x8f;
if (val & 0x80)
pci_set_irq_routing(PCI_INTA + (addr - 0x41), PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA + (addr - 0x41), val & 0xf);
break;
case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */
case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */
case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */
case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
dev->pci_conf_sb[addr] = val;
break;
}
sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] = %02x\n", addr, val);
}
static uint8_t
sis_85c50x_sb_read(int func, int addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] (%02x)\n", addr, dev->pci_conf_sb[addr]);
return dev->pci_conf_sb[addr];
}
static void
sis_85c50x_isa_write(uint16_t addr, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x54: /*Shadow configure*/
if ((dev->pci_conf[0][0x54] & val) ^ 0xf0) {
dev->pci_conf[0][0x54] = val;
sis_85c501_recalcmapping(dev);
case 0x23:
switch (dev->index) {
case 0x80:
dev->regs[dev->index] = val & 0xe7;
break;
case 0x81:
dev->regs[dev->index] = val & 0xf4;
break;
case 0x84: case 0x88: case 0x9: case 0x8a:
case 0x8b:
dev->regs[dev->index] = val;
break;
case 0x85:
outb(0x70, val);
break;
}
break;
}
dev->pci_conf[0][addr] = val;
sis_85c50x_log("85C501-ISA: dev->regs[%02x] = %02x\n", addr, val);
}
static void
sis_85c503_write(int func, int addr, uint8_t val, void *priv)
static uint8_t
sis_85c50x_isa_read(uint16_t addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
uint8_t ret = 0xff;
if (func > 0)
return;
if (addr >= 0x0f && addr < 0x41)
return;
switch(addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x08;
val |= 0x07;
break;
case 0x05:
val = 0;
switch (addr) {
case 0x22:
ret = dev->index;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x41:
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
case 0x23:
if (dev->index == 0x85)
ret = inb(0x70);
else
pci_set_irq_routing(PCI_INTA, val & 0xf);
break;
case 0x42:
if (val & 0x80)
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTC, val & 0xf);
break;
case 0x43:
if (val & 0x80)
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTB, val & 0xf);
break;
case 0x44:
if (val & 0x80)
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTD, val & 0xf);
ret = dev->regs[dev->index];
break;
}
sis_85c50x_log("85C501-ISA: dev->regs[%02x] (%02x)\n", dev->index, ret);
dev->pci_conf[1][addr] = val;
}
static void
sis_85c50x_isa_write(uint16_t port, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
if (port & 1) {
if (dev->cur_reg <= 0x1a)
dev->regs[dev->cur_reg] = val;
} else
dev->cur_reg = val;
}
static uint8_t
sis_85c501_read(int func, int addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
if (func)
return 0xff;
return dev->pci_conf[0][addr];
}
static uint8_t
sis_85c503_read(int func, int addr, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
if (func > 0)
return 0xff;
return dev->pci_conf[1][addr];
}
static uint8_t
sis_85c50x_isa_read(uint16_t port, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
if (port & 1) {
if (dev->cur_reg <= 0x1a)
return dev->regs[dev->cur_reg];
else
return 0xff;
} else
return dev->cur_reg;
}
static void
sis_85c50x_isa_reset(sis_85c50x_t *dev)
{
int mem_size_mb, i = 0;
memset(dev->regs, 0, sizeof(dev->regs));
dev->cur_reg = 0;
for (i = 0; i < 0x27; i++)
dev->regs[i] = 0x00;
dev->regs[9] = 0x40;
mem_size_mb = mem_size >> 10;
switch (mem_size_mb) {
case 0: case 1:
dev->regs[9] |= 0;
break;
case 2: case 3:
dev->regs[9] |= 1;
break;
case 4:
dev->regs[9] |= 2;
break;
case 5:
dev->regs[9] |= 0x20;
break;
case 6: case 7:
dev->regs[9] |= 9;
break;
case 8: case 9:
dev->regs[9] |= 4;
break;
case 10: case 11:
dev->regs[9] |= 5;
break;
case 12: case 13: case 14: case 15:
dev->regs[9] |= 0xB;
break;
case 16:
dev->regs[9] |= 0x13;
break;
case 17:
dev->regs[9] |= 0x21;
break;
case 18: case 19:
dev->regs[9] |= 6;
break;
case 20: case 21: case 22: case 23:
dev->regs[9] |= 0xD;
break;
case 24: case 25: case 26: case 27:
case 28: case 29: case 30: case 31:
dev->regs[9] |= 0xE;
break;
case 32: case 33: case 34: case 35:
dev->regs[9] |= 0x1B;
break;
case 36: case 37: case 38: case 39:
dev->regs[9] |= 0xF;
break;
case 40: case 41: case 42: case 43:
case 44: case 45: case 46: case 47:
dev->regs[9] |= 0x17;
break;
case 48:
dev->regs[9] |= 0x1E;
break;
default:
if (mem_size_mb < 64)
dev->regs[9] |= 0x1E;
else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[9] |= 0x22;
else
dev->regs[9] |= 0x24;
break;
}
dev->regs[0x11] = 9;
dev->regs[0x12] = 0xFF;
dev->regs[0x23] = 0xF0;
dev->regs[0x26] = 1;
io_removehandler(0x22, 0x0002,
sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
io_sethandler(0x22, 0x0002,
sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
return ret;
}
static void
sis_85c50x_reset(void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
uint8_t val = 0;
/* North Bridge (SiS 85C501/502) */
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x06;
dev->pci_conf[0x03] = 0x04;
dev->pci_conf[0x04] = 0x04;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
val = sis_85c501_read(0, 0x54, priv); /* Read current value of 0x44. */
sis_85c501_write(0, 0x54, val & 0xf, priv); /* Turn off shadow BIOS but keep the lower 4 bits. */
sis_85c50x_write(0, 0x51, 0x00, dev);
sis_85c50x_write(0, 0x53, 0x00, dev);
sis_85c50x_write(0, 0x54, 0x00, dev);
sis_85c50x_write(0, 0x55, 0x00, dev);
sis_85c50x_write(0, 0x56, 0x00, dev);
sis_85c50x_write(0, 0x5b, 0x00, dev);
sis_85c50x_write(0, 0x60, 0x00, dev);
sis_85c50x_write(0, 0x64, 0x00, dev);
sis_85c50x_write(0, 0x65, 0x00, dev);
sis_85c50x_write(0, 0x68, 0x00, dev);
sis_85c50x_write(0, 0x69, 0xff, dev);
sis_85c50x_isa_reset(dev);
}
static void
sis_85c50x_setup(sis_85c50x_t *dev)
{
memset(dev, 0, sizeof(sis_85c50x_t));
/* 85c501 */
dev->pci_conf[0][0x00] = 0x39; /*SiS*/
dev->pci_conf[0][0x01] = 0x10;
dev->pci_conf[0][0x02] = 0x06; /*501/502*/
dev->pci_conf[0][0x03] = 0x04;
dev->pci_conf[0][0x04] = 7;
dev->pci_conf[0][0x05] = 0;
dev->pci_conf[0][0x06] = 0x80;
dev->pci_conf[0][0x07] = 0x02;
dev->pci_conf[0][0x08] = 0; /*Device revision*/
dev->pci_conf[0][0x09] = 0x00; /*Device class (PCI bridge)*/
dev->pci_conf[0][0x0a] = 0x00;
dev->pci_conf[0][0x0b] = 0x06;
dev->pci_conf[0][0x0e] = 0x00; /*Single function device*/
dev->pci_conf[0][0x50] = 0xbc;
dev->pci_conf[0][0x51] = 0xfb;
dev->pci_conf[0][0x52] = 0xad;
dev->pci_conf[0][0x53] = 0xfe;
shadowbios = 1;
/* 85c503 */
dev->pci_conf[1][0x00] = 0x39; /*SiS*/
dev->pci_conf[1][0x01] = 0x10;
dev->pci_conf[1][0x02] = 0x08; /*503*/
dev->pci_conf[1][0x03] = 0x00;
dev->pci_conf[1][0x04] = 7;
dev->pci_conf[1][0x05] = 0;
dev->pci_conf[1][0x06] = 0x80;
dev->pci_conf[1][0x07] = 0x02;
dev->pci_conf[1][0x08] = 0; /*Device revision*/
dev->pci_conf[1][0x09] = 0x00; /*Device class (PCI bridge)*/
dev->pci_conf[1][0x0a] = 0x01;
dev->pci_conf[1][0x0b] = 0x06;
dev->pci_conf[1][0x0e] = 0x00; /*Single function device*/
dev->pci_conf[1][0x41] = dev->pci_conf[1][0x42] =
dev->pci_conf[1][0x43] = dev->pci_conf[1][0x44] = 0x80;
/* South Bridge (SiS 85C503) */
dev->pci_conf_sb[0x00] = 0x39;
dev->pci_conf_sb[0x01] = 0x10;
dev->pci_conf_sb[0x02] = 0x08;
dev->pci_conf_sb[0x03] = 0x00;
dev->pci_conf_sb[0x04] = 0x07;
dev->pci_conf_sb[0x05] = 0x00;
dev->pci_conf_sb[0x06] = 0x00;
dev->pci_conf_sb[0x07] = 0x02;
dev->pci_conf_sb[0x08] = 0x00;
dev->pci_conf_sb[0x09] = 0x00;
dev->pci_conf_sb[0x0a] = 0x01;
dev->pci_conf_sb[0x0b] = 0x06;
sis_85c50x_write(0, 0x41, 0x80, dev);
sis_85c50x_write(0, 0x42, 0x80, dev);
sis_85c50x_write(0, 0x43, 0x80, dev);
sis_85c50x_write(0, 0x44, 0x80, dev);
}
static void
sis_85c50x_close(void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
smram_del(dev->smram);
free(dev);
}
@@ -412,30 +372,31 @@ sis_85c50x_close(void *priv)
static void *
sis_85c50x_init(const device_t *info)
{
sis_85c50x_t *dev = (sis_85c50x_t *) malloc(sizeof(sis_85c50x_t));
sis_85c50x_t *dev = (sis_85c50x_t *)malloc(sizeof(sis_85c50x_t));
memset(dev, 0x00, sizeof(sis_85c50x_t));
pci_add_card(0, sis_85c501_read, sis_85c501_write, dev);
pci_add_card(5, sis_85c503_read, sis_85c503_write, dev);
/* 501/502 (Northbridge) */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c50x_read, sis_85c50x_write, dev);
sis_85c50x_setup(dev);
sis_85c50x_isa_reset(dev);
/* 503 (Southbridge) */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_85c50x_sb_read, sis_85c50x_sb_write, dev);
io_sethandler(0x0022, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
device_add(&port_92_pci_device);
dev->smram = smram_add();
dev->port_92 = device_add(&port_92_device);
sis_85c50x_reset(dev);
return dev;
}
const device_t sis_85c50x_device =
{
"SiS 85c501/85c503",
const device_t sis_85c50x_device = {
"SiS 85C50x",
DEVICE_PCI,
0,
sis_85c50x_init,
sis_85c50x_close,
sis_85c50x_reset,
{ NULL },
NULL,
NULL,
sis_85c50x_init, sis_85c50x_close,
sis_85c50x_reset, { NULL },
NULL, NULL,
NULL
};

8
src/chipset/via_apollo.c
View File

@@ -134,7 +134,7 @@ via_apollo_setup(via_apollo_t *dev)
dev->pci_conf[0x57] = 0x01;
}
if (dev->id >= VIA_693A)
if (dev->id >= VIA_694)
dev->pci_conf[0x58] = 0x40;
else if (dev->id >= VIA_585)
dev->pci_conf[0x58] = 0x05;
@@ -211,7 +211,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
return;
if (((addr == 0x78) || (addr >= 0xad)) && (dev->id == VIA_597))
return;
if (((addr == 0x67) || ((addr >= 0xf0) && (addr < 0xfc))) && (dev->id != VIA_691))
if (((addr == 0x67) || ((addr >= 0xf0) && (addr < 0xfc))) && (dev->id < VIA_691))
return;
switch(addr) {
@@ -298,9 +298,9 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf0) | (val & 0xf0);
break;
case 0x54:
if(dev->id == VIA_585)
if (dev->id == VIA_585)
dev->pci_conf[0x54] = val;
else
else
dev->pci_conf[0x54] = (dev->pci_conf[0x54] & ~0x07) | (val & 0x07);
break;

4
src/codegen/codegen_ops.c
View File

@@ -15,9 +15,9 @@
#include "codegen.h"
#include "codegen_ops.h"
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include "codegen_ops_x86-64.h"
#elif defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64
#elif defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
#include "codegen_ops_x86.h"
#endif

24
src/codegen/codegen_ops_x86-64.h
View File

@@ -57,7 +57,7 @@ static inline void call_long(uintptr_t func)
static inline void load_param_1_32(codeblock_t *block, uint32_t param)
{
#if WIN64
#if _WIN64
addbyte(0xb9); /*MOVL $fetchdat,%ecx*/
#else
addbyte(0xbf); /*MOVL $fetchdat,%edi*/
@@ -66,7 +66,7 @@ static inline void load_param_1_32(codeblock_t *block, uint32_t param)
}
static inline void load_param_1_reg_32(int reg)
{
#if WIN64
#if _WIN64
if (reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOV ECX, EAX*/
@@ -82,7 +82,7 @@ static inline void load_param_1_reg_32(int reg)
static inline void load_param_1_64(codeblock_t *block, uint64_t param)
{
addbyte(0x48);
#if WIN64
#if _WIN64
addbyte(0xb9); /*MOVL $fetchdat,%ecx*/
#else
addbyte(0xbf); /*MOVL $fetchdat,%edi*/
@@ -93,7 +93,7 @@ static inline void load_param_1_64(codeblock_t *block, uint64_t param)
static inline void load_param_2_32(codeblock_t *block, uint32_t param)
{
#if WIN64
#if _WIN64
addbyte(0xba); /*MOVL $fetchdat,%edx*/
#else
addbyte(0xbe); /*MOVL $fetchdat,%esi*/
@@ -102,7 +102,7 @@ static inline void load_param_2_32(codeblock_t *block, uint32_t param)
}
static inline void load_param_2_reg_32(int reg)
{
#if WIN64
#if _WIN64
if (reg & 8)
addbyte(0x44);
addbyte(0x89); /*MOV EDX, EAX*/
@@ -117,7 +117,7 @@ static inline void load_param_2_reg_32(int reg)
static inline void load_param_2_64(codeblock_t *block, uint64_t param)
{
addbyte(0x48);
#if WIN64
#if _WIN64
addbyte(0xba); /*MOVL $fetchdat,%edx*/
#else
addbyte(0xbe); /*MOVL $fetchdat,%esi*/
@@ -128,7 +128,7 @@ static inline void load_param_2_reg_64(int reg)
{
if (reg & 8)
{
#if WIN64
#if _WIN64
addbyte(0x4c); /*MOVL EDX,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | ((reg & 7) << 3));
@@ -140,7 +140,7 @@ static inline void load_param_2_reg_64(int reg)
}
else
{
#if WIN64
#if _WIN64
addbyte(0x48); /*MOVL EDX,reg*/
addbyte(0x89);
addbyte(0xc0 | REG_EDX | ((reg & 7) << 3));
@@ -156,7 +156,7 @@ static inline void load_param_3_reg_32(int reg)
{
if (reg & 8)
{
#if WIN64
#if _WIN64
addbyte(0x45); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
@@ -168,7 +168,7 @@ static inline void load_param_3_reg_32(int reg)
}
else
{
#if WIN64
#if _WIN64
addbyte(0x41); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
@@ -183,7 +183,7 @@ static inline void load_param_3_reg_64(int reg)
{
if (reg & 8)
{
#if WIN64
#if _WIN64
addbyte(0x4d); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));
@@ -195,7 +195,7 @@ static inline void load_param_3_reg_64(int reg)
}
else
{
#if WIN64
#if _WIN64
addbyte(0x49); /*MOVL R8,reg*/
addbyte(0x89);
addbyte(0xc0 | ((reg & 7) << 3));

8
src/codegen/codegen_x86-64.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdarg.h>
#include <stdio.h>
@@ -24,7 +24,7 @@
#include <sys/mman.h>
#include <unistd.h>
#endif
#if WIN64
#if _WIN64
#include <windows.h>
#endif
@@ -70,7 +70,7 @@ void codegen_init()
long pagemask = ~(pagesize - 1);
#endif
#if WIN64
#if _WIN64
codeblock = VirtualAlloc(NULL, BLOCK_SIZE * sizeof(codeblock_t), MEM_COMMIT, PAGE_EXECUTE_READWRITE);
#else
codeblock = malloc(BLOCK_SIZE * sizeof(codeblock_t));
@@ -295,7 +295,7 @@ void codegen_block_start_recompile(codeblock_t *block)
block_pos = BLOCK_GPF_OFFSET;
#ifdef OLD_GPF
#if WIN64
#if _WIN64
addbyte(0x48); /*XOR RCX, RCX*/
addbyte(0x31);
addbyte(0xc9);

2
src/codegen/codegen_x86.c
View File

@@ -36,7 +36,7 @@
* Boston, MA 02111-1307
* USA.
*/
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
#include <stdio.h>
#include <stdint.h>

6
src/codegen_new/codegen_allocator.c
View File

@@ -112,10 +112,14 @@ uint8_t *codeblock_allocator_get_ptr(mem_block_t *block)
void codegen_allocator_clean_blocks(struct mem_block_t *block)
{
#if defined __ARM_EABI__ || defined _ARM_ || defined __aarch64__
#if defined __ARM_EABI__ || defined _ARM_ || defined __aarch64__ || defined _M_ARM || defined _M_ARM64
while (1)
{
#ifndef _MSC_VER
__clear_cache(&mem_block_alloc[block->offset], &mem_block_alloc[block->offset + MEM_BLOCK_SIZE]);
#else
FlushInstructionCache(GetCurrentProcess(), &mem_block_alloc[block->offset], MEM_BLOCK_SIZE);
#endif
if (block->next)
block = &mem_blocks[block->next - 1];
else

2
src/codegen_new/codegen_allocator.h
View File

@@ -13,7 +13,7 @@
Due to the chaining, the total memory size is limited by the range of a jump
instruction. ARMv7 is restricted to +/- 32 MB, ARMv8 to +/- 128 MB, x86 to
+/- 2GB. As a result, total memory size is limited to 32 MB on ARMv7*/
#if defined __ARM_EABI__ || _ARM_
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#define MEM_BLOCK_NR 32768
#else
#define MEM_BLOCK_NR 131072

6
src/codegen_new/codegen_backend.h
View File

@@ -1,13 +1,13 @@
#ifndef _CODEGEN_BACKEND_H_
#define _CODEGEN_BACKEND_H_
#if defined __amd64__
#if defined __amd64__ || defined _M_X64
#include "codegen_backend_x86-64.h"
#elif defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
#include "codegen_backend_x86.h"
#elif defined __ARM_EABI__ || defined _ARM_
#elif defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#include "codegen_backend_arm.h"
#elif defined __aarch64__
#elif defined __aarch64__ || defined _M_ARM64
#include "codegen_backend_arm64.h"
#else
#error Dynamic recompiler not implemented on your platform

6
src/codegen_new/codegen_backend_arm.c
View File

@@ -1,4 +1,4 @@
#if defined __ARM_EABI__ || defined _ARM_
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#include <stdint.h>
#include <stdlib.h>
@@ -327,9 +327,13 @@ printf("block_pos=%i\n", block_pos);
block_write_data = NULL;
//fatal("block_pos=%i\n", block_pos);
#if !defined _MSC_VER || defined __clang__
asm("vmrs %0, fpscr\n"
: "=r" (cpu_state.old_fp_control)
);
#else
cpu_state.old_fp_control = _controlfp();
#endif
if ((cpu_state.old_fp_control >> 22) & 3)
fatal("VFP not in nearest rounding mode\n");
}

6
src/codegen_new/codegen_backend_arm64.c
View File

@@ -1,4 +1,4 @@
#ifdef __aarch64__
#if defined __aarch64__ || defined _M_ARM64
#include <stdlib.h>
#include <stdint.h>
@@ -332,9 +332,13 @@ void codegen_backend_init()
codegen_allocator_clean_blocks(block->head_mem_block);
#if !defined _MSC_VER || defined __clang__
asm("mrs %0, fpcr\n"
: "=r" (cpu_state.old_fp_control)
);
#else
cpu_state.old_fp_control = _controlfp();
#endif
}
void codegen_set_rounding_mode(int mode)

2
src/codegen_new/codegen_backend_arm64_ops.c
View File

@@ -1,4 +1,4 @@
#ifdef __aarch64__
#if defined __aarch64__ || defined _M_ARM64
#include <stdint.h>
#include <86box/86box.h>

2
src/codegen_new/codegen_backend_arm64_uops.c
View File

@@ -1,4 +1,4 @@
#ifdef __aarch64__
#if defined __aarch64__ || defined _M_ARM64
#include <stdint.h>
#include <86box/86box.h>

2
src/codegen_new/codegen_backend_arm_ops.c
View File

@@ -1,4 +1,4 @@
#if defined __ARM_EABI__ || defined _ARM_
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#include <stdint.h>
#include <86box/86box.h>

2
src/codegen_new/codegen_backend_arm_uops.c
View File

@@ -1,4 +1,4 @@
#if defined __ARM_EABI__ || defined _ARM_
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
#include <math.h>
#include <stdint.h>

22
src/codegen_new/codegen_backend_x86-64.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdint.h>
#include <86box/86box.h>
@@ -22,6 +22,8 @@
#include <windows.h>
#endif
#include <xmmintrin.h>
void *codegen_mem_load_byte;
void *codegen_mem_load_word;
void *codegen_mem_load_long;
@@ -51,7 +53,7 @@ host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] =
host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
{
#if WIN64
#if _WIN64
/*Windows x86-64 calling convention preserves XMM6-XMM15*/
{REG_XMM6, 0},
{REG_XMM7, 0},
@@ -123,7 +125,7 @@ static void build_load_routine(codeblock_t *block, int size, int is_float)
*misaligned_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)misaligned_offset) - 1;
host_x86_PUSH(block, REG_RAX);
host_x86_PUSH(block, REG_RDX);
#if WIN64
#if _WIN64
host_x86_SUB64_REG_IMM(block, REG_RSP, 0x20);
//host_x86_MOV32_REG_REG(block, REG_ECX, uop->imm_data);
#else
@@ -155,7 +157,7 @@ static void build_load_routine(codeblock_t *block, int size, int is_float)
host_x86_CALL(block, (void *)readmemql);
host_x86_MOVQ_XREG_REG(block, REG_XMM_TEMP, REG_RAX);
}
#if WIN64
#if _WIN64
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x20);
#endif
host_x86_POP(block, REG_RDX);
@@ -221,7 +223,7 @@ static void build_store_routine(codeblock_t *block, int size, int is_float)
*misaligned_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)misaligned_offset) - 1;
host_x86_PUSH(block, REG_RAX);
host_x86_PUSH(block, REG_RDX);
#if WIN64
#if _WIN64
host_x86_SUB64_REG_IMM(block, REG_RSP, 0x28);
if (size == 4 && is_float)
host_x86_MOVD_REG_XREG(block, REG_EDX, REG_XMM_TEMP); //data
@@ -248,7 +250,7 @@ static void build_store_routine(codeblock_t *block, int size, int is_float)
host_x86_CALL(block, (void *)writememll);
else if (size == 8)
host_x86_CALL(block, (void *)writememql);
#if WIN64
#if _WIN64
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x28);
#else
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x8);
@@ -317,7 +319,7 @@ void codegen_backend_init()
build_loadstore_routines(&codeblock[block_current]);
codegen_gpf_rout = &codeblock[block_current].data[block_pos];
#if WIN64
#if _WIN64
host_x86_XOR32_REG_REG(block, REG_ECX, REG_ECX);
host_x86_XOR32_REG_REG(block, REG_EDX, REG_EDX);
#else
@@ -340,11 +342,7 @@ void codegen_backend_init()
block_write_data = NULL;
asm(
"stmxcsr %0\n"
: "=m" (cpu_state.old_fp_control)
);
cpu_state.trunc_fp_control = cpu_state.old_fp_control | 0x6000;
cpu_state.trunc_fp_control = _mm_getcsr() | 0x6000;
}
void codegen_set_rounding_mode(int mode)

2
src/codegen_new/codegen_backend_x86-64_ops.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdint.h>
#include <86box/86box.h>

2
src/codegen_new/codegen_backend_x86-64_ops_sse.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdint.h>
#include <86box/86box.h>

14
src/codegen_new/codegen_backend_x86-64_uops.c
View File

@@ -1,4 +1,4 @@
#ifdef __amd64__
#if defined __amd64__ || defined _M_X64
#include <stdint.h>
#include <86box/86box.h>
@@ -803,7 +803,7 @@ static int codegen_FP_ENTER(codeblock_t *block, uop_t *uop)
host_x86_TEST32_REG_IMM(block, REG_ECX, 0xc);
branch_offset = host_x86_JZ_long(block);
host_x86_MOV32_ABS_IMM(block, &cpu_state.oldpc, uop->imm_data);
#if WIN64
#if _WIN64
host_x86_MOV32_REG_IMM(block, REG_ECX, 7);
#else
host_x86_MOV32_REG_IMM(block, REG_EDI, 7);
@@ -822,7 +822,7 @@ static int codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
host_x86_TEST32_REG_IMM(block, REG_ECX, 0xc);
branch_offset = host_x86_JZ_long(block);
host_x86_MOV32_ABS_IMM(block, &cpu_state.oldpc, uop->imm_data);
#if WIN64
#if _WIN64
host_x86_MOV32_REG_IMM(block, REG_ECX, 7);
#else
host_x86_MOV32_REG_IMM(block, REG_EDI, 7);
@@ -852,7 +852,7 @@ static int codegen_LOAD_FUNC_ARG0(codeblock_t *block, uop_t *uop)
if (REG_IS_W(src_size))
{
#if WIN64
#if _WIN64
host_x86_MOVZX_REG_32_16(block, REG_ECX, src_reg);
#else
host_x86_MOVZX_REG_32_16(block, REG_EDI, src_reg);
@@ -888,7 +888,7 @@ static int codegen_LOAD_FUNC_ARG3(codeblock_t *block, uop_t *uop)
static int codegen_LOAD_FUNC_ARG0_IMM(codeblock_t *block, uop_t *uop)
{
#if WIN64
#if _WIN64
host_x86_MOV32_REG_IMM(block, REG_ECX, uop->imm_data);
#else
host_x86_MOV32_REG_IMM(block, REG_EDI, uop->imm_data);
@@ -897,7 +897,7 @@ static int codegen_LOAD_FUNC_ARG0_IMM(codeblock_t *block, uop_t *uop)
}
static int codegen_LOAD_FUNC_ARG1_IMM(codeblock_t *block, uop_t *uop)
{
#if WIN64
#if _WIN64
host_x86_MOV32_REG_IMM(block, REG_EDX, uop->imm_data);
#else
host_x86_MOV32_REG_IMM(block, REG_ESI, uop->imm_data);
@@ -928,7 +928,7 @@ static int codegen_LOAD_SEG(codeblock_t *block, uop_t *uop)
if (!REG_IS_W(src_size))
fatal("LOAD_SEG %02x %p\n", uop->src_reg_a_real, uop->p);
#endif
#if WIN64
#if _WIN64
host_x86_MOV16_REG_REG(block, REG_CX, src_reg);
host_x86_MOV64_REG_IMM(block, REG_EDX, (uint64_t)uop->p);
#else

6
src/cpu/386_common.c
View File

@@ -1023,12 +1023,6 @@ enter_smm(int in_hlt)
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cx6x86)
return;
if (cpu_iscyrix) {
if (!cyrix.smhr & SMHR_VALID)
cyrix.smhr = (cyrix.arr[3].base + cyrix.arr[3].size) | SMHR_VALID;
smram_state = cyrix.smhr & SMHR_ADDR_MASK;
}
x386_common_log("enter_smm(): smbase = %08X\n", smbase);
x386_common_log("CS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
cpu_state.seg_cs.seg, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low,

26
src/cpu/cpu.c
View File

@@ -353,8 +353,14 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
const CPU *cpu_s = &cpu_family->cpus[cpu];
if (machine_s->cpu_block & cpu_s->cpu_type) /* CPU type blocklist */
return 0;
/* Check CPU blocklist. */
if (machine_s->cpu_block) {
uint8_t i = 0;
while (machine_s->cpu_block[i]) {
if (machine_s->cpu_block[i++] == cpu_s->cpu_type)
return 0;
}
}
uint32_t bus_speed = cpu_s->rspeed / cpu_s->multi;
@@ -375,40 +381,40 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
if (cpu_s->cpu_flags & CPU_FIXED_MULTIPLIER) {
return 1; /* don't care about multiplier compatibility on fixed multiplier CPUs */
} else if (cpu_family->package & CPU_PKG_SOCKET5_7) {
if ((multi == 1.5) && (cpu_s->cpu_type & CPU_5K86) && (machine_s->cpu_min_multi > 1.5)) /* K5 5k86 */
if ((multi == 1.5) && (cpu_s->cpu_type == CPU_5K86) && (machine_s->cpu_min_multi > 1.5)) /* K5 5k86 */
multi = 2.0;
else if (multi == 1.75) /* K5 5k86 */
multi = 2.5;
else if (multi == 2.0) {
if (cpu_s->cpu_type & CPU_5K86) /* K5 5k86 */
if (cpu_s->cpu_type == CPU_5K86) /* K5 5k86 */
multi = 3.0;
else if (cpu_s->cpu_type & (CPU_K6_2P | CPU_K6_3P)) /* K6-2+ / K6-3+ */
else if (cpu_s->cpu_type == CPU_K6_2P || cpu_s->cpu_type == CPU_K6_3P) /* K6-2+ / K6-3+ */
multi = 2.5;
else if ((cpu_s->cpu_type & (CPU_WINCHIP | CPU_WINCHIP2)) && (machine_s->cpu_min_multi > 2.0)) /* WinChip (2) */
else if ((cpu_s->cpu_type == CPU_WINCHIP || cpu_s->cpu_type == CPU_WINCHIP2) && (machine_s->cpu_min_multi > 2.0)) /* WinChip (2) */
multi = 2.5;
}
else if (multi == (7.0 / 3.0)) /* WinChip 2A - 2.33x */
multi = 5.0;
else if (multi == (8.0 / 3.0)) /* WinChip 2A - 2.66x */
multi = 5.5;
else if ((multi == 3.0) && (cpu_s->cpu_type & (CPU_Cx6x86 | CPU_Cx6x86L))) /* 6x86(L) */
else if ((multi == 3.0) && (cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86L)) /* 6x86(L) */
multi = 1.5;
else if (multi == (10.0 / 3.0)) /* WinChip 2A - 3.33x */
multi = 2.0;
else if ((multi == 3.5) && (machine_s->cpu_min_multi < 3.5)) /* standard set by the Pentium MMX */
multi = 1.5;
else if (multi == 4.0) {
if (cpu_s->cpu_type & (CPU_WINCHIP | CPU_WINCHIP2)) { /* WinChip (2) */
if (cpu_s->cpu_type == CPU_WINCHIP || cpu_s->cpu_type == CPU_WINCHIP2) { /* WinChip (2) */
if (machine_s->cpu_min_multi >= 1.5)
multi = 1.5;
else if (machine_s->cpu_min_multi >= 3.5)
multi = 3.5;
else if (machine_s->cpu_min_multi >= 4.5)
multi = 4.5;
} else if (cpu_s->cpu_type & (CPU_Cx6x86 | CPU_Cx6x86L)) /* 6x86(L) */
} else if (cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86L) /* 6x86(L) */
multi = 3.0;
}
else if ((multi == 5.0) && (cpu_s->cpu_type & (CPU_WINCHIP | CPU_WINCHIP2)) && (machine_s->cpu_min_multi > 5.0)) /* WinChip (2) */
else if ((multi == 5.0) && (cpu_s->cpu_type == CPU_WINCHIP || cpu_s->cpu_type == CPU_WINCHIP2) && (machine_s->cpu_min_multi > 5.0)) /* WinChip (2) */
multi = 5.5;
else if ((multi == 6.0) && (machine_s->cpu_max_multi < 6.0)) /* K6-2(+) / K6-3(+) */
multi = 2.0;

102
src/cpu/cpu.h
View File

@@ -32,58 +32,58 @@ enum {
};
enum {
CPU_8088 = (1ULL << 0), /* 808x class CPUs */
CPU_8086 = (1ULL << 1),
CPU_8088 = 1, /* 808x class CPUs */
CPU_8086,
#ifdef USE_NEC_808X
CPU_V20 = (1ULL << 2), /* NEC 808x class CPUs - future proofing */
CPU_V30 = (1ULL << 3),
CPU_V20, /* NEC 808x class CPUs - future proofing */
CPU_V30,
#endif
CPU_286 = (1ULL << 4), /* 286 class CPUs */
CPU_386SX = (1ULL << 5), /* 386 class CPUs */
CPU_386DX = (1ULL << 6),
CPU_IBM386SLC = (1ULL << 7),
CPU_IBM486SLC = (1ULL << 8),
CPU_IBM486BL = (1ULL << 9),
CPU_RAPIDCAD = (1ULL << 10),
CPU_486SLC = (1ULL << 11),
CPU_486DLC = (1ULL << 12),
CPU_i486SX = (1ULL << 13), /* 486 class CPUs */
CPU_Am486SX = (1ULL << 14),
CPU_Cx486S = (1ULL << 15),
CPU_i486SX2 = (1ULL << 16),
CPU_Am486SX2 = (1ULL << 17),
CPU_i486DX = (1ULL << 18),
CPU_i486DX2 = (1ULL << 19),
CPU_Am486DX = (1ULL << 20),
CPU_Am486DX2 = (1ULL << 21),
CPU_Cx486DX = (1ULL << 22),
CPU_Cx486DX2 = (1ULL << 23),
CPU_iDX4 = (1ULL << 24),
CPU_Am486DX4 = (1ULL << 25),
CPU_Cx486DX4 = (1ULL << 26),
CPU_Am5x86 = (1ULL << 27),
CPU_Cx5x86 = (1ULL << 28),
CPU_P24T = (1ULL << 29),
CPU_WINCHIP = (1ULL << 30), /* 586 class CPUs */
CPU_WINCHIP2 = (1ULL << 31),
CPU_PENTIUM = (1ULL << 32),
CPU_PENTIUMMMX = (1ULL << 33),
CPU_Cx6x86 = (1ULL << 34),
CPU_Cx6x86MX = (1ULL << 35),
CPU_Cx6x86L = (1ULL << 36),
CPU_CxGX1 = (1ULL << 37),
CPU_K5 = (1ULL << 38),
CPU_5K86 = (1ULL << 39),
CPU_K6 = (1ULL << 40),
CPU_K6_2 = (1ULL << 41),
CPU_K6_2C = (1ULL << 42),
CPU_K6_3 = (1ULL << 43),
CPU_K6_2P = (1ULL << 44),
CPU_K6_3P = (1ULL << 45),
CPU_CYRIX3S = (1ULL << 46),
CPU_PENTIUMPRO = (1ULL << 47), /* 686 class CPUs */
CPU_PENTIUM2 = (1ULL << 48),
CPU_PENTIUM2D = (1ULL << 49)
CPU_286, /* 286 class CPUs */
CPU_386SX, /* 386 class CPUs */
CPU_386DX,
CPU_IBM386SLC,
CPU_IBM486SLC,
CPU_IBM486BL,
CPU_RAPIDCAD,
CPU_486SLC,
CPU_486DLC,
CPU_i486SX, /* 486 class CPUs */
CPU_Am486SX,
CPU_Cx486S,
CPU_i486SX2,
CPU_Am486SX2,
CPU_i486DX,
CPU_i486DX2,
CPU_Am486DX,
CPU_Am486DX2,
CPU_Cx486DX,
CPU_Cx486DX2,
CPU_iDX4,
CPU_Am486DX4,
CPU_Cx486DX4,
CPU_Am5x86,
CPU_Cx5x86,
CPU_P24T,
CPU_WINCHIP, /* 586 class CPUs */
CPU_WINCHIP2,
CPU_PENTIUM,
CPU_PENTIUMMMX,
CPU_Cx6x86,
CPU_Cx6x86MX,
CPU_Cx6x86L,
CPU_CxGX1,
CPU_K5,
CPU_5K86,
CPU_K6,
CPU_K6_2,
CPU_K6_2C,
CPU_K6_3,
CPU_K6_2P,
CPU_K6_3P,
CPU_CYRIX3S,
CPU_PENTIUMPRO, /* 686 class CPUs */
CPU_PENTIUM2,
CPU_PENTIUM2D
};
enum {
@@ -157,7 +157,7 @@ typedef struct {
const char *manufacturer;
const char *name;
const char *internal_name;
const CPU cpus[32];
const CPU *cpus;
} cpu_family_t;
typedef struct {

142
src/cpu/cpu_table.c
View File

@@ -69,11 +69,11 @@ FPU fpus_internal[] =
const cpu_family_t cpu_families[] = {
{
.package = CPU_PKG_8088, /* pcjr = only 4.77 */
.package = CPU_PKG_8088,
.manufacturer = "Intel",
.name = "8088",
.internal_name = "8088",
.cpus = {
.cpus = (const CPU[]) {
{"4.77", CPU_8088, fpus_8088, 4772728, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
{"7.16", CPU_8088, fpus_8088, 7159092, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
{"8", CPU_8088, fpus_8088, 8000000, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
@@ -87,7 +87,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "8088",
.internal_name = "8088_europc",
.cpus = {
.cpus = (const CPU[]) {
{"4.77", CPU_8088, fpus_8088, 4772728, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
{"7.16", CPU_8088, fpus_8088, 7159092, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
{"9.54", CPU_8088, fpus_8088, 9545456, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
@@ -98,7 +98,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "8086",
.internal_name = "8086",
.cpus = {
.cpus = (const CPU[]) {
{"7.16", CPU_8086, fpus_8088, 7159092, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
{"8", CPU_8086, fpus_8088, 8000000, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
{"9.54", CPU_8086, fpus_8088, 9545456, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
@@ -112,7 +112,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "80286",
.internal_name = "286",
.cpus = {
.cpus = (const CPU[]) {
{"6", CPU_286, fpus_80286, 6000000, 1, 5000, 0, 0, 0, 0, 2,2,2,2, 1},
{"8", CPU_286, fpus_80286, 8000000, 1, 5000, 0, 0, 0, 0, 2,2,2,2, 1},
{"10", CPU_286, fpus_80286, 10000000, 1, 5000, 0, 0, 0, 0, 2,2,2,2, 1},
@@ -127,7 +127,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i386SX",
.internal_name = "i386sx",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_386SX, fpus_80386, 16000000, 1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
{"20", CPU_386SX, fpus_80386, 20000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
{"25", CPU_386SX, fpus_80386, 25000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
@@ -140,7 +140,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am386SX",
.internal_name = "am386sx",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_386SX, fpus_80386, 16000000, 1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
{"20", CPU_386SX, fpus_80386, 20000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
{"25", CPU_386SX, fpus_80386, 25000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
@@ -153,7 +153,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i386DX",
.internal_name = "i386dx",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_386DX, fpus_80386, 16000000, 1, 5000, 0x0308, 0, 0, 0, 3,3,3,3, 2},
{"20", CPU_386DX, fpus_80386, 20000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
{"25", CPU_386DX, fpus_80386, 25000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
@@ -166,7 +166,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "RapidCAD",
.internal_name = "rapidcad",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_RAPIDCAD, fpus_internal, 25000000, 1, 5000, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
{"33", CPU_RAPIDCAD, fpus_internal, 33333333, 1, 5000, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
{"40", CPU_RAPIDCAD, fpus_internal, 40000000, 1, 5000, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
@@ -177,7 +177,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am386DX",
.internal_name = "am386dx",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_386DX, fpus_80386, 25000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
{"33", CPU_386DX, fpus_80386, 33333333, 1, 5000, 0x0308, 0, 0, 0, 6,6,3,3, 4},
{"40", CPU_386DX, fpus_80386, 40000000, 1, 5000, 0x0308, 0, 0, 0, 7,7,3,3, 5},
@@ -190,7 +190,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "ALi",
.name = "M6117",
.internal_name = "m6117",
.cpus = { /* All timings and edx_reset values assumed. */
.cpus = (const CPU[]) { /* All timings and edx_reset values assumed. */
{"33", CPU_386DX, fpus_80386, 33333333, 1, 5000, 0x2308, 0, 0, 0, 6,6,3,3, 4},
{"40", CPU_386DX, fpus_80386, 40000000, 1, 5000, 0x2308, 0, 0, 0, 7,7,3,3, 5},
{"", 0}
@@ -202,7 +202,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "386SLC",
.internal_name = "ibm386slc",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_IBM386SLC, fpus_80386, 16000000, 1, 5000, 0xA301, 0, 0, 0, 3,3,3,3, 2},
{"20", CPU_IBM386SLC, fpus_80386, 20000000, 1, 5000, 0xA301, 0, 0, 0, 4,4,3,3, 3},
{"25", CPU_IBM386SLC, fpus_80386, 25000000, 1, 5000, 0xA301, 0, 0, 0, 4,4,3,3, 3},
@@ -213,7 +213,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486SLC",
.internal_name = "cx486slc",
.cpus = {
.cpus = (const CPU[]) {
{"20", CPU_486SLC, fpus_80386, 20000000, 1, 5000, 0x400, 0, 0x0000, 0, 4,4,3,3, 3},
{"25", CPU_486SLC, fpus_80386, 25000000, 1, 5000, 0x400, 0, 0x0000, 0, 4,4,3,3, 3},
{"33", CPU_486SLC, fpus_80386, 33333333, 1, 5000, 0x400, 0, 0x0000, 0, 6,6,3,3, 4},
@@ -224,7 +224,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486SRx2",
.internal_name = "cx486srx2",
.cpus = {
.cpus = (const CPU[]) {
{"32", CPU_486SLC, fpus_80386, 32000000, 2, 5000, 0x406, 0, 0x0006, 0, 6,6,6,6, 4},
{"40", CPU_486SLC, fpus_80386, 40000000, 2, 5000, 0x406, 0, 0x0006, 0, 8,8,6,6, 6},
{"50", CPU_486SLC, fpus_80386, 50000000, 2, 5000, 0x406, 0, 0x0006, 0, 8,8,6,6, 6},
@@ -235,7 +235,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486SLC",
.internal_name = "ibm486slc",
.cpus = {
.cpus = (const CPU[]) {
{"33", CPU_IBM486SLC, fpus_80386, 33333333, 1, 5000, 0xA401, 0, 0, 0, 6,6,3,3, 4},
{"", 0}
}
@@ -244,7 +244,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486SLC2",
.internal_name = "ibm486slc2",
.cpus = {
.cpus = (const CPU[]) {
{"40", CPU_IBM486SLC, fpus_80386, 40000000, 2, 5000, 0xA421, 0, 0, 0, 7,7,6,6, 5},
{"50", CPU_IBM486SLC, fpus_80386, 50000000, 2, 5000, 0xA421, 0, 0, 0, 8,8,6,6, 6},
{"66", CPU_IBM486SLC, fpus_80386, 66666666, 2, 5000, 0xA421, 0, 0, 0, 12,12,6,6, 8},
@@ -255,7 +255,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486SLC3",
.internal_name = "ibm486slc3",
.cpus = {
.cpus = (const CPU[]) {
{"60", CPU_IBM486SLC, fpus_80386, 60000000, 3, 5000, 0xA439, 0, 0, 0, 12,12,9,9, 7},
{"75", CPU_IBM486SLC, fpus_80386, 75000000, 3, 5000, 0xA439, 0, 0, 0, 12,12,9,9, 9},
{"100", CPU_IBM486SLC, fpus_80386, 100000000, 3, 5000, 0xA439, 0, 0, 0, 18,18,9,9, 12},
@@ -266,7 +266,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486BL2",
.internal_name = "ibm486bl2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_IBM486BL, fpus_80386, 50000000, 2, 5000, 0xA439, 0, 0, 0, 8,8,6,6, 6},
{"66", CPU_IBM486BL, fpus_80386, 66666666, 2, 5000, 0xA439, 0, 0, 0, 12,12,6,6, 8},
{"", 0}
@@ -276,7 +276,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IBM",
.name = "486BL3",
.internal_name = "ibm486bl3",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_IBM486BL, fpus_80386, 75000000, 3, 5000, 0xA439, 0, 0, 0, 12,12,9,9, 9},
{"100", CPU_IBM486BL, fpus_80386, 100000000, 3, 5000, 0xA439, 0, 0, 0, 18,18,9,9, 12},
{"", 0}
@@ -286,7 +286,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DLC",
.internal_name = "cx486dlc",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_486DLC, fpus_80386, 25000000, 1, 5000, 0x401, 0, 0x0001, 0, 4, 4,3,3, 3},
{"33", CPU_486DLC, fpus_80386, 33333333, 1, 5000, 0x401, 0, 0x0001, 0, 6, 6,3,3, 4},
{"40", CPU_486DLC, fpus_80386, 40000000, 1, 5000, 0x401, 0, 0x0001, 0, 7, 7,3,3, 5},
@@ -297,7 +297,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DRx2",
.internal_name = "cx486drx2",
.cpus = {
.cpus = (const CPU[]) {
{"32", CPU_486DLC, fpus_80386, 32000000, 2, 5000, 0x407, 0, 0x0007, 0, 6, 6,6,6, 4},
{"40", CPU_486DLC, fpus_80386, 40000000, 2, 5000, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6},
{"50", CPU_486DLC, fpus_80386, 50000000, 2, 5000, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6},
@@ -309,7 +309,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486SX",
.internal_name = "i486sx",
.cpus = {
.cpus = (const CPU[]) {
{"16", CPU_i486SX, fpus_486sx, 16000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
{"20", CPU_i486SX, fpus_486sx, 20000000, 1, 5000, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"25", CPU_i486SX, fpus_486sx, 25000000, 1, 5000, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
@@ -321,7 +321,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486SX2",
.internal_name = "i486sx2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_i486SX2, fpus_486sx, 50000000, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"66 (Q0569)", CPU_i486SX2, fpus_486sx, 66666666, 2, 5000, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
{"", 0}
@@ -331,7 +331,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486DX",
.internal_name = "i486dx",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_i486DX, fpus_internal, 25000000, 1, 5000, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"33", CPU_i486DX, fpus_internal, 33333333, 1, 5000, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"50", CPU_i486DX, fpus_internal, 50000000, 1, 5000, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
@@ -342,7 +342,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486DX2",
.internal_name = "i486dx2",
.cpus = {
.cpus = (const CPU[]) {
{"40", CPU_i486DX2, fpus_internal, 40000000, 2, 5000, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
{"50", CPU_i486DX2, fpus_internal, 50000000, 2, 5000, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"66", CPU_i486DX2, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
@@ -353,7 +353,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "i486DX2",
.internal_name = "i486dx2_pc330",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_i486DX2, fpus_internal, 50000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"66", CPU_i486DX2, fpus_internal, 66666666, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"", 0}
@@ -363,7 +363,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "iDX4",
.internal_name = "idx4",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_iDX4, fpus_internal, 75000000, 3.0, 5000, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, /*CPUID available on DX4, >= 75 MHz*/
{"100", CPU_iDX4, fpus_internal, 100000000, 3.0, 5000, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"", 0}
@@ -373,7 +373,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "iDX4 OverDrive",
.internal_name = "idx4_od",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_iDX4, fpus_internal, 75000000, 3, 5000, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/
{"100", CPU_iDX4, fpus_internal, 100000000, 3, 5000, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"", 0}
@@ -383,7 +383,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium OverDrive",
.internal_name = "pentium_p24t",
.cpus = {
.cpus = (const CPU[]) {
{"63", CPU_P24T, fpus_internal, 62500000, 2.5, 5000, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"83", CPU_P24T, fpus_internal, 83333333, 2.5, 5000, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"", 0}
@@ -393,7 +393,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486SX",
.internal_name = "am486sx",
.cpus = {
.cpus = (const CPU[]) {
{"33", CPU_Am486SX, fpus_486sx, 33333333, 1, 5000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"40", CPU_Am486SX, fpus_486sx, 40000000, 1, 5000, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"", 0}
@@ -403,7 +403,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486SX2",
.internal_name = "am486sx2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_Am486SX2, fpus_486sx, 50000000, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
{"66", CPU_Am486SX2, fpus_486sx, 66666666, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
{"", 0}
@@ -413,7 +413,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486DX",
.internal_name = "am486dx",
.cpus = {
.cpus = (const CPU[]) {
{"33", CPU_Am486DX, fpus_internal, 33333333, 1, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"40", CPU_Am486DX, fpus_internal, 40000000, 1, 5000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"", 0}
@@ -423,7 +423,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486DX2",
.internal_name = "am486dx2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_Am486DX2, fpus_internal, 50000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"66", CPU_Am486DX2, fpus_internal, 66666666, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"80", CPU_Am486DX2, fpus_internal, 80000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
@@ -434,7 +434,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am486DX4",
.internal_name = "am486dx4",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_Am486DX4, fpus_internal, 75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"90", CPU_Am486DX4, fpus_internal, 90000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"100", CPU_Am486DX4, fpus_internal, 100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
@@ -446,7 +446,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "Am5x86",
.internal_name = "am5x86",
.cpus = {
.cpus = (const CPU[]) {
{"P75", CPU_Am5x86, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
{"P75+", CPU_Am5x86, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
{"P90", CPU_Am5x86, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/
@@ -457,7 +457,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486S",
.internal_name = "cx486s",
.cpus = {
.cpus = (const CPU[]) {
{"25", CPU_Cx486S, fpus_486sx, 25000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"33", CPU_Cx486S, fpus_486sx, 33333333, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"40", CPU_Cx486S, fpus_486sx, 40000000, 1.0, 5000, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
@@ -467,7 +467,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DX",
.internal_name = "cx486dx",
.cpus = {
.cpus = (const CPU[]) {
{"33", CPU_Cx486DX, fpus_internal, 33333333, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"40", CPU_Cx486DX, fpus_internal, 40000000, 1.0, 5000, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"", 0}
@@ -477,7 +477,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DX2",
.internal_name = "cx486dx2",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_Cx486DX2, fpus_internal, 50000000, 2.0, 5000, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"66", CPU_Cx486DX2, fpus_internal, 66666666, 2.0, 5000, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"80", CPU_Cx486DX2, fpus_internal, 80000000, 2.0, 5000, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
@@ -488,7 +488,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx486DX4",
.internal_name = "cx486dx4",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_Cx486DX4, fpus_internal, 75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"100", CPU_Cx486DX4, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"", 0}
@@ -498,7 +498,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx5x86",
.internal_name = "cx5x86",
.cpus = {
.cpus = (const CPU[]) {
{"80", CPU_Cx5x86, fpus_internal, 80000000, 2.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/
{"100", CPU_Cx5x86, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"120", CPU_Cx5x86, fpus_internal, 120000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
@@ -512,7 +512,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "ST",
.name = "STPC-DX",
.internal_name = "stpc_dx",
.cpus = {
.cpus = (const CPU[]) {
{"66", CPU_Cx486DX, fpus_internal, 66666666, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"75", CPU_Cx486DX, fpus_internal, 75000000, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"", 0}
@@ -522,7 +522,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "ST",
.name = "STPC-DX2",
.internal_name = "stpc_dx2",
.cpus = {
.cpus = (const CPU[]) {
{"133", CPU_Cx486DX2, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"", 0}
}
@@ -533,7 +533,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium",
.internal_name = "pentium_p5",
.cpus = {
.cpus = (const CPU[]) {
{"50 (Q0399)", CPU_PENTIUM, fpus_internal, 50000000, 1, 5000, 0x513, 0x513, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 4, 4,3,3, 6},
{"60", CPU_PENTIUM, fpus_internal, 60000000, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 7},
{"66", CPU_PENTIUM, fpus_internal, 66666666, 1, 5000, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6,3,3, 8},
@@ -544,7 +544,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium OverDrive",
.internal_name = "pentium_p54c_od5v",
.cpus = {
.cpus = (const CPU[]) {
{"100", CPU_PENTIUM, fpus_internal, 100000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 8, 8,6,6, 12},
{"120", CPU_PENTIUM, fpus_internal, 120000000, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 14},
{"133", CPU_PENTIUM, fpus_internal, 133333333, 2, 5000, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,6,6, 16},
@@ -555,7 +555,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium",
.internal_name = "pentium_p54c",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_PENTIUM, fpus_internal, 75000000, 1.5, 3520, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"90", CPU_PENTIUM, fpus_internal, 90000000, 1.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"100/50", CPU_PENTIUM, fpus_internal, 100000000, 2.0, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12},
@@ -572,7 +572,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium MMX",
.internal_name = "pentium_p55c",
.cpus = {
.cpus = (const CPU[]) {
{"166", CPU_PENTIUMMMX, fpus_internal, 166666666, 2.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"200", CPU_PENTIUMMMX, fpus_internal, 200000000, 3.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"233", CPU_PENTIUMMMX, fpus_internal, 233333333, 3.5, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
@@ -583,7 +583,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Mobile Pentium MMX",
.internal_name = "pentium_tillamook",
.cpus = {
.cpus = (const CPU[]) {
{"120", CPU_PENTIUMMMX, fpus_internal, 120000000, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"133", CPU_PENTIUMMMX, fpus_internal, 133333333, 2.0, 2800, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"150", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 2800, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
@@ -599,7 +599,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium OverDrive",
.internal_name = "pentium_p54c_od3v",
.cpus = {
.cpus = (const CPU[]) {
{"125", CPU_PENTIUM, fpus_internal, 125000000, 3.0, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15},
{"150", CPU_PENTIUM, fpus_internal, 150000000, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2},
{"166", CPU_PENTIUM, fpus_internal, 166666666, 2.5, 3520, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 20},
@@ -610,7 +610,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium OverDrive MMX",
.internal_name = "pentium_p55c_od",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_PENTIUMMMX, fpus_internal, 75000000, 1.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 7, 7,4,4, 9},
{"125", CPU_PENTIUMMMX, fpus_internal, 125000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12,7,7, 15},
{"150/60", CPU_PENTIUMMMX, fpus_internal, 150000000, 2.5, 3520, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 15,15,7,7, 35/2},
@@ -624,7 +624,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IDT",
.name = "WinChip",
.internal_name = "winchip",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_WINCHIP, fpus_internal, 75000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9},
{"90", CPU_WINCHIP, fpus_internal, 90000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2},
{"100", CPU_WINCHIP, fpus_internal, 100000000, 1.5, 3520, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12},
@@ -643,7 +643,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IDT",
.name = "WinChip 2",
.internal_name = "winchip2",
.cpus = {
.cpus = (const CPU[]) {
{"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8},
{"225", CPU_WINCHIP2, fpus_internal, 225000000, 3.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9},
{"240", CPU_WINCHIP2, fpus_internal, 240000000, 4.0, 3520, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
@@ -655,7 +655,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "IDT",
.name = "WinChip 2A",
.internal_name = "winchip2a",
.cpus = {
.cpus = (const CPU[]) {
{"200", CPU_WINCHIP2, fpus_internal, 200000000, 3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8},
{"233", CPU_WINCHIP2, fpus_internal, 233333333, 3.5, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2},
{"266", CPU_WINCHIP2, fpus_internal, 233333333, 7.0/3.0, 3520, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28},
@@ -669,7 +669,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K5 (5k86)",
.internal_name = "k5_5k86",
.cpus = {
.cpus = (const CPU[]) {
{"75 (P75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"90 (P90)", CPU_K5, fpus_internal, 90000000, 1.5, 3520, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"100 (P100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
@@ -685,7 +685,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K5 (SSA/5)",
.internal_name = "k5_ssa5",
.cpus = {
.cpus = (const CPU[]) {
{"75 (PR75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"90 (PR90)", CPU_K5, fpus_internal, 90000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"100 (PR100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
@@ -698,7 +698,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6 (Model 6)",
.internal_name = "k6_m6",
.cpus = {
.cpus = (const CPU[]) {
{"166", CPU_K6, fpus_internal, 166666666, 2.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"200", CPU_K6, fpus_internal, 200000000, 3.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"233", CPU_K6, fpus_internal, 233333333, 3.5, 3200, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
@@ -709,7 +709,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6 (Model 7)",
.internal_name = "k6_m7",
.cpus = {
.cpus = (const CPU[]) {
{"200", CPU_K6, fpus_internal, 200000000, 3.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"233", CPU_K6, fpus_internal, 233333333, 3.5, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"266", CPU_K6, fpus_internal, 266666666, 4.0, 2200, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
@@ -721,7 +721,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6-2",
.internal_name = "k6_2",
.cpus = {
.cpus = (const CPU[]) {
{"233", CPU_K6_2, fpus_internal, 233333333, 3.5, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28},
{"266", CPU_K6_2, fpus_internal, 266666666, 4.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32},
{"300", CPU_K6_2, fpus_internal, 300000000, 3.0, 2200, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36},
@@ -743,7 +743,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6-2+",
.internal_name = "k6_2p",
.cpus = {
.cpus = (const CPU[]) {
{"450", CPU_K6_2P, fpus_internal, 450000000, 4.5, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"475", CPU_K6_2P, fpus_internal, 475000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57},
{"500", CPU_K6_2P, fpus_internal, 500000000, 5.0, 2000, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60},
@@ -756,7 +756,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6-III",
.internal_name = "k6_3",
.cpus = {
.cpus = (const CPU[]) {
{"400", CPU_K6_3, fpus_internal, 400000000, 4.0, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"450", CPU_K6_3, fpus_internal, 450000000, 4.5, 2200, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"", 0}
@@ -766,7 +766,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "AMD",
.name = "K6-III+",
.internal_name = "k6_3p",
.cpus = {
.cpus = (const CPU[]) {
{"100", CPU_K6_3P, fpus_internal, 100000000, 1.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"400", CPU_K6_3P, fpus_internal, 400000000, 4.0, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"450", CPU_K6_3P, fpus_internal, 450000000, 4.5, 2000, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
@@ -781,7 +781,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx6x86",
.internal_name = "cx6x86",
.cpus = {
.cpus = (const CPU[]) {
{"P90", CPU_Cx6x86, fpus_internal, 80000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
{"PR120+", CPU_Cx6x86, fpus_internal, 100000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"PR133+", CPU_Cx6x86, fpus_internal, 110000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
@@ -795,7 +795,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx6x86L",
.internal_name = "cx6x86l",
.cpus = {
.cpus = (const CPU[]) {
{"PR133+", CPU_Cx6x86L, fpus_internal, 110000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"PR150+", CPU_Cx6x86L, fpus_internal, 120000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"PR166+", CPU_Cx6x86L, fpus_internal, 133333333, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
@@ -807,7 +807,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "Cx6x86MX",
.internal_name = "cx6x86mx",
.cpus = {
.cpus = (const CPU[]) {
{"PR166", CPU_Cx6x86MX, fpus_internal, 133333333, 2.0, 2900, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"PR200", CPU_Cx6x86MX, fpus_internal, 166666666, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"PR233", CPU_Cx6x86MX, fpus_internal, 187500000, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
@@ -819,7 +819,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Cyrix",
.name = "MII",
.internal_name = "mii",
.cpus = {
.cpus = (const CPU[]) {
{"PR300", CPU_Cx6x86MX, fpus_internal, 233333333, 3.5, 2900, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28},
{"PR333", CPU_Cx6x86MX, fpus_internal, 250000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30},
{"PR366", CPU_Cx6x86MX, fpus_internal, 250000000, 2.5, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30},
@@ -834,7 +834,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium Pro",
.internal_name = "pentiumpro",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_PENTIUMPRO, fpus_internal, 50000000, 1.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"60", CPU_PENTIUMPRO, fpus_internal, 60000000, 1.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"66", CPU_PENTIUMPRO, fpus_internal, 66666666, 1.0, 3100, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
@@ -850,7 +850,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium II OverDrive",
.internal_name = "pentium2_od",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_PENTIUM2D, fpus_internal, 50000000, 1.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 4, 4, 3, 3, 6},
{"60", CPU_PENTIUM2D, fpus_internal, 60000000, 1.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 7},
{"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 3300, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8},
@@ -870,7 +870,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium II (Klamath)",
.internal_name = "pentium2_klamath",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_PENTIUM2, fpus_internal, 50000000, 1.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"60", CPU_PENTIUM2, fpus_internal, 60000000, 1.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"66", CPU_PENTIUM2, fpus_internal, 66666666, 1.0, 2800, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
@@ -885,7 +885,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium II (Deschutes)",
.internal_name = "pentium2_deschutes",
.cpus = {
.cpus = (const CPU[]) {
{"50", CPU_PENTIUM2D, fpus_internal, 50000000, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"60", CPU_PENTIUM2D, fpus_internal, 60000000, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
@@ -903,7 +903,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Pentium II Xeon",
.internal_name = "pentium2_xeon",
.cpus = {
.cpus = (const CPU[]) {
{"75", CPU_PENTIUM2D, fpus_internal, 75000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
@@ -917,7 +917,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "Intel",
.name = "Celeron (Mendocino)",
.internal_name = "celeron_mendocino",
.cpus = {
.cpus = (const CPU[]) {
{"66", CPU_PENTIUM2D, fpus_internal, 66666666, 1.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8},
{"100", CPU_PENTIUM2D, fpus_internal, 100000000, 1.5, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 10,10, 6, 6, 12},
{"133", CPU_PENTIUM2D, fpus_internal, 133333333, 2.0, 2050, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC | CPU_FIXED_MULTIPLIER, 12,12, 6, 6, 16},
@@ -937,7 +937,7 @@ const cpu_family_t cpu_families[] = {
.manufacturer = "VIA",
.name = "Cyrix III",
.internal_name = "c3_samuel",
.cpus = {
.cpus = (const CPU[]) {
{"66", CPU_CYRIX3S, fpus_internal, 66666666, 1.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 6, 6, 3, 3, 8}, /* not in multiplier range */
{"233", CPU_CYRIX3S, fpus_internal, 233333333, 3.5, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 21, 21, 9, 9, 28}, /* not in multiplier range */
{"266", CPU_CYRIX3S, fpus_internal, 266666666, 4.0, 2050, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC | CPU_FIXED_MULTIPLIER, 24, 24, 12, 12, 32}, /* not in multiplier range */

14
src/cpu/x87_ops.h
View File

@@ -46,6 +46,12 @@ static int rounding_modes[4] = {FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARDZ
#define STATUS_ZERODIVIDE 4
#if defined(_MSC_VER) && !defined(__clang__)
# define X87_INLINE_ASM defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
#else
# define X87_INLINE_ASM defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64 || defined __amd64__
#endif
#ifdef FPU_8087
#define x87_div(dst, src1, src2) do \
{ \
@@ -311,7 +317,7 @@ static __inline void x87_stmmx(MMX_REG r)
static __inline uint16_t x87_compare(double a, double b)
{
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64
#if X87_INLINE_ASM
uint32_t result;
double ea = a, eb = b;
const uint64_t ia = 0x3fec1a6ff866a936ull;
@@ -325,7 +331,7 @@ static __inline uint16_t x87_compare(double a, double b)
((a == INFINITY) || (a == -INFINITY)) && ((b == INFINITY) || (b == -INFINITY)))
eb = ea;
#ifndef _MSC_VER
#if !defined(_MSC_VER) || defined(__clang__)
/* Memory barrier, to force GCC to write to the input parameters
* before the compare rather than after */
__asm volatile ("" : : : "memory");
@@ -373,10 +379,10 @@ static __inline uint16_t x87_compare(double a, double b)
static __inline uint16_t x87_ucompare(double a, double b)
{
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64 || defined __amd64__
#if X87_INLINE_ASM
uint32_t result;
#ifndef _MSC_VER
#if !defined(_MSC_VER) || defined(__clang__)
/* Memory barrier, to force GCC to write to the input parameters
* before the compare rather than after */
asm volatile ("" : : : "memory");

52
src/device/clock_ics9xxx.c
View File

@@ -78,7 +78,7 @@ typedef struct {
} hw_select;
uint8_t frequencies_ref; /* which other model to use the frequency table from (or 0) */
ics9xxx_frequency_t *frequencies; /* frequency table, if not using another model's table */
const ics9xxx_frequency_t *frequencies; /* frequency table, if not using another model's table */
} ics9xxx_model_t;
typedef struct {
@@ -105,7 +105,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x00, 0xff, 0xff, 0xff, 0x6f, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 5000, .pci_div = 2},
{.bus = 7500, .pci_div = 2},
{.bus = 8333, .pci_div = 2},
@@ -117,7 +117,6 @@ static const ics9xxx_model_t ics9xxx_models[] = {
{0}
}
ICS9xxx_MODEL_END()
#if 0
ICS9xxx_MODEL(ICS9248_39)
.max_reg = 5,
.regs = {0x00, 0x7f, 0xff, 0xbf, 0xf5, 0xff},
@@ -125,12 +124,13 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.hw_select = {0, 3},
.frequencies_ref = ICS9250_08
ICS9xxx_MODEL_END()
#if 0
ICS9xxx_MODEL(ICS9248_81)
.max_reg = 5,
.regs = {0x82, 0xfe, 0x7f, 0xff, 0xff, 0xb7},
.fs_regs = {{0, 4, 1, 0}, {0, 5, 2, 7}, {0, 6, 5, 6}, {0, 2, 5, 3}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 9000, .ram_mult = 1, .pci_div = 3},
{.bus = 6670, .ram_mult = 1.5, .pci_div = 2},
{.bus = 9500, .ram_mult = 2.0/3.0, .pci_div = 3},
@@ -155,7 +155,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x82, 0xff, 0xff, 0xff, 0xd5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .pci_div = 2},
{.bus = 10000, .pci_div = 3},
{.bus = 10030, .pci_div = 3},
@@ -180,7 +180,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x00, 0x7f, 0xff, 0xbf, 0xf5, 0xff, 0x06},
.fs_regs = {{0, 4, 3, 6}, {0, 5, 4, 3}, {0, 6, 1, 7}, {0, 7, 4, 1}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 8000, .pci_div = 2},
{.bus = 7500, .pci_div = 2},
{.bus = 8331, .pci_div = 2},
@@ -221,7 +221,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x82, 0xff, 0xff, 0xff, 0xf5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 12400, .pci_div = 3},
{.bus = 12000, .pci_div = 3},
{.bus = 11499, .pci_div = 3},
@@ -253,7 +253,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0xff, 0xff, 0xec, 0xde, 0xff, 0x06},
.fs_regs = {{0, 4, 4, 5}, {0, 5, 3, 4}, {0, 6, 3, 0}, {0, 7, 3, 1}, {0, 2, 4, 0}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 10300, .pci_div = 3},
{.bus = 10000, .pci_div = 3},
{.bus = 10045, .pci_div = 3},
@@ -294,7 +294,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x1f, 0xff, 0xff, 0xfb, 0xff, 0x06},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6680, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6800, .ram_mult = 1.5, .pci_div = 2},
{.bus = 10030, .ram_mult = 1, .pci_div = 3},
@@ -335,7 +335,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x3f, 0x7f, 0x6f, 0xff, 0xff, 0x06},
.fs_regs = {{0, 4, 2, 7}, {0, 5, 1, 6}, {0, 6, 1, 7}, {0, 7, 3, 4}, {0, 2, 3, 7}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6687, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6867, .ram_mult = 1.5, .pci_div = 2},
@@ -376,7 +376,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x6b, 0x7f, 0xff, 0xff, 0xe7, 0x06},
.fs_regs = {{0, 4, 2, 7}, {0, 5, 5, 3}, {0, 6, 1, 7}, {0, 7, 1, 4}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 9000, .pci_div = 3},
{.bus = 9500, .pci_div = 2},
{.bus = 10100, .pci_div = 2},
@@ -416,7 +416,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.max_reg = 5,
.regs = {0x82, 0xff, 0xff, 0xff, 0xd5, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 2, 4, 1}, {-1, -1, -1, -1}},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .pci_div = 2},
{.bus = 10000, .pci_div = 3},
{.bus = 10030, .pci_div = 3},
@@ -441,7 +441,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x80, 0x4f, 0xff, 0x3f, 0xff, 0xff, 0x06},
.fs_regs = {{0, 4, -1, -1}, {0, 5, -1, -1}, {0, 6, 3, 7}, {0, 1, 1, 4}, {0, 2, 1, 5}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 20000, .pci_div = 5, .agp_div = 2.5},
{.bus = 19000, .pci_div = 5, .agp_div = 2.5},
{.bus = 18000, .pci_div = 5, .agp_div = 2.5},
@@ -482,7 +482,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.fs_regs = {{0, 4, -1, -1}, {0, 5, 4, 3}, {0, 6, -1, -1}, {0, 7, -1, -1}, {0, 2, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
{.bus = 6000, .pci_div = 2},
@@ -524,7 +524,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x00, 0xff, 0xff, 0xff, 0x6d, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 12400, .pci_div = 3},
{.bus = 7500, .pci_div = 2},
{.bus = 8333, .pci_div = 2},
@@ -550,7 +550,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x1f, 0xff, 0xfe, 0x00, 0x00, 0x06},
.fs_regs = {{5, 0, -1, -1}, {5, 3, -1, -1}, {5, 4, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7067, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7466, .ram_mult = 1.5, .pci_div = 2},
@@ -575,7 +575,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x82, 0xcf, 0x7f, 0xff, 0xff, 0xf7},
.fs_regs = {{0, 4, 1, 4}, {0, 5, 5, 7}, {0, 6, 1, 5}, {0, 2, 2, 7}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 9000, .ram_mult = 1, .pci_div = 2},
{.bus = 8901, .ram_mult = 1, .pci_div = 2},
{.bus = 8800, .ram_mult = 1, .pci_div = 2},
@@ -600,7 +600,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x1f, 0xff, 0xff, 0xeb, 0xff},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6781, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7201, .ram_mult = 1.5, .pci_div = 2},
@@ -641,7 +641,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x1f, 0xff, 0xff, 0x00, 0x00, 0x06},
.fs_regs = {{5, 0, -1, -1}, {5, 3, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7267, .ram_mult = 1.5, .pci_div = 2},
@@ -667,7 +667,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0xff, 0xff, 0xff, 0x6d, 0xbf},
.fs_regs = {{0, 4, 4, 7}, {0, 5, 4, 4}, {0, 6, 5, 6}, {0, 7, 4, 1}, {-1, -1, -1, -1}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 8000, .pci_div = 2},
{.bus = 7500, .pci_div = 2},
{.bus = 8331, .pci_div = 2},
@@ -716,7 +716,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x1f, 0xff, 0xff, 0xeb, 0xff},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6900, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 7100, .ram_mult = 1.5, .pci_div = 2},
@@ -757,7 +757,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x1f, 0xff, 0xff, 0xeb, 0xff, 0x06},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 5500, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6680, .ram_mult = 1.5, .pci_div = 2},
@@ -805,7 +805,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x0f, 0xff, 0xfe, 0x00, 0x00, 0x00},
.fs_regs = {{-1, -1, -1, -1}, {-1, -1, -1, -1}, {3, 0, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.hw_select = {-1, -1},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6666, .ram_mult = 1.5, .pci_div = 2},
{.bus = 13332, .ram_mult = 1, .pci_div = 4},
{.bus = 10000, .ram_mult = 1, .pci_div = 3},
@@ -836,7 +836,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x0f, 0xff, 0xff, 0xeb, 0xff, 0x06},
.fs_regs = {{0, 4, 1, 6}, {0, 5, 4, 2}, {0, 6, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6000, .ram_mult = 1.5, .pci_div = 2},
{.bus = 6680, .ram_mult = 1.5, .pci_div = 2},
@@ -882,7 +882,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x18, 0x07, 0xfe, 0xc7, 0xfc, 0x00, 0x80},
.fs_regs = {{0, 0, -1, -1}, {0, 1, -1, -1}, {0, 2, -1, -1}, {-1, -1, -1, -1}, {-1, -1, -1, -1}},
.normal_bits_fixed = 1,
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
{.bus = 6666, .ram_mult = 1, .pci_div = 1},
{.bus = 10000, .ram_mult = 2.0/3.0, .pci_div = 3},
{.bus = 20000, .ram_mult = 1.0/3.0, .pci_div = 6},
@@ -899,7 +899,7 @@ static const ics9xxx_model_t ics9xxx_models[] = {
.regs = {0x02, 0x6f, 0xff, 0xff, 0xef, 0xff, 0x06},
.fs_regs = {{-1, -1, 1, 6}, {-1, -1, 4, 2}, {-1, -1, 1, 5}, {0, 7, 1, 7}, {0, 2, 4, 4}},
.hw_select = {0, 3},
.frequencies = (ics9xxx_frequency_t[]) {
.frequencies = (const ics9xxx_frequency_t[]) {
[0 ... 7] = {.bus = 6667, .ram_mult = 1.5, .pci_div = 2},
[8 ... 15] = {.bus = 10000, .ram_mult = 1, .pci_div = 3},
[16 ... 23] = {.bus = 13333, .ram_mult = 1, .pci_div = 4},

4
src/device/hwm_gl518sm.c
View File

@@ -39,9 +39,9 @@ typedef struct {
hwm_values_t *values;
uint16_t regs[32];
uint8_t addr_register;
uint8_t addr_register: 5;
uint8_t i2c_addr, i2c_state;
uint8_t i2c_addr: 7, i2c_state: 2;
} gl518sm_t;

161
src/device/hwm_lm75.c
View File

@@ -30,12 +30,6 @@
#define LM75_TEMP_TO_REG(t) ((t) << 8)
static uint8_t lm75_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv);
static uint8_t lm75_i2c_read(void *bus, uint8_t addr, void *priv);
static uint8_t lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv);
static void lm75_reset(lm75_t *dev);
#ifdef ENABLE_LM75_LOG
int lm75_do_log = ENABLE_LM75_LOG;
@@ -56,21 +50,6 @@ lm75_log(const char *fmt, ...)
#endif
void
lm75_remap(lm75_t *dev, uint8_t addr)
{
lm75_log("LM75: remapping to SMBus %02Xh\n", addr);
if (dev->i2c_addr < 0x80)
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
dev->i2c_addr = addr;
}
static uint8_t
lm75_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
{
@@ -82,49 +61,6 @@ lm75_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
}
static uint8_t
lm75_i2c_read(void *bus, uint8_t addr, void *priv)
{
lm75_t *dev = (lm75_t *) priv;
uint8_t ret = 0;
if (dev->i2c_state == 0)
dev->i2c_state = 1;
/* The AS99127F hardware monitor uses the addresses of its LM75 devices
to access some of its proprietary registers. Pass this operation on to
the main monitor address through an internal I2C call, if necessary. */
if ((dev->addr_register > 0x7) && ((dev->addr_register & 0xf8) != 0x50) && (dev->as99127f_i2c_addr < 0x80)) {
i2c_start(i2c_smbus, dev->as99127f_i2c_addr, 1);
i2c_write(i2c_smbus, dev->as99127f_i2c_addr, dev->addr_register);
ret = i2c_read(i2c_smbus, dev->as99127f_i2c_addr);
i2c_stop(i2c_smbus, dev->as99127f_i2c_addr);
} else {
switch (dev->addr_register & 0x3) {
case 0x0: /* temperature */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x0 : 0x1);
break;
case 0x1: /* configuration */
ret = lm75_read(dev, 0x2);
break;
case 0x2: /* Thyst */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x3 : 0x4);
break;
case 0x3: /* Tos */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x5 : 0x6);
break;
}
}
if (++dev->i2c_state > 2)
dev->i2c_state = 2;
return ret;
}
uint8_t
lm75_read(lm75_t *dev, uint8_t reg)
{
@@ -143,6 +79,62 @@ lm75_read(lm75_t *dev, uint8_t reg)
}
static uint8_t
lm75_i2c_read(void *bus, uint8_t addr, void *priv)
{
lm75_t *dev = (lm75_t *) priv;
uint8_t ret = 0;
if (dev->i2c_state == 0)
dev->i2c_state = 1;
/* The AS99127F hardware monitor uses its primary LM75 device's
address to access some of its proprietary registers. Pass this
operation on to the main monitor code, if necessary. */
if ((dev->addr_register & 0x80) && dev->as99127f) {
ret = lm78_as99127f_read(dev->as99127f, dev->addr_register);
} else {
switch (dev->addr_register & 0x3) {
case 0x0: /* temperature */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x0 : 0x1);
break;
case 0x1: /* configuration */
ret = lm75_read(dev, 0x2);
break;
case 0x2: /* Thyst */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x3 : 0x4);
break;
case 0x3: /* Tos */
ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x5 : 0x6);
break;
}
}
if (dev->i2c_state < 2)
dev->i2c_state++;
return ret;
}
uint8_t
lm75_write(lm75_t *dev, uint8_t reg, uint8_t val)
{
lm75_log("LM75: write(%02X, %02X)\n", reg, val);
uint8_t reg_idx = (reg & 0x7);
if ((reg_idx <= 0x1) || (reg_idx == 0x7))
return 0; /* read-only registers */
dev->regs[reg_idx] = val;
return 1;
}
static uint8_t
lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
{
@@ -151,22 +143,18 @@ lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
if ((dev->i2c_state > 2) || ((dev->i2c_state == 2) && ((dev->addr_register & 0x3) == 0x1))) {
return 0;
} else if (dev->i2c_state == 0) {
dev->i2c_state = 1;
/* Linux lm75.c driver relies on the address register not changing if bit 2 is set. */
if ((dev->as99127f_i2c_addr < 0x80) || !(data & 0x04))
dev->i2c_state = 1;
/* Linux lm75.c driver relies on the address register not changing if bit 2 is set. */
if (((dev->addr_register & 0x80) && dev->as99127f) || !(data & 0x04))
dev->addr_register = data;
return 1;
}
/* The AS99127F hardware monitor uses the addresses of its LM75 devices
to access some of its proprietary registers. Pass this operation on to
the main monitor address through an internal I2C call, if necessary. */
if ((dev->addr_register > 0x7) && ((dev->addr_register & 0xf8) != 0x50) && (dev->as99127f_i2c_addr < 0x80)) {
i2c_start(i2c_smbus, dev->as99127f_i2c_addr, 0);
i2c_write(i2c_smbus, dev->as99127f_i2c_addr, dev->addr_register);
i2c_write(i2c_smbus, dev->as99127f_i2c_addr, data);
i2c_stop(i2c_smbus, dev->as99127f_i2c_addr);
return 1;
/* The AS99127F hardware monitor uses its primary LM75 device's
address to access some of its proprietary registers. Pass this
operation on to the main monitor code, if necessary. */
if ((dev->addr_register & 0x80) && dev->as99127f) {
return lm78_as99127f_write(dev->as99127f, dev->addr_register, data);
} else {
switch (dev->addr_register & 0x3) {
case 0x0: /* temperature */
@@ -188,25 +176,24 @@ lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
}
if (dev->i2c_state == 1)
dev->i2c_state = 2;
dev->i2c_state = 2;
return 1;
}
uint8_t
lm75_write(lm75_t *dev, uint8_t reg, uint8_t val)
void
lm75_remap(lm75_t *dev, uint8_t addr)
{
lm75_log("LM75: write(%02X, %02X)\n", reg, val);
lm75_log("LM75: remapping to SMBus %02Xh\n", addr);
uint8_t reg_idx = (reg & 0x7);
if (dev->i2c_addr < 0x80)
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
if ((reg_idx <= 0x1) || (reg_idx == 0x7))
return 0; /* read-only registers */
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, lm75_i2c_start, lm75_i2c_read, lm75_i2c_write, NULL, dev);
dev->regs[reg_idx] = val;
return 1;
dev->i2c_addr = addr;
}
@@ -244,8 +231,6 @@ lm75_init(const device_t *info)
hwm_values.temperatures[dev->local >> 8] = 30;
dev->values = &hwm_values;
dev->as99127f_i2c_addr = 0x80;
lm75_reset(dev);
return dev;

671
src/device/hwm_lm78.c
View File

@@ -25,6 +25,8 @@
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/machine.h>
#include <86box/nvr.h>
#include "cpu.h"
#include <86box/i2c.h>
#include <86box/hwm.h>
@@ -48,28 +50,33 @@
typedef struct {
uint32_t local;
hwm_values_t *values;
device_t *lm75[2];
pc_timer_t hard_reset_timer;
uint32_t local;
hwm_values_t *values;
device_t *lm75[2];
pc_timer_t reset_timer;
uint8_t regs[256];
uint8_t regs_782d[2][16];
uint8_t addr_register;
uint8_t data_register;
uint8_t regs[256];
union {
struct {
uint8_t regs[2][16];
} w83782d;
struct {
uint8_t regs[3][128];
uint8_t i2c_addr, i2c_state;
uint8_t nvram[1024], nvram_i2c_state: 2, nvram_updated: 1;
uint16_t nvram_addr_register: 10;
int8_t nvram_block_len: 6;
uint8_t security_i2c_state: 1, security_addr_register: 7;
} as99127f;
};
uint8_t addr_register, data_register;
uint8_t i2c_addr: 7, i2c_state: 1;
} lm78_t;
static uint8_t lm78_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv);
static uint8_t lm78_isa_read(uint16_t port, void *priv);
static uint8_t lm78_i2c_read(void *bus, uint8_t addr, void *priv);
static uint8_t lm78_read(lm78_t *dev, uint8_t reg, uint8_t bank);
static void lm78_isa_write(uint16_t port, uint8_t val, void *priv);
static uint8_t lm78_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv);
static uint8_t lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank);
static void lm78_reset(lm78_t *dev, uint8_t initialization);
static void lm78_remap(lm78_t *dev, uint8_t addr);
#ifdef ENABLE_LM78_LOG
@@ -92,31 +99,223 @@ lm78_log(const char *fmt, ...)
#endif
static void
lm78_remap(lm78_t *dev, uint8_t addr)
void
lm78_nvram(lm78_t *dev, uint8_t save)
{
lm75_t *lm75;
size_t l = strlen(machine_get_internal_name_ex(machine)) + 1;
wchar_t *machine_name = (wchar_t *) malloc(l * sizeof(wchar_t));
mbstowcs(machine_name, machine_get_internal_name_ex(machine), l);
l = wcslen(machine_name) + 14;
wchar_t *nvr_path = (wchar_t *) malloc(l * sizeof(wchar_t));
swprintf(nvr_path, l, L"%ls_as99127f.nvr", machine_name);
if (!(dev->local & LM78_I2C)) return;
lm78_log("LM78: remapping to SMBus %02Xh\n", addr);
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, lm78_i2c_start, lm78_i2c_read, lm78_i2c_write, NULL, dev);
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, lm78_i2c_start, lm78_i2c_read, lm78_i2c_write, NULL, dev);
dev->i2c_addr = addr;
if (dev->local & LM78_AS99127F) {
/* Store the main I2C address on the LM75 devices to ensure reads/writes
to the AS99127F's proprietary registers are passed through to this side. */
for (uint8_t i = 0; i <= 1; i++) {
lm75 = device_get_priv(dev->lm75[i]);
if (lm75)
lm75->as99127f_i2c_addr = dev->i2c_addr;
}
FILE *f = nvr_fopen(nvr_path, save ? L"wb": L"rb");
if (f) {
if (save)
fwrite(&dev->as99127f.nvram, sizeof(dev->as99127f.nvram), 1, f);
else
fread(&dev->as99127f.nvram, sizeof(dev->as99127f.nvram), 1, f);
fclose(f);
}
free(machine_name);
free(nvr_path);
}
static uint8_t
lm78_nvram_start(void *bus, uint8_t addr, uint8_t read, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
dev->as99127f.nvram_i2c_state = 0;
return 1;
}
static uint8_t
lm78_nvram_read(void *bus, uint8_t addr, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
uint8_t ret = 0xff;
switch (dev->as99127f.nvram_i2c_state) {
case 0:
dev->as99127f.nvram_i2c_state = 1;
/* fall-through */
case 1:
ret = dev->as99127f.regs[0][0x0b] & 0x3f;
lm78_log("LM78: nvram_read(blocklen) = %02X\n", ret);
break;
case 2:
ret = dev->as99127f.nvram[dev->as99127f.nvram_addr_register];
lm78_log("LM78: nvram_read(%03X) = %02X\n", dev->as99127f.nvram_addr_register, ret);
dev->as99127f.nvram_addr_register++;
break;
default:
lm78_log("LM78: nvram_read(unknown) = %02X\n", ret);
break;
}
if (dev->as99127f.nvram_i2c_state < 2)
dev->as99127f.nvram_i2c_state++;
return ret;
}
static uint8_t
lm78_nvram_write(void *bus, uint8_t addr, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
switch (dev->as99127f.nvram_i2c_state) {
case 0:
lm78_log("LM78: nvram_write(address, %02X)\n", val);
dev->as99127f.nvram_addr_register = (addr << 8) | val;
break;
case 1:
lm78_log("LM78: nvram_write(blocklen, %02X)\n", val);
dev->as99127f.nvram_block_len = val & 0x3f;
if (dev->as99127f.nvram_block_len <= 0)
dev->as99127f.nvram_i2c_state = 3;
break;
case 2:
lm78_log("LM78: nvram_write(%03X, %02X)\n", dev->as99127f.nvram_addr_register, val);
dev->as99127f.nvram[dev->as99127f.nvram_addr_register++] = val;
dev->as99127f.nvram_updated = 1;
if (--dev->as99127f.nvram_block_len <= 0)
dev->as99127f.nvram_i2c_state = 3;
break;
default:
lm78_log("LM78: nvram_write(unknown, %02X)\n", val);
break;
}
if (dev->as99127f.nvram_i2c_state < 2)
dev->as99127f.nvram_i2c_state++;
return dev->as99127f.nvram_i2c_state < 3;
}
static uint8_t
lm78_security_start(void *bus, uint8_t addr, uint8_t read, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
dev->as99127f.security_i2c_state = 0;
return 1;
}
static uint8_t
lm78_security_read(void *bus, uint8_t addr, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
return dev->as99127f.regs[2][dev->as99127f.security_addr_register++];
}
static uint8_t
lm78_security_write(void *bus, uint8_t addr, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
if (dev->as99127f.security_i2c_state == 0) {
dev->as99127f.security_i2c_state = 1;
dev->as99127f.security_addr_register = val;
} else {
switch (dev->as99127f.security_addr_register) {
case 0xe0: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
/* read-only registers */
return 1;
}
dev->as99127f.regs[2][dev->as99127f.security_addr_register++] = val;
}
return 1;
}
static void
lm78_reset(lm78_t *dev, uint8_t initialization)
{
memset(dev->regs, 0, 256);
memset(dev->regs + 0xc0, 0xff, 32); /* C0-DF are 0xFF on a real AS99127F */
dev->regs[0x40] = 0x08;
dev->regs[0x46] = 0x40;
dev->regs[0x47] = 0x50;
if (dev->local & LM78_I2C) {
if (!initialization) /* don't reset main I2C address if the reset was triggered by the INITIALIZATION bit */
dev->i2c_addr = 0x2d;
dev->regs[0x48] = dev->i2c_addr;
if (dev->local & LM78_WINBOND)
dev->regs[0x4a] = 0x01;
} else {
dev->regs[0x48] = 0x00;
if (dev->local & LM78_WINBOND)
dev->regs[0x4a] = 0x88;
}
if (dev->local & LM78_WINBOND) {
dev->regs[0x49] = 0x02;
dev->regs[0x4b] = 0x44;
dev->regs[0x4c] = 0x01;
dev->regs[0x4d] = 0x15;
dev->regs[0x4e] = 0x80;
dev->regs[0x4f] = LM78_WINBOND_VENDOR_ID >> 8;
dev->regs[0x57] = 0x80;
if (dev->local & LM78_AS99127F) {
dev->regs[0x49] = 0x20;
dev->regs[0x4c] = 0x00;
dev->regs[0x56] = 0xff;
dev->regs[0x57] = 0xff;
dev->regs[0x58] = 0x31;
dev->regs[0x59] = 0x8f;
dev->regs[0x5a] = 0x8f;
dev->regs[0x5b] = 0x2a;
dev->regs[0x5c] = 0xe0;
dev->regs[0x5d] = 0x48;
dev->regs[0x5e] = 0xe2;
dev->regs[0x5f] = 0x1f;
dev->as99127f.regs[0][0x02] = 0xff;
dev->as99127f.regs[0][0x03] = 0xff;
dev->as99127f.regs[0][0x08] = 0xff;
dev->as99127f.regs[0][0x09] = 0xff;
dev->as99127f.regs[0][0x0b] = 0x01;
/* regs[1] and regs[2] start at 0x80 */
dev->as99127f.regs[1][0x00] = 0x88;
dev->as99127f.regs[1][0x01] = 0x10;
dev->as99127f.regs[1][0x04] = 0x01;
dev->as99127f.regs[1][0x05] = 0x1f;
lm78_as99127f_write(dev, 0x06, 0x2f);
dev->as99127f.regs[2][0x60] = 0xf0;
} else if (dev->local & LM78_W83781D) {
dev->regs[0x58] = 0x10;
} else if (dev->local & LM78_W83782D) {
dev->regs[0x58] = 0x30;
}
} else {
dev->regs[0x49] = 0x40;
}
lm78_remap(dev, dev->i2c_addr);
}
@@ -131,6 +330,53 @@ lm78_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
}
static uint8_t
lm78_read(lm78_t *dev, uint8_t reg, uint8_t bank)
{
uint8_t ret = 0, masked_reg = reg, bankswitched = ((reg & 0xf8) == 0x50);
lm75_t *lm75;
if ((dev->local & LM78_AS99127F) && (bank == 3) && (reg != 0x4e)) {
/* AS99127F additional registers */
if (!((dev->local & LM78_AS99127F_REV2) && ((reg == 0x80) || (reg == 0x81))))
ret = dev->as99127f.regs[0][reg & 0x7f];
} else if (bankswitched && ((bank == 1) || (bank == 2))) {
/* LM75 registers */
lm75 = device_get_priv(dev->lm75[bank - 1]);
if (lm75)
ret = lm75_read(lm75, reg);
} else if (bankswitched && ((bank == 4) || (bank == 5) || (bank == 6))) {
/* W83782D additional registers */
if (dev->local & LM78_W83782D) {
if ((bank == 5) && ((reg == 0x50) || (reg == 0x51))) /* voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[7 + (reg & 1)]);
else if (bank < 6)
ret = dev->w83782d.regs[bank - 4][reg & 0x0f];
}
} else {
/* regular registers */
if ((reg >= 0x60) && (reg <= 0x94)) /* read auto-increment value RAM registers from their non-auto-increment locations */
masked_reg = reg & 0x3f;
if ((masked_reg >= 0x20) && (masked_reg <= 0x26)) /* voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[reg & 7]);
else if ((dev->local & LM78_AS99127F) && (masked_reg <= 0x05)) /* AS99127F additional voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[7 + masked_reg]);
else if (masked_reg == 0x27) /* temperature */
ret = dev->values->temperatures[0];
else if ((masked_reg >= 0x28) && (masked_reg <= 0x2a)) /* fan speeds */
ret = LM78_RPM_TO_REG(dev->values->fans[reg & 3], 1 << ((dev->regs[((reg & 3) == 2) ? 0x4b : 0x47] >> ((reg & 3) ? 6 : 4)) & 0x3));
else if ((reg == 0x4f) && (dev->local & LM78_WINBOND)) /* two-byte vendor ID register */
ret = (dev->regs[0x4e] & 0x80) ? (LM78_WINBOND_VENDOR_ID >> 8) : LM78_WINBOND_VENDOR_ID;
else
ret = dev->regs[masked_reg];
}
lm78_log("LM78: read(%02X, %d) = %02X\n", reg, bank, ret);
return ret;
}
static uint8_t
lm78_isa_read(uint16_t port, void *priv)
{
@@ -139,7 +385,7 @@ lm78_isa_read(uint16_t port, void *priv)
switch (port & 0x7) {
case 0x5:
ret = (dev->addr_register & 0x7f);
ret = dev->addr_register & 0x7f;
break;
case 0x6:
@@ -147,7 +393,7 @@ lm78_isa_read(uint16_t port, void *priv)
if (((LM78_WINBOND_BANK == 0) &&
((dev->addr_register == 0x41) || (dev->addr_register == 0x43) || (dev->addr_register == 0x45) || (dev->addr_register == 0x56) ||
((dev->addr_register >= 0x60) && (dev->addr_register < 0x7f)))) ||
((dev->addr_register >= 0x60) && (dev->addr_register < 0x94)))) ||
((dev->local & LM78_W83782D) && (LM78_WINBOND_BANK == 5) && (dev->addr_register >= 0x50) && (dev->addr_register < 0x58))) {
/* auto-increment registers */
dev->addr_register++;
@@ -172,103 +418,18 @@ lm78_i2c_read(void *bus, uint8_t addr, void *priv)
}
static uint8_t
lm78_read(lm78_t *dev, uint8_t reg, uint8_t bank)
uint8_t
lm78_as99127f_read(void *priv, uint8_t reg)
{
uint8_t ret = 0, masked_reg = reg, bankswitched = ((reg & 0xf8) == 0x50);
lm75_t *lm75;
lm78_t *dev = (lm78_t *) priv;
uint8_t ret = dev->as99127f.regs[1][reg & 0x7f];
if (bankswitched && ((bank == 1) || (bank == 2))) {
/* LM75 registers */
lm75 = device_get_priv(dev->lm75[bank - 1]);
if (lm75)
ret = lm75_read(lm75, reg);
} else if (bankswitched && ((bank == 4) || (bank == 5) || (bank == 6))) {
/* W83782D additional registers */
if (dev->local & LM78_W83782D) {
if ((bank == 5) && ((reg == 0x50) || (reg == 0x51))) /* voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[7 + (reg & 1)]);
else if (bank < 6)
ret = dev->regs_782d[bank - 4][reg & 0x0f];
}
} else {
/* regular registers */
ret = dev->regs[reg];
if (reg >= 0x40)
masked_reg = reg & 0x3f; /* match both non-auto-increment and auto-increment locations */
if ((masked_reg >= 0x20) && (masked_reg <= 0x26)) /* voltages */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[reg & 7]);
else if (masked_reg == 0x27) /* temperature */
ret = dev->values->temperatures[0];
else if ((masked_reg >= 0x28) && (masked_reg <= 0x2a)) /* fan speeds */
ret = LM78_RPM_TO_REG(dev->values->fans[reg & 3], 1 << ((dev->regs[((reg & 3) == 2) ? 0x4b : 0x47] >> ((reg & 3) ? 6 : 4)) & 0x3));
else if ((reg == 0x4f) && (dev->local & LM78_WINBOND)) /* two-byte vendor ID register */
ret = ((dev->regs[0x4e] & 0x80) ? (LM78_WINBOND_VENDOR_ID >> 8) : LM78_WINBOND_VENDOR_ID);
else if ((reg >= 0x60) && (reg <= 0x7f)) /* read auto-increment value RAM registers from their non-auto-increment locations */
ret = dev->regs[reg & 0x3f];
else if (dev->local & LM78_AS99127F) { /* AS99127F mirrored registers */
masked_reg = reg & 0x7f;
if (masked_reg == 0x00) /* IN2 Low Limit */
ret = dev->regs[0x30];
else if ((masked_reg == 0x01) || (masked_reg == 0x04)) /* IN3 */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[3]);
else if (masked_reg == 0x05) /* IN2 */
ret = LM78_VOLTAGE_TO_REG(dev->values->voltages[2]);
else if (masked_reg == 0x08) /* IN3 Low Limit */
ret = dev->regs[0x32];
else if ((reg >= 0x80) && (reg <= 0x92)) /* mirror [0x00:0x12] to [0x80:0x92] */
ret = dev->regs[masked_reg];
}
}
lm78_log("LM78: read(%02X, %d) = %02X\n", reg, bank, ret);
lm78_log("LM78: read(%02X, AS99127F) = %02X\n", reg, ret);
return ret;
}
static void
lm78_isa_write(uint16_t port, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
switch (port & 0x7) {
case 0x5:
dev->addr_register = (val & 0x7f);
break;
case 0x6:
lm78_write(dev, dev->addr_register, val, LM78_WINBOND_BANK);
if (((LM78_WINBOND_BANK == 0) &&
((dev->addr_register == 0x41) || (dev->addr_register == 0x43) || (dev->addr_register == 0x45) || (dev->addr_register == 0x56) ||
((dev->addr_register >= 0x60) && (dev->addr_register < 0x7f)))) ||
((dev->local & LM78_W83782D) && (LM78_WINBOND_BANK == 5) && (dev->addr_register >= 0x50) && (dev->addr_register < 0x58))) {
/* auto-increment registers */
dev->addr_register++;
}
break;
default:
lm78_log("LM78: Write %02X to unknown ISA port %d\n", val, port & 0x7);
break;
}
}
static uint8_t
lm78_i2c_write(void *bus, uint8_t addr, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
if (dev->i2c_state == 0) {
dev->i2c_state = 1;
dev->addr_register = val;
} else
lm78_write(dev, dev->addr_register++, val, LM78_WINBOND_BANK);
return 1;
}
static uint8_t
lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
{
@@ -276,12 +437,27 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
lm78_log("LM78: write(%02X, %d, %02X)\n", reg, bank, val);
if ((reg & 0xf8) == 0x50) {
if ((dev->local & LM78_AS99127F) && (bank == 3) && (reg != 0x4e)) {
/* AS99127F additional registers */
reg &= 0x7f;
switch (reg) {
case 0x00: case 0x01: case 0x04: case 0x05: case 0x06: case 0x07:
/* read-only registers */
return 0;
case 0x20:
val &= 0x7f;
break;
}
dev->as99127f.regs[0][reg] = val;
return 1;
} else if ((reg & 0xf8) == 0x50) {
if ((bank == 1) || (bank == 2)) {
/* LM75 registers */
lm75 = device_get_priv(dev->lm75[bank - 1]);
if (lm75)
lm75_write(lm75, reg, val);
return lm75_write(lm75, reg, val);
return 1;
} else if (dev->local & LM78_W83782D) {
/* W83782D additional registers */
@@ -293,7 +469,7 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
return 0;
}
dev->regs_782d[0][reg & 0x0f] = val;
dev->w83782d.regs[0][reg & 0x0f] = val;
return 1;
} else if (bank == 5) {
switch (reg) {
@@ -303,19 +479,21 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
return 0;
}
dev->regs_782d[1][reg & 0x0f] = val;
dev->w83782d.regs[1][reg & 0x0f] = val;
return 1;
} else if (bank == 6) {
return 0;
}
}
}
}
/* regular registers */
switch (reg) {
case 0x41: case 0x42: case 0x4f: case 0x58:
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: case 0x28: case 0x29: case 0x2a:
case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67: case 0x68: case 0x69: case 0x6a:
case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05:
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85:
/* read-only registers */
return 0;
@@ -326,12 +504,10 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
break;
}
if ((reg >= 0x60) && (reg <= 0x7f)) /* write auto-increment value RAM registers to their non-auto-increment locations */
dev->regs[reg & 0x3f] = val;
else if ((reg >= 0x80) && (reg <= 0x92)) /* AS99127F mirrors [0x00:0x12] to [0x80:0x92] */
dev->regs[reg & 0x7f] = val;
else
dev->regs[reg] = val;
if ((reg >= 0x60) && (reg <= 0x94)) /* write auto-increment value RAM registers to their non-auto-increment locations */
reg &= 0x3f;
uint8_t prev = dev->regs[reg];
dev->regs[reg] = val;
switch (reg) {
case 0x40:
@@ -363,26 +539,107 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
lm75 = device_get_priv(dev->lm75[i]);
if (!lm75)
continue;
if (dev->regs[0x4a] & (0x08 * (0x10 * i))) /* DIS_T2 and DIS_T3 bit disable those interfaces */
if (val & (0x08 * (0x10 * i))) /* DIS_T2 and DIS_T3 bit disable those interfaces */
lm75_remap(lm75, 0x80);
else
lm75_remap(lm75, 0x48 + ((dev->regs[0x4a] >> (i * 4)) & 0x7));
lm75_remap(lm75, 0x48 + ((val >> (i * 4)) & 0x7));
}
}
break;
case 0x81:
/* CUV4X-LS performs a hard reset through this register. */
if ((dev->local & LM78_AS99127F) && (val == 0xa9)) {
lm78_log("LM78: Hard reset requested through AS99127F\n");
timer_set_delay_u64(&dev->hard_reset_timer, 1); /* hard reset on a timer to avoid issues caused by invalidation of the I2C bus */
case 0x5c:
/* enable/disable AS99127F NVRAM */
if (dev->local & LM78_AS99127F) {
if (prev & 0x01)
i2c_removehandler(i2c_smbus, (prev & 0xf8) >> 1, 4, lm78_nvram_start, lm78_nvram_read, lm78_nvram_write, NULL, dev);
if (val & 0x01)
i2c_sethandler(i2c_smbus, (val & 0xf8) >> 1, 4, lm78_nvram_start, lm78_nvram_read, lm78_nvram_write, NULL, dev);
}
break;
}
return 1;
}
static void
lm78_isa_write(uint16_t port, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
switch (port & 0x7) {
case 0x5:
dev->addr_register = val & 0x7f;
break;
case 0x6:
lm78_write(dev, dev->addr_register, val, LM78_WINBOND_BANK);
if (((LM78_WINBOND_BANK == 0) &&
((dev->addr_register == 0x41) || (dev->addr_register == 0x43) || (dev->addr_register == 0x45) || (dev->addr_register == 0x56) ||
((dev->addr_register >= 0x60) && (dev->addr_register < 0x94)))) ||
((dev->local & LM78_W83782D) && (LM78_WINBOND_BANK == 5) && (dev->addr_register >= 0x50) && (dev->addr_register < 0x58))) {
/* auto-increment registers */
dev->addr_register++;
}
break;
case 0x87:
/* Other AS99127F boards perform a soft reset through this register. */
if ((dev->local & LM78_AS99127F) && (val == 0x01)) {
lm78_log("LM78: Soft reset requested through AS99127F\n");
default:
lm78_log("LM78: Write %02X to unknown ISA port %d\n", val, port & 0x7);
break;
}
}
static uint8_t
lm78_i2c_write(void *bus, uint8_t addr, uint8_t val, void *priv)
{
lm78_t *dev = (lm78_t *) priv;
if (dev->i2c_state == 0) {
dev->i2c_state = 1;
dev->addr_register = val;
} else
lm78_write(dev, dev->addr_register++, val, LM78_WINBOND_BANK);
return 1;
}
uint8_t
lm78_as99127f_write(void *priv, uint8_t reg, uint8_t val)
{
lm78_t *dev = (lm78_t *) priv;
lm78_log("LM78: write(%02X, AS99127F, %02X)\n", reg, val);
reg &= 0x7f;
uint8_t prev = dev->as99127f.regs[1][reg];
dev->as99127f.regs[1][reg] = val;
switch (reg) {
case 0x01:
if (val & 0x40) {
dev->as99127f.regs[1][0x00] = 0x88;
dev->as99127f.regs[1][0x01] &= 0xe0;
dev->as99127f.regs[1][0x03] &= 0xf7;
dev->as99127f.regs[1][0x07] &= 0xfe;
}
if (!(val & 0x10)) { /* CUV4X-LS */
lm78_log("LM78: Reset requested through AS99127F CLKRST\n");
timer_set_delay_u64(&dev->reset_timer, 300000 * TIMER_USEC);
}
break;
case 0x06:
/* security device I2C address */
i2c_removehandler(i2c_smbus, prev & 0x7f, 1, lm78_security_start, lm78_security_read, lm78_security_write, NULL, dev);
i2c_sethandler(i2c_smbus, val & 0x7f, 1, lm78_security_start, lm78_security_read, lm78_security_write, NULL, dev);
break;
case 0x07:
if (val & 0x01) { /* other AS99127F boards */
lm78_log("LM78: Reset requested through AS99127F GPO15\n");
resetx86();
}
break;
@@ -393,79 +650,34 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
static void
lm78_hard_reset_timer(void *priv)
lm78_reset_timer(void *priv)
{
pc_reset_hard();
}
static void
lm78_reset(lm78_t *dev, uint8_t initialization)
lm78_remap(lm78_t *dev, uint8_t addr)
{
memset(dev->regs, 0, 256);
memset(dev->regs + 0xc0, 0xff, 32); /* C0-DF are 0xFF at least on the AS99127F */
lm75_t *lm75;
dev->regs[0x40] = 0x08;
dev->regs[0x46] = 0x40;
dev->regs[0x47] = 0x50;
if (dev->local & LM78_I2C) {
if (!initialization) /* don't reset main I2C address if the reset was triggered by the INITIALIZATION bit */
dev->i2c_addr = 0x2d;
dev->regs[0x48] = dev->i2c_addr;
if (dev->local & LM78_WINBOND)
dev->regs[0x4a] = 0x01;
} else {
dev->regs[0x48] = 0x00;
if (dev->local & LM78_WINBOND)
dev->regs[0x4a] = 0x88;
if (!(dev->local & LM78_I2C)) return;
lm78_log("LM78: remapping to SMBus %02Xh\n", addr);
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, lm78_i2c_start, lm78_i2c_read, lm78_i2c_write, NULL, dev);
if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, lm78_i2c_start, lm78_i2c_read, lm78_i2c_write, NULL, dev);
dev->i2c_addr = addr;
if (dev->local & LM78_AS99127F) {
/* Store our handle on the primary LM75 device to ensure reads/writes
to the AS99127F's proprietary registers are passed through to this side. */
if ((lm75 = device_get_priv(dev->lm75[0])))
lm75->as99127f = dev;
}
if (dev->local & LM78_WINBOND) {
dev->regs[0x49] = 0x02;
dev->regs[0x4b] = 0x44;
dev->regs[0x4c] = 0x01;
dev->regs[0x4d] = 0x15;
dev->regs[0x4e] = 0x80;
dev->regs[0x4f] = (LM78_WINBOND_VENDOR_ID >> 8);
dev->regs[0x57] = 0x80;
/* Initialize proprietary registers on the AS99127F. The BIOS accesses some
of these on boot through read_byte_cmd on the TEMP2 address, hanging on
POST code C1 if they're defaulted to 0. There's no documentation on what
these are for. The following values were dumped from a live, initialized
AS99127F Rev. 2 on a P4B motherboard, and they seem to work well enough. */
if (dev->local & LM78_AS99127F) {
/* 0x00 appears to mirror IN2 Low Limit */
/* 0x01 appears to mirror IN3 */
dev->regs[0x02] = LM78_VOLTAGE_TO_REG(2800); /* appears to be a "maximum VCORE" of some kind; must read 2.8V on P3 boards */
dev->regs[0x03] = 0x60;
/* 0x04 appears to mirror IN3 */
/* 0x05 appears to mirror IN2 */
dev->regs[0x07] = 0xcd;
/* 0x08 appears to mirror IN3 Low Limit */
dev->regs[0x09] = dev->regs[0x0f] = dev->regs[0x11] = 0xf8; /* three instances of */
dev->regs[0x0a] = dev->regs[0x10] = dev->regs[0x12] = 0xa5; /* the same word */
dev->regs[0x0b] = 0xac;
dev->regs[0x0c] = 0x8c;
dev->regs[0x0d] = 0x68;
dev->regs[0x0e] = 0x54;
dev->regs[0x53] = dev->regs[0x54] = dev->regs[0x55] = 0xff;
dev->regs[0x58] = 0x31;
dev->regs[0x59] = dev->regs[0x5a] = 0x8f;
dev->regs[0x5c] = 0xe0;
dev->regs[0x5d] = 0x48;
dev->regs[0x5e] = 0xe2;
dev->regs[0x5f] = 0x3f;
} else if (dev->local & LM78_W83781D) {
dev->regs[0x58] = 0x10;
} else if (dev->local & LM78_W83782D) {
dev->regs[0x58] = 0x30;
}
} else {
dev->regs[0x49] = 0x40;
}
lm78_remap(dev, dev->i2c_addr);
}
@@ -478,6 +690,9 @@ lm78_close(void *priv)
if (isa_io)
io_removehandler(isa_io, 8, lm78_isa_read, NULL, NULL, lm78_isa_write, NULL, NULL, dev);
if (dev->as99127f.nvram_updated)
lm78_nvram(dev, 1);
free(dev);
}
@@ -508,17 +723,23 @@ lm78_init(const device_t *info)
RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */
LM78_NEG_VOLTAGE(12000, 2100), /* -12V */
LM78_NEG_VOLTAGE(5000, 909), /* -5V */
RESISTOR_DIVIDER(5000, 51, 75), /* W83782D only: +5VSB (5.1K/7.5K divider suggested in the datasheet) */
3000 /* W83782D only: Vbat */
RESISTOR_DIVIDER(5000, 51, 75), /* W83782D/AS99127F only: +5VSB (5.1K/7.5K divider suggested in the datasheet) */
3000, /* W83782D/AS99127F only: Vbat */
2500, /* AS99127F only: +2.5V */
1500, /* AS99127F only: +1.5V */
3000, /* AS99127F only: NVRAM */
3300 /* AS99127F only: +3.3VSB */
}
};
/* Set chip-specific default values. */
if (dev->local & LM78_AS99127F) {
/* AS99127: different -12V Rin value (bruteforced) */
/* AS99127F: different -12V Rin value (bruteforced) */
defaults.voltages[5] = LM78_NEG_VOLTAGE(12000, 2400);
timer_add(&dev->hard_reset_timer, lm78_hard_reset_timer, dev, 0);
timer_add(&dev->reset_timer, lm78_reset_timer, dev, 0);
lm78_nvram(dev, 0);
} else if (dev->local & LM78_W83782D) {
/* W83782D: different negative voltage formula */
defaults.voltages[5] = LM78_NEG_VOLTAGE2(12000, 232);
@@ -563,7 +784,7 @@ const device_t lm78_device = {
};
/* Winbond W83781D (or ASUS AS97127F) on ISA and SMBus. */
/* Winbond W83781D on ISA and SMBus. */
const device_t w83781d_device = {
"Winbond W83781D Hardware Monitor",
DEVICE_ISA,
@@ -574,8 +795,8 @@ const device_t w83781d_device = {
};
/* The ASUS AS99127F is a customized W83781D with no ISA interface (I2C
only), added proprietary registers and different chip/vendor IDs. */
/* The AS99127F is an ASIC manufactured by Holtek for ASUS, containing an
I2C-only W83781D clone with additional voltages, GPIOs and fan control. */
const device_t as99127f_device = {
"ASUS AS99127F Rev. 1 Hardware Monitor",
DEVICE_ISA,
@@ -586,7 +807,7 @@ const device_t as99127f_device = {
};
/* Rev. 2 changes the vendor ID back to Winbond's and brings some other changes. */
/* Rev. 2 is manufactured by Winbond and differs only in GPI registers. */
const device_t as99127f_rev2_device = {
"ASUS AS99127F Rev. 2 Hardware Monitor",
DEVICE_ISA,

71
src/device/keyboard_xt.c
View File

@@ -330,7 +330,8 @@ const scancode scancode_xt[512] = {
static uint8_t key_queue[16];
static int key_queue_start = 0,
key_queue_end = 0;
static int is_t1x00 = 0;
static int is_tandy = 0, is_t1x00 = 0,
is_amstrad = 0;
#ifdef ENABLE_KEYBOARD_XT_LOG
@@ -453,42 +454,36 @@ kbd_adddata_process(uint16_t val, void (*adddata)(uint16_t val))
if (!adddata)
return;
if (is_tandy) {
adddata(val);
return;
}
keyboard_get_states(NULL, &num_lock, NULL);
shift_states = keyboard_get_shift() & STATE_SHIFT_MASK;
shift_states = keyboard_get_shift() & STATE_LSHIFT;
if (is_amstrad)
num_lock = !num_lock;
/* If NumLock is on, invert the left shift state so we can always check for
the the same way flag being set (and with NumLock on that then means it
is actually *NOT* set). */
if (num_lock)
shift_states ^= STATE_LSHIFT;
switch(val) {
case FAKE_LSHIFT_ON:
if (num_lock) {
if (!shift_states) {
/* Num lock on and no shifts are pressed, send non-inverted fake shift. */
adddata(0x2a);
}
} else {
if (shift_states & STATE_LSHIFT) {
/* Num lock off and left shift pressed. */
adddata(0xaa);
}
if (shift_states & STATE_RSHIFT) {
/* Num lock off and right shift pressed. */
adddata(0xb6);
}
/* If NumLock is on, fake shifts are sent when shift is *NOT* presed,
if NumLock is off, fake shifts are sent when shift is pressed. */
if (shift_states) {
/* Send fake shift. */
adddata(num_lock ? 0x2a : 0xaa);
}
break;
case FAKE_LSHIFT_OFF:
if (num_lock) {
if (!shift_states) {
/* Num lock on and no shifts are pressed, send non-inverted fake shift. */
adddata(0xaa);
}
} else {
if (shift_states & STATE_LSHIFT) {
/* Num lock off and left shift pressed. */
adddata(0x2a);
}
if (shift_states & STATE_RSHIFT) {
/* Num lock off and right shift pressed. */
adddata(0x36);
}
if (shift_states) {
/* Send fake shift. */
adddata(num_lock ? 0xaa : 0x2a);
}
break;
default:
@@ -540,13 +535,13 @@ kbd_write(uint16_t port, uint8_t val, void *priv)
#ifdef ENABLE_KEYBOARD_XT_LOG
if (kbd->type <= 1)
kbd_log("Casette motor is %s\n", !(val & 0x08) ? "ON" : "OFF");
kbd_log("Cassette motor is %s\n", !(val & 0x08) ? "ON" : "OFF");
#endif
break;
#ifdef ENABLE_KEYBOARD_XT_LOG
case 0x62:
if (kbd->type <= 1)
kbd_log("Casette IN is %i\n", !!(val & 0x10));
kbd_log("Cassette IN is %i\n", !!(val & 0x10));
break;
#endif
}
@@ -606,10 +601,8 @@ kbd_read(uint16_t port, void *priv)
/* Olivetti M19 or Zenith Data Systems Z-151*/
if (kbd->pb & 0x04)
ret = kbd->pd & 0xbf;
//return 0x00;
else
ret = kbd->pd >> 4;
//return 0x00;
}
else {
if (kbd->pb & 0x08)
@@ -664,6 +657,13 @@ kbd_reset(void *priv)
}
void
keyboard_set_is_amstrad(int ams)
{
is_amstrad = ams;
}
static void *
kbd_init(const device_t *info)
{
@@ -802,8 +802,11 @@ kbd_init(const device_t *info)
keyboard_set_table(scancode_xt);
is_tandy = (kbd->type == 5);
is_t1x00 = (kbd->type == 6);
is_amstrad = 0;
return(kbd);
}

9
src/disk/hdc_ide_cmd640.c
View File

@@ -378,6 +378,7 @@ cmd640_init(const device_t *info)
dev->regs[0x01] = 0x10;
dev->regs[0x02] = 0x40; /* PCI-0640B */
dev->regs[0x03] = 0x06;
dev->regs[0x04] = 0x01; /* Apparently required by the ASUS PCI/I-P5SP4 AND PCI/I-P54SP4 */
dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
dev->regs[0x08] = 0x02; /* Revision 02 */
dev->regs[0x09] = info->local; /* Programming interface */
@@ -395,7 +396,7 @@ cmd640_init(const device_t *info)
dev->regs[0x3c] = 0x14; /* IRQ 14 */
dev->regs[0x3d] = 0x01; /* INTA */
device_add(&ide_vlb_2ch_device);
device_add(&ide_pci_2ch_device);
dev->slot = pci_add_card(PCI_ADD_IDE, cmd640_pci_read, cmd640_pci_write, dev);
dev->irq_mode[0] = dev->irq_mode[1] = 0;
@@ -410,7 +411,7 @@ cmd640_init(const device_t *info)
ide_board_set_force_ata3(0, 1);
ide_board_set_force_ata3(1, 1);
ide_pri_disable();
// ide_pri_disable();
} else if (info->flags & DEVICE_VLB) {
if ((info->local & 0xffff) == 0x0078)
dev->regs[0x50] |= 0x20; /* 0 = 178h, 17Ch; 1 = 078h, 07Ch */
@@ -418,9 +419,9 @@ cmd640_init(const device_t *info)
accessing the configuration registers */
dev->in_cfg = 1; /* Configuration register are accessible */
device_add(&ide_pci_2ch_device);
device_add(&ide_vlb_2ch_device);
io_sethandler(0x0078, 0x0008,
io_sethandler(info->local & 0xffff, 0x0008,
cmd640_vlb_read, cmd640_vlb_readw, cmd640_vlb_readl,
cmd640_vlb_write, cmd640_vlb_writew, cmd640_vlb_writel,
dev);

2
src/include/86box/chipset.h
View File

@@ -95,9 +95,7 @@ extern const device_t sis_85c461_device;
extern const device_t sis_85c471_device;
extern const device_t sis_85c496_device;
extern const device_t sis_85c496_ls486e_device;
#if defined(DEV_BRANCH) && defined(USE_SIS_85C50X)
extern const device_t sis_85c50x_device;
#endif
/* ST */
#if defined(DEV_BRANCH) && defined(USE_STPC)

2
src/include/86box/clock.h
View File

@@ -21,8 +21,8 @@
enum {
ICS9xxx_xx,
ICS9150_08,
#if 0
ICS9248_39,
#if 0
ICS9248_81,
ICS9248_95,
ICS9248_98,

21
src/include/86box/hwm.h
View File

@@ -25,28 +25,33 @@
typedef struct {
uint16_t fans[4];
uint8_t temperatures[4];
uint16_t voltages[10];
uint16_t voltages[13];
} hwm_values_t;
typedef struct {
uint32_t local;
uint32_t local;
hwm_values_t *values;
void *as99127f;
uint8_t regs[8];
uint8_t addr_register;
uint8_t temp_idx;
uint8_t i2c_addr, i2c_state;
uint8_t as99127f_i2c_addr;
uint8_t regs[8];
uint8_t addr_register;
uint8_t i2c_addr: 7, i2c_state: 2;
} lm75_t;
/* hwm.c */
extern uint16_t hwm_get_vcore();
/* hwm_lm75.c */
extern void lm75_remap(lm75_t *dev, uint8_t addr);
extern uint8_t lm75_read(lm75_t *dev, uint8_t reg);
extern uint8_t lm75_write(lm75_t *dev, uint8_t reg, uint8_t val);
/* hwm_lm78.c */
extern uint8_t lm78_as99127f_read(void *priv, uint8_t reg);
extern uint8_t lm78_as99127f_write(void *priv, uint8_t reg, uint8_t val);
/* hwm_vt82c686.c */
extern void vt82c686_hwm_write(uint8_t addr, uint8_t val, void *priv);

1
src/include/86box/keyboard.h
View File

@@ -103,6 +103,7 @@ extern void keyboard_set_states(uint8_t cl, uint8_t nl, uint8_t sl);
extern int keyboard_recv(uint16_t key);
extern int keyboard_isfsexit(void);
extern int keyboard_ismsexit(void);
extern void keyboard_set_is_amstrad(int ams);
extern void keyboard_at_adddata_keyboard_raw(uint8_t val);
extern void keyboard_at_adddata_mouse(uint8_t val);

11
src/include/86box/machine.h
View File

@@ -85,6 +85,7 @@
#define IS_ARCH(m, a) (machines[m].flags & (a)) ? 1 : 0;
#define IS_AT(m) ((machines[m].flags & 0x00000FC8) && !(machines[m].flags & MACHINE_PC98)) ? 1 : 0;
#define CPU_BLOCK(...) (const uint8_t[]) {__VA_ARGS__, 0}
#define MACHINE_MULTIPLIER_FIXED -1, -1
@@ -145,7 +146,7 @@ typedef struct _machine_ {
const char *internal_name;
const char type;
uint32_t cpu_package;
uint64_t cpu_block;
const uint8_t *cpu_block;
uint32_t cpu_min_bus;
uint32_t cpu_max_bus;
uint16_t cpu_min_voltage;
@@ -301,6 +302,7 @@ extern int machine_at_403tg_init(const machine_t *);
extern int machine_at_pc330_6571_init(const machine_t *);
extern int machine_at_sis401_init(const machine_t *);
extern int machine_at_av4_init(const machine_t *);
extern int machine_at_valuepoint433_init(const machine_t *);
extern int machine_at_vli486sv2g_init(const machine_t *);
@@ -354,10 +356,8 @@ extern int machine_at_excalibur_init(const machine_t *);
extern int machine_at_batman_init(const machine_t *);
extern int machine_at_ambradp60_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_DELLS4)
extern int machine_at_dellxp60_init(const machine_t *);
extern int machine_at_opti560l_init(const machine_t *);
#endif
extern int machine_at_valuepointp60_init(const machine_t *);
extern int machine_at_p5mp3_init(const machine_t *);
extern int machine_at_pb520r_init(const machine_t *);
@@ -376,6 +376,10 @@ extern int machine_at_vectra54_init(const machine_t *);
extern int machine_at_powermate_v_init(const machine_t *);
extern int machine_at_acerv30_init(const machine_t *);
extern int machine_at_p5sp4_init(const machine_t *);
extern int machine_at_p54sp4_init(const machine_t *);
extern int machine_at_sq588_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_endeavor_get_device(void);
#define at_vectra54_get_device at_endeavor_get_device
@@ -469,6 +473,7 @@ extern int machine_at_p6sba_init(const machine_t *);
extern int machine_at_ergox365_init(const machine_t *);
#endif
extern int machine_at_ficka6130_init(const machine_t *);
extern int machine_at_p3v133_init(const machine_t *);
extern int machine_at_p3v4x_init(const machine_t *);
#ifdef EMU_DEVICE_H

1
src/include/86box/sio.h
View File

@@ -23,6 +23,7 @@ extern const device_t f82c710_device;
extern const device_t fdc37c661_device;
extern const device_t fdc37c663_device;
extern const device_t fdc37c665_device;
extern const device_t fdc37c665_ide_device;
extern const device_t fdc37c666_device;
extern const device_t fdc37c669_device;
extern const device_t fdc37c669_370_device;

1
src/include/86box/vid_svga.h
View File

@@ -22,6 +22,7 @@
#define FLAG_ADDR_BY8 2
#define FLAG_EXT_WRITE 4
#define FLAG_LATCH8 8
#define FLAG_NOSKEW 16
typedef struct {

12
src/include/86box/vid_voodoo_codegen_x86-64.h
View File

@@ -9,13 +9,17 @@
#include <sys/mman.h>
#include <unistd.h>
#endif
#if WIN64
#if _WIN64
#define BITMAP windows_BITMAP
#include <windows.h>
#undef BITMAP
#endif
#ifdef _MSC_VER
#include <intrin.h>
#else
#include <xmmintrin.h>
#endif
#define BLOCK_NUM 8
#define BLOCK_MASK (BLOCK_NUM-1)
@@ -752,7 +756,7 @@ static inline void voodoo_generate(uint8_t *code_block, voodoo_t *voodoo, voodoo
addbyte(0x6f);
addbyte(0x07 | (3 << 3));
#if WIN64
#if _WIN64
addbyte(0x48); /*MOV RDI, RCX (voodoo_state)*/
addbyte(0x89);
addbyte(0xcf);
@@ -3428,7 +3432,7 @@ void voodoo_codegen_init(voodoo_t *voodoo)
{
int c;
#if WIN64
#if _WIN64
voodoo->codegen_data = VirtualAlloc(NULL, sizeof(voodoo_x86_data_t) * BLOCK_NUM * 4, MEM_COMMIT, PAGE_EXECUTE_READWRITE);
#else
voodoo->codegen_data = mmap(0, sizeof(voodoo_x86_data_t) * BLOCK_NUM*4, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_ANON|MAP_PRIVATE, 0, 0);
@@ -3458,7 +3462,7 @@ void voodoo_codegen_init(voodoo_t *voodoo)
void voodoo_codegen_close(voodoo_t *voodoo)
{
#if WIN64
#if _WIN64
VirtualFree(voodoo->codegen_data, 0, MEM_RELEASE);
#else
munmap(voodoo->codegen_data, sizeof(voodoo_x86_data_t) * BLOCK_NUM*4);

4
src/include/86box/vid_voodoo_codegen_x86.h
View File

@@ -15,7 +15,11 @@
#undef BITMAP
#endif
#ifdef _MSC_VER
#include <intrin.h>
#else
#include <xmmintrin.h>
#endif
#define BLOCK_NUM 8
#define BLOCK_MASK (BLOCK_NUM-1)

2
src/include/86box/vid_voodoo_render.h
View File

@@ -1,4 +1,4 @@
#if !(defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined WIN32 || defined _WIN32 || defined _WIN32) && !(defined __amd64__)
#if !(defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64)
#define NO_CODEGEN
#endif

11
src/include/slirp/libslirp.h
View File

@@ -16,6 +16,17 @@
#include "libslirp-version.h"
/* Windows does not define ssize_t, so we need to define it here. */
#ifndef _SSIZE_T_DEFINED
# define _SSIZE_T_DEFINED
# undef ssize_t
# ifdef _WIN64
# define ssize_t int64_t
# else
# define ssize_t int32_t
# endif
#endif
#ifdef __cplusplus
extern "C" {
#endif

24
src/include/tinyglib.h
View File

@@ -58,16 +58,17 @@
#define G_SPAWN_SEARCH_PATH 0
#if defined(__LP64__) || defined(__LLP64__)
#if defined(__LP64__) || defined(__LLP64__) || defined(_WIN64)
# define GLIB_SIZEOF_VOID_P 8
#else
# define GLIB_SIZEOF_VOID_P 4
#endif
#ifdef __LP64__
# define GLIB_SIZEOF_LONG 8
# if defined(__LLP64__) || defined(_WIN64)
# define GLIB_SIZEOF_LONG 4
# else
# define GLIB_SIZEOF_LONG 8
# endif
# define GLIB_SIZEOF_SIZE_T 8
# define GLIB_SIZEOF_SSIZE_T 8
#else
# define GLIB_SIZEOF_VOID_P 4
# define GLIB_SIZEOF_LONG 4
# define GLIB_SIZEOF_SIZE_T 4
# define GLIB_SIZEOF_SSIZE_T 4
@@ -76,6 +77,17 @@
/* Types */
/* Windows does not define ssize_t, so we need to define it here. */
#ifndef _SSIZE_T_DEFINED
# define _SSIZE_T_DEFINED
# undef ssize_t
# ifdef _WIN64
# define ssize_t int64_t
# else
# define ssize_t int32_t
# endif
#endif
#define gboolean int
#define gchar char
#define gint int

13
src/machine/m_amstrad.c
View File

@@ -1715,8 +1715,13 @@ vid_close_200(void *priv)
{
amsvid_t *vid = (amsvid_t *)priv;
free(vid->cga.vram);
free(vid->mda.vram);
if (vid->cga.vram != vid->mda.vram) {
free(vid->cga.vram);
free(vid->mda.vram);
} else
free(vid->cga.vram);
vid->cga.vram = vid->mda.vram = NULL;
free(vid);
}
@@ -2111,8 +2116,7 @@ kbd_adddata(uint16_t val)
static void
kbd_adddata_ex(uint16_t val)
{
kbd_adddata(val);
// kbd_adddata_process(val, kbd_adddata);
kbd_adddata_process(val, kbd_adddata);
}
@@ -2495,6 +2499,7 @@ machine_amstrad_init(const machine_t *model, int type)
keyboard_set_table(scancode_xt);
keyboard_send = kbd_adddata_ex;
keyboard_scan = 1;
keyboard_set_is_amstrad(((type == AMS_PC1512) || (type == AMS_PC1640)) ? 0 : 1);
io_sethandler(0x0078, 2,
ms_read, NULL, NULL, ms_write, NULL, NULL, ams);

22
src/machine/m_at_386dx_486.c
View File

@@ -102,6 +102,27 @@ machine_at_sis401_init(const machine_t *model)
return ret;
}
int
machine_at_av4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/av4/amibios_486dx_isa_bios_aa4025963.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&sis_85c460_device);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
return ret;
}
int
machine_at_valuepoint433_init(const machine_t *model) // hangs without the PS/2 mouse
{
@@ -121,6 +142,7 @@ machine_at_valuepoint433_init(const machine_t *model) // hangs without the PS/2
return ret;
}
int
machine_at_ecs386_init(const machine_t *model)
{

38
src/machine/m_at_slot1.c
View File

@@ -550,6 +550,44 @@ machine_at_ficka6130_init(const machine_t *model)
}
int
machine_at_p3v133_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p3v133/1003.002",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro133_device);
device_add(&via_vt82c596b_device);
device_add(&w83977ef_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(ics9xxx_get(ICS9248_39));
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
device_add(&w83781d_device); /* fans: Chassis, CPU, Power; temperatures: MB, unused, CPU */
hwm_values.temperatures[1] = 0; /* unused */
hwm_values.temperatures[2] -= 3; /* CPU offset */
return ret;
}
int
machine_at_p3v4x_init(const machine_t *model)
{

92
src/machine/m_at_socket4_5.c
View File

@@ -122,7 +122,6 @@ machine_at_batman_init(const machine_t *model)
}
#if defined(DEV_BRANCH) && defined(USE_DELLS4)
int
machine_at_dellxp60_init(const machine_t *model)
{
@@ -184,7 +183,6 @@ machine_at_opti560l_init(const machine_t *model)
return ret;
}
#endif
int
@@ -646,3 +644,93 @@ machine_at_acerv30_init(const machine_t *model)
return ret;
}
static void
machine_at_sp4_common_init(const machine_t *model)
{
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
/* Excluded: 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14 */
pci_register_slot(0x0D, PCI_CARD_IDE, 1, 2, 3, 4);
/* Excluded: 02, 03*, 04*, 05*, 06*, 07*, 08* */
/* Slots: 09 (04), 0A (03), 0B (02), 0C (07) */
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_85c50x_device);
device_add(&ide_cmd640_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
int
machine_at_p5sp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p5sp4/0106.001",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_sp4_common_init(model);
return ret;
}
int
machine_at_p54sp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p54sp4/SI5I0204.AWD",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_sp4_common_init(model);
return ret;
}
int
machine_at_sq588_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/sq588/sq588b03.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
/* Correct: 0D (01), 0F (02), 11 (03), 13 (04) */
pci_register_slot(0x02, PCI_CARD_IDE, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_85c50x_device);
device_add(&ide_cmd640_pci_single_channel_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_ide_device);
device_add(&sst_flash_29ee010_device);
return ret;
}

8
src/machine/m_tandy.c
View File

@@ -298,11 +298,11 @@ static const scancode scancode_tandy[512] = {
{ {0}, {0} }, { {0}, {0} }, /*140*/
{ {0}, {0} }, { {0}, {0} },
{ {0x46, 0}, {0xc6, 0} }, { {0x47, 0}, {0xc7, 0} }, /*144*/
{ {0x48, 0}, {0xc8, 0} }, { {0x49, 0}, {0xc9, 0} },
{ {0}, {0} }, { {0x4b, 0}, {0xcb, 0} }, /*148*/
{ {0}, {0} }, { {0x4d, 0}, {0xcd, 0} },
{ {0x29, 0}, {0xa9, 0} }, { {0x49, 0}, {0xc9, 0} },
{ {0}, {0} }, { {0x2b, 0}, {0xab, 0} }, /*148*/
{ {0}, {0} }, { {0x4e, 0}, {0xce, 0} },
{ {0}, {0} }, { {0x4f, 0}, {0xcf, 0} }, /*14c*/
{ {0x50, 0}, {0xd0, 0} }, { {0x51, 0}, {0xd1, 0} },
{ {0x4a, 0}, {0xca, 0} }, { {0x51, 0}, {0xd1, 0} },
{ {0x52, 0}, {0xd2, 0} }, { {0x53, 0}, {0xd3, 0} }, /*150*/
{ {0}, {0} }, { {0}, {0} },
{ {0}, {0} }, { {0}, {0} }, /*154*/

287
src/machine/m_xt_olivetti.c
View File

@@ -118,6 +118,7 @@ m24_log(const char *fmt, ...)
#define m24_log(fmt, ...)
#endif
static void
m24_kbd_poll(void *priv)
{
@@ -171,9 +172,8 @@ m24_kbd_write(uint16_t port, uint8_t val, void *priv)
#endif
#if 0
if (ram[8] == 0xc3) {
if (ram[8] == 0xc3)
output = 3;
}
#endif
switch (port) {
case 0x60:
@@ -242,6 +242,7 @@ m24_kbd_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
m24_kbd_read(uint16_t port, void *priv)
{
@@ -279,11 +280,13 @@ m24_kbd_read(uint16_t port, void *priv)
return(ret);
}
static void
m24_kbd_close(void *priv)
{
olim24_kbd_t *kbd = (olim24_kbd_t *)priv;
/* Stop the timer. */
olim24_kbd_t *kbd = (olim24_kbd_t *)priv;
/* Stop the timer. */
timer_disable(&kbd->send_delay_timer);
/* Disable scanning. */
@@ -293,12 +296,13 @@ m24_kbd_close(void *priv)
io_removehandler(0x0060, 2,
m24_kbd_read, NULL, NULL, m24_kbd_write, NULL, NULL, kbd);
io_removehandler(0x0064, 1,
io_removehandler(0x0064, 1,
m24_kbd_read, NULL, NULL, m24_kbd_write, NULL, NULL, kbd);
free(kbd);
}
static void
m24_kbd_reset(void *priv)
{
@@ -319,6 +323,7 @@ m24_kbd_reset(void *priv)
m24_kbd->scan[6] = 0x50;
}
static int
ms_poll(int x, int y, int z, int b, void *priv)
{
@@ -401,10 +406,12 @@ ms_poll(int x, int y, int z, int b, void *priv)
return(0);
}
static void
m24_kbd_init(olim24_kbd_t *kbd){
m24_kbd_init(olim24_kbd_t *kbd)
{
/* Initialize the keyboard. */
/* Initialize the keyboard. */
io_sethandler(0x0060, 2,
m24_kbd_read, NULL, NULL, m24_kbd_write, NULL, NULL, kbd);
io_sethandler(0x0064, 1,
@@ -418,152 +425,160 @@ m24_kbd_init(olim24_kbd_t *kbd){
mouse_set_poll(ms_poll, kbd);
keyboard_set_table(scancode_xt);
keyboard_set_is_amstrad(0);
}
static void
m19_vid_out(uint16_t addr, uint8_t val, void *priv)
{
olim19_vid_t *vid = (olim19_vid_t *)priv;
int oldmode = vid->mode;
/* activating plantronics mode */
if (addr == 0x3dd){
/* already in graphics mode */
if ((val & 0x30) && (vid->ogc.cga.cgamode & 0x2)) {
vid->mode = PLANTRONICS_MODE;
} else {
vid->mode = OLIVETTI_OGC_MODE;
}
/* setting graphics mode */
} else if (addr == 0x3d8) {
if ((val & 0x2) && (vid->colorplus.control & 0x30)){
vid->mode = PLANTRONICS_MODE;
} else {
vid->mode = OLIVETTI_OGC_MODE;
}
olim19_vid_t *vid = (olim19_vid_t *)priv;
int oldmode = vid->mode;
/* activating plantronics mode */
if (addr == 0x3dd) {
/* already in graphics mode */
if ((val & 0x30) && (vid->ogc.cga.cgamode & 0x2))
vid->mode = PLANTRONICS_MODE;
else
vid->mode = OLIVETTI_OGC_MODE;
/* setting graphics mode */
} else if (addr == 0x3d8) {
if ((val & 0x2) && (vid->colorplus.control & 0x30))
vid->mode = PLANTRONICS_MODE;
else
vid->mode = OLIVETTI_OGC_MODE;
}
/* video mode changed */
if (oldmode != vid->mode) {
/* activate Plantronics emulation */
if (vid->mode == PLANTRONICS_MODE){
timer_disable(&vid->ogc.cga.timer);
timer_set_delay_u64(&vid->colorplus.cga.timer, 0);
/* return to OGC mode */
} else {
timer_disable(&vid->colorplus.cga.timer);
timer_set_delay_u64(&vid->ogc.cga.timer, 0);
}
/* video mode changed */
if(oldmode != vid->mode){
/* activate Plantronics emulation */
if (vid->mode == PLANTRONICS_MODE){
timer_disable(&vid->ogc.cga.timer);
timer_set_delay_u64(&vid->colorplus.cga.timer, 0);
/* return to OGC mode */
} else {
timer_disable(&vid->colorplus.cga.timer);
timer_set_delay_u64(&vid->ogc.cga.timer, 0);
}
colorplus_recalctimings(&vid->colorplus);
ogc_recalctimings(&vid->ogc);
}
colorplus_out(addr, val, &vid->colorplus);
ogc_out(addr, val, &vid->ogc);
colorplus_recalctimings(&vid->colorplus);
ogc_recalctimings(&vid->ogc);
}
colorplus_out(addr, val, &vid->colorplus);
ogc_out(addr, val, &vid->ogc);
}
static uint8_t
m19_vid_in(uint16_t addr, void *priv)
{
olim19_vid_t *vid = (olim19_vid_t *)priv;
if ( vid->mode == PLANTRONICS_MODE ) {
return colorplus_in(addr, &vid->colorplus);
} else {
return ogc_in(addr, &vid->ogc);
olim19_vid_t *vid = (olim19_vid_t *)priv;
if (vid->mode == PLANTRONICS_MODE)
return colorplus_in(addr, &vid->colorplus);
else
return ogc_in(addr, &vid->ogc);
}
}
static uint8_t
m19_vid_read(uint32_t addr, void *priv)
{
olim19_vid_t *vid = (olim19_vid_t *)priv;
vid->colorplus.cga.mapping = vid->ogc.cga.mapping;
if ( vid->mode == PLANTRONICS_MODE ) {
return colorplus_read(addr, &vid->colorplus);
} else {
return ogc_read(addr, &vid->ogc);
}
olim19_vid_t *vid = (olim19_vid_t *)priv;
vid->colorplus.cga.mapping = vid->ogc.cga.mapping;
if (vid->mode == PLANTRONICS_MODE)
return colorplus_read(addr, &vid->colorplus);
else
return ogc_read(addr, &vid->ogc);
}
static void
m19_vid_write(uint32_t addr, uint8_t val, void *priv)
{
olim19_vid_t *vid = (olim19_vid_t *)priv;
colorplus_write(addr, val, &vid->colorplus);
ogc_write(addr, val, &vid->ogc);
olim19_vid_t *vid = (olim19_vid_t *)priv;
colorplus_write(addr, val, &vid->colorplus);
ogc_write(addr, val, &vid->ogc);
}
static void
m19_vid_close(void *priv)
{
olim19_vid_t *vid = (olim19_vid_t *)priv;
free(vid->ogc.cga.vram);
olim19_vid_t *vid = (olim19_vid_t *)priv;
free(vid->ogc.cga.vram);
free(vid->colorplus.cga.vram);
free(vid);
free(vid);
}
static void
m19_vid_speed_changed(void *priv)
{
olim19_vid_t *vid = (olim19_vid_t *)priv;
colorplus_recalctimings(&vid->colorplus);
ogc_recalctimings(&vid->ogc);
olim19_vid_t *vid = (olim19_vid_t *)priv;
colorplus_recalctimings(&vid->colorplus);
ogc_recalctimings(&vid->ogc);
}
static void
m19_vid_init(olim19_vid_t *vid){
m19_vid_init(olim19_vid_t *vid)
{
/* int display_type; */
vid->mode = OLIVETTI_OGC_MODE;
//int display_type;
vid->mode = OLIVETTI_OGC_MODE;
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_m19_vid);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_m19_vid);
/* display_type = device_get_config_int("display_type"); */
//display_type = device_get_config_int("display_type");
/* OGC emulation part begin */
loadfont_ex(L"roms/machines/olivetti_m19/BIOS.BIN", 1, 90);
/* composite is not working yet */
vid->ogc.cga.composite = 0; // (display_type != CGA_RGB);
//vid->ogc.cga.snow_enabled = device_get_config_int("snow_enabled");
vid->ogc.cga.vram = malloc(0x8000);
/* OGC emulation part begin */
loadfont_ex(L"roms/machines/olivetti_m19/BIOS.BIN", 1, 90);
/* composite is not working yet */
vid->ogc.cga.composite = 0; // (display_type != CGA_RGB);
/* vid->ogc.cga.snow_enabled = device_get_config_int("snow_enabled"); */
//cga_comp_init(vid->ogc.cga.revision);
//vid->ogc.cga.rgb_type = device_get_config_int("rgb_type");
//cga_palette = (vid->ogc.cga.rgb_type << 1);
vid->ogc.cga.vram = malloc(0x8000);
/* cga_comp_init(vid->ogc.cga.revision); */
/* vid->ogc.cga.rgb_type = device_get_config_int("rgb_type"); */
/* cga_palette = (vid->ogc.cga.rgb_type << 1); */
cga_palette = 0;
cgapal_rebuild();
ogc_mdaattr_rebuild();
cgapal_rebuild();
ogc_mdaattr_rebuild();
/* color display */
// if (device_get_config_int("rgb_type")==0 || device_get_config_int("rgb_type") == 4)
vid->ogc.mono_display = 1;
// else
// vid->ogc.mono_display = 1;
/* OGC emulation part end */
/* Plantronics emulation part begin*/
/* composite is not working yet */
vid->colorplus.cga.composite = 0; //(display_type != CGA_RGB);
// vid->colorplus.cga.snow_enabled = device_get_config_int("snow_enabled");
/* color display */
/* if (device_get_config_int("rgb_type")==0 || device_get_config_int("rgb_type") == 4) */
vid->ogc.mono_display = 1;
/* else */
/* vid->ogc.mono_display = 1; */
/* OGC emulation part end */
/* Plantronics emulation part begin*/
/* composite is not working yet */
vid->colorplus.cga.composite = 0; //(display_type != CGA_RGB);
/* vid->colorplus.cga.snow_enabled = device_get_config_int("snow_enabled"); */
vid->colorplus.cga.vram = malloc(0x8000);
//vid->colorplus.cga.cgamode = 0x1;
/* Plantronics emulation part end*/
timer_add(&vid->ogc.cga.timer, ogc_poll, &vid->ogc, 1);
timer_add(&vid->colorplus.cga.timer, colorplus_poll, &vid->colorplus, 1);
timer_disable(&vid->colorplus.cga.timer);
mem_mapping_add(&vid->ogc.cga.mapping, 0xb8000, 0x08000, m19_vid_read, NULL, NULL, m19_vid_write, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, vid);
io_sethandler(0x03d0, 0x0010, m19_vid_in, NULL, NULL, m19_vid_out, NULL, NULL, vid);
vid->mode = OLIVETTI_OGC_MODE;
/* vid->colorplus.cga.cgamode = 0x1; */
/* Plantronics emulation part end*/
timer_add(&vid->ogc.cga.timer, ogc_poll, &vid->ogc, 1);
timer_add(&vid->colorplus.cga.timer, colorplus_poll, &vid->colorplus, 1);
timer_disable(&vid->colorplus.cga.timer);
mem_mapping_add(&vid->ogc.cga.mapping, 0xb8000, 0x08000, m19_vid_read, NULL, NULL, m19_vid_write, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, vid);
io_sethandler(0x03d0, 0x0010, m19_vid_in, NULL, NULL, m19_vid_out, NULL, NULL, vid);
vid->mode = OLIVETTI_OGC_MODE;
}
const device_t m24_kbd_device = {
"Olivetti M24 keyboard and mouse",
0,
@@ -590,11 +605,13 @@ m19_get_device(void)
return &m19_vid_device;
}
static uint8_t
m24_read(uint16_t port, void *priv)
{
uint8_t ret = 0x00;
int i, fdd_count = 0;
uint8_t ret = 0x00;
int i, fdd_count = 0;
switch (port) {
/*
* port 66:
@@ -610,7 +627,7 @@ m24_read(uint16_t port, void *priv)
/* Switch 5 - 8087 present */
if (hasfpu)
ret |= 0x10;
/*
/*
* Switches 1, 2, 3, 4 - installed memory
* Switch 8 - Use memory bank 1
*/
@@ -650,10 +667,9 @@ m24_read(uint16_t port, void *priv)
*/
case 0x67:
for (i = 0; i < FDD_NUM; i++) {
if (fdd_get_flags(i)) {
if (fdd_get_flags(i))
fdd_count++;
}
}
/* Switches 7, 8 - floppy drives. */
if (!fdd_count)
@@ -674,17 +690,19 @@ m24_read(uint16_t port, void *priv)
/* Switch 2 - Set fast startup */
ret |= 0x2;
}
}
return(ret);
}
const device_t *
m24_get_device(void)
{
return &ogc_m24_device;
}
int
machine_xt_olim24_init(const machine_t *model)
{
@@ -708,22 +726,21 @@ machine_xt_olim24_init(const machine_t *model)
machine_common_init(model);
device_add(&fdc_xt_device);
//address 66-67 = mainboard dip-switch settings
io_sethandler(0x0066, 2, m24_read, NULL, NULL, NULL, NULL, NULL, NULL);
/* Address 66-67 = mainboard dip-switch settings */
io_sethandler(0x0066, 2, m24_read, NULL, NULL, NULL, NULL, NULL, NULL);
m24_kbd_init(m24_kbd);
device_add_ex(&m24_kbd_device, m24_kbd);
m24_kbd_init(m24_kbd);
device_add_ex(&m24_kbd_device, m24_kbd);
/* FIXME: make sure this is correct?? */
/* FIXME: make sure this is correct?? */
device_add(&at_nvr_device);
if (joystick_type)
device_add(&gameport_device);
device_add(&gameport_device);
nmi_init();
return ret;
return ret;
}
/*
@@ -746,10 +763,10 @@ machine_xt_olim240_init(const machine_t *model)
pit_ctr_set_out_func(&pit->counters[1], pit_refresh_timer_xt);
/*
* port 60: should return jumper settings only under unknown conditions
* SWB on mainboard (off=1)
* bit 7 - use BIOS HD on mainboard (on) / on controller (off)
/*
* port 60: should return jumper settings only under unknown conditions
* SWB on mainboard (off=1)
* bit 7 - use BIOS HD on mainboard (on) / on controller (off)
* bit 6 - use OCG/CGA display adapter (on) / other display adapter (off)
*/
device_add(&keyboard_at_olivetti_device);
@@ -757,11 +774,11 @@ machine_xt_olim240_init(const machine_t *model)
/* FIXME: make sure this is correct?? */
device_add(&at_nvr_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_xt_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_xt_device);
if (joystick_type)
device_add(&gameport_device);
if (joystick_type)
device_add(&gameport_device);
nmi_init();
@@ -787,19 +804,19 @@ machine_xt_olim19_init(const machine_t *model)
olim19_vid_t *vid;
/* do not move memory allocation elsewhere */
vid = (olim19_vid_t *)malloc(sizeof(olim19_vid_t));
memset(vid, 0x00, sizeof(olim19_vid_t));
/* Do not move memory allocation elsewhere. */
vid = (olim19_vid_t *)malloc(sizeof(olim19_vid_t));
memset(vid, 0x00, sizeof(olim19_vid_t));
machine_common_init(model);
device_add(&fdc_xt_device);
m19_vid_init(vid);
device_add_ex(&m19_vid_device, vid);
m19_vid_init(vid);
device_add_ex(&m19_vid_device, vid);
device_add(&keyboard_xt_olivetti_device);
nmi_init();
device_add(&keyboard_xt_olivetti_device);
nmi_init();
return ret;

83
src/machine/machine_table.c
View File

@@ -34,23 +34,23 @@
const machine_type_t machine_types[] = {
{ "None", MACHINE_TYPE_NONE },
{ "8088", MACHINE_TYPE_8088 },
{ "8086", MACHINE_TYPE_8086 },
{ "80286", MACHINE_TYPE_286 },
{ "i386SX", MACHINE_TYPE_386SX },
{ "i386DX", MACHINE_TYPE_386DX },
{ "i486", MACHINE_TYPE_486 },
{ "Socket 4", MACHINE_TYPE_SOCKET4 },
{ "Socket 5", MACHINE_TYPE_SOCKET5 },
{ "Socket 7-3V", MACHINE_TYPE_SOCKET7_3V },
{ "Socket 7", MACHINE_TYPE_SOCKET7 },
{ "Super Socket 7", MACHINE_TYPE_SOCKETS7 },
{ "Socket 8", MACHINE_TYPE_SOCKET8 },
{ "Slot 1", MACHINE_TYPE_SLOT1 },
{ "Slot 2", MACHINE_TYPE_SLOT2 },
{ "Socket 370", MACHINE_TYPE_SOCKET370 },
{ "Miscellaneous", MACHINE_TYPE_MISC }
{ "None", MACHINE_TYPE_NONE },
{ "8088", MACHINE_TYPE_8088 },
{ "8086", MACHINE_TYPE_8086 },
{ "80286", MACHINE_TYPE_286 },
{ "i386SX", MACHINE_TYPE_386SX },
{ "i386DX", MACHINE_TYPE_386DX },
{ "i486", MACHINE_TYPE_486 },
{ "Socket 4", MACHINE_TYPE_SOCKET4 },
{ "Socket 5", MACHINE_TYPE_SOCKET5 },
{ "Socket 7 (Single Voltage)", MACHINE_TYPE_SOCKET7_3V },
{ "Socket 7 (Dual Voltage)", MACHINE_TYPE_SOCKET7 },
{ "Super Socket 7", MACHINE_TYPE_SOCKETS7 },
{ "Socket 8", MACHINE_TYPE_SOCKET8 },
{ "Slot 1", MACHINE_TYPE_SLOT1 },
{ "Slot 2", MACHINE_TYPE_SLOT2 },
{ "Socket 370", MACHINE_TYPE_SOCKET370 },
{ "Miscellaneous", MACHINE_TYPE_MISC }
};
@@ -95,8 +95,8 @@ const machine_t machines[] = {
{ "[8086] Amstrad PC3086", "pc3086", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO_FIXED | MACHINE_MOUSE, 640, 640, 640, 63, machine_pc3086_init, pc3086_get_device },
{ "[8086] Amstrad PC20(0)", "pc200", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_pc200_init, pc200_get_device },
{ "[8086] Amstrad PPC512/640", "ppc512", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_NONMI, 512, 640, 128, 63, machine_ppc512_init, ppc512_get_device },
{ "[8086] Compaq Deskpro", "deskpro", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_compaq_deskpro_init, NULL },
{ "[8086] Olivetti M21/24/24SP", "olivetti_m24", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_xt_olim24_init, m24_get_device },
{ "[8086] Compaq Deskpro", "deskpro", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_compaq_deskpro_init, NULL },
{ "[8086] Olivetti M21/24/24SP", "olivetti_m24", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_xt_olim24_init, m24_get_device },
{ "[8086] Olivetti M240", "olivetti_m240", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_olim240_init, NULL },
{ "[8086] Schetmash Iskra-3104", "iskra3104", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC, 128, 640, 128, 0, machine_xt_iskra3104_init, NULL },
{ "[8086] Tandy 1000 SL/2", "tandy1000sl2", MACHINE_TYPE_8086, CPU_PKG_8086, 0, 0, 0, 0, 0, 0, 0, MACHINE_PC | MACHINE_VIDEO_FIXED, 512, 768, 128, 0, machine_tandy1000sl2_init, tandy1k_sl_get_device },
@@ -194,6 +194,7 @@ const machine_t machines[] = {
{ "[OPTi 802G] IBM PC 330 (type 6571)", "pc330_6571", MACHINE_TYPE_486, CPU_PKG_SOCKET3_PC330, 0, 25000000, 33333333, 0, 0, 2.0, 3.0, MACHINE_VLB | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_pc330_6571_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB, 1024, 65536, 1024, 127, machine_at_403tg_init, NULL },
{ "[SiS 401] AMI 486 Clone", "sis401", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_sis401_init, NULL },
{ "[SiS 460] ABIT AV4", "av4", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_av4_init, NULL },
{ "[SiS 461] IBM PS/ValuePoint 433DX/Si", "valuepoint433", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_valuepoint433_init, NULL },
{ "[SiS 471] AMI 486 Clone", "ami471", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_ami471_init, NULL },
{ "[SiS 471] AMI WinBIOS 486 clone", "win471", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_win471_init, NULL },
@@ -236,19 +237,20 @@ const machine_t machines[] = {
/* Socket 4 machines */
/* 430LX */
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 196608, 2048, 127, machine_at_p5mp3_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_DELLS4)
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 131072, 2048, 127, machine_at_dellxp60_init, NULL },
{ "[i430LX] Dell OptiPlex 560/L", "opti560l", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_opti560l_init, NULL },
#endif
{ "[i430LX] IBM Ambra DP60 PCI", "ambradp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_ambradp60_init, NULL },
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_valuepointp60_init, NULL },
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_batman_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_586mc1_init, NULL },
{ "[i430LX] Packard Bell PB520R", "pb520r", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 139264, 2048, 127, machine_at_pb520r_init, at_pb520r_get_device },
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 196608, 2048, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 131072, 2048, 127, machine_at_dellxp60_init, NULL },
{ "[i430LX] Dell OptiPlex 560/L", "opti560l", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_opti560l_init, NULL },
{ "[i430LX] IBM Ambra DP60 PCI", "ambradp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_ambradp60_init, NULL },
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_valuepointp60_init, NULL },
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_batman_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_586mc1_init, NULL },
{ "[i430LX] Packard Bell PB520R", "pb520r", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 139264, 2048, 127, machine_at_pb520r_init, at_pb520r_get_device },
/* OPTi 596/597 */
{ "[OPTi 597] AMI Excalibur VLB", "excalibur", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 0, 0, MACHINE_MULTIPLIER_FIXED, MACHINE_VLB | MACHINE_IDE, 2048, 65536, 2048, 127, machine_at_excalibur_init, NULL },
{ "[OPTi 597] AMI Excalibur VLB", "excalibur", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_VLB | MACHINE_IDE, 2048, 65536, 2048, 127, machine_at_excalibur_init, NULL },
/* SiS 85C50x */
{ "[SiS 85C50x] ASUS PCI/I-P5SP4", "p5sp4", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p5sp4_init, NULL },
/* Socket 5 machines */
/* 430NX */
@@ -264,7 +266,11 @@ const machine_t machines[] = {
{ "[i430FX] NEC PowerMate V", "powermate_v", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_powermate_v_init, NULL },
{ "[i430FX] PC Partner MB500N", "mb500n", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mb500n_init, NULL },
/* Socket 7 machines */
/* SiS 85C50x */
{ "[SiS 85C50x] ASUS PCI/I-P54SP4", "p54sp4", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_K5, CPU_5K86), 40000000, 66666667, 3380, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54sp4_init, NULL },
{ "[SiS 85C50x] BCM SQ-588", "sq588", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_PENTIUMMMX), 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_sq588_init, NULL },
/* Socket 7 (Single Voltage) machines */
/* 430FX */
{ "[i430FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3600, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54tp4xe_init, NULL },
{ "[i430FX] ASUS P/I-P54TP4XE (MR BIOS)", "mr586", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3600, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mr586_init, NULL },
@@ -273,7 +279,7 @@ const machine_t machines[] = {
{ "[i430FX] Intel Advanced/ATX (MR BIOS)", "mrthor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_mrthor_init, NULL },
{ "[i430FX] Intel Advanced/EV", "endeavor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_endeavor_init, at_endeavor_get_device },
{ "[i430FX] Packard Bell PB640", "pb640", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_pb640_init, at_pb640_get_device },
{ "[i430FX] QDI Chariot", "chariot", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, CPU_WINCHIP|CPU_WINCHIP2|CPU_Cx6x86|CPU_Cx6x86L|CPU_Cx6x86MX, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_chariot_init, NULL },
{ "[i430FX] QDI Chariot", "chariot", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_WINCHIP, CPU_WINCHIP2, CPU_Cx6x86, CPU_Cx6x86L, CPU_Cx6x86MX), 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_chariot_init, NULL },
/* 430HX */
{ "[i430HX] Acer M3A", "acerm3a", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3300, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_acerm3a_init, NULL },
@@ -281,7 +287,12 @@ const machine_t machines[] = {
{ "[i430HX] Biostar MB-8500TUC", "8500tuc", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_8500tuc_init, NULL },
{ "[i430HX] SuperMicro Super P55T2S", "p55t2s", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3300, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 127, machine_at_p55t2s_init, NULL },
{ "[i430HX] Acer V35N", "acerv35n", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, CPU_Cx6x86MX, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_acerv35n_init, NULL },
/* 430VX */
{ "[i430VX] Gateway 2000 Tigereye", "gw2kte", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_gw2kte_init, NULL },
/* Socket 7 (Dual Voltage) machines */
/* 430HX */
{ "[i430HX] Acer V35N", "acerv35n", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_Cx6x86MX), 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 196608, 8192, 127, machine_at_acerv35n_init, NULL },
{ "[i430HX] ASUS P/I-P55T2P4", "p55t2p4", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 83333333, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 127, machine_at_p55t2p4_init, NULL },
{ "[i430HX] Micronics M7S-Hi", "m7shi", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 511, machine_at_m7shi_init, NULL },
{ "[i430HX] Intel TC430HX", "tc430hx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 255, machine_at_tc430hx_init, NULL },
@@ -294,7 +305,6 @@ const machine_t machines[] = {
{ "[i430VX] Biostar MB-8500TVX-A", "8500tvxa", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2600, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_8500tvxa_init, NULL },
{ "[i430VX] Compaq Presario 4500", "presario4500", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_presario4500_init, NULL },
{ "[i430VX] Epox P55-VA", "p55va", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p55va_init, NULL },
{ "[i430VX] Gateway 2000 Tigereye", "gw2kte", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_gw2kte_init, NULL },
{ "[i430VX] HP Brio 80xx", "brio80xx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 66666667, 66666667, 2200, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_brio80xx_init, NULL },
{ "[i430VX] Packard Bell PB680", "pb680", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_pb680_init, NULL },
{ "[i430VX] Shuttle HOT-557", "430vx", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_i430vx_init, NULL },
@@ -364,6 +374,7 @@ const machine_t machines[] = {
/* VIA Apollo Pro */
{ "[VIA Apollo Pro] FIC KA-6130", "ficka6130", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 3.5, 5.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 255, machine_at_ficka6130_init, NULL },
{ "[VIA Apollo Pro133] ASUS P3V133", "p3v133", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 150000000, 1300, 3500, 2.0, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1572864, 8192, 255, machine_at_p3v133_init, NULL },
{ "[VIA Apollo Pro133A] ASUS P3V4X", "p3v4x", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 150000000, 1300, 3500, 2.0, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,2097152, 8192, 255, machine_at_p3v4x_init, NULL },
/* Slot 2 machines */
@@ -390,14 +401,14 @@ const machine_t machines[] = {
/* VIA Apollo Pro */
{ "[VIA Apollo Pro] PC Partner APAS3", "apas3", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 100000000, 1800, 3500, 3.0, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_apas3_init, NULL },
{ "[VIA Apollo Pro133] ECS P6BAP", "p6bap", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, 2.0, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1572864, 8192, 255, machine_at_p6bap_init, NULL },
{ "[VIA Apollo Pro133A] AEWIN WCF-681", "wcf681", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 133333333, 1300, 3500, 0, 0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_wcf681_init, NULL },
{ "[VIA Apollo Pro133A] ASUS CUV4X-LS", "cuv4xls", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, 2.0, 8.0, (MACHINE_AGP & ~MACHINE_AT) | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 16384,1572864, 8192, 255, machine_at_cuv4xls_init, NULL },
{ "[VIA Apollo Pro133A] Acorp 6VIA90AP", "6via90ap", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, MACHINE_MULTIPLIER_FIXED, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1572864, 8192, 255, machine_at_6via90ap_init, NULL },
{ "[VIA Apollo Pro133A] ECS P6BAP", "p6bap", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, 2.0, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1572864, 8192, 255, machine_at_p6bap_init, NULL },
{ "[VIA Apollo ProMedia] Jetway 603TCF", "603tcf", MACHINE_TYPE_SOCKET370, CPU_PKG_SOCKET370, 0, 66666667, 150000000, 1300, 3500, 2.0, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_603tcf_init, NULL },
/* Miscellaneous/Fake/Hypervisor machines */
{ "[i440BX] Microsoft Virtual PC 2007", "vpc2007", MACHINE_TYPE_MISC, CPU_PKG_SLOT1, CPU_PENTIUM2 | CPU_CYRIX3S, 0, 0, 0, 0, 0, 0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_vpc2007_init, NULL },
{ "[i440BX] Microsoft Virtual PC 2007", "vpc2007", MACHINE_TYPE_MISC, CPU_PKG_SLOT1, CPU_BLOCK(CPU_PENTIUM2, CPU_CYRIX3S), 0, 0, 0, 0, 0, 0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_vpc2007_init, NULL },
{ NULL, NULL, MACHINE_TYPE_NONE, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL }
};

2
src/network/network.c
View File

@@ -54,7 +54,7 @@
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <sys/time.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>

24
src/network/slirp/ip.h
View File

@@ -71,6 +71,9 @@ typedef uint32_t n_long; /* long as received from the net */
/*
* Structure of an internet header, naked of options.
*/
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct ip {
#if G_BYTE_ORDER == G_BIG_ENDIAN
uint8_t ip_v : 4, /* version */
@@ -91,6 +94,9 @@ struct ip {
uint16_t ip_sum; /* checksum */
struct in_addr ip_src, ip_dst; /* source and dest address */
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
#define IP_MAXPACKET 65535 /* maximum packet size */
@@ -134,6 +140,9 @@ struct ip {
/*
* Time stamp option structure.
*/
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct ip_timestamp {
uint8_t ipt_code; /* IPOPT_TS */
uint8_t ipt_len; /* size of structure (variable) */
@@ -153,6 +162,9 @@ struct ip_timestamp {
} ipt_ta[1];
} ipt_timestamp;
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
/* flag bits for ipt_flg */
#define IPOPT_TS_TSONLY 0 /* timestamps only */
@@ -178,6 +190,9 @@ struct ip_timestamp {
#define IP_MSS 576 /* default maximum segment size */
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
#if GLIB_SIZEOF_VOID_P == 4
struct mbuf_ptr {
struct mbuf *mptr;
@@ -188,6 +203,9 @@ struct mbuf_ptr {
struct mbuf *mptr;
} SLIRP_PACKED;
#endif
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
struct qlink {
void *next, *prev;
};
@@ -195,6 +213,9 @@ struct qlink {
/*
* Overlay for ip header used by other protocols (tcp, udp).
*/
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct ipovly {
struct mbuf_ptr ih_mbuf; /* backpointer to mbuf */
uint8_t ih_x1; /* (unused) */
@@ -203,6 +224,9 @@ struct ipovly {
struct in_addr ih_src; /* source internet address */
struct in_addr ih_dst; /* destination internet address */
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
/*
* Ip reassembly queue structure. Each fragment

6
src/network/slirp/ip6_icmp.h
View File

@@ -115,6 +115,9 @@ G_STATIC_ASSERT(sizeof(struct icmp6) == 40);
/*
* NDP Options
*/
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct ndpopt {
uint8_t ndpopt_type; /* Option type */
uint8_t ndpopt_len; /* /!\ In units of 8 octets */
@@ -142,6 +145,9 @@ struct ndpopt {
#define ndpopt_rdnss ndpopt_body.rdnss
} ndpopt_body;
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
/* NDP options type */
#define NDPOPT_LINKLAYER_SOURCE 1 /* Source Link-Layer Address */

11
src/network/slirp/libslirp.h
View File

@@ -16,6 +16,17 @@
#include "libslirp-version.h"
/* Windows does not define ssize_t, so we need to define it here. */
#ifndef _SSIZE_T_DEFINED
# define _SSIZE_T_DEFINED
# undef ssize_t
# ifdef _WIN64
# define ssize_t int64_t
# else
# define ssize_t int32_t
# endif
#endif
#ifdef __cplusplus
extern "C" {
#endif

4
src/network/slirp/misc.c
View File

@@ -8,7 +8,7 @@
#include <sys/un.h>
#endif
inline void insque(void *a, void *b)
extern inline void insque(void *a, void *b)
{
register struct quehead *element = (struct quehead *)a;
register struct quehead *head = (struct quehead *)b;
@@ -19,7 +19,7 @@ inline void insque(void *a, void *b)
(struct quehead *)element;
}
inline void remque(void *a)
extern inline void remque(void *a)
{
register struct quehead *element = (struct quehead *)a;
((struct quehead *)(element->qh_link))->qh_rlink = element->qh_rlink;

6
src/network/slirp/slirp.h
View File

@@ -75,6 +75,9 @@ struct ethhdr {
unsigned short h_proto; /* packet type ID field */
};
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct slirp_arphdr {
unsigned short ar_hrd; /* format of hardware address */
unsigned short ar_pro; /* format of protocol address */
@@ -90,6 +93,9 @@ struct slirp_arphdr {
unsigned char ar_tha[ETH_ALEN]; /* target hardware address */
uint32_t ar_tip; /* target IP address */
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
#define ARP_TABLE_SIZE 16

6
src/network/slirp/tftp.h
View File

@@ -20,6 +20,9 @@
#define TFTP_FILENAME_MAX 512
#define TFTP_BLOCKSIZE_MAX 1428
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(push, 1)
#endif
struct tftp_t {
struct udphdr udp;
uint16_t tp_op;
@@ -35,6 +38,9 @@ struct tftp_t {
char tp_buf[TFTP_BLOCKSIZE_MAX + 2];
} x;
} SLIRP_PACKED;
#if defined(_MSC_VER) && !defined (__clang__)
#pragma pack(pop)
#endif
struct tftp_session {
Slirp *slirp;

15
src/network/slirp/util.h
View File

@@ -30,10 +30,11 @@
#include <stdio.h>
#include <assert.h>
#include <errno.h>
#ifndef _WIN32
#include <unistd.h>
#endif
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <inttypes.h>
#ifdef _WIN32
@@ -45,8 +46,10 @@
#include <netinet/in.h>
#endif
#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
#define SLIRP_PACKED __attribute__((gcc_struct, packed))
#if defined(_MSC_VER) && !defined(__clang__)
#define SLIRP_PACKED
#elif defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
#define SLIRP_PACKED __attribute__((gcc_struct, packed))
#else
#define SLIRP_PACKED __attribute__((packed))
#endif
@@ -56,11 +59,7 @@
#endif
#ifndef container_of
#define container_of(ptr, type, member) \
__extension__({ \
void *__mptr = (void *)(ptr); \
((type *)(__mptr - offsetof(type, member))); \
})
#define container_of(ptr, type, member) ((type *)((char *)(ptr) - offsetof(type, member)));
#endif
#ifndef G_SIZEOF_MEMBER

2
src/network/slirp/vmstate.h
View File

@@ -39,7 +39,9 @@
#ifndef VMSTATE_H_
#define VMSTATE_H_
#ifndef _WIN32
#include <unistd.h>
#endif
#include <stdint.h>
#include <stdbool.h>
#include "slirp.h"

35
src/sio/sio_fdc37c66x.c
View File

@@ -38,7 +38,7 @@
typedef struct {
uint8_t chip_id, tries,
regs[16];
has_ide, regs[16];
int cur_reg,
com3_addr, com4_addr;
fdc_t *fdc;
@@ -131,6 +131,18 @@ fdc_handler(fdc37c66x_t *dev)
}
static void
ide_handler(fdc37c66x_t *dev)
{
ide_sec_disable();
ide_set_base(1, (dev->regs[0x05] & 0x02) ? 0x170 : 0x1f0);
ide_set_side(1, (dev->regs[0x05] & 0x02) ? 0x376 : 0x3f6);
if (dev->regs[0x00] & 0x01)
ide_sec_enable();
}
static void
fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
{
@@ -152,6 +164,8 @@ fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
switch(dev->cur_reg) {
case 0:
if (dev->has_ide && (valxor & 0x01))
ide_handler(dev);
if (valxor & 0x10)
fdc_handler(dev);
break;
@@ -183,6 +197,8 @@ fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
case 5:
if (valxor & 0x01)
fdc_handler(dev);
if (dev->has_ide && (valxor & 0x02))
ide_handler(dev);
if (valxor & 0x18)
fdc_update_densel_force(dev->fdc, (dev->regs[5] & 0x18) >> 3);
if (valxor & 0x20)
@@ -237,6 +253,9 @@ fdc37c66x_reset(fdc37c66x_t *dev)
dev->regs[0x6] = 0xff;
dev->regs[0xd] = dev->chip_id;
dev->regs[0xe] = 0x01;
if (dev->has_ide)
ide_handler(dev);
}
@@ -260,7 +279,10 @@ fdc37c66x_init(const device_t *info)
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->chip_id = info->local;
dev->chip_id = info->local & 0xff;
dev->has_ide = !!(info->local & 0x100);
if (dev->has_ide)
io_sethandler(0x03f0, 0x0002,
fdc37c66x_read, NULL, NULL, fdc37c66x_write, NULL, NULL, dev);
@@ -291,6 +313,15 @@ const device_t fdc37c665_device = {
NULL
};
const device_t fdc37c665_ide_device = {
"SMC FDC37C665 Super I/O",
0,
0x165,
fdc37c66x_init, fdc37c66x_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t fdc37c666_device = {
"SMC FDC37C666 Super I/O",
0,

20
src/sio/sio_vt82c686.c
View File

@@ -33,10 +33,9 @@
typedef struct {
uint8_t config_enable, cur_reg, regs[32],
fdc_dma, fdc_irq, uart_irq[2], lpt_dma, lpt_irq;
fdc_t *fdc;
serial_t *uart[2];
uint8_t cur_reg, regs[32], fdc_dma, fdc_irq, uart_irq[2], lpt_dma, lpt_irq;
fdc_t *fdc;
serial_t *uart[2];
} vt82c686_t;
@@ -100,9 +99,6 @@ static void
vt82c686_write(uint16_t port, uint8_t val, void *priv)
{
vt82c686_t *dev = (vt82c686_t *) priv;
if (!dev->config_enable)
return;
if (!(port & 1)) {
dev->cur_reg = val;
@@ -196,13 +192,9 @@ vt82c686_sio_write(uint8_t addr, uint8_t val, void *priv)
break;
case 0x85:
io_removehandler(0x3f0, 0x0002,
vt82c686_read, NULL, NULL, vt82c686_write, NULL, NULL, dev);
if (val & 0x01)
io_sethandler(0x3f0, 0x0002,
vt82c686_read, NULL, NULL, vt82c686_write, NULL, NULL, dev);
dev->config_enable = val & 0x02;
io_removehandler(0x3f0, 2, vt82c686_read, NULL, NULL, vt82c686_write, NULL, NULL, dev);
if (val & 0x02)
io_sethandler(0x3f0, 2, vt82c686_read, NULL, NULL, vt82c686_write, NULL, NULL, dev);
break;
}
}

4
src/sound/resid-fp/sid.cc
View File

@@ -29,7 +29,7 @@ enum host_cpu_feature {
};
/* This code is appropriate for 32-bit and 64-bit x86 CPUs. */
#if defined(__x86_64__) || defined(__i386__) || defined(_MSC_VER)
#if defined(__x86_64__) || defined(__i386__) || defined(_M_IX86) || (defined(_M_X64) && !(defined(_MSC_VER) && !defined(__clang__)))
struct cpu_x86_regs_s {
unsigned int eax;
@@ -43,7 +43,7 @@ static cpu_x86_regs_t get_cpuid_regs(unsigned int index)
{
cpu_x86_regs_t retval;
#if defined(_MSC_VER) /* MSVC assembly */
#if defined(_MSC_VER) && !defined(__clang__) /* MSVC assembly */
__asm {
mov eax, [index]
cpuid

2
src/sound/resid-fp/siddefs-fp.h
View File

@@ -74,7 +74,7 @@ const char* resid_version_string = VERSION;
// Inlining on/off.
#define RESID_INLINE inline
#if defined(__SSE__) || (defined(_MSC_VER) && (_MSC_VER >= 1300))
#if defined(__SSE__) || (defined(_M_IX86_FP ) && _M_IX86_FP >= 1) || defined(_M_X64)
#define RESID_USE_SSE 1
#else
#define RESID_USE_SSE 0

1
src/video/vid_et4000w32.c
View File

@@ -1312,6 +1312,7 @@ void *et4000w32p_init(const device_t *info)
et4000->svga.clock_gen = et4000->svga.ramdac;
et4000->svga.getclock = stg_getclock;
et4000->svga.adv_flags |= FLAG_NOSKEW;
break;
case ET4000W32_DIAMOND:

4
src/video/vid_svga.c
View File

@@ -445,7 +445,7 @@ svga_recalctimings(svga_t *svga)
svga->interlace = 0;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]);
svga->ca_adj = 0;
svga->rowcount = svga->crtc[9] & 31;
@@ -459,6 +459,8 @@ svga_recalctimings(svga_t *svga)
svga->hdisp *= (svga->seqregs[1] & 1) ? 16 : 18;
} else {
svga->render = svga_render_text_80;
if (!(svga->adv_flags & FLAG_NOSKEW))
svga->ma_latch += ((svga->crtc[8] & 0x60) >> 5);
svga->hdisp *= (svga->seqregs[1] & 1) ? 8 : 9;
}
svga->hdisp_old = svga->hdisp;

29
src/video/vid_voodoo_banshee.c
View File

@@ -2083,8 +2083,8 @@ static void banshee_overlay_draw(svga_t *svga, int displine)
case VIDPROCCFG_FILTER_MODE_DITHER_4X4:
if (banshee->voodoo->scrfilter && banshee->voodoo->scrfilterEnabled)
{
uint8_t fil[(svga->overlay_latch.xsize) * 3];
uint8_t fil3[(svga->overlay_latch.xsize) * 3];
uint8_t *fil = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *fil3 = malloc((svga->overlay_latch.xsize) * 3);
if (banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE) /* leilei HACK - don't know of real 4x1 hscaled behavior yet, double for now */
{
@@ -2146,6 +2146,9 @@ static void banshee_overlay_draw(svga_t *svga, int displine)
fil[(x)*3+2] = vb_filter_v1_rb [fil[x*3+2]] [fil3[(x+1) *3+2]];
p[x] = (fil[x*3+2] << 16) | (fil[x*3+1] << 8) | fil[x*3];
}
free(fil);
free(fil3);
}
else /* filter disabled by emulator option */
{
@@ -2168,14 +2171,14 @@ static void banshee_overlay_draw(svga_t *svga, int displine)
case VIDPROCCFG_FILTER_MODE_DITHER_2X2:
if (banshee->voodoo->scrfilter && banshee->voodoo->scrfilterEnabled)
{
uint8_t fil[(svga->overlay_latch.xsize) * 3];
uint8_t soak[(svga->overlay_latch.xsize) * 3];
uint8_t soak2[(svga->overlay_latch.xsize) * 3];
uint8_t *fil = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *soak = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *soak2 = malloc((svga->overlay_latch.xsize) * 3);
uint8_t samp1[(svga->overlay_latch.xsize) * 3];
uint8_t samp2[(svga->overlay_latch.xsize) * 3];
uint8_t samp3[(svga->overlay_latch.xsize) * 3];
uint8_t samp4[(svga->overlay_latch.xsize) * 3];
uint8_t *samp1 = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *samp2 = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *samp3 = malloc((svga->overlay_latch.xsize) * 3);
uint8_t *samp4 = malloc((svga->overlay_latch.xsize) * 3);
src = &svga->vram[src_addr2 & svga->vram_mask];
OVERLAY_SAMPLE(banshee->overlay_buffer[1]);
@@ -2229,6 +2232,14 @@ static void banshee_overlay_draw(svga_t *svga, int displine)
p[x] = (fil[x*3+2] << 16) | (fil[x*3+1] << 8) | fil[x*3];
}
}
free(fil);
free(soak);
free(soak2);
free(samp1);
free(samp2);
free(samp3);
free(samp4);
}
else /* filter disabled by emulator option */
{

12
src/video/vid_voodoo_display.c
View File

@@ -368,7 +368,7 @@ static void voodoo_filterline_v1(voodoo_t *voodoo, uint8_t *fil, int column, uin
int x;
// Scratchpad for avoiding feedback streaks
uint8_t fil3[(voodoo->h_disp) * 3];
uint8_t *fil3 = malloc((voodoo->h_disp) * 3);
/* 16 to 32-bit */
for (x=0; x<column;x++)
@@ -426,6 +426,8 @@ static void voodoo_filterline_v1(voodoo_t *voodoo, uint8_t *fil, int column, uin
fil[(x)*3+1] = voodoo->thefilterg[fil3[x*3+1]][fil3[ (x+1) *3+1]];
fil[(x)*3+2] = voodoo->thefilter[fil3[x*3+2]][fil3[ (x+1) *3+2]];
}
free(fil3);
}
@@ -434,7 +436,7 @@ static void voodoo_filterline_v2(voodoo_t *voodoo, uint8_t *fil, int column, uin
int x;
// Scratchpad for blending filter
uint8_t fil3[(voodoo->h_disp) * 3];
uint8_t *fil3 = malloc((voodoo->h_disp) * 3);
/* 16 to 32-bit */
for (x=0; x<column;x++)
@@ -491,6 +493,8 @@ static void voodoo_filterline_v2(voodoo_t *voodoo, uint8_t *fil, int column, uin
fil3[(column-1)*3] = voodoo->thefilterb [fil[(column-1)*3]][((src[column] & 31) << 3)];
fil3[(column-1)*3+1] = voodoo->thefilterg [fil[(column-1)*3+1]][(((src[column] >> 5) & 63) << 2)];
fil3[(column-1)*3+2] = voodoo->thefilter [fil[(column-1)*3+2]][(((src[column] >> 11) & 31) << 3)];
free(fil3);
}
void voodoo_callback(void *p)
@@ -545,7 +549,7 @@ void voodoo_callback(void *p)
if (voodoo->scrfilter && voodoo->scrfilterEnabled)
{
uint8_t fil[(voodoo->h_disp) * 3]; /* interleaved 24-bit RGB */
uint8_t *fil = malloc((voodoo->h_disp) * 3); /* interleaved 24-bit RGB */
if (voodoo->type == VOODOO_2)
voodoo_filterline_v2(voodoo, fil, voodoo->h_disp, src, voodoo->line);
@@ -556,6 +560,8 @@ void voodoo_callback(void *p)
{
p[x] = (voodoo->clutData256[fil[x*3]].b << 0 | voodoo->clutData256[fil[x*3+1]].g << 8 | voodoo->clutData256[fil[x*3+2]].r << 16);
}
free(fil);
}
else
{

4
src/video/vid_voodoo_render.c
View File

@@ -684,9 +684,9 @@ static inline void voodoo_tmu_fetch_and_blend(voodoo_t *voodoo, voodoo_params_t
state->tex_a[0] ^= 0xff;
}
#if (defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined WIN32 || defined _WIN32 || defined _WIN32) && !(defined __amd64__)
#if (defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86) && !(defined __amd64__ || defined _M_X64)
#include <86box/vid_voodoo_codegen_x86.h>
#elif (defined __amd64__)
#elif (defined __amd64__ || defined _M_X64)
#include <86box/vid_voodoo_codegen_x86-64.h>
#else
int voodoo_recomp = 0;

24
src/win/86Box.rc
View File

@@ -15,11 +15,9 @@
* Copyright 2016-2019 Miran Grca.
* Copyright 2018,2019 David Hrdlička.
*/
#include <inttypes.h>
#define IN_RESOURCE_H
#include <86box/resource.h>
#include <86box/86box.h>
#include <86box/plat.h>
#include <86box/language.h>
#include <86box/version.h>
#undef IN_RESOURCE_H
@@ -395,11 +393,11 @@ DLG_CFG_INPUT DIALOG DISCARDABLE 107, 0, 267, 65
STYLE DS_CONTROL | WS_CHILD
FONT 9, "Segoe UI"
BEGIN
LTEXT "Mouse :",IDT_1709,7,9,57,10
LTEXT "Mouse:",IDT_1709,7,9,57,10
COMBOBOX IDC_COMBO_MOUSE,71,7,140,120,CBS_DROPDOWNLIST |
WS_VSCROLL | WS_TABSTOP
PUSHBUTTON "Configure",IDC_CONFIGURE_MOUSE,214,7,46,12
LTEXT "Joystick :",IDT_1710,7,27,58,10
LTEXT "Joystick:",IDT_1710,7,27,58,10
COMBOBOX IDC_COMBO_JOYSTICK,71,25,189,120,CBS_DROPDOWNLIST |
WS_VSCROLL | WS_TABSTOP
PUSHBUTTON "Joystick 1...",IDC_JOY1,7,44,50,14
@@ -499,17 +497,17 @@ DLG_CFG_STORAGE DIALOG DISCARDABLE 107, 0, 267, 111
STYLE DS_CONTROL | WS_CHILD
FONT 9, "Segoe UI"
BEGIN
LTEXT "SCSI Controller:",IDT_1717,7,9,48,10
LTEXT "SCSI Controller:",IDT_1717,7,9,64,10
COMBOBOX IDC_COMBO_SCSI,64,7,155,120,CBS_DROPDOWNLIST |
WS_VSCROLL | WS_TABSTOP
PUSHBUTTON "Configure",IDC_CONFIGURE_SCSI,222,7,38,12
LTEXT "HD Controller:",IDT_1718,7,28,48,10
LTEXT "HD Controller:",IDT_1718,7,28,64,10
COMBOBOX IDC_COMBO_HDC,64,26,155,120,CBS_DROPDOWNLIST |
WS_VSCROLL | WS_TABSTOP
PUSHBUTTON "Configure",IDC_CONFIGURE_HDC,222,26,38,12
LTEXT "FD Controller:",IDT_1768,7,47,48,10
LTEXT "FD Controller:",IDT_1768,7,47,64,10
COMBOBOX IDC_COMBO_FDC,64,45,155,120,CBS_DROPDOWNLIST |
WS_VSCROLL | WS_TABSTOP
PUSHBUTTON "Configure",IDC_CONFIGURE_FDC,222,45,38,12
@@ -530,7 +528,7 @@ BEGIN
CONTROL "List1",IDC_LIST_HARD_DISKS,"SysListView32",LVS_REPORT |
LVS_SHOWSELALWAYS | LVS_SINGLESEL | WS_BORDER |
WS_TABSTOP,7,18,253,92
LTEXT "Hard disks:",IDT_1720,7,7,34,8
LTEXT "Hard disks:",IDT_1720,7,7,253,8
PUSHBUTTON "&New...",IDC_BUTTON_HDD_ADD_NEW,60,137,62,10
PUSHBUTTON "&Existing...",IDC_BUTTON_HDD_ADD,129,137,62,10
PUSHBUTTON "&Remove",IDC_BUTTON_HDD_REMOVE,198,137,62,10
@@ -597,7 +595,7 @@ BEGIN
CONTROL "List1",IDC_LIST_FLOPPY_DRIVES,"SysListView32",
LVS_REPORT | LVS_SHOWSELALWAYS | LVS_SINGLESEL | WS_BORDER |
WS_TABSTOP,7,18,253,60
LTEXT "Floppy drives:",IDT_1737,7,7,43,8
LTEXT "Floppy drives:",IDT_1737,7,7,253,8
COMBOBOX IDC_COMBO_FD_TYPE,33,85,90,12,CBS_DROPDOWNLIST |
WS_VSCROLL | WS_TABSTOP
LTEXT "Type:",IDT_1738,7,87,24,8
@@ -609,7 +607,7 @@ BEGIN
CONTROL "List1",IDC_LIST_CDROM_DRIVES,"SysListView32",LVS_REPORT |
LVS_SHOWSELALWAYS | LVS_SINGLESEL | WS_BORDER |
WS_TABSTOP,7,117,253,60
LTEXT "CD-ROM drives:",IDT_1739,7,107,50,8
LTEXT "CD-ROM drives:",IDT_1739,7,107,253,8
COMBOBOX IDC_COMBO_CD_BUS,33,185,90,12,CBS_DROPDOWNLIST |
WS_VSCROLL | WS_TABSTOP
LTEXT "Bus:",IDT_1740,7,187,24,8
@@ -632,7 +630,7 @@ BEGIN
CONTROL "List1",IDC_LIST_MO_DRIVES,"SysListView32",LVS_REPORT |
LVS_SHOWSELALWAYS | LVS_SINGLESEL | WS_BORDER |
WS_TABSTOP,7,17,253,60
LTEXT "MO drives:",IDT_1769,7,7,50,8
LTEXT "MO drives:",IDT_1769,7,7,253,8
COMBOBOX IDC_COMBO_MO_BUS,33,85,90,12,CBS_DROPDOWNLIST |
WS_VSCROLL | WS_TABSTOP
LTEXT "Bus:",IDT_1770,7,87,24,8
@@ -649,7 +647,7 @@ BEGIN
CONTROL "List1",IDC_LIST_ZIP_DRIVES,"SysListView32",LVS_REPORT |
LVS_SHOWSELALWAYS | LVS_SINGLESEL | WS_BORDER |
WS_TABSTOP,7,137,253,60
LTEXT "ZIP drives:",IDT_1759,7,127,50,8
LTEXT "ZIP drives:",IDT_1759,7,127,253,8
COMBOBOX IDC_COMBO_ZIP_BUS,23,205,90,12,CBS_DROPDOWNLIST |
WS_VSCROLL | WS_TABSTOP
LTEXT "Bus:",IDT_1753,7,207,14,8

12
src/win/Makefile.mingw
View File

@@ -96,9 +96,6 @@ ifeq ($(DEV_BUILD), y)
ifndef USE_VECT486VL
USE_VECT486VL := y
endif
ifndef USE_DELLS4
USE_DELLS4 := y
endif
else
ifndef DEBUG
DEBUG := n
@@ -169,9 +166,6 @@ else
ifndef USE_VECT486VL
USE_VECT486VL := n
endif
ifndef USE_DELLS4
USE_DELLS4 := n
endif
endif
# Defaults for several build options (possibly defined in a chained file.)
@@ -570,10 +564,6 @@ ifeq ($(USE_VECT486VL), y)
OPTS += -DUSE_VECT486VL
endif
ifeq ($(USE_DELLS4), y)
OPTS += -DUSE_DELLS4
endif
endif
@@ -606,7 +596,7 @@ CPUOBJ := cpu.o cpu_table.o \
CHIPSETOBJ := acc2168.o cs8230.o ali1429.o headland.o intel_82335.o cs4031.o \
intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o opti495.o opti895.o opti5x7.o scamp.o scat.o via_vt82c49x.o via_vt82c505.o \
sis_85c310.o sis_85c4xx.o sis_85c496.o opti283.o opti291.o umc491.o \
sis_85c310.o sis_85c4xx.o sis_85c496.o sis_85c50x.o opti283.o opti291.o umc491.o \
via_apollo.o via_pipc.o wd76c10.o vl82c480.o
MCHOBJ := machine.o machine_table.o \

6
src/win/win_devconf.c
View File

@@ -519,7 +519,7 @@ deviceconfig_inst_open(HWND hwnd, const device_t *device, int inst)
item->id = id++;
item->cx = 60;
item->cy = 15;
item->cy = 20;
item->style = WS_CHILD | WS_VISIBLE;
@@ -566,7 +566,7 @@ deviceconfig_inst_open(HWND hwnd, const device_t *device, int inst)
item->id = id++;
item->cx = 60;
item->cy = 15;
item->cy = 20;
item->style = WS_CHILD | WS_VISIBLE;
@@ -633,7 +633,7 @@ deviceconfig_inst_open(HWND hwnd, const device_t *device, int inst)
item->id = id++;
item->cx = 60;
item->cy = 15;
item->cy = 20;
item->style = WS_CHILD | WS_VISIBLE;

9
src/win/win_ui.c
View File

@@ -70,8 +70,11 @@ extern WCHAR wopenfilestring[512];
/* Local data. */
static wchar_t wTitle[512];
#ifndef NO_KEYBOARD_HOOK
static HHOOK hKeyboardHook;
static int hook_enabled = 0, manager_wm = 0;
static int hook_enabled = 0;
#endif
static int manager_wm = 0;
static int save_window_pos = 0, pause_state = 0;
static int dpi = 96;
static int padded_frame = 0;
@@ -295,6 +298,7 @@ ResetAllMenus(void)
}
#ifndef NO_KEYBOARD_HOOK
static LRESULT CALLBACK
LowLevelKeyboardProc(int nCode, WPARAM wParam, LPARAM lParam)
{
@@ -326,6 +330,7 @@ LowLevelKeyboardProc(int nCode, WPARAM wParam, LPARAM lParam)
return(CallNextHookEx(hKeyboardHook, nCode, wParam, lParam));
}
#endif
void
@@ -360,7 +365,9 @@ plat_power_off(void)
run before the main thread is terminated */
cycles -= 99999999;
#ifndef NO_KEYBOARD_HOOK
UnhookWindowsHookEx(hKeyboardHook);
#endif
KillTimer(hwndMain, TIMER_1SEC);
PostQuitMessage(0);