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it's definitely argb + some fixes

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This commit is contained in:
starfrost013
2025-03-20 21:35:56 +00:00
parent fea521d3ac
commit 57d725742e
8 changed files with 14 additions and 23 deletions
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15
src/include/86box/nv/classes/vid_nv3_classes.h
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@@ -100,22 +100,13 @@ typedef struct nv3_class_ctx_switch_method_s
} nv3_class_ctx_switch_method_t;
/* 32-bit BGRA format colour for 2D acceleration */
typedef struct nv3_color_bgra_32_s
{
uint8_t b;
uint8_t g;
uint8_t r;
uint8_t a;
} nv3_color_bgra_32_t;
/* 32-bit ARGB format colour for internal D3D5 stuff */
typedef struct nv3_color_argb_32_s
{
uint8_t a;
uint8_t r;
uint8_t g;
uint8_t b;
uint8_t a;
} nv3_color_argb_32_t;
/* 30-bit colour format for internal PGRAPH use */
@@ -375,7 +366,7 @@ typedef struct nv3_object_class_007
/* In case your points weren't colourful enough */
typedef struct nv3_object_class_008_cpoint_s
{
nv3_color_argb_32_t color; // BGRA-format 32-bit color
nv3_color_argb_32_t color; // argb-format 32-bit color
nv3_position_16_t position; //
} nv3_object_class_008_cpoint_t;
@@ -1083,7 +1074,7 @@ typedef struct nv3_d3d5_alpha_control_s
typedef struct nv3_d3d5_coordinate_s
{
nv3_d3d5_specular_t specular_reflection_parameters;
nv3_color_bgra_32_t color; // YOU HAVE TO FLIP THE ENDIANNESS. NVIDIA??? WHAT???
nv3_color_argb_32_t color; // YOU HAVE TO FLIP THE ENDIANNESS. NVIDIA??? WHAT???
// Seems more plausible for these specifically to be floats.
// Also makes my life easier...

3
src/include/86box/nv/vid_nv3.h
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@@ -35,10 +35,9 @@ extern const device_config_t nv3_config[];
#define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start
#define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN
// DMA channels are basically the number of contexts that the gpu can deal with at once.
// THere are 64 DMA channels grouped into 8 "channels" with 8 "subchannels" each. You can only use one channel at a time. An arbitrary number of 8 objects can be submitted.
// Channel 0 is always taken up by NV drivers.
// Subchannels deal with specific parts of the GPU and are manipulated by the driver to manipulate the gpu.
#define NV3_DMA_CHANNELS 8
#define NV3_DMA_SUBCHANNELS_PER_CHANNEL 8

4
src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c
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@@ -69,13 +69,13 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_
nv3->pgraph.image_in_memory.pitch = param & 0x1FF0;
nv3->pgraph.bpitch[src_buffer_id] = param & 0x1FF0; // 12:0
nv_log("Image in Memory BUFL%d PITCH=0x%04x", src_buffer_id, nv3->pgraph.bpitch[src_buffer_id]);
nv_log("Image in Memory BUF%d PITCH=0x%04x", src_buffer_id, nv3->pgraph.bpitch[src_buffer_id]);
break;
/* Byte offset in GPU VRAM of top left pixel (22:0) */
case NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET:
nv3->pgraph.boffset[src_buffer_id] = param & ((1 << NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END) - 0x10);
nv_log("Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x", src_buffer_id, nv3->pgraph.image_in_memory.linear_address);
nv_log("Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x", src_buffer_id, nv3->pgraph.boffset[src_buffer_id]);
break;
default:
nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id);

6
src/video/nv/nv3/classes/nv3_class_shared_methods.c
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@@ -84,8 +84,8 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t
notify.nanoseconds = nv3->ptimer.time;
notify.status = NV3_NOTIFICATION_STATUS_DONE_OK; // it should be fine to just signal that it's ok
// this is completely speculative and i have no idea
notify.info32 = grobj.grobj_0;
// these are only nonzero when there is an error
notify.info32 = notify.info16 = 0;
// notify object base=grobj_1 >> 12
uint32_t notify_obj_base = grobj.grobj_1 >> 12;
@@ -156,7 +156,7 @@ void nv3_notify_if_needed(uint32_t name, uint32_t method_id, nv3_ramin_context_t
}
/* send the notification off */
nv_log("About to send the notification to 0x%08x (Check target)", final_address);
nv_log("About to send hardware notification to 0x%08x (Check target)\n", final_address);
switch (info_notification_target)
{
case NV3_NOTIFICATION_TARGET_NVM:

3
src/video/nv/nv3/render/nv3_render_core.c
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@@ -33,4 +33,5 @@
uint32_t nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, nv3_render_operation_type rop)
{
return video_rop_gdi_ternary(rop, dst, pattern, src);
}
}

2
src/video/nv/nv3/subsystems/nv3_pfb.c
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@@ -172,7 +172,7 @@ void nv3_pfb_config0_write(uint32_t val)
uint32_t new_pfb_htotal = (nv3->pfb.config_0 & 0x3F) << 5;
// i don't think 16:9 is supported
uint32_t new_pfb_vtotal = new_pfb_htotal * (4.0/3.0);
uint32_t new_pfb_vtotal = new_pfb_htotal * (3.0/4.0);
uint32_t new_bit_depth = (nv3->pfb.config_0 >> 8) & 0x03;
nv_log("Framebuffer Config Change\n");

2
src/video/nv/nv3/subsystems/nv3_pfifo.c
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@@ -824,7 +824,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t object_name)
nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address) << 2;
nv_log("Submitted object [PIO]: Channel %d.%d, Object Name 0x%08x, Method ID 0x%04x (Put Address is now %d)\n",
nv_log("Submitted object [PIO]: Channel %d.%d, Parameter 0x%08x, Method ID 0x%04x (Put Address is now %d)\n",
channel, subchannel, object_name, method_offset, nv3->pfifo.cache1_settings.put_address);
// Now we're done. Phew!

2
src/video/nv/nv3/subsystems/nv3_pramin.c
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@@ -440,7 +440,7 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u
fatal("NV3: Invalid graphics object class ID name=0x%04x type=%04x, interpreted by pgraph as: %04x (Contact starfrost)",
name, obj_context_struct.class_id, obj_context_struct.class_id & 0x1F);
}
else if (obj_context_struct.channel > NV3_DMA_CHANNELS)
else if (obj_context_struct.channel > (NV3_DMA_CHANNELS - 1))
fatal("NV3: Super fucked up graphics object. Contact starfrost with the error string: DMA Channel ID=%d, it should be 0-7", obj_context_struct.channel);
// Illegal accesses sent to RAMRO, so ignore here