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PCI: Make PCI configuration reads and writes length-aware and fix the DC390 PCI device ID AND'ing with EEPROM DO.

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This commit is contained in:
OBattler
2026-01-24 16:10:08 +01:00
committed by Dmitry Borisov
parent c6d272fa9e
commit 570483a828
58 changed files with 484 additions and 450 deletions
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4
src/chipset/ali1435.c
View File

@@ -98,7 +98,7 @@ ali1435_update_irqs(ali1435_t *dev, int set)
}
static void
ali1435_pci_write(int func, int addr, uint8_t val, void *priv)
ali1435_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1435_t *dev = (ali1435_t *) priv;
int irq;
@@ -163,7 +163,7 @@ ali1435_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali1435_pci_read(int func, int addr, void *priv)
ali1435_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
const ali1435_t *dev = (ali1435_t *) priv;
uint8_t ret;

4
src/chipset/ali1489.c
View File

@@ -411,7 +411,7 @@ ali1489_read(uint16_t addr, void *priv)
}
static void
ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ali1489_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1489_t *dev = (ali1489_t *) priv;
@@ -434,7 +434,7 @@ ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
ali1489_pci_read(UNUSED(int func), int addr, void *priv)
ali1489_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const ali1489_t *dev = (ali1489_t *) priv;
uint8_t ret = 0xff;

18
src/chipset/ali1531.c
View File

@@ -132,7 +132,7 @@ ali1531_shadow_recalc(UNUSED(int cur_reg), ali1531_t *dev)
}
static void
ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ali1531_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1531_t *dev = (ali1531_t *) priv;
@@ -298,7 +298,7 @@ ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
ali1531_read(UNUSED(int func), int addr, void *priv)
ali1531_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const ali1531_t *dev = (ali1531_t *) priv;
uint8_t ret = 0xff;
@@ -341,18 +341,18 @@ ali1531_reset(void *priv)
dev->pci_conf[0x5a] = 0x20;
dev->pci_conf[0x70] = 0x22;
ali1531_write(0, 0x42, 0x00, dev);
ali1531_write(0, 0x43, 0x00, dev);
ali1531_write(0, 0x42, 1, 0x00, dev);
ali1531_write(0, 0x43, 1, 0x00, dev);
ali1531_write(0, 0x47, 0x00, dev);
ali1531_write(0, 0x48, 0x00, dev);
ali1531_write(0, 0x47, 1, 0x00, dev);
ali1531_write(0, 0x48, 1, 0x00, dev);
for (uint8_t i = 0; i < 4; i++)
ali1531_write(0, 0x4c + i, 0x00, dev);
ali1531_write(0, 0x4c + i, 1, 0x00, dev);
for (uint8_t i = 0; i < 16; i += 2) {
ali1531_write(0, 0x60 + i, 0x08, dev);
ali1531_write(0, 0x61 + i, 0x40, dev);
ali1531_write(0, 0x60 + i, 1, 0x08, dev);
ali1531_write(0, 0x61 + i, 1, 0x40, dev);
}
}

20
src/chipset/ali1541.c
View File

@@ -177,7 +177,7 @@ ali1541_mask_bar(ali1541_t *dev)
}
static void
ali1541_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ali1541_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1541_t *dev = (ali1541_t *) priv;
@@ -562,7 +562,7 @@ ali1541_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
ali1541_read(UNUSED(int func), int addr, void *priv)
ali1541_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const ali1541_t *dev = (ali1541_t *) priv;
uint8_t ret = 0xff;
@@ -613,20 +613,20 @@ ali1541_reset(void *priv)
dev->pci_conf[0xe0] = 0x01;
cpu_cache_int_enabled = 1;
ali1541_write(0, 0x42, 0x00, dev);
ali1541_write(0, 0x42, 1, 0x00, dev);
ali1541_write(0, 0x54, 0x00, dev);
ali1541_write(0, 0x55, 0x00, dev);
ali1541_write(0, 0x54, 1, 0x00, dev);
ali1541_write(0, 0x55, 1, 0x00, dev);
for (uint8_t i = 0; i < 4; i++)
ali1541_write(0, 0x56 + i, 0x00, dev);
ali1541_write(0, 0x56 + i, 1, 0x00, dev);
ali1541_write(0, 0x60, 0x07, dev);
ali1541_write(0, 0x61, 0x40, dev);
ali1541_write(0, 0x60, 1, 0x07, dev);
ali1541_write(0, 0x61, 1, 0x40, dev);
for (uint8_t i = 0; i < 14; i += 2) {
ali1541_write(0, 0x62 + i, 0x00, dev);
ali1541_write(0, 0x63 + i, 0x00, dev);
ali1541_write(0, 0x62 + i, 1, 0x00, dev);
ali1541_write(0, 0x63 + i, 1, 0x00, dev);
}
}

130
src/chipset/ali1543.c
View File

@@ -112,13 +112,13 @@ ali1533_ddma_handler(UNUSED(ali1543_t *dev))
static void ali5229_ide_handler(ali1543_t *dev);
static void ali5229_ide_irq_handler(ali1543_t *dev);
static void ali5229_write(int func, int addr, uint8_t val, void *priv);
static void ali5229_write(int func, int addr, int len, uint8_t val, void *priv);
static void ali7101_write(int func, int addr, uint8_t val, void *priv);
static uint8_t ali7101_read(int func, int addr, void *priv);
static void ali7101_write(int func, int addr, int len, uint8_t val, void *priv);
static uint8_t ali7101_read(int func, int addr, int len, void *priv);
static void
ali1533_write(int func, int addr, uint8_t val, void *priv)
ali1533_write(int func, int addr, int len, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M1533: dev->pci_conf[%02x] = %02x\n", addr, val);
@@ -453,7 +453,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x7c ... 0xff:
if ((dev->type == 1) && !dev->pmu_dev_enable) {
dev->pmu_dev_enable = 1;
ali7101_write(func, addr, val, priv);
ali7101_write(func, addr, len, val, priv);
dev->pmu_dev_enable = 0;
}
break;
@@ -464,7 +464,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali1533_read(int func, int addr, void *priv)
ali1533_read(int func, int addr, int len, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
@@ -478,7 +478,7 @@ ali1533_read(int func, int addr, void *priv)
ret = (ret & 0xbf) | (dev->ide_dev_enable ? 0x40 : 0x00);
else if ((dev->type == 1) && ((addr >= 0x7c) && (addr <= 0xff)) && !dev->pmu_dev_enable) {
dev->pmu_dev_enable = 1;
ret = ali7101_read(func, addr, priv);
ret = ali7101_read(func, addr, len, priv);
dev->pmu_dev_enable = 0;
}
}
@@ -690,23 +690,23 @@ ali5229_chip_reset(ali1543_t *dev)
dev->ide_conf[0x4f] = 0x1a;
}
ali5229_write(0, 0x04, 0x05, dev);
ali5229_write(0, 0x10, 0xf1, dev);
ali5229_write(0, 0x11, 0x01, dev);
ali5229_write(0, 0x14, 0xf5, dev);
ali5229_write(0, 0x15, 0x03, dev);
ali5229_write(0, 0x18, 0x71, dev);
ali5229_write(0, 0x19, 0x01, dev);
ali5229_write(0, 0x1a, 0x75, dev);
ali5229_write(0, 0x1b, 0x03, dev);
ali5229_write(0, 0x20, 0x01, dev);
ali5229_write(0, 0x21, 0xf0, dev);
ali5229_write(0, 0x4d, 0x00, dev);
ali5229_write(0, 0x04, 1, 0x05, dev);
ali5229_write(0, 0x10, 1, 0xf1, dev);
ali5229_write(0, 0x11, 1, 0x01, dev);
ali5229_write(0, 0x14, 1, 0xf5, dev);
ali5229_write(0, 0x15, 1, 0x03, dev);
ali5229_write(0, 0x18, 1, 0x71, dev);
ali5229_write(0, 0x19, 1, 0x01, dev);
ali5229_write(0, 0x1a, 1, 0x75, dev);
ali5229_write(0, 0x1b, 1, 0x03, dev);
ali5229_write(0, 0x20, 1, 0x01, dev);
ali5229_write(0, 0x21, 1, 0xf0, dev);
ali5229_write(0, 0x4d, 1, 0x00, dev);
dev->ide_conf[0x09] = 0xfa;
ali5229_write(0, 0x09, 0xfa, dev);
ali5229_write(0, 0x52, 0x00, dev);
ali5229_write(0, 0x09, 1, 0xfa, dev);
ali5229_write(0, 0x52, 1, 0x00, dev);
ali5229_write(0, 0x50, 0x02, dev);
ali5229_write(0, 0x50, 1, 0x02, dev);
sff_set_slot(dev->ide_controller[0], dev->ide_slot);
sff_set_slot(dev->ide_controller[1], dev->ide_slot);
@@ -716,7 +716,7 @@ ali5229_chip_reset(ali1543_t *dev)
}
static void
ali5229_write(int func, int addr, uint8_t val, void *priv)
ali5229_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M5229: [W] dev->ide_conf[%02x] = %02x\n", addr, val);
@@ -885,7 +885,7 @@ ali5229_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali5229_read(int func, int addr, void *priv)
ali5229_read(int func, int addr, UNUSED(int len), void *priv)
{
const ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
@@ -908,7 +908,7 @@ ali5229_read(int func, int addr, void *priv)
}
static void
ali5237_write(int func, int addr, uint8_t val, void *priv)
ali5237_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M5237: dev->usb_conf[%02x] = %02x\n", addr, val);
@@ -975,7 +975,7 @@ ali5237_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali5237_read(int func, int addr, void *priv)
ali5237_read(int func, int addr, UNUSED(int len), void *priv)
{
const ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
@@ -987,7 +987,7 @@ ali5237_read(int func, int addr, void *priv)
}
static void
ali7101_write(int func, int addr, uint8_t val, void *priv)
ali7101_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M7101: [W] dev->pmu_conf[%02x] = %02x\n", addr, val);
@@ -1408,7 +1408,7 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ali7101_read(int func, int addr, void *priv)
ali7101_read(int func, int addr, UNUSED(int len), void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
@@ -1516,11 +1516,11 @@ ali1543_reset(void *priv)
dev->usb_conf[0x0b] = 0x0c;
dev->usb_conf[0x3d] = 0x01;
ali5237_write(0, 0x04, 0x00, dev);
ali5237_write(0, 0x10, 0x00, dev);
ali5237_write(0, 0x11, 0x00, dev);
ali5237_write(0, 0x12, 0x00, dev);
ali5237_write(0, 0x13, 0x00, dev);
ali5237_write(0, 0x04, 1, 0x00, dev);
ali5237_write(0, 0x10, 1, 0x00, dev);
ali5237_write(0, 0x11, 1, 0x00, dev);
ali5237_write(0, 0x12, 1, 0x00, dev);
ali5237_write(0, 0x13, 1, 0x00, dev);
/* M7101 */
memset(dev->pmu_conf, 0x00, sizeof(dev->pmu_conf));
@@ -1536,26 +1536,26 @@ ali1543_reset(void *priv)
acpi_set_slot(dev->acpi, dev->pmu_slot);
acpi_set_nvr(dev->acpi, dev->nvr);
ali7101_write(0, 0x04, 0x0f, dev);
ali7101_write(0, 0x10, 0x01, dev);
ali7101_write(0, 0x11, 0x00, dev);
ali7101_write(0, 0x12, 0x00, dev);
ali7101_write(0, 0x13, 0x00, dev);
ali7101_write(0, 0x14, 0x01, dev);
ali7101_write(0, 0x15, 0x00, dev);
ali7101_write(0, 0x16, 0x00, dev);
ali7101_write(0, 0x17, 0x00, dev);
ali7101_write(0, 0x40, 0x00, dev);
ali7101_write(0, 0x41, 0x00, dev);
ali7101_write(0, 0x42, 0x00, dev);
ali7101_write(0, 0x43, 0x00, dev);
ali7101_write(0, 0x77, 0x00, dev);
ali7101_write(0, 0xbd, 0x00, dev);
ali7101_write(0, 0xc0, 0x00, dev);
ali7101_write(0, 0xc1, 0x00, dev);
ali7101_write(0, 0xc2, 0x00, dev);
ali7101_write(0, 0xc3, 0x00, dev);
ali7101_write(0, 0xe0, 0x00, dev);
ali7101_write(0, 0x04, 1, 0x0f, dev);
ali7101_write(0, 0x10, 1, 0x01, dev);
ali7101_write(0, 0x11, 1, 0x00, dev);
ali7101_write(0, 0x12, 1, 0x00, dev);
ali7101_write(0, 0x13, 1, 0x00, dev);
ali7101_write(0, 0x14, 1, 0x01, dev);
ali7101_write(0, 0x15, 1, 0x00, dev);
ali7101_write(0, 0x16, 1, 0x00, dev);
ali7101_write(0, 0x17, 1, 0x00, dev);
ali7101_write(0, 0x40, 1, 0x00, dev);
ali7101_write(0, 0x41, 1, 0x00, dev);
ali7101_write(0, 0x42, 1, 0x00, dev);
ali7101_write(0, 0x43, 1, 0x00, dev);
ali7101_write(0, 0x77, 1, 0x00, dev);
ali7101_write(0, 0xbd, 1, 0x00, dev);
ali7101_write(0, 0xc0, 1, 0x00, dev);
ali7101_write(0, 0xc1, 1, 0x00, dev);
ali7101_write(0, 0xc2, 1, 0x00, dev);
ali7101_write(0, 0xc3, 1, 0x00, dev);
ali7101_write(0, 0xe0, 1, 0x00, dev);
/* Do the bridge last due to device deactivations. */
/* M1533 */
@@ -1570,19 +1570,19 @@ ali1543_reset(void *priv)
dev->pci_conf[0x0a] = 0x01;
dev->pci_conf[0x0b] = 0x06;
ali1533_write(0, 0x41, 0x00, dev); /* Disables the keyboard and mouse IRQ latch. */
ali1533_write(0, 0x48, 0x00, dev); /* Disables all IRQ's. */
ali1533_write(0, 0x44, 0x00, dev);
ali1533_write(0, 0x4d, 0x00, dev);
ali1533_write(0, 0x53, 0x00, dev);
ali1533_write(0, 0x58, 0x00, dev);
ali1533_write(0, 0x5f, 0x00, dev);
ali1533_write(0, 0x72, 0x00, dev);
ali1533_write(0, 0x74, 0x00, dev);
ali1533_write(0, 0x75, 0x00, dev);
ali1533_write(0, 0x76, 0x00, dev);
ali1533_write(0, 0x41, 1, 0x00, dev); /* Disables the keyboard and mouse IRQ latch. */
ali1533_write(0, 0x48, 1, 0x00, dev); /* Disables all IRQ's. */
ali1533_write(0, 0x44, 1, 0x00, dev);
ali1533_write(0, 0x4d, 1, 0x00, dev);
ali1533_write(0, 0x53, 1, 0x00, dev);
ali1533_write(0, 0x58, 1, 0x00, dev);
ali1533_write(0, 0x5f, 1, 0x00, dev);
ali1533_write(0, 0x72, 1, 0x00, dev);
ali1533_write(0, 0x74, 1, 0x00, dev);
ali1533_write(0, 0x75, 1, 0x00, dev);
ali1533_write(0, 0x76, 1, 0x00, dev);
if (dev->type == 1)
ali1533_write(0, 0x78, 0x00, dev);
ali1533_write(0, 0x78, 1, 0x00, dev);
unmask_a20_in_smm = 1;
}

8
src/chipset/ali1621.c
View File

@@ -255,7 +255,7 @@ ali1621_mask_bar(ali1621_t *dev)
}
static void
ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ali1621_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
ali1621_t *dev = (ali1621_t *) priv;
@@ -581,7 +581,7 @@ ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
ali1621_read(UNUSED(int func), int addr, void *priv)
ali1621_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const ali1621_t *dev = (ali1621_t *) priv;
uint8_t ret = 0xff;
@@ -647,10 +647,10 @@ ali1621_reset(void *priv)
dev->pci_conf[0xf2] = dev->pci_conf[0xf6] = dev->pci_conf[0xfa] = dev->pci_conf[0xfe] = 0x21;
dev->pci_conf[0xf3] = dev->pci_conf[0xf7] = dev->pci_conf[0xfb] = dev->pci_conf[0xff] = 0x43;
ali1621_write(0, 0x83, 0x08, dev);
ali1621_write(0, 0x83, 1, 0x08, dev);
for (uint8_t i = 0; i < 4; i++)
ali1621_write(0, 0x84 + i, 0x00, dev);
ali1621_write(0, 0x84 + i, 1, 0x00, dev);
}
static void

4
src/chipset/ims8848.c
View File

@@ -292,7 +292,7 @@ ims8848_read(uint16_t addr, void *priv)
}
static void
ims8849_pci_write(int func, int addr, uint8_t val, void *priv)
ims8849_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
ims8848_t *dev = (ims8848_t *) priv;
@@ -326,7 +326,7 @@ ims8849_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
ims8849_pci_read(int func, int addr, void *priv)
ims8849_pci_read(int func, UNUSED(int len), int addr, void *priv)
{
const ims8848_t *dev = (ims8848_t *) priv;
uint8_t ret = 0xff;

26
src/chipset/intel_420ex.c
View File

@@ -183,7 +183,7 @@ i420ex_drb_recalc(i420ex_t *dev)
static void
i420ex_write(int func, int addr, uint8_t val, void *priv)
i420ex_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
@@ -397,7 +397,7 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
i420ex_read(int func, int addr, void *priv)
i420ex_read(int func, int addr, UNUSED(int len), void *priv)
{
const i420ex_t *dev = (i420ex_t *) priv;
uint8_t ret;
@@ -472,31 +472,31 @@ i420ex_reset(void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
i420ex_write(0, 0x48, 0x00, priv);
i420ex_write(0, 0x48, 1, 0x00, priv);
/* Disable the PIC mouse latch. */
i420ex_write(0, 0x4e, 0x03, priv);
i420ex_write(0, 0x4e, 1, 0x03, priv);
for (uint8_t i = 0; i < 7; i++)
i420ex_write(0, 0x59 + i, 0x00, priv);
i420ex_write(0, 0x59 + i, 1, 0x00, priv);
for (uint8_t i = 0; i <= 4; i++)
dev->regs[0x60 + i] = 0x01;
dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */
dev->smram_locked = 0;
i420ex_write(0, 0x70, 0x00, priv);
i420ex_write(0, 0x70, 1, 0x00, priv);
mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
i420ex_write(0, 0xa0, 0x08, priv);
i420ex_write(0, 0xa2, 0x00, priv);
i420ex_write(0, 0xa4, 0x00, priv);
i420ex_write(0, 0xa5, 0x00, priv);
i420ex_write(0, 0xa6, 0x00, priv);
i420ex_write(0, 0xa7, 0x00, priv);
i420ex_write(0, 0xa8, 0x0f, priv);
i420ex_write(0, 0xa0, 1, 0x08, priv);
i420ex_write(0, 0xa2, 1, 0x00, priv);
i420ex_write(0, 0xa4, 1, 0x00, priv);
i420ex_write(0, 0xa5, 1, 0x00, priv);
i420ex_write(0, 0xa6, 1, 0x00, priv);
i420ex_write(0, 0xa7, 1, 0x00, priv);
i420ex_write(0, 0xa8, 1, 0x0f, priv);
}
static void

40
src/chipset/intel_4x0.c
View File

@@ -243,7 +243,7 @@ pm2_cntrl_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
}
static void
i4x0_write(int func, int addr, uint8_t val, void *priv)
i4x0_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
uint8_t *regs = (uint8_t *) dev->regs;
@@ -1535,7 +1535,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
i4x0_read(int func, int addr, void *priv)
i4x0_read(int func, int addr, UNUSED(int len), void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
uint8_t ret = 0xff;
@@ -1563,12 +1563,12 @@ i4x0_reset(void *priv)
memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x59, 0x00, priv);
i4x0_write(0, 0x59, 1, 0x00, priv);
else
i4x0_write(0, 0x59, 0x0f, priv);
i4x0_write(0, 0x59, 1, 0x0f, priv);
for (uint8_t i = 0; i < 6; i++)
i4x0_write(0, 0x5a + i, 0x00, priv);
i4x0_write(0, 0x5a + i, 1, 0x00, priv);
for (uint8_t i = 0; i <= dev->max_drb; i++)
dev->regs[0x60 + i] = dev->drb_default;
@@ -1582,18 +1582,18 @@ i4x0_reset(void *priv)
if (dev->type >= INTEL_430FX) {
dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x02, priv);
i4x0_write(0, 0x72, 1, 0x02, priv);
} else if (dev->type >= INTEL_430LX) {
dev->regs[0x72] &= 0xf7; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x00, priv);
i4x0_write(0, 0x72, 1, 0x00, priv);
} else {
dev->regs[0x57] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x57, 0x02, priv);
i4x0_write(0, 0x57, 1, 0x02, priv);
}
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv);
1, (dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv);
}
}
@@ -1932,24 +1932,24 @@ i4x0_init(const device_t *info)
else if (dev->type >= INTEL_440LX)
cpu_set_agp_speed(cpu_busspeed);
i4x0_write(regs[0x59], 0x59, 0x00, dev);
i4x0_write(regs[0x5a], 0x5a, 0x00, dev);
i4x0_write(regs[0x5b], 0x5b, 0x00, dev);
i4x0_write(regs[0x5c], 0x5c, 0x00, dev);
i4x0_write(regs[0x5d], 0x5d, 0x00, dev);
i4x0_write(regs[0x5e], 0x5e, 0x00, dev);
i4x0_write(regs[0x5f], 0x5f, 0x00, dev);
i4x0_write(regs[0x59], 0x59, 1, 0x00, dev);
i4x0_write(regs[0x5a], 0x5a, 1, 0x00, dev);
i4x0_write(regs[0x5b], 0x5b, 1, 0x00, dev);
i4x0_write(regs[0x5c], 0x5c, 1, 0x00, dev);
i4x0_write(regs[0x5d], 0x5d, 1, 0x00, dev);
i4x0_write(regs[0x5e], 0x5e, 1, 0x00, dev);
i4x0_write(regs[0x5f], 0x5f, 1, 0x00, dev);
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x72, 0x02, dev);
i4x0_write(0, 0x72, 1, 0x02, dev);
else if (dev->type >= INTEL_430LX)
i4x0_write(0, 0x72, 0x00, dev);
i4x0_write(0, 0x72, 1, 0x00, dev);
else
i4x0_write(0, 0x57, 0x02, dev);
i4x0_write(0, 0x57, 1, 0x02, dev);
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev);
1, (dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev);
}
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev, &dev->pci_slot);

16
src/chipset/intel_i450kx.c
View File

@@ -126,7 +126,7 @@ i450kx_vid_buf_recalc(i450kx_t *dev, int bus)
}
static void
pb_write(int func, int addr, uint8_t val, void *priv)
pb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
i450kx_t *dev = (i450kx_t *) priv;
@@ -371,7 +371,7 @@ pb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
pb_read(int func, int addr, void *priv)
pb_read(int func, int addr, UNUSED(int len), void *priv)
{
const i450kx_t *dev = (i450kx_t *) priv;
uint8_t ret = 0xff;
@@ -400,7 +400,7 @@ mc_fill_drbs(i450kx_t *dev)
}
static void
mc_write(int func, int addr, uint8_t val, void *priv)
mc_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
i450kx_t *dev = (i450kx_t *) priv;
@@ -601,7 +601,7 @@ mc_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
mc_read(int func, int addr, void *priv)
mc_read(int func, int addr, UNUSED(int len), void *priv)
{
const i450kx_t *dev = (i450kx_t *) priv;
uint8_t ret = 0xff;
@@ -707,9 +707,9 @@ i450kx_reset(void *priv)
#endif
i450kx_smram_recalc(dev, 1);
i450kx_vid_buf_recalc(dev, 1);
pb_write(0, 0x59, 0x30, dev);
pb_write(0, 0x59, 1, 0x30, dev);
for (i = 0x5a; i <= 0x5f; i++)
pb_write(0, i, 0x33, dev);
pb_write(0, i, 1, 0x33, dev);
/* Defaults MC */
dev->mc_pci_conf[0x00] = 0x86;
@@ -779,9 +779,9 @@ i450kx_reset(void *priv)
i450kx_smram_recalc(dev, 0);
i450kx_vid_buf_recalc(dev, 0);
mc_write(0, 0x59, 0x03, dev);
mc_write(0, 0x59, 1, 0x03, dev);
for (i = 0x5a; i <= 0x5f; i++)
mc_write(0, i, 0x00, dev);
mc_write(0, i, 1, 0x00, dev);
for (i = 0x60; i <= 0x6f; i++)
dev->mc_pci_conf[i] = 0x01;
}

90
src/chipset/intel_piix.c
View File

@@ -464,7 +464,7 @@ piix_trap_update(void *priv)
}
static void
piix_write(int func, int addr, uint8_t val, void *priv)
piix_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
piix_t *dev = (piix_t *) priv;
uint8_t *fregs;
@@ -1192,7 +1192,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
piix_read(int func, int addr, void *priv)
piix_read(int func, int addr, UNUSED(int len), void *priv)
{
piix_t *dev = (piix_t *) priv;
uint8_t ret = 0xff;
@@ -1447,68 +1447,68 @@ piix_reset(void *priv)
const piix_t *dev = (piix_t *) priv;
if (dev->type > 3) {
piix_write(3, 0x04, 0x00, priv);
piix_write(3, 0x5b, 0x00, priv);
piix_write(3, 0x04, 1, 0x00, priv);
piix_write(3, 0x5b, 1, 0x00, priv);
} else {
piix_write(0, 0xa0, 0x08, priv);
piix_write(0, 0xa2, 0x00, priv);
piix_write(0, 0xa4, 0x00, priv);
piix_write(0, 0xa5, 0x00, priv);
piix_write(0, 0xa6, 0x00, priv);
piix_write(0, 0xa7, 0x00, priv);
piix_write(0, 0xa8, 0x0f, priv);
piix_write(0, 0xa0, 1, 0x08, priv);
piix_write(0, 0xa2, 1, 0x00, priv);
piix_write(0, 0xa4, 1, 0x00, priv);
piix_write(0, 0xa5, 1, 0x00, priv);
piix_write(0, 0xa6, 1, 0x00, priv);
piix_write(0, 0xa7, 1, 0x00, priv);
piix_write(0, 0xa8, 1, 0x0f, priv);
}
/* Disable the PIC mouse latch. */
piix_write(0, 0x4e, 0x03, priv);
piix_write(0, 0x4e, 1, 0x03, priv);
if (dev->type == 5)
piix_write(0, 0xe1, 0x40, priv);
piix_write(1, 0x04, 0x00, priv);
piix_write(0, 0xe1, 1, 0x40, priv);
piix_write(1, 0x04, 1, 0x00, priv);
if (dev->type == 5) {
piix_write(1, 0x09, 0x8a, priv);
piix_write(1, 0x10, 0xf1, priv);
piix_write(1, 0x11, 0x01, priv);
piix_write(1, 0x14, 0xf5, priv);
piix_write(1, 0x15, 0x03, priv);
piix_write(1, 0x18, 0x71, priv);
piix_write(1, 0x19, 0x01, priv);
piix_write(1, 0x1c, 0x75, priv);
piix_write(1, 0x1d, 0x03, priv);
piix_write(1, 0x09, 1, 0x8a, priv);
piix_write(1, 0x10, 1, 0xf1, priv);
piix_write(1, 0x11, 1, 0x01, priv);
piix_write(1, 0x14, 1, 0xf5, priv);
piix_write(1, 0x15, 1, 0x03, priv);
piix_write(1, 0x18, 1, 0x71, priv);
piix_write(1, 0x19, 1, 0x01, priv);
piix_write(1, 0x1c, 1, 0x75, priv);
piix_write(1, 0x1d, 1, 0x03, priv);
} else
piix_write(1, 0x09, 0x80, priv);
piix_write(1, 0x20, 0x01, priv);
piix_write(1, 0x21, 0x00, priv);
piix_write(1, 0x41, 0x00, priv);
piix_write(1, 0x43, 0x00, priv);
piix_write(1, 0x09, 1, 0x80, priv);
piix_write(1, 0x20, 1, 0x01, priv);
piix_write(1, 0x21, 1, 0x00, priv);
piix_write(1, 0x41, 1, 0x00, priv);
piix_write(1, 0x43, 1, 0x00, priv);
ide_pri_disable();
ide_sec_disable();
if (dev->type >= 3) {
piix_write(2, 0x04, 0x00, priv);
piix_write(2, 0x04, 1, 0x00, priv);
if (dev->type == 5) {
piix_write(2, 0x10, 0x00, priv);
piix_write(2, 0x11, 0x00, priv);
piix_write(2, 0x12, 0x00, priv);
piix_write(2, 0x13, 0x00, priv);
piix_write(2, 0x10, 1, 0x00, priv);
piix_write(2, 0x11, 1, 0x00, priv);
piix_write(2, 0x12, 1, 0x00, priv);
piix_write(2, 0x13, 1, 0x00, priv);
} else {
piix_write(2, 0x20, 0x01, priv);
piix_write(2, 0x21, 0x00, priv);
piix_write(2, 0x22, 0x00, priv);
piix_write(2, 0x23, 0x00, priv);
piix_write(2, 0x20, 1, 0x01, priv);
piix_write(2, 0x21, 1, 0x00, priv);
piix_write(2, 0x22, 1, 0x00, priv);
piix_write(2, 0x23, 1, 0x00, priv);
}
}
if (dev->type >= 4) {
piix_write(0, 0xb0, is_pentium ? 0x00 : 0x04, priv);
piix_write(3, 0x40, 0x01, priv);
piix_write(3, 0x41, 0x00, priv);
piix_write(3, 0x5b, 0x00, priv);
piix_write(3, 0x80, 0x00, priv);
piix_write(3, 0x90, 0x01, priv);
piix_write(3, 0x91, 0x00, priv);
piix_write(3, 0xd2, 0x00, priv);
piix_write(0, 0xb0, 1, is_pentium ? 0x00 : 0x04, priv);
piix_write(3, 0x40, 1, 0x01, priv);
piix_write(3, 0x41, 1, 0x00, priv);
piix_write(3, 0x5b, 1, 0x00, priv);
piix_write(3, 0x80, 1, 0x00, priv);
piix_write(3, 0x90, 1, 0x01, priv);
piix_write(3, 0x91, 1, 0x00, priv);
piix_write(3, 0xd2, 1, 0x00, priv);
}
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);

22
src/chipset/intel_sio.c
View File

@@ -135,7 +135,7 @@ sio_timer_readw(uint16_t addr, void *priv)
}
static void
sio_write(int func, int addr, uint8_t val, void *priv)
sio_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
sio_t *dev = (sio_t *) priv;
uint8_t old;
@@ -324,7 +324,7 @@ sio_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sio_read(int func, int addr, void *priv)
sio_read(int func, int addr, UNUSED(int len), void *priv)
{
const sio_t *dev = (sio_t *) priv;
uint8_t ret;
@@ -473,20 +473,20 @@ sio_reset(void *priv)
const sio_t *dev = (sio_t *) priv;
/* Disable the PIC mouse latch. */
sio_write(0, 0x4d, 0x40, priv);
sio_write(0, 0x4d, 1, 0x40, priv);
sio_write(0, 0x57, 0x04, priv);
sio_write(0, 0x57, 1, 0x04, priv);
dma_set_params(1, 0xffffffff);
if (dev->id == 0x03) {
sio_write(0, 0xa0, 0x08, priv);
sio_write(0, 0xa2, 0x00, priv);
sio_write(0, 0xa4, 0x00, priv);
sio_write(0, 0xa5, 0x00, priv);
sio_write(0, 0xa6, 0x00, priv);
sio_write(0, 0xa7, 0x00, priv);
sio_write(0, 0xa8, 0x0f, priv);
sio_write(0, 0xa0, 1, 0x08, priv);
sio_write(0, 0xa2, 1, 0x00, priv);
sio_write(0, 0xa4, 1, 0x00, priv);
sio_write(0, 0xa5, 1, 0x00, priv);
sio_write(0, 0xa6, 1, 0x00, priv);
sio_write(0, 0xa7, 1, 0x00, priv);
sio_write(0, 0xa8, 1, 0x0f, priv);
}
}

5
src/chipset/opti822.c
View File

@@ -48,7 +48,6 @@ typedef struct opti822_t {
uint8_t pci_regs[256];
} opti822_t;
// #define ENABLE_OPTI822_LOG 1
#ifdef ENABLE_OPTI822_LOG
int opti822_do_log = ENABLE_OPTI822_LOG;
@@ -131,7 +130,7 @@ opti822_update_irqs(opti822_t *dev, int set)
}
static void
opti822_pci_write(int func, int addr, uint8_t val, void *priv)
opti822_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
opti822_t *dev = (opti822_t *) priv;
int irq;
@@ -336,7 +335,7 @@ opti822_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
opti822_pci_read(int func, int addr, void *priv)
opti822_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
const opti822_t *dev = (opti822_t *) priv;
uint8_t ret;

8
src/chipset/sis_5511.c
View File

@@ -76,7 +76,7 @@ typedef struct sis_5511_t {
} sis_5511_t;
static void
sis_5511_write(int func, int addr, uint8_t val, void *priv)
sis_5511_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
@@ -87,7 +87,7 @@ sis_5511_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5511_read(int func, int addr, void *priv)
sis_5511_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
uint8_t ret = 0xff;
@@ -101,7 +101,7 @@ sis_5511_read(int func, int addr, void *priv)
}
static void
sis_5513_write(int func, int addr, uint8_t val, void *priv)
sis_5513_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
@@ -114,7 +114,7 @@ sis_5513_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5513_read(int func, int addr, void *priv)
sis_5513_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
uint8_t ret = 0xff;

8
src/chipset/sis_5571.c
View File

@@ -75,7 +75,7 @@ typedef struct sis_5571_t {
} sis_5571_t;
static void
sis_5571_write(int func, int addr, uint8_t val, void *priv)
sis_5571_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
@@ -86,7 +86,7 @@ sis_5571_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5571_read(int func, int addr, void *priv)
sis_5571_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
uint8_t ret = 0xff;
@@ -100,7 +100,7 @@ sis_5571_read(int func, int addr, void *priv)
}
static void
sis_5572_write(int func, int addr, uint8_t val, void *priv)
sis_5572_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
@@ -120,7 +120,7 @@ sis_5572_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5572_read(int func, int addr, void *priv)
sis_5572_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
uint8_t ret = 0xff;

8
src/chipset/sis_5581.c
View File

@@ -75,7 +75,7 @@ typedef struct sis_5581_t {
} sis_5581_t;
static void
sis_5581_write(int func, int addr, uint8_t val, void *priv)
sis_5581_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
@@ -86,7 +86,7 @@ sis_5581_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5581_read(int func, int addr, void *priv)
sis_5581_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
uint8_t ret = 0xff;
@@ -100,7 +100,7 @@ sis_5581_read(int func, int addr, void *priv)
}
static void
sis_5582_write(int func, int addr, uint8_t val, void *priv)
sis_5582_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
@@ -120,7 +120,7 @@ sis_5582_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5582_read(int func, int addr, void *priv)
sis_5582_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
uint8_t ret = 0xff;

8
src/chipset/sis_5591.c
View File

@@ -76,7 +76,7 @@ typedef struct sis_5591_t {
} sis_5591_t;
static void
sis_5591_write(int func, int addr, uint8_t val, void *priv)
sis_5591_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
@@ -89,7 +89,7 @@ sis_5591_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5591_read(int func, int addr, void *priv)
sis_5591_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
uint8_t ret = 0xff;
@@ -105,7 +105,7 @@ sis_5591_read(int func, int addr, void *priv)
}
static void
sis_5595_write(int func, int addr, uint8_t val, void *priv)
sis_5595_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
@@ -125,7 +125,7 @@ sis_5595_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5595_read(int func, int addr, void *priv)
sis_5595_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
uint8_t ret = 0xff;

8
src/chipset/sis_5600.c
View File

@@ -76,7 +76,7 @@ typedef struct sis_5600_t {
} sis_5600_t;
static void
sis_5600_write(int func, int addr, uint8_t val, void *priv)
sis_5600_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
@@ -89,7 +89,7 @@ sis_5600_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5600_read(int func, int addr, void *priv)
sis_5600_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
uint8_t ret = 0xff;
@@ -105,7 +105,7 @@ sis_5600_read(int func, int addr, void *priv)
}
static void
sis_5595_write(int func, int addr, uint8_t val, void *priv)
sis_5595_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
@@ -125,7 +125,7 @@ sis_5595_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_5595_read(int func, int addr, void *priv)
sis_5595_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
uint8_t ret = 0xff;

52
src/chipset/sis_85c496.c
View File

@@ -216,7 +216,7 @@ sis_85c496_drb_recalc(sis_85c496_t *dev)
/* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */
static void
sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
sis_85c49x_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t old;
@@ -507,7 +507,7 @@ sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
sis_85c49x_pci_read(UNUSED(int func), int addr, void *priv)
sis_85c49x_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t ret = dev->pci_conf[addr];
@@ -577,35 +577,35 @@ sis_85c496_reset(void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
sis_85c49x_pci_write(0, 0x44, 0x00, dev);
sis_85c49x_pci_write(0, 0x45, 0x00, dev);
sis_85c49x_pci_write(0, 0x58, 0x00, dev);
sis_85c49x_pci_write(0, 0x59, 0x00, dev);
sis_85c49x_pci_write(0, 0x5a, 0x00, dev);
// sis_85c49x_pci_write(0, 0x5a, 0x06, dev);
sis_85c49x_pci_write(0, 0x44, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x45, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x58, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x59, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x5a, 1, 0x00, dev);
// sis_85c49x_pci_write(0, 0x5a, 1, 0x06, dev);
for (uint8_t i = 0; i < 8; i++)
dev->pci_conf[0x48 + i] = 0x02;
sis_85c49x_pci_write(0, 0x80, 0x00, dev);
sis_85c49x_pci_write(0, 0x81, 0x00, dev);
sis_85c49x_pci_write(0, 0x9e, 0x00, dev);
sis_85c49x_pci_write(0, 0x8d, 0x00, dev);
sis_85c49x_pci_write(0, 0xa0, 0xff, dev);
sis_85c49x_pci_write(0, 0xa1, 0xff, dev);
sis_85c49x_pci_write(0, 0xc0, 0x00, dev);
sis_85c49x_pci_write(0, 0xc1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc2, 0x00, dev);
sis_85c49x_pci_write(0, 0xc3, 0x00, dev);
sis_85c49x_pci_write(0, 0xc8, 0x00, dev);
sis_85c49x_pci_write(0, 0xc9, 0x00, dev);
sis_85c49x_pci_write(0, 0xca, 0x00, dev);
sis_85c49x_pci_write(0, 0xcb, 0x00, dev);
sis_85c49x_pci_write(0, 0x80, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x81, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x9e, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0x8d, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xa0, 1, 0xff, dev);
sis_85c49x_pci_write(0, 0xa1, 1, 0xff, dev);
sis_85c49x_pci_write(0, 0xc0, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc1, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc2, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc3, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc8, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc9, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xca, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xcb, 1, 0x00, dev);
sis_85c49x_pci_write(0, 0xd0, 0x79, dev);
sis_85c49x_pci_write(0, 0xd1, 0xff, dev);
sis_85c49x_pci_write(0, 0xd0, 0x78, dev);
sis_85c49x_pci_write(0, 0xd4, 0x00, dev);
sis_85c49x_pci_write(0, 0xd0, 1, 0x79, dev);
sis_85c49x_pci_write(0, 0xd1, 1, 0xff, dev);
sis_85c49x_pci_write(0, 0xd0, 1, 0x78, dev);
sis_85c49x_pci_write(0, 0xd4, 1, 0x00, dev);
dev->pci_conf[0x67] = 0x00;
dev->pci_conf[0xc6] = 0x00;

38
src/chipset/sis_85c50x.c
View File

@@ -199,7 +199,7 @@ sis_85c50x_smm_recalc(sis_85c50x_t *dev)
}
static void
sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
sis_85c50x_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
@@ -311,7 +311,7 @@ sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_85c50x_read(int func, int addr, void *priv)
sis_85c50x_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_85c50x_t *dev = (sis_85c50x_t *) priv;
uint8_t ret = 0xff;
@@ -344,7 +344,7 @@ sis_85c50x_ide_recalc(sis_85c50x_t *dev)
}
static void
sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
sis_85c50x_sb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
@@ -393,7 +393,7 @@ sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
sis_85c50x_sb_read(int func, int addr, void *priv)
sis_85c50x_sb_read(int func, int addr, UNUSED(int len), void *priv)
{
const sis_85c50x_t *dev = (sis_85c50x_t *) priv;
uint8_t ret = 0xff;
@@ -553,17 +553,17 @@ sis_85c50x_reset(void *priv)
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
sis_85c50x_write(0, 0x51, 0x00, dev);
sis_85c50x_write(0, 0x53, 0x00, dev);
sis_85c50x_write(0, 0x54, 0x00, dev);
sis_85c50x_write(0, 0x55, 0x00, dev);
sis_85c50x_write(0, 0x56, 0x00, dev);
sis_85c50x_write(0, 0x5b, 0x00, dev);
sis_85c50x_write(0, 0x60, 0x00, dev);
sis_85c50x_write(0, 0x64, 0x00, dev);
sis_85c50x_write(0, 0x65, 0x00, dev);
sis_85c50x_write(0, 0x68, 0x00, dev);
sis_85c50x_write(0, 0x69, 0xff, dev);
sis_85c50x_write(0, 0x51, 1, 0x00, dev);
sis_85c50x_write(0, 0x53, 1, 0x00, dev);
sis_85c50x_write(0, 0x54, 1, 0x00, dev);
sis_85c50x_write(0, 0x55, 1, 0x00, dev);
sis_85c50x_write(0, 0x56, 1, 0x00, dev);
sis_85c50x_write(0, 0x5b, 1, 0x00, dev);
sis_85c50x_write(0, 0x60, 1, 0x00, dev);
sis_85c50x_write(0, 0x64, 1, 0x00, dev);
sis_85c50x_write(0, 0x65, 1, 0x00, dev);
sis_85c50x_write(0, 0x68, 1, 0x00, dev);
sis_85c50x_write(0, 0x69, 1, 0xff, dev);
if (dev->type & 1) {
for (uint8_t i = 0; i < 8; i++)
@@ -586,10 +586,10 @@ sis_85c50x_reset(void *priv)
dev->pci_conf_sb[0x0b] = 0x06;
if (dev->type & 2)
dev->pci_conf_sb[0x0e] = 0x80;
sis_85c50x_sb_write(0, 0x41, 0x80, dev);
sis_85c50x_sb_write(0, 0x42, 0x80, dev);
sis_85c50x_sb_write(0, 0x43, 0x80, dev);
sis_85c50x_sb_write(0, 0x44, 0x80, dev);
sis_85c50x_sb_write(0, 0x41, 1, 0x80, dev);
sis_85c50x_sb_write(0, 0x42, 1, 0x80, dev);
sis_85c50x_sb_write(0, 0x43, 1, 0x80, dev);
sis_85c50x_sb_write(0, 0x44, 1, 0x80, dev);
if (dev->type & 2) {
/* IDE (SiS 5503) */

20
src/chipset/stpc.c
View File

@@ -213,7 +213,7 @@ stpc_localbus_read(uint16_t addr, void *priv)
}
static void
stpc_nb_write(int func, int addr, uint8_t val, void *priv)
stpc_nb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
@@ -260,7 +260,7 @@ stpc_nb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
stpc_nb_read(int func, int addr, void *priv)
stpc_nb_read(int func, int addr, UNUSED(int len), void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
@@ -337,7 +337,7 @@ stpc_ide_bm_handlers(stpc_t *dev)
}
static void
stpc_ide_write(int func, int addr, uint8_t val, void *priv)
stpc_ide_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
@@ -445,7 +445,7 @@ stpc_ide_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
stpc_ide_read(int func, int addr, void *priv)
stpc_ide_read(int func, int addr, UNUSED(int len), void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
@@ -466,12 +466,12 @@ stpc_ide_read(int func, int addr, void *priv)
}
static void
stpc_isab_write(int func, int addr, uint8_t val, void *priv)
stpc_isab_write(int func, int addr, int len, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
if ((func == 1) && (dev->local != STPC_ATLAS)) {
stpc_ide_write(0, addr, val, priv);
stpc_ide_write(0, addr, len, val, priv);
return;
}
@@ -507,13 +507,13 @@ stpc_isab_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
stpc_isab_read(int func, int addr, void *priv)
stpc_isab_read(int func, int addr, int len, void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if ((func == 1) && (dev->local != STPC_ATLAS))
ret = stpc_ide_read(0, addr, priv);
ret = stpc_ide_read(0, addr, len, priv);
else if (func > 0)
ret = 0xff;
else
@@ -524,7 +524,7 @@ stpc_isab_read(int func, int addr, void *priv)
}
static void
stpc_usb_write(int func, int addr, uint8_t val, void *priv)
stpc_usb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
@@ -571,7 +571,7 @@ stpc_usb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
stpc_usb_read(int func, int addr, void *priv)
stpc_usb_read(int func, int addr, UNUSED(int len), void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;

5
src/chipset/umc_8886.c
View File

@@ -84,6 +84,7 @@
#include <86box/machine.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -187,7 +188,7 @@ umc_8886_irq_recalc(umc_8886_t *dev)
}
static void
umc_8886_write(int func, int addr, uint8_t val, void *priv)
umc_8886_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
umc_8886_t *dev = (umc_8886_t *) priv;
@@ -293,7 +294,7 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
umc_8886_read(int func, int addr, void *priv)
umc_8886_read(int func, int addr, UNUSED(int len), void *priv)
{
const umc_8886_t *dev = (umc_8886_t *) priv;
uint8_t ret = 0xff;

4
src/chipset/umc_8890.c
View File

@@ -119,7 +119,7 @@ um8890_smram(umc_8890_t *dev)
}
static void
um8890_write(int func, int addr, uint8_t val, void *priv)
um8890_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
@@ -158,7 +158,7 @@ um8890_write(int func, int addr, uint8_t val, void *priv)
static uint8_t
um8890_read(int func, int addr, void *priv)
um8890_read(int func, int addr, UNUSED(int len), void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
uint8_t ret = 0xff;

4
src/chipset/umc_hb4.c
View File

@@ -275,7 +275,7 @@ hb4_smram(hb4_t *dev)
}
static void
hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv)
hb4_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
hb4_t *dev = (hb4_t *) priv;
@@ -336,7 +336,7 @@ hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
hb4_read(int func, int addr, void *priv)
hb4_read(int func, int addr, UNUSED(int len), void *priv)
{
const hb4_t *dev = (hb4_t *) priv;
uint8_t ret = 0xff;

15
src/chipset/via_apollo.c
View File

@@ -29,6 +29,7 @@
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
#include <86box/spd.h>
#include <86box/agpgart.h>
@@ -225,7 +226,7 @@ via_apollo_setup(via_apollo_t *dev)
}
static void
via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
via_apollo_host_bridge_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
via_apollo_t *dev = (via_apollo_t *) priv;
if (func)
@@ -684,7 +685,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
via_apollo_read(int func, int addr, void *priv)
via_apollo_read(int func, int addr, UNUSED(int len), void *priv)
{
const via_apollo_t *dev = (via_apollo_t *) priv;
uint8_t ret = 0xff;
@@ -701,11 +702,11 @@ via_apollo_read(int func, int addr, void *priv)
}
static void
via_apollo_write(int func, int addr, uint8_t val, void *priv)
via_apollo_write(int func, int addr, int len, uint8_t val, void *priv)
{
switch (func) {
case 0:
via_apollo_host_bridge_write(func, addr, val, priv);
via_apollo_host_bridge_write(func, addr, len, val, priv);
break;
default:
break;
@@ -715,9 +716,9 @@ via_apollo_write(int func, int addr, uint8_t val, void *priv)
static void
via_apollo_reset(void *priv)
{
via_apollo_write(0, 0x61, 0x00, priv);
via_apollo_write(0, 0x62, 0x00, priv);
via_apollo_write(0, 0x63, 0x00, priv);
via_apollo_write(0, 0x61, 1, 0x00, priv);
via_apollo_write(0, 0x62, 1, 0x00, priv);
via_apollo_write(0, 0x63, 1, 0x00, priv);
}
static void *

46
src/chipset/via_pipc.c
View File

@@ -170,8 +170,8 @@ pipc_log(const char *fmt, ...)
static void pipc_sgd_handlers(pipc_t *dev, uint8_t modem);
static void pipc_codec_handlers(pipc_t *dev, uint8_t modem);
static void pipc_sb_handlers(pipc_t *dev, uint8_t modem);
static uint8_t pipc_read(int func, int addr, void *priv);
static void pipc_write(int func, int addr, uint8_t val, void *priv);
static uint8_t pipc_read(int func, int addr, int len, void *priv);
static void pipc_write(int func, int addr, int len, uint8_t val, void *priv);
static void
pipc_io_trap_pact(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
@@ -930,7 +930,7 @@ pipc_sb_get_buffer(int32_t *buffer, int len, void *priv)
}
static uint8_t
pipc_read(int func, int addr, void *priv)
pipc_read(int func, int addr, UNUSED(int len), void *priv)
{
pipc_t *dev = (pipc_t *) priv;
uint8_t ret = 0xff;
@@ -1026,7 +1026,7 @@ pipc_ddma_update(pipc_t *dev, int addr)
}
static void
pipc_write(int func, int addr, uint8_t val, void *priv)
pipc_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
pipc_t *dev = (pipc_t *) priv;
int c;
@@ -1661,34 +1661,34 @@ pipc_reset(void *priv)
pipc_t *dev = (pipc_t *) priv;
uint8_t pm_func = dev->usb[1] ? 4 : 3;
pipc_write(pm_func, 0x41, 0x00, priv);
pipc_write(pm_func, 0x48, 0x01, priv);
pipc_write(pm_func, 0x49, 0x00, priv);
pipc_write(pm_func, 0x41, 1, 0x00, priv);
pipc_write(pm_func, 0x48, 1, 0x01, priv);
pipc_write(pm_func, 0x49, 1, 0x00, priv);
dev->power_regs[0x42] = ((dev->local >> 16) == VIA_PIPC_586) ? 0x00 : 0x50;
acpi_set_irq_line(dev->acpi, 0x00);
pipc_write(1, 0x04, 0x80, priv);
pipc_write(1, 0x09, 0x85, priv);
pipc_write(1, 0x10, 0xf1, priv);
pipc_write(1, 0x11, 0x01, priv);
pipc_write(1, 0x14, 0xf5, priv);
pipc_write(1, 0x15, 0x03, priv);
pipc_write(1, 0x18, 0x71, priv);
pipc_write(1, 0x19, 0x01, priv);
pipc_write(1, 0x1c, 0x75, priv);
pipc_write(1, 0x1d, 0x03, priv);
pipc_write(1, 0x20, 0x01, priv);
pipc_write(1, 0x21, 0xcc, priv);
pipc_write(1, 0x04, 1, 0x80, priv);
pipc_write(1, 0x09, 1, 0x85, priv);
pipc_write(1, 0x10, 1, 0xf1, priv);
pipc_write(1, 0x11, 1, 0x01, priv);
pipc_write(1, 0x14, 1, 0xf5, priv);
pipc_write(1, 0x15, 1, 0x03, priv);
pipc_write(1, 0x18, 1, 0x71, priv);
pipc_write(1, 0x19, 1, 0x01, priv);
pipc_write(1, 0x1c, 1, 0x75, priv);
pipc_write(1, 0x1d, 1, 0x03, priv);
pipc_write(1, 0x20, 1, 0x01, priv);
pipc_write(1, 0x21, 1, 0xcc, priv);
if (dev->local <= VIA_PIPC_586B)
pipc_write(1, 0x40, 0x04, priv);
pipc_write(1, 0x40, 1, 0x04, priv);
else
pipc_write(1, 0x40, 0x00, priv);
pipc_write(1, 0x40, 1, 0x00, priv);
if (dev->local < VIA_PIPC_586B)
pipc_write(0, 0x44, 0x00, priv);
pipc_write(0, 0x44, 1, 0x00, priv);
pipc_write(0, 0x77, 0x00, priv);
pipc_write(0, 0x77, 1, 0x00, priv);
sff_set_slot(dev->bm[0], dev->pci_slot);
sff_set_slot(dev->bm[1], dev->pci_slot);

16
src/chipset/via_vt82c505.c
View File

@@ -38,7 +38,7 @@ typedef struct vt82c505_t {
} vt82c505_t;
static void
vt82c505_write(int func, int addr, uint8_t val, void *priv)
vt82c505_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t irq;
@@ -126,7 +126,7 @@ vt82c505_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
vt82c505_read(int func, int addr, void *priv)
vt82c505_read(int func, int addr, UNUSED(int len), void *priv)
{
const vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t ret = 0xff;
@@ -147,7 +147,7 @@ vt82c505_out(uint16_t addr, uint8_t val, void *priv)
if (addr == 0xa8)
dev->index = val;
else if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
vt82c505_write(0, dev->index, val, priv);
vt82c505_write(0, dev->index, 1, val, priv);
}
static uint8_t
@@ -157,7 +157,7 @@ vt82c505_in(uint16_t addr, void *priv)
uint8_t ret = 0xff;
if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
ret = vt82c505_read(0, dev->index, priv);
ret = vt82c505_read(0, dev->index, 1, priv);
return ret;
}
@@ -173,16 +173,16 @@ vt82c505_reset(void *priv)
for (uint8_t i = 0x80; i <= 0x9f; i++) {
switch (i) {
case 0x81:
vt82c505_write(0, i, 0x01, priv);
vt82c505_write(0, i, 1, 0x01, priv);
break;
case 0x84:
vt82c505_write(0, i, 0x03, priv);
vt82c505_write(0, i, 1, 0x03, priv);
break;
case 0x93:
vt82c505_write(0, i, 0x40, priv);
vt82c505_write(0, i, 1, 0x40, priv);
break;
default:
vt82c505_write(0, i, 0x00, priv);
vt82c505_write(0, i, 1, 0x00, priv);
break;
}
}

8
src/chipset/vl82c59x.c
View File

@@ -208,7 +208,7 @@ vl82c59x_set_pm_io(void *priv)
}
static void
vl82c59x_write(int func, int addr, uint8_t val, void *priv)
vl82c59x_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
@@ -275,7 +275,7 @@ vl82c59x_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
vl82c59x_read(int func, int addr, void *priv)
vl82c59x_read(int func, int addr, UNUSED(int len), void *priv)
{
const vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t ret = 0xff;
@@ -292,7 +292,7 @@ vl82c59x_read(int func, int addr, void *priv)
}
static void
vl82c59x_sb_write(int func, int addr, uint8_t val, void *priv)
vl82c59x_sb_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t irq;
@@ -380,7 +380,7 @@ vl82c59x_sb_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
vl82c59x_sb_read(int func, int addr, void *priv)
vl82c59x_sb_read(int func, int addr, UNUSED(int len), void *priv)
{
const vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t ret = 0xff;

5
src/device/pci_bridge.c
View File

@@ -28,6 +28,7 @@
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#define PCI_BRIDGE_DEC_21150 0x10110022
#define PCI_BRIDGE_DEC_21152 0x10110024
@@ -93,7 +94,7 @@ pci_bridge_get_bus_index(void *priv)
}
static void
pci_bridge_write(int func, int addr, uint8_t val, void *priv)
pci_bridge_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
pci_bridge_t *dev = (pci_bridge_t *) priv;
@@ -391,7 +392,7 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
pci_bridge_read(int func, int addr, void *priv)
pci_bridge_read(int func, int addr, UNUSED(int len), void *priv)
{
const pci_bridge_t *dev = (pci_bridge_t *) priv;
uint8_t ret;

100
src/device/vfio.c
View File

@@ -246,12 +246,12 @@ vfio_log(const char *fmt, ...)
#endif
static uint8_t vfio_bar_gettype(vfio_device_t *dev, vfio_region_t *bar);
static uint8_t vfio_config_readb(int func, int addr, void *priv);
static uint16_t vfio_config_readw(int func, int addr, void *priv);
static uint32_t vfio_config_readl(int func, int addr, void *priv);
static void vfio_config_writeb(int func, int addr, uint8_t val, void *priv);
static void vfio_config_writew(int func, int addr, uint16_t val, void *priv);
static void vfio_config_writel(int func, int addr, uint32_t val, void *priv);
static uint8_t vfio_config_readb(int func, int addr, int len, void *priv);
static uint16_t vfio_config_readw(int func, int addr, int len, void *priv);
static uint32_t vfio_config_readl(int func, int addr, int len, void *priv);
static void vfio_config_writeb(int func, int addr, int len, uint8_t val, void *priv);
static void vfio_config_writew(int func, int addr, int len, uint16_t val, void *priv);
static void vfio_config_writel(int func, int addr, int len, uint32_t val, void *priv);
static void vfio_irq_intx_setpin(vfio_device_t *dev);
static void vfio_irq_msi_disable(vfio_device_t *dev);
static void vfio_irq_msix_disable(vfio_device_t *dev);
@@ -371,7 +371,7 @@ vfio_quirk_configmirror_readb(uint32_t addr, void *priv)
vfio_mem_readb_fd(addr, bar);
/* Read configuration register. */
uint8_t ret = vfio_config_readb(0, addr - bar->quirks.configmirror.offset, dev);
uint8_t ret = vfio_config_readb(0, addr - bar->quirks.configmirror.offset, 1, dev);
vfio_log_op("VFIO %s: Config mirror: Read %02X from index %02X\n",
dev->name, ret, addr - bar->quirks.configmirror.offset);
@@ -388,7 +388,7 @@ vfio_quirk_configmirror_readw(uint32_t addr, void *priv)
vfio_mem_readw_fd(addr, bar);
/* Read configuration register. */
uint16_t ret = vfio_config_readw(0, addr - bar->quirks.configmirror.offset, dev);
uint16_t ret = vfio_config_readw(0, addr - bar->quirks.configmirror.offset, 2, dev);
vfio_log_op("VFIO %s: Config mirror: Read %04X from index %02X\n",
dev->name, ret, addr - bar->quirks.configmirror.offset);
@@ -405,7 +405,7 @@ vfio_quirk_configmirror_readl(uint32_t addr, void *priv)
vfio_mem_readl_fd(addr, bar);
/* Read configuration register. */
uint32_t ret = vfio_config_readl(0, addr - bar->quirks.configmirror.offset, dev);
uint32_t ret = vfio_config_readl(0, addr - bar->quirks.configmirror.offset, 4, dev);
vfio_log_op("VFIO %s: Config mirror: Read %08X from index %02X\n",
dev->name, ret, addr - bar->quirks.configmirror.offset);
@@ -421,7 +421,7 @@ vfio_quirk_configmirror_writeb(uint32_t addr, uint8_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: Config mirror: Write %02X to index %02X\n",
dev->name, val, addr - bar->quirks.configmirror.offset);
vfio_config_writeb(0, addr - bar->quirks.configmirror.offset, val, dev);
vfio_config_writeb(0, addr - bar->quirks.configmirror.offset, 1, val, dev);
}
static void
@@ -433,7 +433,7 @@ vfio_quirk_configmirror_writew(uint32_t addr, uint16_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: Config mirror: Write %04X to index %02X\n",
dev->name, val, addr - bar->quirks.configmirror.offset);
vfio_config_writew(0, addr - bar->quirks.configmirror.offset, val, dev);
vfio_config_writew(0, addr - bar->quirks.configmirror.offset, 2, val, dev);
}
static void
@@ -445,7 +445,7 @@ vfio_quirk_configmirror_writel(uint32_t addr, uint32_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: Config mirror: Write %08X to index %02X\n",
dev->name, val, addr - bar->quirks.configmirror.offset);
vfio_config_writel(0, addr - bar->quirks.configmirror.offset, val, dev);
vfio_config_writel(0, addr - bar->quirks.configmirror.offset, 4, val, dev);
}
static void
@@ -541,11 +541,11 @@ vfio_quirk_configwindow_data_readb(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
uint32_t index = bar->quirks.configwindow.index;
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[0].start, dev);
ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[0].start, 1, dev);
vfio_log_op("VFIO %s: Config window: Read %02X from primary index %08X\n",
dev->name, ret, index);
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[1].start, dev);
ret = vfio_config_readb(0, index - bar->quirks.configwindow.offset[1].start, 1, dev);
vfio_log_op("VFIO %s: Config window: Read %02X from secondary index %08X\n",
dev->name, ret, index);
}
@@ -565,11 +565,11 @@ vfio_quirk_configwindow_data_readw(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
uint32_t index = bar->quirks.configwindow.index;
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[0].start, dev);
ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[0].start, 2, dev);
vfio_log_op("VFIO %s: Config window: Read %04X from primary index %08X\n",
dev->name, ret, index);
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[1].start, dev);
ret = vfio_config_readw(0, index - bar->quirks.configwindow.offset[1].start, 2, dev);
vfio_log_op("VFIO %s: Config window: Read %04X from secondary index %08X\n",
dev->name, ret, index);
}
@@ -589,11 +589,11 @@ vfio_quirk_configwindow_data_readl(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
uint32_t index = bar->quirks.configwindow.index;
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[0].start, dev);
ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[0].start, 4, dev);
vfio_log_op("VFIO %s: Config window: Read %08X from primary index %08X\n",
dev->name, ret, index);
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[1].start, dev);
ret = vfio_config_readl(0, index - bar->quirks.configwindow.offset[1].start, 4, dev);
vfio_log_op("VFIO %s: Config window: Read %08X from secondary index %08X\n",
dev->name, ret, index);
}
@@ -612,12 +612,12 @@ vfio_quirk_configwindow_data_writeb(uint16_t addr, uint8_t val, void *priv)
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
vfio_log_op("VFIO %s: Config window: Write %02X to primary index %08X\n",
dev->name, val, index);
vfio_config_writeb(0, index - bar->quirks.configwindow.offset[0].start, val, dev);
vfio_config_writeb(0, index - bar->quirks.configwindow.offset[0].start, 1, val, dev);
return;
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
vfio_log_op("VFIO %s: Config window: Write %02X to secondary index %08X\n",
dev->name, val, index);
vfio_config_writeb(0, index - bar->quirks.configwindow.offset[1].start, val, dev);
vfio_config_writeb(0, index - bar->quirks.configwindow.offset[1].start, 1, val, dev);
return;
}
@@ -636,12 +636,12 @@ vfio_quirk_configwindow_data_writew(uint16_t addr, uint16_t val, void *priv)
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
vfio_log_op("VFIO %s: Config window: Write %04X to primary index %08X\n",
dev->name, val, index);
vfio_config_writew(0, index - bar->quirks.configwindow.offset[0].start, val, dev);
vfio_config_writew(0, index - bar->quirks.configwindow.offset[0].start, 2, val, dev);
return;
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
vfio_log_op("VFIO %s: Config window: Write %04X to secondary index %08X\n",
dev->name, val, index);
vfio_config_writew(0, index - bar->quirks.configwindow.offset[1].start, val, dev);
vfio_config_writew(0, index - bar->quirks.configwindow.offset[1].start, 2, val, dev);
return;
}
@@ -660,12 +660,12 @@ vfio_quirk_configwindow_data_writel(uint16_t addr, uint32_t val, void *priv)
if ((index >= bar->quirks.configwindow.offset[0].start) && (index <= bar->quirks.configwindow.offset[0].end)) {
vfio_log_op("VFIO %s: Config window: Write %08X to primary index %08X\n",
dev->name, val, index);
vfio_config_writel(0, index - bar->quirks.configwindow.offset[0].start, val, dev);
vfio_config_writel(0, index - bar->quirks.configwindow.offset[0].start, 4, val, dev);
return;
} else if ((index >= bar->quirks.configwindow.offset[1].start) && (index <= bar->quirks.configwindow.offset[1].end)) {
vfio_log_op("VFIO %s: Config window: Write %08X to secondary index %08X\n",
dev->name, val, index);
vfio_config_writel(0, index - bar->quirks.configwindow.offset[1].start, val, dev);
vfio_config_writel(0, index - bar->quirks.configwindow.offset[1].start, 4, val, dev);
return;
}
@@ -1037,7 +1037,7 @@ vfio_quirk_nvidia3d0_data_readb(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
if ((prev_state == NVIDIA_3D0_READ) && (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000))) {
ret = vfio_config_readb(0, dev->quirks.nvidia3d0.index, dev);
ret = vfio_config_readb(0, dev->quirks.nvidia3d0.index, 1, dev);
vfio_log_op("VFIO %s: NVIDIA 3D0: Read %02X from index %08X\n", dev->name,
ret, dev->quirks.nvidia3d0.index);
}
@@ -1057,7 +1057,7 @@ vfio_quirk_nvidia3d0_data_readw(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
if ((prev_state == NVIDIA_3D0_READ) && (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000))) {
ret = vfio_config_readw(0, dev->quirks.nvidia3d0.index, dev);
ret = vfio_config_readw(0, dev->quirks.nvidia3d0.index, 2, dev);
vfio_log_op("VFIO %s: NVIDIA 3D0: Read %04X from index %08X\n", dev->name,
ret, dev->quirks.nvidia3d0.index);
}
@@ -1077,7 +1077,7 @@ vfio_quirk_nvidia3d0_data_readl(uint16_t addr, void *priv)
/* Read configuration register if part of the main PCI configuration space. */
if ((prev_state == NVIDIA_3D0_READ) && (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000))) {
ret = vfio_config_readl(0, dev->quirks.nvidia3d0.index, dev);
ret = vfio_config_readl(0, dev->quirks.nvidia3d0.index, 4, dev);
vfio_log_op("VFIO %s: NVIDIA 3D0: Read %08X from index %08X\n", dev->name,
ret, dev->quirks.nvidia3d0.index);
}
@@ -1104,7 +1104,7 @@ vfio_quirk_nvidia3d0_data_writeb(uint16_t addr, uint8_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: NVIDIA 3D0: Write %02X to index %08X\n", dev->name,
val, dev->quirks.nvidia3d0.index);
vfio_config_writeb(0, dev->quirks.nvidia3d0.index, val, dev);
vfio_config_writeb(0, dev->quirks.nvidia3d0.index, val, 1, dev);
return;
}
}
@@ -1131,7 +1131,7 @@ vfio_quirk_nvidia3d0_data_writew(uint16_t addr, uint16_t val, void *priv)
if (((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00001800) || ((dev->quirks.nvidia3d0.index & 0xffffff00) == 0x00088000)) {
vfio_log_op("VFIO %s: NVIDIA 3D0: Write %04X to index %08X\n", dev->name,
val, dev->quirks.nvidia3d0.index);
vfio_config_writew(0, dev->quirks.nvidia3d0.index, val, dev);
vfio_config_writew(0, dev->quirks.nvidia3d0.index, val, 2, dev);
return;
}
}
@@ -1159,7 +1159,7 @@ vfio_quirk_nvidia3d0_data_writel(uint16_t addr, uint32_t val, void *priv)
/* Write configuration register. */
vfio_log_op("VFIO %s: NVIDIA 3D0: Write %08X to index %08X\n", dev->name,
val, dev->quirks.nvidia3d0.index);
vfio_config_writel(0, dev->quirks.nvidia3d0.index, val, dev);
vfio_config_writel(0, dev->quirks.nvidia3d0.index, val, 4, dev);
return;
}
}
@@ -1198,7 +1198,7 @@ vfio_quirk_remap(vfio_device_t *dev, vfio_region_t *bar, uint8_t enable)
/* BAR 2 configuration space mirror, and BAR 1/4 configuration space window. */
if (j && !i) {
/* QEMU only enables the mirror here if BAR 2 is 64-bit capable. */
if ((bar->bar_id == 2) && ((vfio_config_readb(0, 0x18, dev) & 0x07) == 0x04))
if ((bar->bar_id == 2) && ((vfio_config_readb(0, 0x18, 1, dev) & 0x07) == 0x04))
vfio_quirk_configmirror(dev, bar, 0x4000, 0, enable);
else if (bar->bar_id == 4)
vfio_quirk_configwindow(dev, bar, 0x00, 4, 0x04, 4, 0x4000, 0x4000, enable);
@@ -1479,7 +1479,7 @@ ceilpow2(uint32_t size)
}
static uint8_t
vfio_config_readb(int func, int addr, void *priv)
vfio_config_readb(int func, int addr, UNUSED(int len), void *priv)
{
vfio_device_t *dev = (vfio_device_t *) priv;
if (func)
@@ -1602,19 +1602,19 @@ end:
}
static uint16_t
vfio_config_readw(int func, int addr, void *priv)
vfio_config_readw(int func, int addr, UNUSED(int len), void *priv)
{
return vfio_config_readb(func, addr, priv) | (vfio_config_readb(func, addr + 1, priv) << 8);
return vfio_config_readb(func, addr, 2, priv) | (vfio_config_readb(func, addr + 1, 2, priv) << 8);
}
static uint32_t
vfio_config_readl(int func, int addr, void *priv)
vfio_config_readl(int func, int addr, UNUSED(int len), void *priv)
{
return vfio_config_readb(func, addr, priv) | (vfio_config_readb(func, addr + 1, priv) << 8) | (vfio_config_readb(func, addr + 2, priv) << 16) | (vfio_config_readb(func, addr + 3, priv) << 24);
return vfio_config_readb(func, addr, 4, priv) | (vfio_config_readb(func, addr + 1, 4, priv) << 8) | (vfio_config_readb(func, addr + 2, 4, priv) << 16) | (vfio_config_readb(func, addr + 3, 4, priv) << 24);
}
static void
vfio_config_writeb(int func, int addr, uint8_t val, void *priv)
vfio_config_writeb(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
vfio_device_t *dev = (vfio_device_t *) priv;
if (func)
@@ -1850,19 +1850,19 @@ end:
}
static void
vfio_config_writew(int func, int addr, uint16_t val, void *priv)
vfio_config_writew(int func, int addr, UNUSED(int len), uint16_t val, void *priv)
{
vfio_config_writeb(func, addr, val, priv);
vfio_config_writeb(func, addr | 1, val >> 8, priv);
vfio_config_writeb(func, addr, 2, val, priv);
vfio_config_writeb(func, addr | 1, 2, val >> 8, priv);
}
static void
vfio_config_writel(int func, int addr, uint32_t val, void *priv)
vfio_config_writel(int func, int addr, UNUSED(int len), uint32_t val, void *priv)
{
vfio_config_writeb(func, addr, val, priv);
vfio_config_writeb(func, addr | 1, val >> 8, priv);
vfio_config_writeb(func, addr | 2, val >> 16, priv);
vfio_config_writeb(func, addr | 3, val >> 24, priv);
vfio_config_writeb(func, addr, 4, val, priv);
vfio_config_writeb(func, addr | 1, 4, val >> 8, priv);
vfio_config_writeb(func, addr | 2, 4, val >> 16, priv);
vfio_config_writeb(func, addr | 3, 4, val >> 24, priv);
}
static void
@@ -2549,13 +2549,13 @@ vfio_dev_prereset(vfio_device_t *dev)
/* Extra steps for devices with power management capability. */
if (dev->pm_cap) {
/* Make sure the device is in D0 state. */
uint8_t pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, dev),
uint8_t pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, 1, dev),
state = pm_ctrl & 0x03;
if (state) {
pm_ctrl &= ~0x03;
vfio_config_writeb(0, dev->pm_cap + 4, pm_ctrl, dev);
vfio_config_writeb(0, dev->pm_cap + 4, pm_ctrl, 1, dev);
pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, dev);
pm_ctrl = vfio_config_readb(0, dev->pm_cap + 4, 1, dev);
state = pm_ctrl & 0x03;
if (state)
vfio_log("VFIO %s: Device stuck in D%d state\n", dev->name, state);
@@ -2566,10 +2566,10 @@ vfio_dev_prereset(vfio_device_t *dev)
}
/* Enable function-level reset if supported. */
dev->can_flr_reset = (dev->pcie_cap && (vfio_config_readb(0, dev->pcie_cap + 7, dev) & 0x10)) || (dev->af_cap && (vfio_config_readb(0, dev->af_cap + 3, dev) & 0x02));
dev->can_flr_reset = (dev->pcie_cap && (vfio_config_readb(0, dev->pcie_cap + 7, 1, dev) & 0x10)) || (dev->af_cap && (vfio_config_readb(0, dev->af_cap + 3, 1, dev) & 0x02));
/* Disable bus master, BARs, expansion ROM and VGA regions; also enable INTx. */
vfio_config_writew(0, 0x04, vfio_config_readw(0, 0x04, dev) & ~0x0407, dev);
vfio_config_writew(0, 0x04, vfio_config_readw(0, 0x04, 2, dev) & ~0x0407, dev);
}
static void

5
src/disk/hdc_ide_cmd640.c
View File

@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -289,7 +290,7 @@ cmd640_vlb_readl(uint16_t addr, void *priv)
}
static void
cmd640_pci_write(int func, int addr, uint8_t val, void *priv)
cmd640_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
@@ -367,7 +368,7 @@ cmd640_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
cmd640_pci_read(int func, int addr, void *priv)
cmd640_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
uint8_t ret = 0xff;

5
src/disk/hdc_ide_cmd646.c
View File

@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -296,7 +297,7 @@ cmd646_bios_handler(cmd646_t *dev)
}
static void
cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
cmd646_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
int reg50 = dev->regs[0x50];
@@ -481,7 +482,7 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
cmd646_pci_read(int func, int addr, void *priv)
cmd646_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
uint8_t ret = 0xff;

5
src/disk/hdc_ide_rz1000.c
View File

@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -108,7 +109,7 @@ rz1000_ide_handlers(rz1000_t *dev)
}
static void
rz1000_pci_write(int func, int addr, uint8_t val, void *priv)
rz1000_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
rz1000_t *dev = (rz1000_t *) priv;
@@ -138,7 +139,7 @@ rz1000_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
rz1000_pci_read(int func, int addr, void *priv)
rz1000_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
rz1000_t *dev = (rz1000_t *) priv;
uint8_t ret = 0xff;

5
src/disk/hdc_ide_w83769f.c
View File

@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -233,7 +234,7 @@ w83769f_vlb_readl(uint16_t addr, void *priv)
}
static void
w83769f_pci_write(int func, int addr, uint8_t val, void *priv)
w83769f_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
@@ -252,7 +253,7 @@ w83769f_pci_write(int func, int addr, uint8_t val, void *priv)
}
static uint8_t
w83769f_pci_read(int func, int addr, void *priv)
w83769f_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
uint8_t ret = 0xff;

8
src/include/86box/pci.h
View File

@@ -266,12 +266,12 @@ extern void pci_remap_bus(uint8_t bus_index, uint8_t bus_number);
extern void pci_register_bus_slot(int bus, int card, int type, int inta, int intb, int intc, int intd);
/* Add a PCI card. */
extern void pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot);
extern void pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, int len, void *priv),
void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot);
/* Add an instance of the PCI bridge. */
extern void pci_add_bridge(uint8_t agp, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv,
extern void pci_add_bridge(uint8_t agp, uint8_t (*read)(int func, int addr, int len, void *priv),
void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv,
uint8_t *slot);
/* Register the cards that have been added into slots. */

4
src/network/net_ne2000.c
View File

@@ -799,7 +799,7 @@ nic_update_bios(nic_t *dev)
}
static uint8_t
nic_pci_read(UNUSED(int func), int addr, void *priv)
nic_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const nic_t *dev = (nic_t *) priv;
uint8_t ret = 0x00;
@@ -894,7 +894,7 @@ nic_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
nic_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
nic_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
nic_t *dev = (nic_t *) priv;
uint8_t valxor;

4
src/network/net_pcnet.c
View File

@@ -2588,7 +2588,7 @@ pcnet_ioset(nic_t *dev, uint16_t addr, int len)
}
static void
pcnet_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
pcnet_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
nic_t *dev = (nic_t *) priv;
uint8_t valxor;
@@ -2671,7 +2671,7 @@ pcnet_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
static uint8_t
pcnet_pci_read(UNUSED(int func), int addr, void *priv)
pcnet_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const nic_t *dev = (nic_t *) priv;

4
src/network/net_rtl8139.c
View File

@@ -3100,7 +3100,7 @@ rtl8139_timer(void *priv)
}
static uint8_t
rtl8139_pci_read(UNUSED(int func), int addr, void *priv)
rtl8139_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const RTL8139State *s = (RTL8139State *) priv;
@@ -3157,7 +3157,7 @@ rtl8139_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
rtl8139_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
rtl8139_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
RTL8139State *s = (RTL8139State *) priv;

4
src/network/net_tulip.c
View File

@@ -1182,7 +1182,7 @@ tulip_srom_crc(uint8_t *eeprom)
}
static uint8_t
tulip_pci_read(UNUSED(int func), int addr, void *priv)
tulip_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const TULIPState *s = (TULIPState *) priv;
uint8_t ret = 0;
@@ -1301,7 +1301,7 @@ tulip_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
tulip_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
tulip_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
TULIPState *s = (TULIPState *) priv;

52
src/pci.c
View File

@@ -40,15 +40,15 @@ typedef struct pci_card_t {
uint8_t irq_routing[PCI_INT_PINS_NUM];
void * priv;
void (*write)(int func, int addr, uint8_t val, void *priv);
uint8_t (*read)(int func, int addr, void *priv);
void (*write)(int func, int addr, int len, uint8_t val, void *priv);
uint8_t (*read)(int func, int addr, int len, void *priv);
} pci_card_t;
typedef struct pci_card_desc_t {
uint8_t type;
void * priv;
void (*write)(int func, int addr, uint8_t val, void *priv);
uint8_t (*read)(int func, int addr, void *priv);
void (*write)(int func, int addr, int len, uint8_t val, void *priv);
uint8_t (*read)(int func, int addr, int len, void *priv);
uint8_t *slot;
} pci_card_desc_t;
@@ -91,6 +91,7 @@ static int pci_card;
static int pci_bus;
static int pci_key;
static int pci_trc_reg = 0;
static int pci_access_len = 0;
static uint32_t pci_enable = 0x00000000;
static void pci_reset_regs(void);
@@ -174,7 +175,7 @@ pci_irq(uint8_t slot, uint8_t pci_int, int level, int set, uint8_t *irq_state)
return;
if (pci_flags & FLAG_NO_IRQ_STEERING)
irq_line = pci_cards[slot].read(0, 0x3c, pci_cards[slot].priv);
irq_line = pci_cards[slot].read(0, 0x3c, 1, pci_cards[slot].priv);
else {
irq_routing = pci_cards[slot].irq_routing[pci_int_index];
@@ -349,12 +350,12 @@ pci_reg_write(uint16_t port, uint8_t val)
slot = pci_card_to_slot_mapping[pci_bus_number_to_index_mapping[pci_bus]][pci_card];
if (slot != PCI_CARD_INVALID) {
if (pci_cards[slot].write)
pci_cards[slot].write(pci_func, pci_index | (port & 0x03), val, pci_cards[slot].priv);
pci_cards[slot].write(pci_func, pci_index | (port & 0x03), pci_access_len, val, pci_cards[slot].priv);
}
pci_log("PCI: [WB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X = %02X\n",
pci_log("PCI: [WB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X, length %I = %02X\n",
(port >= 0xc000) ? 2 : 1, slot,
(slot == PCI_CARD_INVALID) ? "non-existent" : (pci_cards[slot].write ? "used" : "unused"),
pci_card, pci_bus, pci_func, pci_index | (port & 0x03), val);
pci_card, pci_bus, pci_func, pci_index | (port & 0x03), pci_access_len, val);
}
static void
@@ -364,6 +365,8 @@ pci_reset_regs(void)
pci_enable = 0x00000000;
pci_flags &= ~(FLAG_CONFIG_IO_ON | FLAG_CONFIG_M1_IO_ON);
pci_access_len = 1;
}
void
@@ -496,16 +499,24 @@ pci_writew(uint16_t port, uint16_t val, UNUSED(void *priv))
{
if (port & 0x0001) {
/* Non-aligned access, split into two byte accesses. */
if (pci_access_len == 1)
pci_access_len = 2;
pci_write(port, val & 0xff, priv);
pci_write(port + 1, val >> 8, priv);
if (pci_access_len == 2)
pci_access_len = 1;
} else {
/* Aligned access, still split because we cheat. */
switch (port) {
case 0xcfc:
case 0xcfe:
case 0xc000 ... 0xcffe:
if (pci_access_len == 1)
pci_access_len = 2;
pci_write(port, val & 0xff, priv);
pci_write(port + 1, val >> 8, priv);
if (pci_access_len == 2)
pci_access_len = 1;
break;
default:
@@ -519,8 +530,10 @@ pci_writel(uint16_t port, uint32_t val, UNUSED(void *priv))
{
if (port & 0x0003) {
/* Non-aligned access, split into two word accesses. */
pci_access_len = 4;
pci_writew(port, val & 0xffff, priv);
pci_writew(port + 2, val >> 16, priv);
pci_access_len = 1;
} else {
/* Aligned access. */
switch (port) {
@@ -545,8 +558,10 @@ pci_writel(uint16_t port, uint32_t val, UNUSED(void *priv))
case 0xcfc:
case 0xc000 ... 0xcffc:
/* Still split because we cheat. */
pci_access_len = 4;
pci_writew(port, val & 0xffff, priv);
pci_writew(port + 2, val >> 16, priv);
pci_access_len = 1;
break;
default:
@@ -569,12 +584,12 @@ pci_reg_read(uint16_t port)
slot = pci_card_to_slot_mapping[pci_bus_number_to_index_mapping[pci_bus]][pci_card];
if (slot != PCI_CARD_INVALID) {
if (pci_cards[slot].read)
ret = pci_cards[slot].read(pci_func, pci_index | (port & 0x03), pci_cards[slot].priv);
ret = pci_cards[slot].read(pci_func, pci_index | (port & 0x03), pci_access_len, pci_cards[slot].priv);
}
pci_log("PCI: [RB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X = %02X\n",
pci_log("PCI: [RB] Mechanism #%i, slot %02X, %s card %02X:%02X, function %02X, index %02X, length %i = %02X\n",
(port >= 0xc000) ? 2 : 1, slot,
(slot == PCI_CARD_INVALID) ? "non-existent" : (pci_cards[slot].read ? "used" : "unused"),
pci_card, pci_bus, pci_func, pci_index | (port & 0x03), ret);
pci_card, pci_bus, pci_access_len, pci_index | (port & 0x03), pci_func, ret);
return ret;
}
@@ -643,8 +658,12 @@ pci_readw(uint16_t port, UNUSED(void *priv))
case 0xcfc:
case 0xcfe:
case 0xc000 ... 0xcffe:
if (pci_access_len == 1)
pci_access_len = 2;
ret = pci_read(port, priv);
ret |= ((uint16_t) pci_read(port + 1, priv)) << 8;
if (pci_access_len == 2)
pci_access_len = 1;
break;
default:
@@ -662,8 +681,10 @@ pci_readl(uint16_t port, UNUSED(void *priv))
if (port & 0x0003) {
/* Non-aligned access, split into two word accesses. */
pci_access_len = 4;
ret = pci_readw(port, priv);
ret |= ((uint32_t) pci_readw(port + 2, priv)) << 16;
pci_access_len = 1;
} else {
/* Aligned access. */
switch (port) {
@@ -682,8 +703,10 @@ pci_readl(uint16_t port, UNUSED(void *priv))
case 0xcfc:
case 0xc000 ... 0xcffc:
/* Still split because we cheat. */
pci_access_len = 4;
ret = pci_readw(port, priv);
ret |= ((uint32_t) pci_readw(port + 2, priv)) << 16;
pci_access_len = 1;
break;
}
}
@@ -781,8 +804,8 @@ pci_find_slot(uint8_t add_type, uint8_t ignore_slot)
/* Add a PCI card. */
void
pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot)
pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, int len, void *priv),
void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot)
{
pci_card_desc_t *dev;
@@ -853,7 +876,8 @@ pci_register_card(int pci_card)
/* Add an instance of the PCI bridge. */
void
pci_add_bridge(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot)
pci_add_bridge(uint8_t add_type, uint8_t (*read)(int func, int addr, int len, void *priv),
void (*write)(int func, int addr, int len, uint8_t val, void *priv), void *priv, uint8_t *slot)
{
pci_card_t *card;
uint8_t bridge_slot = (add_type == PCI_ADD_NORMAL) ? last_normal_pci_card_id : pci_find_slot(add_type, 0xff);

4
src/pci_dummy.c
View File

@@ -38,7 +38,7 @@ pci_dummy_interrupt(int set, pci_dummy_t *dev)
}
static uint8_t
pci_dummy_read(uint16_t port, void *priv)
pci_dummy_read(uint16_t port, UNUSED(int len), void *priv)
{
pci_dummy_t *dev = (pci_dummy_t *) priv;
uint8_t ret = 0xff;
@@ -90,7 +90,7 @@ pci_dummy_readl(uint16_t port, void *priv)
}
static void
pci_dummy_write(uint16_t port, UNUSED(uint8_t val), void *priv)
pci_dummy_write(uint16_t port, UNUSED(uint8_t val), UNUSED(int len), void *priv)
{
pci_dummy_t *dev = (pci_dummy_t *) priv;

4
src/scsi/scsi_buslogic.c
View File

@@ -1117,7 +1117,7 @@ BuslogicBIOSUpdate(buslogic_data_t *bl)
}
static uint8_t
BuslogicPCIRead(UNUSED(int func), int addr, void *priv)
BuslogicPCIRead(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const x54x_t *dev = (x54x_t *) priv;
#ifdef ENABLE_BUSLOGIC_LOG
@@ -1203,7 +1203,7 @@ BuslogicPCIRead(UNUSED(int func), int addr, void *priv)
}
static void
BuslogicPCIWrite(UNUSED(int func), int addr, uint8_t val, void *priv)
BuslogicPCIWrite(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;

4
src/scsi/scsi_ncr53c8xx.c
View File

@@ -2283,7 +2283,7 @@ uint8_t ncr53c8xx_pci_regs[256];
bar_t ncr53c8xx_pci_bar[4];
static uint8_t
ncr53c8xx_pci_read(UNUSED(int func), int addr, void *priv)
ncr53c8xx_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
@@ -2387,7 +2387,7 @@ ncr53c8xx_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
ncr53c8xx_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ncr53c8xx_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
uint8_t valxor;

17
src/scsi/scsi_pcscsi.c
View File

@@ -1997,7 +1997,7 @@ esp_bios_disable(esp_t *dev)
#define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08
static uint8_t
esp_pci_read(UNUSED(int func), int addr, void *priv)
esp_pci_read(UNUSED(int func), int addr, int len, void *priv)
{
esp_t *dev = (esp_t *) priv;
@@ -2009,12 +2009,15 @@ esp_pci_read(UNUSED(int func), int addr, void *priv)
if (!dev->has_bios || dev->local)
return 0x22;
else {
if (nmc93cxx_eeprom_read(dev->eeprom))
return 0x22;
else {
dev->eeprom->dev.out = 1;
return 2;
uint8_t ret = 0x22;
if (len == 1) {
/* First byte of address space is AND-ed with EEPROM DO line */
if (!nmc93cxx_eeprom_read(dev->eeprom))
ret &= 0x00;
}
return ret;
}
break;
case 0x01:
@@ -2084,7 +2087,7 @@ esp_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
esp_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
esp_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
esp_t *dev = (esp_t *) priv;
uint8_t valxor;

8
src/sound/snd_audiopci.c
View File

@@ -1905,7 +1905,7 @@ update_legacy(es137x_t *dev, uint32_t old_legacy_ctrl)
}
static uint8_t
es1370_pci_read(int func, int addr, void *priv)
es1370_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
const es137x_t *dev = (es137x_t *) priv;
@@ -2001,7 +2001,7 @@ es1370_pci_read(int func, int addr, void *priv)
}
static uint8_t
es1371_pci_read(int func, int addr, void *priv)
es1371_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
const es137x_t *dev = (es137x_t *) priv;
@@ -2103,7 +2103,7 @@ es137x_io_set(es137x_t *dev, int set)
}
static void
es1370_pci_write(int func, int addr, uint8_t val, void *priv)
es1370_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
es137x_t *dev = (es137x_t *) priv;
@@ -2154,7 +2154,7 @@ es1370_pci_write(int func, int addr, uint8_t val, void *priv)
}
static void
es1371_pci_write(int func, int addr, uint8_t val, void *priv)
es1371_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
es137x_t *dev = (es137x_t *) priv;

4
src/sound/snd_cmi8x38.c
View File

@@ -966,7 +966,7 @@ cmi8x38_remap(cmi8x38_t *dev)
}
static uint8_t
cmi8x38_pci_read(int func, int addr, void *priv)
cmi8x38_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
const cmi8x38_t *dev = (cmi8x38_t *) priv;
uint8_t ret = 0xff;
@@ -980,7 +980,7 @@ cmi8x38_pci_read(int func, int addr, void *priv)
}
static void
cmi8x38_pci_write(int func, int addr, uint8_t val, void *priv)
cmi8x38_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;

4
src/video/vid_ati_mach64.c
View File

@@ -5129,7 +5129,7 @@ mach64_writel_be(uint32_t addr, uint32_t val, void *priv)
}
uint8_t
mach64_pci_read(UNUSED(int func), int addr, void *priv)
mach64_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const mach64_t *mach64 = (mach64_t *) priv;
@@ -5214,7 +5214,7 @@ mach64_pci_read(UNUSED(int func), int addr, void *priv)
}
void
mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
mach64_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;

4
src/video/vid_ati_mach8.c
View File

@@ -7092,7 +7092,7 @@ ati8514_pos_write(uint16_t port, uint8_t val, void *priv)
}
static uint8_t
mach32_pci_read(UNUSED(int func), int addr, void *priv)
mach32_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const mach_t *mach = (mach_t *) priv;
uint8_t ret = 0x00;
@@ -7171,7 +7171,7 @@ mach32_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
mach32_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
mach32_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
if ((addr >= 0x30) && (addr <= 0x33) && !mach->has_bios)

5
src/video/vid_bochs_vbe.c
View File

@@ -39,6 +39,7 @@
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
@@ -628,7 +629,7 @@ bochs_vbe_in(uint16_t addr, void *priv)
}
static uint8_t
bochs_vbe_pci_read(const int func, const int addr, void *priv)
bochs_vbe_pci_read(const int func, const int addr, UNUSED(const int len), void *priv)
{
const bochs_vbe_t *dev = (bochs_vbe_t *) priv;
uint8_t ret = 0x00;
@@ -711,7 +712,7 @@ bochs_vbe_disable_handlers(bochs_vbe_t *dev)
}
static void
bochs_vbe_pci_write(const int func, const int addr, const uint8_t val, void *priv)
bochs_vbe_pci_write(const int func, const int addr, UNUSED(const int len), const uint8_t val, void *priv)
{
bochs_vbe_t *dev = (bochs_vbe_t *) priv;

4
src/video/vid_chips_69000.c
View File

@@ -2141,7 +2141,7 @@ chips_69000_in(uint16_t addr, void *priv)
}
static uint8_t
chips_69000_pci_read(UNUSED(int func), int addr, void *priv)
chips_69000_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
chips_69000_t *chips = (chips_69000_t *) priv;
uint8_t ret = 0x00;
@@ -2215,7 +2215,7 @@ chips_69000_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
chips_69000_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
chips_69000_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
chips_69000_t *chips = (chips_69000_t *) priv;

4
src/video/vid_cl54xx.c
View File

@@ -3934,7 +3934,7 @@ gd54xx_start_blit(uint32_t cpu_dat, uint32_t count, gd54xx_t *gd54xx, svga_t *sv
}
static uint8_t
cl_pci_read(UNUSED(int func), int addr, void *priv)
cl_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const gd54xx_t *gd54xx = (gd54xx_t *) priv;
const svga_t *svga = &gd54xx->svga;
@@ -4046,7 +4046,7 @@ cl_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
cl_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
cl_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
const svga_t *svga = &gd54xx->svga;

4
src/video/vid_et4000w32.c
View File

@@ -2652,7 +2652,7 @@ et4000w32p_io_set(et4000w32p_t *et4000)
}
uint8_t
et4000w32p_pci_read(UNUSED(int func), int addr, void *priv)
et4000w32p_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const et4000w32p_t *et4000 = (et4000w32p_t *) priv;
@@ -2709,7 +2709,7 @@ et4000w32p_pci_read(UNUSED(int func), int addr, void *priv)
}
void
et4000w32p_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
et4000w32p_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
et4000w32p_t *et4000 = (et4000w32p_t *) priv;
svga_t *svga = &et4000->svga;

4
src/video/vid_mga.c
View File

@@ -6337,7 +6337,7 @@ mystique_tvp3026_gpio_write(uint8_t cntl, uint8_t data, void *priv)
}
static uint8_t
mystique_pci_read(UNUSED(int func), int addr, void *priv)
mystique_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
uint8_t ret = 0x00;
@@ -6574,7 +6574,7 @@ mystique_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
mystique_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
mystique_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;

12
src/video/vid_s3.c
View File

@@ -458,8 +458,8 @@ static void s3_accel_out_l(uint16_t port, uint32_t val, void *priv);
static uint8_t s3_accel_in(uint16_t port, void *priv);
static uint16_t s3_accel_in_w(uint16_t port, void *priv);
static uint32_t s3_accel_in_l(uint16_t port, void *priv);
static uint8_t s3_pci_read(int func, int addr, void *priv);
static void s3_pci_write(int func, int addr, uint8_t val, void *priv);
static uint8_t s3_pci_read(int func, int addr, int len, void *priv);
static void s3_pci_write(int func, int addr, int len, uint8_t val, void *priv);
#ifdef ENABLE_S3_LOG
int s3_do_log = ENABLE_S3_LOG;
@@ -2013,7 +2013,7 @@ s3_accel_write_fifo(s3_t *s3, uint32_t addr, uint8_t val)
int addr_lo = addr & 1;
if (svga->crtc[0x53] & 0x08) {
if ((addr >= 0x08000) && (addr <= 0x0803f))
s3_pci_write(0, addr & 0xff, val, s3);
s3_pci_write(0, addr & 0xff, 1, val, s3);
}
switch (addr & 0x1fffe) {
@@ -6736,7 +6736,7 @@ s3_accel_read(uint32_t addr, void *priv)
if (svga->crtc[0x53] & 0x08) {
if ((addr >= 0x08000) && (addr <= 0x0803f))
return s3_pci_read(0, addr & 0xff, s3);
return s3_pci_read(0, addr & 0xff, 1, s3);
switch (addr & 0x1ffff) {
case 0x83b0 ... 0x83df:
return s3_in(addr & 0x3ff, s3);
@@ -11001,7 +11001,7 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
}
static uint8_t
s3_pci_read(UNUSED(int func), int addr, void *priv)
s3_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const s3_t *s3 = (s3_t *) priv;
const svga_t *svga = &s3->svga;
@@ -11090,7 +11090,7 @@ s3_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
s3_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
s3_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;

4
src/video/vid_s3_virge.c
View File

@@ -5024,7 +5024,7 @@ s3_virge_overlay_draw(svga_t *svga, int displine)
}
static uint8_t
s3_virge_pci_read(UNUSED(int func), int addr, void *priv)
s3_virge_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const virge_t *virge = (virge_t *) priv;
const svga_t *svga = &virge->svga;
@@ -5189,7 +5189,7 @@ s3_virge_pci_read(UNUSED(int func), int addr, void *priv)
}
static void
s3_virge_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
s3_virge_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
virge_t *virge = (virge_t *) priv;
svga_t *svga = &virge->svga;

4
src/video/vid_tgui9440.c
View File

@@ -1096,7 +1096,7 @@ tgui_hwcursor_draw(svga_t *svga, int displine)
}
uint8_t
tgui_pci_read(UNUSED(int func), int addr, void *priv)
tgui_pci_read(UNUSED(int func), int addr, UNUSED(int len), void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
@@ -1166,7 +1166,7 @@ tgui_pci_read(UNUSED(int func), int addr, void *priv)
}
void
tgui_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
tgui_pci_write(UNUSED(int func), int addr, UNUSED(int len), uint8_t val, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
svga_t *svga = &tgui->svga;

4
src/video/vid_voodoo.c
View File

@@ -1005,7 +1005,7 @@ voodoo_recalcmapping(voodoo_set_t *set)
}
uint8_t
voodoo_pci_read(int func, int addr, void *priv)
voodoo_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
const voodoo_t *voodoo = (voodoo_t *) priv;
@@ -1069,7 +1069,7 @@ voodoo_pci_read(int func, int addr, void *priv)
}
void
voodoo_pci_write(int func, int addr, uint8_t val, void *priv)
voodoo_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;

4
src/video/vid_voodoo_banshee.c
View File

@@ -3066,7 +3066,7 @@ banshee_vsync_callback(svga_t *svga)
}
static uint8_t
banshee_pci_read(int func, int addr, void *priv)
banshee_pci_read(int func, int addr, UNUSED(int len), void *priv)
{
const banshee_t *banshee = (banshee_t *) priv;
#if 0
@@ -3276,7 +3276,7 @@ banshee_pci_read(int func, int addr, void *priv)
}
static void
banshee_pci_write(int func, int addr, uint8_t val, void *priv)
banshee_pci_write(int func, int addr, UNUSED(int len), uint8_t val, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
#if 0