mirror of
https://github.com/86Box/86Box.git
synced 2026-02-21 17:15:32 -07:00
Fixed off by one errors in (S)VGA horizontal blanking start calculation.
This commit is contained in:
@@ -914,7 +914,7 @@ ibm8514_accel_out(uint16_t port, uint32_t val, svga_t *svga, int len)
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if (!(port & 1)) {
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if (((dev->disp_cntl & 0x60) == 0x20) || (((dev->disp_cntl & 0x60) == 0x40) && !(dev->accel.advfunc_cntl & 0x04))) {
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dev->hsync_start = val;
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dev->hblankstart = (dev->hsync_start & 0x07) + 1;
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dev->hblankstart = (dev->hsync_start & 0x07);
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}
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}
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ibm8514_log("IBM 8514/A: H_SYNC_STRT write 0AE8 = %d\n", val + 1);
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@@ -408,7 +408,7 @@ ati28800_recalctimings(svga_t *svga)
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int clock_sel;
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if (ati28800->regs[0xad] & 0x08)
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svga->hblankstart = ((ati28800->regs[0x0d] >> 2) << 8) + svga->crtc[2] + 1;
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svga->hblankstart = ((ati28800->regs[0x0d] >> 2) << 8) + svga->crtc[2];
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clock_sel = ((svga->miscout >> 2) & 3) | ((ati28800->regs[0xbe] & 0x10) >> 1) |
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((ati28800->regs[0xb9] & 2) << 1);
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@@ -492,8 +492,7 @@ ati28800_recalctimings(svga_t *svga)
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else {
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svga->render = svga_render_15bpp_highres;
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svga->hdisp >>= 1;
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svga->hblankstart = ((svga->hblankstart - 1) >> 1) + 1;
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svga->hblank_end_val >>= 1;
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svga->dots_per_clock >>= 1;
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svga->rowoffset <<= 1;
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svga->ma_latch <<= 1;
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}
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@@ -516,7 +516,7 @@ mach64_recalctimings(svga_t *svga)
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svga->htotal = (mach64->crtc_h_total_disp & 255) + 1;
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svga->hdisp_time = svga->hdisp = ((mach64->crtc_h_total_disp >> 16) & 255) + 1;
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svga->hblankstart = (mach64->crtc_h_sync_strt_wid & 255) +
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((mach64->crtc_h_sync_strt_wid >> 8) & 7) + 1;
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((mach64->crtc_h_sync_strt_wid >> 8) & 7);
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svga->hblank_end_val = (svga->hblankstart +
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((mach64->crtc_h_sync_strt_wid >> 16) & 31) - 1) & 63;
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svga->vsyncstart = (mach64->crtc_v_sync_strt_wid & 2047) + 1;
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@@ -2547,7 +2547,7 @@ mach_recalctimings(svga_t *svga)
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int clock_sel;
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if (mach->regs[0xad] & 0x08)
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svga->hblankstart = ((mach->regs[0x0d] >> 2) << 8) + svga->crtc[2] + 1;
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svga->hblankstart = ((mach->regs[0x0d] >> 2) << 8) + svga->crtc[2];
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clock_sel = ((svga->miscout >> 2) & 3) | ((mach->regs[0xbe] & 0x10) >> 1) | ((mach->regs[0xb9] & 2) << 1);
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@@ -3636,7 +3636,7 @@ mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8
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if (!(port & 1)) {
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if (((dev->disp_cntl & 0x60) == 0x20) || (((dev->disp_cntl & 0x60) == 0x40) && !(dev->accel.advfunc_cntl & 0x04)) || (mach->accel.clock_sel & 0x01)) {
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dev->hsync_start = val;
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dev->hblankstart = (dev->hsync_start & 0x07) + 1;
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dev->hblankstart = (dev->hsync_start & 0x07);
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}
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}
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mach_log("ATI 8514/A: H_SYNC_STRT write 0AE8 = %d\n", val + 1);
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@@ -1886,10 +1886,10 @@ chips_69000_pci_write(int func, int addr, uint8_t val, void *p)
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}
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case 0x13:
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{
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if (!(chips->pci_conf_status & PCI_COMMAND_MEM)) {
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// if (!(chips->pci_conf_status & PCI_COMMAND_MEM)) {
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chips->linear_mapping.base = val << 24;
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break;
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}
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// break;
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// }
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mem_mapping_set_addr(&chips->linear_mapping, val << 24, (1 << 24));
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break;
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}
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@@ -1750,7 +1750,7 @@ gd54xx_recalctimings(svga_t *svga)
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uint8_t rdmask;
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uint8_t linedbl = svga->dispend * 9 / 10 >= svga->hdisp;
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svga->hblankstart = svga->crtc[2] + 1;
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svga->hblankstart = svga->crtc[2];
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if (svga->crtc[0x1b] & ((svga->crtc[0x27] >= CIRRUS_ID_CLGD5424) ? 0xa0 : 0x20)) {
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/* Special blanking mode: the blank start and end become components of the window generator,
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@@ -1763,7 +1763,7 @@ gd54xx_recalctimings(svga_t *svga)
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svga->hblank_end_mask = 0x000000ff;
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if (svga->crtc[0x1b] & 0x20) {
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svga->hblankstart = svga->crtc[1]/* + ((svga->crtc[3] >> 5) & 3)*/ + 1;
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svga->hblankstart = svga->crtc[1]/* + ((svga->crtc[3] >> 5) & 3) + 1*/;
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svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
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/* In this mode, the dots per clock are always 8 or 16, never 9 or 18. */
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@@ -650,7 +650,7 @@ et4000_recalctimings(svga_t *svga)
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svga->ma_latch |= (svga->crtc[0x33] & 3) << 16;
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svga->hblankstart = (((svga->crtc[0x3f] & 0x10) >> 4) << 8) + svga->crtc[2] + 1;
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svga->hblankstart = (((svga->crtc[0x3f] & 0x10) >> 4) << 8) + svga->crtc[2];
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if (svga->crtc[0x35] & 1)
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svga->vblankstart += 0x400;
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@@ -690,14 +690,12 @@ et4000_recalctimings(svga_t *svga)
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case 15:
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case 16:
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svga->hdisp /= 2;
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svga->hblankstart /= 2;
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svga->hblank_end_val /= 2;
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svga->dots_per_clock /= 2;
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break;
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case 24:
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svga->hdisp /= 3;
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svga->hblankstart /= 3;
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svga->hblank_end_val /= 3;
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svga->dots_per_clock /= 3;
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break;
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default:
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@@ -432,7 +432,7 @@ et4000w32p_recalctimings(svga_t *svga)
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svga->ma_latch |= (svga->crtc[0x33] & 0x7) << 16;
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svga->hblankstart = (((svga->crtc[0x3f] & 0x10) >> 4) << 8) + svga->crtc[2] + 1;
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svga->hblankstart = (((svga->crtc[0x3f] & 0x10) >> 4) << 8) + svga->crtc[2];
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if (svga->crtc[0x35] & 0x01)
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svga->vblankstart += 0x400;
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@@ -714,7 +714,7 @@ ht216_recalctimings(svga_t *svga)
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svga->vram_display_mask = (ht216->ht_regs[0xf6] & 0x40) ? ht216->vram_mask : 0x3ffff;
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if (ht216->ht_regs[0xe0] & 0x20)
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svga->hblankstart = ((ht216->ht_regs[0xca] >> 2) << 8) + svga->crtc[4] + 1;
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svga->hblankstart = ((ht216->ht_regs[0xca] >> 2) << 8) + svga->crtc[4];
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}
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static void
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@@ -945,7 +945,7 @@ mystique_recalctimings(svga_t *svga)
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if (mystique->crtcext_regs[1] & CRTCX_R1_HTOTAL8)
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svga->htotal |= 0x100;
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svga->hblankstart = (((mystique->crtcext_regs[1] & 0x02) >> 2) << 8) + svga->crtc[2] + 1;
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svga->hblankstart = (((mystique->crtcext_regs[1] & 0x02) >> 2) << 8) + svga->crtc[2];
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if (mystique->crtcext_regs[2] & CRTCX_R2_VTOTAL10)
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svga->vtotal |= 0x400;
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@@ -3312,7 +3312,7 @@ s3_recalctimings(svga_t *svga)
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if (svga->crtc[0x33] & 0x20) {
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/* The S3 version of the Cirrus' special blanking mode, with identical behavior. */
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svga->hblankstart = (((svga->crtc[0x5d] & 0x02) >> 1) << 8) + svga->crtc[1]/* +
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((svga->crtc[3] >> 5) & 3)*/ + 1;
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((svga->crtc[3] >> 5) & 3) + 1*/;
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svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
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svga->monitor->mon_overscan_y = 0;
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@@ -3324,7 +3324,7 @@ s3_recalctimings(svga_t *svga)
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if (s3->chip >= S3_VISION964)
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svga->hblank_end_mask = 0x7f;
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} else if (s3->chip >= S3_86C801) {
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svga->hblankstart = (((svga->crtc[0x5d] & 0x04) >> 2) << 8) + svga->crtc[2] + 1;
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svga->hblankstart = (((svga->crtc[0x5d] & 0x04) >> 2) << 8) + svga->crtc[2];
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if (s3->chip >= S3_VISION964) {
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/* NOTE: The S3 Trio64V+ datasheet says this is bit 7, but then where is bit 6?
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@@ -4160,7 +4160,7 @@ s3_trio64v_recalctimings(svga_t *svga)
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if ((svga->crtc[0x33] & 0x20) || ((svga->crtc[0x67] & 0xc) == 0xc)) {
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/* The S3 version of the Cirrus' special blanking mode, with identical behavior. */
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svga->hblankstart = (((svga->crtc[0x5d] & 0x02) >> 1) << 8) + svga->crtc[1]/* +
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((svga->crtc[3] >> 5) & 3)*/ + 1;
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((svga->crtc[3] >> 5) & 3) + 1*/;
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svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
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svga->monitor->mon_overscan_y = 0;
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@@ -4169,7 +4169,7 @@ s3_trio64v_recalctimings(svga_t *svga)
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/* Also make sure vertical blanking starts on display end. */
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svga->vblankstart = svga->dispend;
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} else {
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svga->hblankstart = (((svga->crtc[0x5d] & 0x04) >> 2) << 8) + svga->crtc[2] + 1;
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svga->hblankstart = (((svga->crtc[0x5d] & 0x04) >> 2) << 8) + svga->crtc[2];
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/* NOTE: The S3 Trio64V+ datasheet says this is bit 7, but then where is bit 6?
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The datasheets for the pre-Trio64V+ cards say +64, which implies bit 6,
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@@ -827,7 +827,7 @@ s3_virge_recalctimings(svga_t *svga)
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if ((svga->crtc[0x33] & 0x20) || ((svga->crtc[0x67] & 0xc) == 0xc)) {
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/* The S3 version of the Cirrus' special blanking mode, with identical behavior. */
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svga->hblankstart = (((svga->crtc[0x5d] & 0x02) >> 1) << 8) + svga->crtc[1]/* +
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((svga->crtc[3] >> 5) & 3)*/ + 1;
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((svga->crtc[3] >> 5) & 3) + 1*/;
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svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
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svga->monitor->mon_overscan_y = 0;
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@@ -836,7 +836,7 @@ s3_virge_recalctimings(svga_t *svga)
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/* Also make sure vertical blanking starts on display end. */
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svga->vblankstart = svga->dispend;
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} else {
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svga->hblankstart = (((svga->crtc[0x5d] & 0x04) >> 2) << 8) + svga->crtc[2] + 1;
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svga->hblankstart = (((svga->crtc[0x5d] & 0x04) >> 2) << 8) + svga->crtc[2];
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svga->hblank_end_val = (svga->crtc[3] & 0x1f) | (((svga->crtc[5] & 0x80) >> 7) << 5) |
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(((svga->crtc[0x5d] & 0x08) >> 3) << 6);
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@@ -750,7 +750,7 @@ svga_recalctimings(svga_t *svga)
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} else
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svga->monitor->mon_overscan_x = 16;
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svga->hblankstart = svga->crtc[2] + 1;
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svga->hblankstart = svga->crtc[2];
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svga->hblank_end_val = (svga->crtc[3] & 0x1f) | ((svga->crtc[5] & 0x80) ? 0x20 : 0x00);
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svga->hblank_end_mask = 0x0000003f;
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@@ -558,10 +558,10 @@ banshee_recalctimings(svga_t *svga)
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that is, no overscan and relying on display end to blank. */
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if (banshee->vgaInit0 & 0x40) {
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svga->hblankstart = svga->crtc[1]/* + ((svga->crtc[3] >> 5) & 3)*/ +
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(((svga->crtc[0x1a] & 0x04) >> 2) << 8) + 1;
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(((svga->crtc[0x1a] & 0x04) >> 2) << 8);
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svga->hblank_end_mask = 0x0000007f;
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} else {
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svga->hblankstart = svga->crtc[1]/* + ((svga->crtc[3] >> 5) & 3)*/ + 1;
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svga->hblankstart = svga->crtc[1]/* + ((svga->crtc[3] >> 5) & 3)*/;
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svga->hblank_end_mask = 0x0000003f;
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}
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svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
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@@ -579,12 +579,12 @@ banshee_recalctimings(svga_t *svga)
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svga->linedbl = 0;
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} else {
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if (banshee->vgaInit0 & 0x40) {
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svga->hblankstart = (((svga->crtc[0x1a] & 0x10) >> 4) << 8) + svga->crtc[2] + 1;
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svga->hblankstart = (((svga->crtc[0x1a] & 0x10) >> 4) << 8) + svga->crtc[2];
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svga->hblank_end_val = (svga->crtc[3] & 0x1f) | (((svga->crtc[5] & 0x80) >> 7) << 5) |
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(((svga->crtc[0x1a] & 0x20) >> 5) << 6);
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svga->hblank_end_mask = 0x0000007f;
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} else {
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svga->hblankstart = svga->crtc[2] + 1;
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svga->hblankstart = svga->crtc[2];
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svga->hblank_end_val = (svga->crtc[3] & 0x1f) | (((svga->crtc[5] & 0x80) >> 7) << 5);
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svga->hblank_end_mask = 0x0000003f;
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}
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@@ -652,9 +652,6 @@ banshee_recalctimings(svga_t *svga)
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if (banshee->vidProcCfg & VIDPROCCFG_2X_MODE) {
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svga->hdisp *= 2;
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// svga->htotal *= 2;
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// svga->hblankstart *= 2;
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// svga->hblank_end_val *= 2;
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svga->dots_per_clock *= 2;
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}
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