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Added PAE, ported K6, P6, and WinChip 2 timings to the old recompiler, added a bunch of CPU's to the old recompiler, done some x87 fixes for both recompilers, added PAE, and fixed root directory entries for single-sided 5.25" DD floppies in the New Floppy Image dialog.

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This commit is contained in:
OBattler
2020-04-10 01:08:52 +02:00
parent ef1454b949
commit 2a0b3eb9c5
41 changed files with 8340 additions and 2359 deletions
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7
src/chipset/intel_4x0.c
View File

@@ -192,9 +192,15 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
if (base[0] != 0x00000000) {
/* If OSS = 1 and LSS = 0, extended SMRAM is visible outside SMM. */
i4x0_smram_map(0, base[0], size[0], ((regs[0x72] & 0x38) == 0x20) || s);
/* If base is on top of memory, this mapping will point to RAM.
TODO: It should actually point to EXTERNAL (with a SMRAM mapping) instead. */
/* If we are open, not closed, and not locked, point to RAM. */
/* If the register is set accordingly, disable the mapping also in SMM. */
i4x0_smram_map(0, base[0], size[0], !(regs[0x72] & 0x10) || s);
/* If base is on top of memory, this mapping will point to RAM.
TODO: It should actually point to EXTERNAL (with a SMRAM mapping) instead. */
/* If we are not closed, point to RAM. */
}
}
}
@@ -1359,6 +1365,7 @@ static void
i4x0_write(regs[0x5d], 0x5d, 0x00, dev);
i4x0_write(regs[0x5e], 0x5e, 0x00, dev);
i4x0_write(regs[0x5f], 0x5f, 0x00, dev);
i4x0_write(regs[0x72], 0x72, 0x00, dev);
// smbase = 0xa0000;

11
src/config.c
View File

@@ -282,8 +282,10 @@ config_read(wchar_t *fn)
if (feof(f)) break;
/* Make sure there are no stray newlines or hard-returns in there. */
if (buff[wcslen(buff)-1] == L'\n') buff[wcslen(buff)-1] = L'\0';
if (buff[wcslen(buff)-1] == L'\r') buff[wcslen(buff)-1] = L'\0';
if (wcslen(buff) > 0)
if (buff[wcslen(buff)-1] == L'\n') buff[wcslen(buff)-1] = L'\0';
if (wcslen(buff) > 0)
if (buff[wcslen(buff)-1] == L'\r') buff[wcslen(buff)-1] = L'\0';
/* Skip any leading whitespace. */
c = 0;
@@ -2292,7 +2294,10 @@ config_set_string(char *head, char *name, char *val)
if (ent == NULL)
ent = create_entry(section, name);
memcpy(ent->data, val, sizeof(ent->data));
if ((strlen(val) + 1) <= sizeof(ent->data))
memcpy(ent->data, val, strlen(val) + 1);
else
memcpy(ent->data, val, sizeof(ent->data));
mbstowcs(ent->wdata, ent->data, sizeof_w(ent->wdata));
}

4
src/cpu/codegen.c
View File

@@ -11,9 +11,10 @@
void (*codegen_timing_start)();
void (*codegen_timing_prefix)(uint8_t prefix, uint32_t fetchdat);
void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32);
void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
void (*codegen_timing_block_start)();
void (*codegen_timing_block_end)();
int (*codegen_timing_jump_cycles)();
void codegen_timing_set(codegen_timing_t *timing)
{
@@ -22,6 +23,7 @@ void codegen_timing_set(codegen_timing_t *timing)
codegen_timing_opcode = timing->opcode;
codegen_timing_block_start = timing->block_start;
codegen_timing_block_end = timing->block_end;
codegen_timing_jump_cycles = timing->jump_cycles;
}
int codegen_in_recompile;

9
src/cpu/codegen.h
View File

@@ -319,23 +319,28 @@ extern int codegen_block_cycles;
extern void (*codegen_timing_start)();
extern void (*codegen_timing_prefix)(uint8_t prefix, uint32_t fetchdat);
extern void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32);
extern void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
extern void (*codegen_timing_block_start)();
extern void (*codegen_timing_block_end)();
extern int (*codegen_timing_jump_cycles)();
typedef struct codegen_timing_t
{
void (*start)();
void (*prefix)(uint8_t prefix, uint32_t fetchdat);
void (*opcode)(uint8_t opcode, uint32_t fetchdat, int op_32);
void (*opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
void (*block_start)();
void (*block_end)();
int (*jump_cycles)();
} codegen_timing_t;
extern codegen_timing_t codegen_timing_pentium;
extern codegen_timing_t codegen_timing_686;
extern codegen_timing_t codegen_timing_486;
extern codegen_timing_t codegen_timing_winchip;
extern codegen_timing_t codegen_timing_winchip2;
extern codegen_timing_t codegen_timing_k6;
extern codegen_timing_t codegen_timing_p6;
void codegen_timing_set(codegen_timing_t *timing);

6
src/cpu/codegen_ops_x86-64.h
View File

@@ -5359,7 +5359,7 @@ static inline void MEM_CHECK_WRITE(x86seg *seg)
load_param_1_reg_32(REG_EDI);
load_param_2_32(&codeblock[block_current], 1);
call(&codeblock[block_current], (uintptr_t)mmutranslatereal);
call(&codeblock[block_current], (uintptr_t)mmutranslatereal32);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte((uint8_t)cpu_state_offset(abrt));
@@ -5498,7 +5498,7 @@ static inline void MEM_CHECK_WRITE_W(x86seg *seg)
jump_pos = block_pos;
load_param_1_reg_32(REG_EBX);
load_param_2_32(&codeblock[block_current], 1);
call(&codeblock[block_current], (uintptr_t)mmutranslatereal);
call(&codeblock[block_current], (uintptr_t)mmutranslatereal32);
addbyte(0x83); /*ADD EBX, 1*/
addbyte(0xc3);
addbyte(1);
@@ -5647,7 +5647,7 @@ static inline void MEM_CHECK_WRITE_L(x86seg *seg)
jump_pos = block_pos;
load_param_1_reg_32(REG_EBX);
load_param_2_32(&codeblock[block_current], 1);
call(&codeblock[block_current], (uintptr_t)mmutranslatereal);
call(&codeblock[block_current], (uintptr_t)mmutranslatereal32);
addbyte(0x83); /*ADD EBX, 3*/
addbyte(0xc3);
addbyte(3);

7
src/cpu/codegen_timing_486.c
View File

@@ -300,7 +300,7 @@ void codegen_timing_486_prefix(uint8_t prefix, uint32_t fetchdat)
last_prefix = prefix;
}
void codegen_timing_486_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
void codegen_timing_486_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
{
int **timings;
uint64_t *deps;
@@ -360,7 +360,7 @@ void codegen_timing_486_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
{
case 0x80: case 0x82: case 0x83:
timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
opcode = (fetchdat >> 3) & 7;
break;
case 0x81:
@@ -416,5 +416,6 @@ codegen_timing_t codegen_timing_486 =
codegen_timing_486_prefix,
codegen_timing_486_opcode,
codegen_timing_486_block_start,
codegen_timing_486_block_end
codegen_timing_486_block_end,
NULL
};

7
src/cpu/codegen_timing_686.c
View File

@@ -826,7 +826,7 @@ static int check_agi(uint64_t *deps, uint8_t opcode, uint32_t fetchdat, int op_3
return 0;
}
void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
{
uint32_t *timings;
uint64_t *deps;
@@ -886,7 +886,7 @@ void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
{
case 0x80: case 0x82: case 0x83:
timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
opcode = (fetchdat >> 3) & 7;
break;
case 0x81:
@@ -1052,5 +1052,6 @@ codegen_timing_t codegen_timing_686 =
codegen_timing_686_prefix,
codegen_timing_686_opcode,
codegen_timing_686_block_start,
codegen_timing_686_block_end
codegen_timing_686_block_end,
NULL
};

188
src/cpu/codegen_timing_common.c
View File

@@ -4,8 +4,9 @@
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include "codegen_timing_common.h"
#include <86box/mem.h>
#include "codegen_timing_common.h"
uint64_t opcode_deps[256] =
{
@@ -280,7 +281,7 @@ uint64_t opcode_deps_0f[256] =
/*00*/ MODRM, MODRM, MODRM, MODRM,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, MODRM, 0, MODRM,
/*10*/ 0, 0, 0, 0,
0, 0, 0, 0,
@@ -362,7 +363,7 @@ uint64_t opcode_deps_0f_mod3[256] =
/*00*/ MODRM, MODRM, MODRM, MODRM,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, MODRM, 0, MODRM,
/*10*/ 0, 0, 0, 0,
0, 0, 0, 0,
@@ -440,6 +441,171 @@ uint64_t opcode_deps_0f_mod3[256] =
MODRM, MODRM, MODRM, 0,
};
uint64_t opcode_deps_0f0f[256] =
{
/*00*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, MODRM, 0, 0,
/*10*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, MODRM, 0, 0,
/*20*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*30*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*40*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*50*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*60*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*70*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*80*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*90*/ MODRM, 0, 0, 0,
MODRM, 0, MODRM, MODRM,
0, 0, MODRM, 0,
0, 0, MODRM, 0,
/*a0*/ MODRM, 0, 0, 0,
MODRM, 0, MODRM, MODRM,
0, 0, 0, 0,
0, 0, 0, 0,
/*b0*/ MODRM, 0, 0, 0,
MODRM, 0, MODRM, MODRM,
0, 0, 0, 0,
0, 0, 0, MODRM,
/*c0*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*d0*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*e0*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*f0*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
};
uint64_t opcode_deps_0f0f_mod3[256] =
{
/*00*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, MODRM, 0, 0,
/*10*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, MODRM, 0, 0,
/*20*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*30*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*40*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*50*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*60*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*70*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*80*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*90*/ MODRM, 0, 0, 0,
MODRM, 0, MODRM, MODRM,
0, 0, MODRM, 0,
0, 0, MODRM, 0,
/*a0*/ MODRM, 0, 0, 0,
MODRM, 0, MODRM, MODRM,
0, 0, 0, 0,
0, 0, 0, 0,
/*b0*/ MODRM, 0, 0, 0,
MODRM, 0, MODRM, MODRM,
0, 0, 0, 0,
0, 0, 0, MODRM,
/*c0*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*d0*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*e0*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
/*f0*/ 0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
};
uint64_t opcode_deps_shift[8] =
{
MODRM, MODRM, MODRM, MODRM,
@@ -664,21 +830,21 @@ uint64_t opcode_deps_df_mod3[8] =
uint64_t opcode_deps_81[8] =
{
MODRM, MODRM, MODRM, MODRM,
MODRM, MODRM, MODRM, MODRM
MODRM | HAS_IMM1632, MODRM | HAS_IMM1632, MODRM | HAS_IMM1632, MODRM | HAS_IMM1632,
MODRM | HAS_IMM1632, MODRM | HAS_IMM1632, MODRM | HAS_IMM1632, MODRM | HAS_IMM1632
};
uint64_t opcode_deps_81_mod3[8] =
{
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | MODRM
SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632,
SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM1632, SRCDEP_RM | MODRM | HAS_IMM1632
};
uint64_t opcode_deps_8x[8] =
{
MODRM, MODRM, MODRM, MODRM,
MODRM, MODRM, MODRM, MODRM
MODRM | HAS_IMM8, MODRM | HAS_IMM8, MODRM | HAS_IMM8, MODRM | HAS_IMM8,
MODRM | HAS_IMM8, MODRM | HAS_IMM8, MODRM | HAS_IMM8, MODRM | HAS_IMM8
};
uint64_t opcode_deps_8x_mod3[8] =
{
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | MODRM
SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8,
SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8, SRCDEP_RM | DSTDEP_RM | MODRM | HAS_IMM8, SRCDEP_RM | MODRM | HAS_IMM8
};

6
src/cpu/codegen_timing_common.h
View File

@@ -73,6 +73,10 @@
#define FPU_FXCH (1ull << 33)
#define HAS_IMM8 (1ull << 34)
#define HAS_IMM1632 (1ull << 35)
#define REGMASK_IMPL_ESP (1 << 8)
#define REGMASK_SHIFTPACK (1 << 9)
#define REGMASK_MULTIPLY (1 << 9)
@@ -82,6 +86,8 @@ extern uint64_t opcode_deps[256];
extern uint64_t opcode_deps_mod3[256];
extern uint64_t opcode_deps_0f[256];
extern uint64_t opcode_deps_0f_mod3[256];
extern uint64_t opcode_deps_0f0f[256];
extern uint64_t opcode_deps_0f0f_mod3[256];
extern uint64_t opcode_deps_shift[8];
extern uint64_t opcode_deps_shift_mod3[8];
extern uint64_t opcode_deps_shift_cl[8];

2353
src/cpu/codegen_timing_k6.c Normal file
View File

File diff suppressed because it is too large Load Diff

2330
src/cpu/codegen_timing_p6.c Normal file
View File

File diff suppressed because it is too large Load Diff

7
src/cpu/codegen_timing_pentium.c
View File

@@ -1076,7 +1076,7 @@ static void codegen_instruction(uint64_t *timings, uint64_t *deps, uint8_t opcod
}
}
void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
{
uint64_t *timings;
uint64_t *deps;
@@ -1137,7 +1137,7 @@ void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
{
case 0x80: case 0x82: case 0x83:
timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
opcode = (fetchdat >> 3) & 7;
break;
case 0x81:
@@ -1318,5 +1318,6 @@ codegen_timing_t codegen_timing_pentium =
codegen_timing_pentium_prefix,
codegen_timing_pentium_opcode,
codegen_timing_pentium_block_start,
codegen_timing_pentium_block_end
codegen_timing_pentium_block_end,
NULL
};

7
src/cpu/codegen_timing_winchip.c
View File

@@ -300,7 +300,7 @@ void codegen_timing_winchip_prefix(uint8_t prefix, uint32_t fetchdat)
last_prefix = prefix;
}
void codegen_timing_winchip_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
void codegen_timing_winchip_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
{
int **timings;
uint64_t *deps;
@@ -360,7 +360,7 @@ void codegen_timing_winchip_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
{
case 0x80: case 0x82: case 0x83:
timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x_mod3;
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
opcode = (fetchdat >> 3) & 7;
break;
case 0x81:
@@ -416,5 +416,6 @@ codegen_timing_t codegen_timing_winchip =
codegen_timing_winchip_prefix,
codegen_timing_winchip_opcode,
codegen_timing_winchip_block_start,
codegen_timing_winchip_block_end
codegen_timing_winchip_block_end,
NULL
};

743
src/cpu/codegen_timing_winchip2.c Normal file
View File

@@ -0,0 +1,743 @@
/*Since IDT/Centaur didn't document cycle timings in the WinChip datasheets, and
I don't currently own a WinChip 2 to test against, most of the timing here is
a guess. This code makes the current (probably wrong) assumptions :
- FPU uses same timings as a Pentium, except for FXCH (which doesn't pair)
- 3DNow! instructions perfectly pair
- MMX follows mostly Pentium rules - one pipeline has shift/pack, one has
multiply, and other instructions can execute in either pipeline
- Instructions with prefixes can pair if both instructions are fully decoded
when the first instruction starts execution.*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include "x86.h"
#include "x86_ops.h"
#include "x87.h"
#include "codegen.h"
#include "codegen_ops.h"
#include "codegen_timing_common.h"
/*Instruction has different execution time for 16 and 32 bit data. Does not pair */
#define CYCLES_HAS_MULTI (1 << 31)
#define CYCLES_FPU (1 << 30)
#define CYCLES_IS_MMX_MUL (1 << 29)
#define CYCLES_IS_MMX_SHIFT (1 << 28)
#define CYCLES_IS_MMX_ANY (1 << 27)
#define CYCLES_IS_3DNOW (1 << 26)
#define CYCLES_MMX_MUL(c) (CYCLES_IS_MMX_MUL | c)
#define CYCLES_MMX_SHIFT(c) (CYCLES_IS_MMX_SHIFT | c)
#define CYCLES_MMX_ANY(c) (CYCLES_IS_MMX_ANY | c)
#define CYCLES_3DNOW(c) (CYCLES_IS_3DNOW | c)
#define CYCLES_IS_MMX (CYCLES_IS_MMX_MUL | CYCLES_IS_MMX_SHIFT | CYCLES_IS_MMX_ANY | CYCLES_IS_3DNOW)
#define GET_CYCLES(c) (c & ~(CYCLES_HAS_MULTI | CYCLES_FPU | CYCLES_IS_MMX))
#define CYCLES(c) c
#define CYCLES2(c16, c32) (CYCLES_HAS_MULTI | c16 | (c32 << 8))
/*comp_time = cycles until instruction complete
i_overlap = cycles that overlap with integer
f_overlap = cycles that overlap with subsequent FPU*/
#define FPU_CYCLES(comp_time, i_overlap, f_overlap) (comp_time) | (i_overlap << 8) | (f_overlap << 16) | CYCLES_FPU
#define FPU_COMP_TIME(timing) (timing & 0xff)
#define FPU_I_OVERLAP(timing) ((timing >> 8) & 0xff)
#define FPU_F_OVERLAP(timing) ((timing >> 16) & 0xff)
#define FPU_I_LATENCY(timing) (FPU_COMP_TIME(timing) - FPU_I_OVERLAP(timing))
#define FPU_F_LATENCY(timing) (FPU_I_OVERLAP(timing) - FPU_F_OVERLAP(timing))
#define FPU_RESULT_LATENCY(timing) ((timing >> 8) & 0xff)
#define INVALID 0
static uint32_t opcode_timings[256] =
{
/*00*/ CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(1), CYCLES(1), CYCLES(2), CYCLES(3), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(1), CYCLES(1), CYCLES(2), INVALID,
/*10*/ CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(1), CYCLES(1), CYCLES(2), CYCLES(3), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(1), CYCLES(1), CYCLES(2), CYCLES(3),
/*20*/ CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(3), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(3),
/*30*/ CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(2),
/*40*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*50*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*60*/ CYCLES(11), CYCLES(9), CYCLES(7), CYCLES(9), CYCLES(4), CYCLES(4), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES2(17,25), CYCLES(1), CYCLES2(17,20), CYCLES(17), CYCLES(17), CYCLES(17), CYCLES(17),
/*70*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*80*/ CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(5), CYCLES(5), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(3), CYCLES(1), CYCLES(5), CYCLES(6),
/*90*/ CYCLES(1), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(0), CYCLES(4), CYCLES(4), CYCLES(5), CYCLES(2), CYCLES(3),
/*a0*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(7), CYCLES(7), CYCLES(8), CYCLES(8), CYCLES(1), CYCLES(1), CYCLES(5), CYCLES(5), CYCLES(5), CYCLES(5), CYCLES(6), CYCLES(6),
/*b0*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*c0*/ CYCLES(4), CYCLES(4), CYCLES(5), CYCLES(5), CYCLES(6), CYCLES(6), CYCLES(1), CYCLES(1), CYCLES(14), CYCLES(5), CYCLES(0), CYCLES(0), CYCLES(0), CYCLES(0), CYCLES(3), CYCLES(0),
/*d0*/ CYCLES(4), CYCLES(4), CYCLES(4), CYCLES(4), CYCLES(15), CYCLES(14), CYCLES(2), CYCLES(4), INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*e0*/ CYCLES(6), CYCLES(6), CYCLES(6), CYCLES(5), CYCLES(14), CYCLES(14), CYCLES(16), CYCLES(16), CYCLES(3), CYCLES(3), CYCLES(17), CYCLES(3), CYCLES(14), CYCLES(14), CYCLES(14), CYCLES(14),
/*f0*/ CYCLES(4), CYCLES(0), CYCLES(0), CYCLES(0), CYCLES(4), CYCLES(2), INVALID, INVALID, CYCLES(2), CYCLES(2), CYCLES(3), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(3), INVALID
};
static uint32_t opcode_timings_mod3[256] =
{
/*00*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(2), CYCLES(3), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(2), INVALID,
/*10*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(2), CYCLES(3), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(2), CYCLES(3),
/*20*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(3), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(3),
/*30*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(2), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(2),
/*40*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*50*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*60*/ CYCLES(11), CYCLES(9), CYCLES(7), CYCLES(9), CYCLES(4), CYCLES(4), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES2(14,25), CYCLES(1), CYCLES2(17,20), CYCLES(17), CYCLES(17), CYCLES(17), CYCLES(17),
/*70*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*80*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(5), CYCLES(5), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(2), CYCLES(1), CYCLES(2), CYCLES(1),
/*90*/ CYCLES(1), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(0), CYCLES(4), CYCLES(4), CYCLES(5), CYCLES(2), CYCLES(3),
/*a0*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(7), CYCLES(7), CYCLES(8), CYCLES(8), CYCLES(1), CYCLES(1), CYCLES(5), CYCLES(5), CYCLES(5), CYCLES(5), CYCLES(6), CYCLES(6),
/*b0*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*c0*/ CYCLES(4), CYCLES(4), CYCLES(5), CYCLES(5), CYCLES(6), CYCLES(6), CYCLES(1), CYCLES(1), CYCLES(14), CYCLES(5), CYCLES(0), CYCLES(0), CYCLES(0), CYCLES(0), CYCLES(3), CYCLES(0),
/*d0*/ CYCLES(4), CYCLES(4), CYCLES(4), CYCLES(4), CYCLES(15), CYCLES(14), CYCLES(2), CYCLES(4), INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*e0*/ CYCLES(6), CYCLES(6), CYCLES(6), CYCLES(5), CYCLES(14), CYCLES(14), CYCLES(16), CYCLES(16), CYCLES(3), CYCLES(3), CYCLES(17), CYCLES(3), CYCLES(14), CYCLES(14), CYCLES(14), CYCLES(14),
/*f0*/ CYCLES(4), CYCLES(0), CYCLES(0), CYCLES(0), CYCLES(4), CYCLES(2), INVALID, INVALID, CYCLES(2), CYCLES(2), CYCLES(3), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(3), INVALID,
};
static uint32_t opcode_timings_0f[256] =
{
/*00*/ CYCLES(20), CYCLES(11), CYCLES(11), CYCLES(10), INVALID, CYCLES(195), CYCLES(7), INVALID, CYCLES(1000), CYCLES(10000), INVALID, INVALID, INVALID, CYCLES_3DNOW(1), CYCLES(1), CYCLES_3DNOW(1),
/*10*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*20*/ CYCLES(6), CYCLES(6), CYCLES(6), CYCLES(6), CYCLES(6), CYCLES(6), INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*30*/ CYCLES(9), CYCLES(1), CYCLES(9), INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*40*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*50*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*60*/ CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), INVALID, INVALID, CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2),
/*70*/ INVALID, CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES(100), INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2),
/*80*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*90*/ CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3),
/*a0*/ CYCLES(3), CYCLES(3), CYCLES(14), CYCLES(8), CYCLES(3), CYCLES(4), INVALID, INVALID, CYCLES(3), CYCLES(3), INVALID, CYCLES(13), CYCLES(3), CYCLES(3), INVALID, CYCLES2(18,30),
/*b0*/ CYCLES(10), CYCLES(10), CYCLES(6), CYCLES(13), CYCLES(6), CYCLES(6), CYCLES(3), CYCLES(3), INVALID, INVALID, CYCLES(6), CYCLES(13), CYCLES(7), CYCLES(7), CYCLES(3), CYCLES(3),
/*c0*/ CYCLES(4), CYCLES(4), INVALID, INVALID, INVALID, INVALID, INVALID, CYCLES(3), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*d0*/ INVALID, CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), INVALID, CYCLES_MMX_MUL(2), INVALID, INVALID, CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), INVALID, CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), INVALID, CYCLES_MMX_ANY(2),
/*e0*/ INVALID, CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), INVALID, INVALID, CYCLES_MMX_MUL(2), INVALID, INVALID, CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), INVALID, CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), INVALID, CYCLES_MMX_ANY(2),
/*f0*/ INVALID, CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), CYCLES_MMX_SHIFT(2), INVALID, CYCLES_MMX_MUL(2), INVALID, INVALID, CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), INVALID, CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), CYCLES_MMX_ANY(2), INVALID,
};
static uint32_t opcode_timings_0f_mod3[256] =
{
/*00*/ CYCLES(20), CYCLES(11), CYCLES(11), CYCLES(10), INVALID, CYCLES(195), CYCLES(7), INVALID, CYCLES(1000), CYCLES(10000), INVALID, INVALID, INVALID, CYCLES_3DNOW(1), CYCLES(1), CYCLES_3DNOW(1),
/*10*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*20*/ CYCLES(6), CYCLES(6), CYCLES(6), CYCLES(6), CYCLES(6), CYCLES(6), INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*30*/ CYCLES(9), CYCLES(1), CYCLES(9), INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*40*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*50*/ INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
/*60*/ CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID, INVALID, CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1),
/*70*/ INVALID, CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES(100), INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1),
/*80*/ CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*90*/ CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3),
/*a0*/ CYCLES(3), CYCLES(3), CYCLES(14), CYCLES(8), CYCLES(3), CYCLES(4), INVALID, INVALID, CYCLES(3), CYCLES(3), INVALID, CYCLES(13), CYCLES(3), CYCLES(3), INVALID, CYCLES2(18,30),
/*b0*/ CYCLES(10), CYCLES(10), CYCLES(6), CYCLES(13), CYCLES(6), CYCLES(6), CYCLES(3), CYCLES(3), INVALID, INVALID, CYCLES(6), CYCLES(13), CYCLES(7), CYCLES(7), CYCLES(3), CYCLES(3),
/*c0*/ CYCLES(4), CYCLES(4), INVALID, INVALID, INVALID, INVALID, INVALID, CYCLES(3), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1), CYCLES(1),
/*d0*/ INVALID, CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID, CYCLES_MMX_MUL(1), INVALID, INVALID, CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID, CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID, CYCLES_MMX_ANY(1),
/*e0*/ INVALID, CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID, INVALID, CYCLES_MMX_MUL(1), INVALID, INVALID, CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID, CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID, CYCLES_MMX_ANY(1),
/*f0*/ INVALID, CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), CYCLES_MMX_SHIFT(1), INVALID, CYCLES_MMX_MUL(1), INVALID, INVALID, CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID, CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), CYCLES_MMX_ANY(1), INVALID,
};
static uint32_t opcode_timings_shift[8] =
{
CYCLES(7), CYCLES(7), CYCLES(10), CYCLES(10), CYCLES(7), CYCLES(7), CYCLES(7), CYCLES(7)
};
static uint32_t opcode_timings_shift_mod3[8] =
{
CYCLES(3), CYCLES(3), CYCLES(9), CYCLES(9), CYCLES(3), CYCLES(3), CYCLES(3), CYCLES(3)
};
static uint32_t opcode_timings_f6[8] =
{
CYCLES(2), INVALID, CYCLES(2), CYCLES(2), CYCLES(13), CYCLES(14), CYCLES(16), CYCLES(19)
};
static uint32_t opcode_timings_f6_mod3[8] =
{
CYCLES(1), INVALID, CYCLES(1), CYCLES(1), CYCLES(13), CYCLES(14), CYCLES(16), CYCLES(19)
};
static uint32_t opcode_timings_f7[8] =
{
CYCLES(2), INVALID, CYCLES(2), CYCLES(2), CYCLES(21), CYCLES2(22,38), CYCLES2(24,40), CYCLES2(27,43)
};
static uint32_t opcode_timings_f7_mod3[8] =
{
CYCLES(1), INVALID, CYCLES(1), CYCLES(1), CYCLES(21), CYCLES2(22,38), CYCLES2(24,40), CYCLES2(27,43)
};
static uint32_t opcode_timings_ff[8] =
{
CYCLES(2), CYCLES(2), CYCLES(5), CYCLES(0), CYCLES(5), CYCLES(0), CYCLES(5), INVALID
};
static uint32_t opcode_timings_ff_mod3[8] =
{
CYCLES(1), CYCLES(1), CYCLES(5), CYCLES(0), CYCLES(5), CYCLES(0), CYCLES(5), INVALID
};
static uint32_t opcode_timings_d8[8] =
{
/* FADDs FMULs FCOMs FCOMPs*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
/* FSUBs FSUBRs FDIVs FDIVRs*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2), FPU_CYCLES(39,38,2), FPU_CYCLES(39,38,2)
};
static uint32_t opcode_timings_d8_mod3[8] =
{
/* FADD FMUL FCOM FCOMP*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
/* FSUB FSUBR FDIV FDIVR*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2), FPU_CYCLES(39,38,2), FPU_CYCLES(39,38,2)
};
static uint32_t opcode_timings_d9[8] =
{
/* FLDs FSTs FSTPs*/
FPU_CYCLES(1,0,0), INVALID, FPU_CYCLES(2,0,0), FPU_CYCLES(2,0,0),
/* FLDENV FLDCW FSTENV FSTCW*/
FPU_CYCLES(32,0,0), FPU_CYCLES(8,0,0), FPU_CYCLES(48,0,0), FPU_CYCLES(2,0,0)
};
static uint32_t opcode_timings_d9_mod3[64] =
{
/*FLD*/
FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
/*FXCH*/
FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
/*FNOP*/
FPU_CYCLES(3,0,0), INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
/*FSTP*/
FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
/* opFCHS opFABS*/
FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), INVALID, INVALID,
/* opFTST opFXAM*/
FPU_CYCLES(1,0,0), FPU_CYCLES(21,4,0), INVALID, INVALID,
/* opFLD1 opFLDL2T opFLDL2E opFLDPI*/
FPU_CYCLES(2,0,0), FPU_CYCLES(5,2,2), FPU_CYCLES(5,2,2), FPU_CYCLES(5,2,2),
/* opFLDEG2 opFLDLN2 opFLDZ*/
FPU_CYCLES(5,2,2), FPU_CYCLES(5,2,2), FPU_CYCLES(2,0,0), INVALID,
/* opF2XM1 opFYL2X opFPTAN opFPATAN*/
FPU_CYCLES(53,2,2), FPU_CYCLES(103,2,2),FPU_CYCLES(120,36,0),FPU_CYCLES(112,2,2),
/* opFDECSTP opFINCSTP,*/
INVALID, INVALID, FPU_CYCLES(2,0,0), FPU_CYCLES(2,0,0),
/* opFPREM opFSQRT opFSINCOS*/
FPU_CYCLES(64,2,2), INVALID, FPU_CYCLES(70,69,2),FPU_CYCLES(89,2,2),
/* opFRNDINT opFSCALE opFSIN opFCOS*/
FPU_CYCLES(9,0,0), FPU_CYCLES(20,5,0), FPU_CYCLES(65,2,2), FPU_CYCLES(65,2,2)
};
static uint32_t opcode_timings_da[8] =
{
/* FIADDl FIMULl FICOMl FICOMPl*/
FPU_CYCLES(6,2,2), FPU_CYCLES(6,2,2), FPU_CYCLES(4,0,0), FPU_CYCLES(4,0,0),
/* FISUBl FISUBRl FIDIVl FIDIVRl*/
FPU_CYCLES(6,2,2), FPU_CYCLES(6,2,2), FPU_CYCLES(42,38,2), FPU_CYCLES(42,38,2)
};
static uint32_t opcode_timings_da_mod3[8] =
{
INVALID, INVALID, INVALID, INVALID,
/* FCOMPP*/
INVALID, FPU_CYCLES(1,0,0), INVALID, INVALID
};
static uint32_t opcode_timings_db[8] =
{
/* FLDil FSTil FSTPil*/
FPU_CYCLES(3,2,2), INVALID, FPU_CYCLES(6,0,0), FPU_CYCLES(6,0,0),
/* FLDe FSTPe*/
INVALID, FPU_CYCLES(3,0,0), INVALID, FPU_CYCLES(3,0,0)
};
static uint32_t opcode_timings_db_mod3[64] =
{
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
/* opFNOP opFCLEX opFINIT*/
INVALID, FPU_CYCLES(1,0,0), FPU_CYCLES(7,0,0), FPU_CYCLES(17,0,0),
/* opFNOP opFNOP*/
FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0), INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
INVALID, INVALID, INVALID, INVALID,
};
static uint32_t opcode_timings_dc[8] =
{
/* FADDd FMULd FCOMd FCOMPd*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2), FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
/* FSUBd FSUBRd FDIVd FDIVRd*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2), FPU_CYCLES(39,38,2), FPU_CYCLES(39,38,2)
};
static uint32_t opcode_timings_dc_mod3[8] =
{
/* opFADDr opFMULr*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2),INVALID, INVALID,
/* opFSUBRr opFSUBr opFDIVRr opFDIVr*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2),FPU_CYCLES(39,38,2), FPU_CYCLES(39,38,2)
};
static uint32_t opcode_timings_dd[8] =
{
/* FLDd FSTd FSTPd*/
FPU_CYCLES(1,0,0), INVALID, FPU_CYCLES(2,0,0), FPU_CYCLES(2,0,0),
/* FRSTOR FSAVE FSTSW*/
FPU_CYCLES(70,0,0), INVALID, FPU_CYCLES(127,0,0), FPU_CYCLES(6,0,0)
};
static uint32_t opcode_timings_dd_mod3[8] =
{
/* FFFREE FST FSTP*/
FPU_CYCLES(2,0,0), INVALID, FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),
/* FUCOM FUCOMP*/
FPU_CYCLES(1,0,0), FPU_CYCLES(1,0,0),INVALID, INVALID
};
static uint32_t opcode_timings_de[8] =
{
/* FIADDw FIMULw FICOMw FICOMPw*/
FPU_CYCLES(6,2,2), FPU_CYCLES(6,2,2), FPU_CYCLES(4,0,0), FPU_CYCLES(4,0,0),
/* FISUBw FISUBRw FIDIVw FIDIVRw*/
FPU_CYCLES(6,2,2), FPU_CYCLES(6,2,2), FPU_CYCLES(42,38,2), FPU_CYCLES(42,38,2)
};
static uint32_t opcode_timings_de_mod3[8] =
{
/* FADDP FMULP FCOMPP*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2), INVALID, FPU_CYCLES(1,0,0),
/* FSUBP FSUBRP FDIVP FDIVRP*/
FPU_CYCLES(3,2,2), FPU_CYCLES(3,2,2), FPU_CYCLES(39,38,2), FPU_CYCLES(39,38,2)
};
static uint32_t opcode_timings_df[8] =
{
/* FILDiw FISTiw FISTPiw*/
FPU_CYCLES(3,2,2), INVALID, FPU_CYCLES(6,0,0), FPU_CYCLES(6,0,0),
/* FILDiq FBSTP FISTPiq*/
INVALID, FPU_CYCLES(3,2,2), FPU_CYCLES(148,0,0), FPU_CYCLES(6,0,0)
};
static uint32_t opcode_timings_df_mod3[8] =
{
INVALID, INVALID, INVALID, INVALID,
/* FSTSW AX*/
FPU_CYCLES(6,0,0), INVALID, INVALID, INVALID
};
static uint32_t opcode_timings_8x[8] =
{
CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2)
};
static uint32_t opcode_timings_8x_mod3[8] =
{
CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2)
};
static uint32_t opcode_timings_81[8] =
{
CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2)
};
static uint32_t opcode_timings_81_mod3[8] =
{
CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2), CYCLES(2)
};
static int timing_count;
static uint8_t last_prefix;
static uint32_t regmask_modified;
static int decode_delay, decode_delay_offset;
static int fpu_latency;
static int fpu_st_latency[8];
static int u_pipe_full;
static uint32_t u_pipe_opcode;
static uint32_t *u_pipe_timings;
static uint32_t u_pipe_op_32;
static uint32_t u_pipe_regmask;
static uint32_t u_pipe_fetchdat;
static int u_pipe_decode_delay_offset;
static uint64_t *u_pipe_deps;
int can_pair(uint32_t timing_a, uint32_t timing_b, uint8_t regmask_b)
{
/*Only MMX/3DNow instructions can pair*/
if (!(timing_b & CYCLES_IS_MMX))
return 0;
/*Only one MMX multiply per cycle*/
if ((timing_a & CYCLES_IS_MMX_MUL) && (timing_b & CYCLES_IS_MMX_MUL))
return 0;
/*Only one MMX shift/pack per cycle*/
if ((timing_a & CYCLES_IS_MMX_SHIFT) && (timing_b & CYCLES_IS_MMX_SHIFT))
return 0;
/*Second instruction can not access registers written by first*/
if (u_pipe_regmask & regmask_b)
return 0;
/*Must have had enough time to decode prefixes*/
if ((decode_delay+decode_delay_offset+u_pipe_decode_delay_offset) > 0)
return 0;
return 1;
}
static inline int COUNT(uint32_t c, int op_32)
{
if (c & CYCLES_FPU)
return FPU_I_LATENCY(c);
if (c & CYCLES_HAS_MULTI)
{
if (op_32 & 0x100)
return (c >> 8) & 0xff;
return c & 0xff;
}
return GET_CYCLES(c);
}
static int check_agi(uint64_t *deps, uint8_t opcode, uint32_t fetchdat, int op_32)
{
uint32_t addr_regmask = get_addr_regmask(deps[opcode], fetchdat, op_32);
/*Instructions that use ESP implicitly (eg PUSH, POP, CALL etc) do not
cause AGIs with each other, but do with instructions that use it explicitly*/
if ((addr_regmask & REGMASK_IMPL_ESP) && (regmask_modified & (1 << REG_ESP)) && !(regmask_modified & REGMASK_IMPL_ESP))
addr_regmask |= (1 << REG_ESP);
return (regmask_modified & addr_regmask) & ~REGMASK_IMPL_ESP;
}
static int codegen_fpu_latencies(uint64_t deps, int reg)
{
int latency = fpu_latency;
if ((deps & FPU_RW_ST0) && fpu_st_latency[0] && fpu_st_latency[0] > latency)
latency = fpu_st_latency[0];
if ((deps & FPU_RW_ST1) && fpu_st_latency[1] && fpu_st_latency[1] > latency)
latency = fpu_st_latency[1];
if ((deps & FPU_RW_STREG) && fpu_st_latency[reg] && fpu_st_latency[reg] > latency)
latency = fpu_st_latency[reg];
return latency;
}
#define SUB_AND_CLAMP(latency, count) \
latency -= count; \
if (latency < 0) \
latency = 0
static void codegen_fpu_latency_clock(int count)
{
SUB_AND_CLAMP(fpu_latency, count);
SUB_AND_CLAMP(fpu_st_latency[0], count);
SUB_AND_CLAMP(fpu_st_latency[1], count);
SUB_AND_CLAMP(fpu_st_latency[2], count);
SUB_AND_CLAMP(fpu_st_latency[3], count);
SUB_AND_CLAMP(fpu_st_latency[4], count);
SUB_AND_CLAMP(fpu_st_latency[5], count);
SUB_AND_CLAMP(fpu_st_latency[6], count);
SUB_AND_CLAMP(fpu_st_latency[7], count);
}
static void codegen_instruction(uint32_t *timings, uint64_t *deps, uint8_t opcode, uint32_t fetchdat, int decode_delay_offset, int op_32, int exec_delay)
{
int instr_cycles, latency = 0;
if ((timings[opcode] & CYCLES_FPU) && !(deps[opcode] & FPU_FXCH))
instr_cycles = latency = codegen_fpu_latencies(deps[opcode], fetchdat & 7);
else
instr_cycles = 0;
if ((decode_delay + decode_delay_offset) > 0)
codegen_fpu_latency_clock(decode_delay + decode_delay_offset + instr_cycles);
else
codegen_fpu_latency_clock(instr_cycles);
instr_cycles += COUNT(timings[opcode], op_32);
instr_cycles += exec_delay;
if ((decode_delay + decode_delay_offset) > 0)
codegen_block_cycles += instr_cycles + decode_delay + decode_delay_offset;
else
codegen_block_cycles += instr_cycles;
decode_delay = (-instr_cycles) + 1;
if (deps[opcode] & FPU_POP)
{
int c;
for (c = 0; c < 7; c++)
fpu_st_latency[c] = fpu_st_latency[c+1];
fpu_st_latency[7] = 0;
}
if (deps[opcode] & FPU_POP2)
{
int c;
for (c = 0; c < 6; c++)
fpu_st_latency[c] = fpu_st_latency[c+2];
fpu_st_latency[6] = fpu_st_latency[7] = 0;
}
if (timings[opcode] & CYCLES_FPU)
{
/* if (fpu_latency)
fatal("Bad latency FPU\n");*/
fpu_latency = FPU_F_LATENCY(timings[opcode]);
}
if (deps[opcode] & FPU_PUSH)
{
int c;
for (c = 0; c < 7; c++)
fpu_st_latency[c+1] = fpu_st_latency[c];
fpu_st_latency[0] = 0;
}
if (deps[opcode] & FPU_WRITE_ST0)
{
/* if (fpu_st_latency[0])
fatal("Bad latency ST0\n");*/
fpu_st_latency[0] = FPU_RESULT_LATENCY(timings[opcode]);
}
if (deps[opcode] & FPU_WRITE_ST1)
{
/* if (fpu_st_latency[1])
fatal("Bad latency ST1\n");*/
fpu_st_latency[1] = FPU_RESULT_LATENCY(timings[opcode]);
}
if (deps[opcode] & FPU_WRITE_STREG)
{
int reg = fetchdat & 7;
if (deps[opcode] & FPU_POP)
reg--;
if (reg >= 0 &&
!(reg == 0 && (deps[opcode] & FPU_WRITE_ST0)) &&
!(reg == 1 && (deps[opcode] & FPU_WRITE_ST1)))
{
/* if (fpu_st_latency[reg])
fatal("Bad latency STREG %i %08x %i %016llx %02x\n",fpu_st_latency[reg], fetchdat, reg, timings[opcode], opcode);*/
fpu_st_latency[reg] = FPU_RESULT_LATENCY(timings[opcode]);
}
}
}
static void codegen_timing_winchip2_block_start()
{
regmask_modified = 0;
decode_delay = decode_delay_offset = 0;
u_pipe_full = 0;
}
static void codegen_timing_winchip2_start()
{
timing_count = 0;
last_prefix = 0;
}
static void codegen_timing_winchip2_prefix(uint8_t prefix, uint32_t fetchdat)
{
if (prefix == 0x0f)
{
/*0fh prefix is 'free'*/
last_prefix = prefix;
return;
}
/*On WinChip all prefixes take 1 cycle to decode. Decode may be shadowed
by execution of previous instructions*/
decode_delay_offset++;
last_prefix = prefix;
}
static void codegen_timing_winchip2_opcode(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc)
{
uint32_t *timings;
uint64_t *deps;
int mod3 = ((fetchdat & 0xc0) == 0xc0);
int bit8 = !(opcode & 1);
int agi_stall = 0;
switch (last_prefix)
{
case 0x0f:
timings = mod3 ? opcode_timings_0f_mod3 : opcode_timings_0f;
deps = mod3 ? opcode_deps_0f_mod3 : opcode_deps_0f;
break;
case 0xd8:
timings = mod3 ? opcode_timings_d8_mod3 : opcode_timings_d8;
deps = mod3 ? opcode_deps_d8_mod3 : opcode_deps_d8;
opcode = (opcode >> 3) & 7;
break;
case 0xd9:
timings = mod3 ? opcode_timings_d9_mod3 : opcode_timings_d9;
deps = mod3 ? opcode_deps_d9_mod3 : opcode_deps_d9;
opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
break;
case 0xda:
timings = mod3 ? opcode_timings_da_mod3 : opcode_timings_da;
deps = mod3 ? opcode_deps_da_mod3 : opcode_deps_da;
opcode = (opcode >> 3) & 7;
break;
case 0xdb:
timings = mod3 ? opcode_timings_db_mod3 : opcode_timings_db;
deps = mod3 ? opcode_deps_db_mod3 : opcode_deps_db;
opcode = mod3 ? opcode & 0x3f : (opcode >> 3) & 7;
break;
case 0xdc:
timings = mod3 ? opcode_timings_dc_mod3 : opcode_timings_dc;
deps = mod3 ? opcode_deps_dc_mod3 : opcode_deps_dc;
opcode = (opcode >> 3) & 7;
break;
case 0xdd:
timings = mod3 ? opcode_timings_dd_mod3 : opcode_timings_dd;
deps = mod3 ? opcode_deps_dd_mod3 : opcode_deps_dd;
opcode = (opcode >> 3) & 7;
break;
case 0xde:
timings = mod3 ? opcode_timings_de_mod3 : opcode_timings_de;
deps = mod3 ? opcode_deps_de_mod3 : opcode_deps_de;
opcode = (opcode >> 3) & 7;
break;
case 0xdf:
timings = mod3 ? opcode_timings_df_mod3 : opcode_timings_df;
deps = mod3 ? opcode_deps_df_mod3 : opcode_deps_df;
opcode = (opcode >> 3) & 7;
break;
default:
switch (opcode)
{
case 0x80: case 0x82: case 0x83:
timings = mod3 ? opcode_timings_8x_mod3 : opcode_timings_8x;
deps = mod3 ? opcode_deps_8x_mod3 : opcode_deps_8x;
opcode = (fetchdat >> 3) & 7;
break;
case 0x81:
timings = mod3 ? opcode_timings_81_mod3 : opcode_timings_81;
deps = mod3 ? opcode_deps_81_mod3 : opcode_deps_81;
opcode = (fetchdat >> 3) & 7;
break;
case 0xc0: case 0xc1: case 0xd0: case 0xd1: case 0xd2: case 0xd3:
timings = mod3 ? opcode_timings_shift_mod3 : opcode_timings_shift;
deps = mod3 ? opcode_deps_shift_mod3 : opcode_deps_shift;
opcode = (fetchdat >> 3) & 7;
break;
case 0xf6:
timings = mod3 ? opcode_timings_f6_mod3 : opcode_timings_f6;
deps = mod3 ? opcode_deps_f6_mod3 : opcode_deps_f6;
opcode = (fetchdat >> 3) & 7;
break;
case 0xf7:
timings = mod3 ? opcode_timings_f7_mod3 : opcode_timings_f7;
deps = mod3 ? opcode_deps_f7_mod3 : opcode_deps_f7;
opcode = (fetchdat >> 3) & 7;
break;
case 0xff:
timings = mod3 ? opcode_timings_ff_mod3 : opcode_timings_ff;
deps = mod3 ? opcode_deps_ff_mod3 : opcode_deps_ff;
opcode = (fetchdat >> 3) & 7;
break;
default:
timings = mod3 ? opcode_timings_mod3 : opcode_timings;
deps = mod3 ? opcode_deps_mod3 : opcode_deps;
break;
}
}
if (u_pipe_full)
{
uint8_t regmask = get_srcdep_mask(deps[opcode], fetchdat, bit8, u_pipe_op_32);
if (can_pair(u_pipe_timings[u_pipe_opcode], timings[opcode], regmask))
{
int cycles_a = u_pipe_timings[u_pipe_opcode] & 0xff;
int cycles_b = timings[opcode] & 0xff;
uint32_t timing = (cycles_a > cycles_b) ? u_pipe_timings[u_pipe_opcode] : timings[opcode];
uint64_t temp_deps = 0;
if (check_agi(deps, opcode, fetchdat, op_32) || check_agi(u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_op_32))
agi_stall = 1;
codegen_instruction(&timing, &temp_deps, 0, 0, 0, 0, agi_stall);
u_pipe_full = 0;
decode_delay_offset = 0;
regmask_modified = get_dstdep_mask(deps[opcode], fetchdat, bit8) | u_pipe_regmask;
return;
}
else
{
/*No pairing, run first instruction now*/
if (check_agi(u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_op_32))
agi_stall = 1;
codegen_instruction(u_pipe_timings, u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_decode_delay_offset, u_pipe_op_32, agi_stall);
u_pipe_full = 0;
regmask_modified = u_pipe_regmask;
}
}
if (timings[opcode] & CYCLES_IS_MMX)
{
/*Might pair with next instruction*/
u_pipe_full = 1;
u_pipe_opcode = opcode;
u_pipe_timings = timings;
u_pipe_op_32 = op_32;
u_pipe_regmask = get_dstdep_mask(deps[opcode], fetchdat, bit8);
u_pipe_fetchdat = fetchdat;
u_pipe_decode_delay_offset = decode_delay_offset;
u_pipe_deps = deps;
decode_delay_offset = 0;
return;
}
if (check_agi(deps, opcode, fetchdat, op_32))
agi_stall = 1;
codegen_instruction(timings, deps, opcode, fetchdat, decode_delay_offset, op_32, agi_stall);
decode_delay_offset = 0;
regmask_modified = get_dstdep_mask(deps[opcode], fetchdat, bit8);
}
static void codegen_timing_winchip2_block_end()
{
if (u_pipe_full)
{
int agi_stall = 0;
if (check_agi(u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_op_32))
agi_stall = 1;
codegen_instruction(u_pipe_timings, u_pipe_deps, u_pipe_opcode, u_pipe_fetchdat, u_pipe_decode_delay_offset, u_pipe_op_32, agi_stall);
u_pipe_full = 0;
}
}
codegen_timing_t codegen_timing_winchip2 =
{
codegen_timing_winchip2_start,
codegen_timing_winchip2_prefix,
codegen_timing_winchip2_opcode,
codegen_timing_winchip2_block_start,
codegen_timing_winchip2_block_end,
NULL
};

29
src/cpu/codegen_x86-64.c
View File

@@ -1067,7 +1067,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
}
generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32);
codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
if ((op_table == x86_dynarec_opcodes &&
((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
@@ -1075,6 +1075,24 @@ generate_call:
(opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) ||
(op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80)))
{
/*On some CPUs (eg K6), a jump/branch instruction may be able to pair with
subsequent instructions, so no cycles may have been deducted for it yet.
To prevent having zero cycle blocks (eg with a jump instruction pointing
to itself), apply the cycles that would be taken if this jump is taken,
then reverse it for subsequent instructions if the jump is not taken*/
int jump_cycles = 0;
if (codegen_timing_jump_cycles != NULL)
codegen_timing_jump_cycles();
if (jump_cycles)
{
addbyte(0x81); /*SUB $jump_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t)cpu_state_offset(_cycles));
addlong((uint32_t)jump_cycles);
}
/*Opcode is likely to cause block to exit, update cycle count*/
if (codegen_block_cycles)
{
@@ -1092,6 +1110,15 @@ generate_call:
addlong(codegen_block_ins);
codegen_block_ins = 0;
}
if (jump_cycles)
{
addbyte(0x81); /*SUB $jump_cycles, cyclcs*/
addbyte(0x6d);
addbyte((uint8_t)cpu_state_offset(_cycles));
addlong((uint32_t)jump_cycles);
jump_cycles = 0;
}
}
if ((op_table == x86_dynarec_opcodes_REPNE || op_table == x86_dynarec_opcodes_REPE) && !op_table[opcode | op_32])

49
src/cpu/codegen_x86.c
View File

@@ -977,8 +977,8 @@ static uint32_t gen_MEM_CHECK_WRITE()
addbyte(0x6a); /*PUSH 1*/
addbyte(1);
addbyte(0x57); /*PUSH EDI*/
addbyte(0xe8); /*CALL mmutranslatereal*/
addlong((uint32_t)mmutranslatereal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0xe8); /*CALL mmutranslatereal32*/
addlong((uint32_t)mmutranslatereal32 - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x83); /*ADD ESP, 8*/
addbyte(0xc4);
addbyte(8);
@@ -1049,8 +1049,8 @@ static uint32_t gen_MEM_CHECK_WRITE_W()
addbyte(0x6a); /*PUSH 1*/
addbyte(1);
addbyte(0x57); /*PUSH EDI*/
addbyte(0xe8); /*CALL mmutranslatereal*/
addlong((uint32_t)mmutranslatereal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0xe8); /*CALL mmutranslatereal32*/
addlong((uint32_t)mmutranslatereal32 - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x5f); /*POP EDI*/
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
@@ -1131,8 +1131,8 @@ static uint32_t gen_MEM_CHECK_WRITE_L()
addbyte(0x6a); /*PUSH 1*/
addbyte(1);
addbyte(0x57); /*PUSH EDI*/
addbyte(0xe8); /*CALL mmutranslatereal*/
addlong((uint32_t)mmutranslatereal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0xe8); /*CALL mmutranslatereal32*/
addlong((uint32_t)mmutranslatereal32 - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0x5f); /*POP EDI*/
addbyte(0x83); /*ADD ESP, 4*/
addbyte(0xc4);
@@ -1874,7 +1874,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
int pc_off = 0;
int test_modrm = 1;
int c;
op_ea_seg = &cpu_state.seg_ds;
op_ssegs = 0;
op_old_pc = old_pc;
@@ -2031,7 +2031,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
}
generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32);
codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
if ((op_table == x86_dynarec_opcodes &&
((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
@@ -2039,10 +2039,28 @@ generate_call:
(opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) ||
(op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80)))
{
/*On some CPUs (eg K6), a jump/branch instruction may be able to pair with
subsequent instructions, so no cycles may have been deducted for it yet.
To prevent having zero cycle blocks (eg with a jump instruction pointing
to itself), apply the cycles that would be taken if this jump is taken,
then reverse it for subsequent instructions if the jump is not taken*/
int jump_cycles = 0;
if (codegen_timing_jump_cycles != NULL)
codegen_timing_jump_cycles();
if (jump_cycles)
{
addbyte(0x81); /*SUB $jump_cycles, cycles*/
addbyte(0x6d);
addbyte((uint8_t)cpu_state_offset(_cycles));
addlong(jump_cycles);
}
/*Opcode is likely to cause block to exit, update cycle count*/
if (codegen_block_cycles)
{
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x81); /*SUB $codegen_block_cycles, cycles*/
addbyte(0x6d);
addbyte((uint8_t)cpu_state_offset(_cycles));
addlong(codegen_block_cycles);
@@ -2066,6 +2084,15 @@ generate_call:
codegen_block_full_ins = 0;
}
#endif
if (jump_cycles)
{
addbyte(0x81); /*SUB $jump_cycles, cycles*/
addbyte(0x6d);
addbyte((uint8_t)cpu_state_offset(_cycles));
addlong(jump_cycles);
jump_cycles = 0;
}
}
if ((op_table == x86_dynarec_opcodes_REPNE || op_table == x86_dynarec_opcodes_REPE) && !op_table[opcode | op_32])
@@ -2099,7 +2126,7 @@ generate_call:
addbyte(0xC6); /*MOVB [ssegs],op_ssegs*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(ssegs));
addbyte(op_pc + pc_off);
addbyte(op_pc + pc_off);
}
if (!test_modrm ||
@@ -2140,7 +2167,7 @@ generate_call:
addbyte(0xC7); /*MOVL pc,new_pc*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(pc));
addlong(op_pc + pc_off);
addlong(op_pc + pc_off);
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
addbyte(0x45);

161
src/cpu/x86seg.c
View File

@@ -391,12 +391,17 @@ void loadseg(uint16_t seg, x86seg *s)
{
if (!(seg&~3))
{
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Stack segment is zero",seg&~3);
return;
}
if ((seg&3)!=CPL || dpl!=CPL)
if ((seg&3)!=CPL)
{
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Stack segment RPL != CPL",seg&~3);
return;
}
if (dpl!=CPL)
{
x86gpf("loadseg(): Stack segment DPL != CPL",seg&~3);
return;
}
switch ((segdat[2]>>8)&0x1F)
@@ -404,7 +409,7 @@ void loadseg(uint16_t seg, x86seg *s)
case 0x12: case 0x13: case 0x16: case 0x17: /*r/w*/
break;
default:
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Unknown stack segment type",seg&~3);
return;
}
if (!(segdat[2]&0x8000))
@@ -423,16 +428,21 @@ void loadseg(uint16_t seg, x86seg *s)
case 0x10: case 0x11: case 0x12: case 0x13: /*Data segments*/
case 0x14: case 0x15: case 0x16: case 0x17:
case 0x1A: case 0x1B: /*Readable non-conforming code*/
if ((seg&3)>dpl || (CPL)>dpl)
if ((seg&3)>dpl)
{
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Normal segment is zero",seg&~3);
return;
}
if ((CPL)>dpl)
{
x86gpf("loadseg(): Normal segment DPL < CPL",seg&~3);
return;
}
break;
case 0x1E: case 0x1F: /*Readable conforming code*/
break;
default:
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Unknown normal segment type",seg&~3);
return;
}
}
@@ -519,7 +529,7 @@ void loadcs(uint16_t seg)
{
if (addr>=ldt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("loadcs(): Protected mode selector > LDT limit",seg&~3);
return;
}
addr+=ldt.base;
@@ -528,7 +538,7 @@ void loadcs(uint16_t seg)
{
if (addr>=gdt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("loadcs(): Protected mode selector > GDT limit",seg&~3);
return;
}
addr+=gdt.base;
@@ -544,12 +554,12 @@ void loadcs(uint16_t seg)
{
if ((seg&3)>CPL)
{
x86gpf(NULL,seg&~3);
x86gpf("loadcs(): Non-conforming RPL > CPL",seg&~3);
return;
}
if (CPL != DPL)
{
x86gpf("loadcs(): CPL != DPL",seg&~3);
x86gpf("loadcs(): Non-conforming CPL != DPL",seg&~3);
return;
}
}
@@ -579,13 +589,13 @@ void loadcs(uint16_t seg)
{
if (!(segdat[2]&0x8000))
{
x86np("Load CS system seg not present\n", seg & 0xfffc);
x86np("Load CS system seg not present", seg & 0xfffc);
return;
}
switch (segdat[2]&0xF00)
{
default:
x86gpf(NULL,seg&~3);
x86gpf("Load CS system segment has bits 0-3 of access rights set",seg&~3);
return;
}
}
@@ -614,7 +624,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
{
if (!(seg&~3))
{
x86gpf(NULL,0);
x86gpf("loadcsjmp(): Selector is zero",0);
return;
}
addr=seg&~7;
@@ -622,7 +632,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
{
if (addr>=ldt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("loacsjmp(): Selector > LDT limit",seg&~3);
return;
}
addr+=ldt.base;
@@ -631,7 +641,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
{
if (addr>=gdt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("loacsjmp(): Selector > GDT limit",seg&~3);
return;
}
addr+=gdt.base;
@@ -700,9 +710,14 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
cgate16=!cgate32;
oldcs=CS;
cpu_state.oldpc = cpu_state.pc;
if ((DPL < CPL) || (DPL < (seg&3)))
if (DPL < CPL)
{
x86gpf(NULL,seg&~3);
x86gpf("loadcsjmp(): Call gate DPL < CPL",seg&~3);
return;
}
if (DPL < (seg&3))
{
x86gpf("loadcsjmp(): Call gate DPL< RPL",seg&~3);
return;
}
if (DPL < CPL)
@@ -732,7 +747,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
{
if (addr>=ldt.limit)
{
x86gpf(NULL,seg2&~3);
x86gpf("loadcsjmp(): Call gate selector > LDT limit",seg2&~3);
return;
}
addr+=ldt.base;
@@ -741,7 +756,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
{
if (addr>=gdt.limit)
{
x86gpf(NULL,seg2&~3);
x86gpf("loadcsjmp(): Call gate selector > GDT limit",seg2&~3);
return;
}
addr+=gdt.base;
@@ -769,7 +784,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming code*/
if (DPL > CPL)
{
x86gpf(NULL,seg2&~3);
x86gpf("loadcsjmp(): Non-conforming DPL > CPL",seg2&~3);
return;
}
/*FALLTHROUGH*/
@@ -789,7 +804,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
break;
default:
x86gpf(NULL,seg2&~3);
x86gpf("loadcsjmp(): Unknown type",seg2&~3);
return;
}
cycles -= timing_jmp_pm_gate;
@@ -910,7 +925,7 @@ void loadcscall(uint16_t seg)
if (csout) x86seg_log("Protected mode CS load! %04X\n",seg);
if (!(seg&~3))
{
x86gpf(NULL,0);
x86gpf("loadcscall(): Protected mode selector is zero",0);
return;
}
addr=seg&~7;
@@ -918,7 +933,7 @@ void loadcscall(uint16_t seg)
{
if (addr>=ldt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("loadcscall(): Selector > LDT limit",seg&~3);
return;
}
addr+=ldt.base;
@@ -927,7 +942,7 @@ void loadcscall(uint16_t seg)
{
if (addr>=gdt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("loadcscall(): Selector > GDT limit",seg&~3);
return;
}
addr+=gdt.base;
@@ -948,18 +963,18 @@ void loadcscall(uint16_t seg)
{
if ((seg&3)>CPL)
{
x86gpf("loadcscall(): segment > CPL",seg&~3);
x86gpf("loadcscall(): Non-conforming RPL > CPL",seg&~3);
return;
}
if (CPL != DPL)
{
x86gpf(NULL,seg&~3);
x86gpf("loadcscall(): Non-conforming CPL != DPL",seg&~3);
return;
}
}
if (CPL < DPL)
{
x86gpf(NULL,seg&~3);
x86gpf("loadcscall(): CPL < DPL",seg&~3);
return;
}
if (!(segdat[2]&0x8000))
@@ -1033,7 +1048,7 @@ void loadcscall(uint16_t seg)
{
if (addr>=ldt.limit)
{
x86gpf(NULL,seg2&~3);
x86gpf("loadcscall(): ex Selector > LDT limit",seg2&~3);
return;
}
addr+=ldt.base;
@@ -1042,7 +1057,7 @@ void loadcscall(uint16_t seg)
{
if (addr>=gdt.limit)
{
x86gpf(NULL,seg2&~3);
x86gpf("loadcscall(): ex Selector > GDT limit",seg2&~3);
return;
}
addr+=gdt.base;
@@ -1241,7 +1256,7 @@ void loadcscall(uint16_t seg)
}
else if (DPL > CPL)
{
x86gpf(NULL,seg2&~3);
x86gpf("loadcscall(): Call PM Gate Inner DPL > CPL",seg2&~3);
return;
}
/*FALLTHROUGH*/
@@ -1261,7 +1276,7 @@ void loadcscall(uint16_t seg)
break;
default:
x86gpf(NULL,seg2&~3);
x86gpf("loadcscall(): Unknown subtype",seg2&~3);
return;
}
break;
@@ -1275,7 +1290,7 @@ void loadcscall(uint16_t seg)
break;
default:
x86gpf(NULL,seg&~3);
x86gpf("loadcscall(): Unknown type",seg&~3);
return;
}
}
@@ -1331,7 +1346,7 @@ void pmoderetf(int is32, uint16_t off)
{
if (addr>=ldt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("pmoderetf(): Selector > LDT limit",seg&~3);
return;
}
addr+=ldt.base;
@@ -1340,7 +1355,7 @@ void pmoderetf(int is32, uint16_t off)
{
if (addr>=gdt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("pmoderetf(): Selector > GDT limit",seg&~3);
return;
}
addr+=gdt.base;
@@ -1366,7 +1381,7 @@ void pmoderetf(int is32, uint16_t off)
if (CPL != DPL)
{
ESP=oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmoderetf(): Non-conforming CPL != DPL",seg&~3);
return;
}
break;
@@ -1374,12 +1389,12 @@ void pmoderetf(int is32, uint16_t off)
if (CPL < DPL)
{
ESP=oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmoderetf(): Conforming CPL < DPL",seg&~3);
return;
}
break;
default:
x86gpf(NULL,seg&~3);
x86gpf("pmoderetf(): Unknown type",seg&~3);
return;
}
if (!(segdat[2]&0x8000))
@@ -1414,7 +1429,7 @@ void pmoderetf(int is32, uint16_t off)
if ((seg&3) != DPL)
{
ESP=oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmoderetf(): Non-conforming RPL != DPL",seg&~3);
return;
}
x86seg_log("RETF non-conforming, %i %i\n",seg&3, DPL);
@@ -1423,14 +1438,14 @@ void pmoderetf(int is32, uint16_t off)
if ((seg&3) < DPL)
{
ESP=oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmoderetf(): Conforming RPL < DPL",seg&~3);
return;
}
x86seg_log("RETF conforming, %i %i\n",seg&3, DPL);
break;
default:
ESP=oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmoderetf(): Unknown type",seg&~3);
return;
}
if (!(segdat[2]&0x8000))
@@ -1455,7 +1470,7 @@ void pmoderetf(int is32, uint16_t off)
if (!(newss&~3))
{
ESP=oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmoderetf(): New SS selector is zero",newss&~3);
return;
}
addr=newss&~7;
@@ -1464,7 +1479,7 @@ void pmoderetf(int is32, uint16_t off)
if (addr>=ldt.limit)
{
ESP=oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmoderetf(): New SS selector > LDT limit",newss&~3);
return;
}
addr+=ldt.base;
@@ -1474,7 +1489,7 @@ void pmoderetf(int is32, uint16_t off)
if (addr>=gdt.limit)
{
ESP=oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmoderetf(): New SS selector > GDT limit",newss&~3);
return;
}
addr+=gdt.base;
@@ -1488,13 +1503,13 @@ void pmoderetf(int is32, uint16_t off)
if ((newss & 3) != (seg & 3))
{
ESP=oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmoderetf(): New SS RPL > CS RPL",newss&~3);
return;
}
if ((segdat2[2]&0x1A00)!=0x1200)
{
ESP=oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmoderetf(): New SS unknown type",newss&~3);
return;
}
if (!(segdat2[2]&0x8000))
@@ -1506,7 +1521,7 @@ void pmoderetf(int is32, uint16_t off)
if (DPL2 != (seg & 3))
{
ESP=oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmoderetf(): New SS DPL != CS RPL",newss&~3);
return;
}
SS=newss;
@@ -1564,7 +1579,7 @@ void pmodeint(int num, int soft)
if (cpu_state.eflags&VM_FLAG && IOPL!=3 && soft)
{
x86seg_log("V86 banned int\n");
x86gpf(NULL,0);
x86gpf("pmodeint(): V86 banned int",0);
return;
}
addr=(num<<3);
@@ -1582,9 +1597,9 @@ void pmodeint(int num, int soft)
}
else
{
x86gpf(NULL,(num*8)+2+((soft)?0:1));
x86gpf("pmodeint(): Vector > IDT limit",(num*8)+2+((soft)?0:1));
}
x86seg_log("addr >= IDT.limit\n");
x86seg_log("addr >= IDT.limit\n");
return;
}
addr+=idt.base;
@@ -1598,12 +1613,12 @@ void pmodeint(int num, int soft)
x86seg_log("Addr %08X seg %04X %04X %04X %04X\n",addr,segdat[0],segdat[1],segdat[2],segdat[3]);
if (!(segdat[2]&0x1F00))
{
x86gpf(NULL,(num*8)+2);
x86gpf("pmodeint(): Vector descriptor with bad type",(num*8)+2);
return;
}
if (DPL<CPL && soft)
{
x86gpf(NULL,(num*8)+2);
x86gpf("pmodeint(): Vector DPL < CPL",(num*8)+2);
return;
}
type=segdat[2]&0x1F00;
@@ -1624,7 +1639,7 @@ void pmodeint(int num, int soft)
{
if (addr>=ldt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("pmodeint(): Interrupt or trap gate selector > LDT limit",seg&~3);
return;
}
addr+=ldt.base;
@@ -1633,7 +1648,7 @@ void pmodeint(int num, int soft)
{
if (addr>=gdt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("pmodeint(): Interrupt or trap gate selector > GDT limit", seg&~3);
return;
}
addr+=gdt.base;
@@ -1647,7 +1662,7 @@ void pmodeint(int num, int soft)
if (DPL2 > CPL)
{
x86gpf(NULL,seg&~3);
x86gpf("pmodeint(): Interrupt or trap gate DPL > CPL",seg&~3);
return;
}
switch (segdat2[2]&0x1F00)
@@ -1662,7 +1677,7 @@ void pmodeint(int num, int soft)
}
if ((cpu_state.eflags&VM_FLAG) && DPL2)
{
x86gpf(NULL,segdat[1]&0xFFFC);
x86gpf("pmodeint(): Interrupt or trap gate non-zero DPL in V86 mode",segdat[1]&0xFFFC);
return;
}
/*Load new stack*/
@@ -1774,7 +1789,7 @@ void pmodeint(int num, int soft)
}
else if (DPL2!=CPL)
{
x86gpf(NULL,seg&~3);
x86gpf("pmodeint(): DPL != CPL",seg&~3);
return;
}
/*FALLTHROUGH*/
@@ -1786,7 +1801,7 @@ void pmodeint(int num, int soft)
}
if ((cpu_state.eflags & VM_FLAG) && DPL2<CPL)
{
x86gpf(NULL,seg&~3);
x86gpf("pmodeint(): DPL < CPL in V86 mode",seg&~3);
return;
}
if (type>0x800)
@@ -1804,7 +1819,7 @@ void pmodeint(int num, int soft)
new_cpl = CS & 3;
break;
default:
x86gpf(NULL,seg&~3);
x86gpf("pmodeint(): Unknown type",seg&~3);
return;
}
do_seg_load(&cpu_state.seg_cs, segdat2);
@@ -1838,7 +1853,7 @@ void pmodeint(int num, int soft)
{
if (addr>=ldt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("pmodeint(): Task gate selector > LDT limit",seg&~3);
return;
}
addr+=ldt.base;
@@ -1847,7 +1862,7 @@ void pmodeint(int num, int soft)
{
if (addr>=gdt.limit)
{
x86gpf(NULL,seg&~3);
x86gpf("pmodeint(): Task gate selector > GDT limit",seg&~3);
return;
}
addr+=gdt.base;
@@ -1926,7 +1941,7 @@ void pmodeiret(int is32)
if (seg&4)
{
x86seg_log("TS LDT %04X %04X IRET\n",seg,gdt.limit);
x86ts(NULL,seg&~3);
x86ts("pmodeiret(): Selector points to LDT",seg&~3);
return;
}
else
@@ -2016,7 +2031,7 @@ void pmodeiret(int is32)
if (addr>=ldt.limit)
{
ESP = oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmodeiret(): Selector > LDT limit",seg&~3);
return;
}
addr+=ldt.base;
@@ -2026,7 +2041,7 @@ void pmodeiret(int is32)
if (addr>=gdt.limit)
{
ESP = oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmodeiret(): Selector > GDT limit",seg&~3);
return;
}
addr+=gdt.base;
@@ -2034,7 +2049,7 @@ void pmodeiret(int is32)
if ((seg&3) < CPL)
{
ESP = oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmodeiret(): RPL < CPL",seg&~3);
return;
}
cpl_override=1;
@@ -2049,7 +2064,7 @@ void pmodeiret(int is32)
if ((seg&3) != DPL)
{
ESP = oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmodeiret(): Non-conforming RPL != DPL",seg&~3);
return;
}
break;
@@ -2057,7 +2072,7 @@ void pmodeiret(int is32)
if ((seg&3) < DPL)
{
ESP = oldsp;
x86gpf(NULL,seg&~3);
x86gpf("pmodeiret(): Conforming RPL < DPL",seg&~3);
return;
}
break;
@@ -2107,7 +2122,7 @@ void pmodeiret(int is32)
if (!(newss&~3))
{
ESP = oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmodeiret(): New SS selector is zero",newss&~3);
return;
}
addr=newss&~7;
@@ -2116,7 +2131,7 @@ void pmodeiret(int is32)
if (addr>=ldt.limit)
{
ESP = oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmodeiret(): New SS selector > LDT limit",newss&~3);
return;
}
addr+=ldt.base;
@@ -2126,7 +2141,7 @@ void pmodeiret(int is32)
if (addr>=gdt.limit)
{
ESP = oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmodeiret(): New SS selector > GDT limit",newss&~3);
return;
}
addr+=gdt.base;
@@ -2139,19 +2154,19 @@ void pmodeiret(int is32)
if ((newss & 3) != (seg & 3))
{
ESP = oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmodeiret(): New SS RPL > CS RPL",newss&~3);
return;
}
if ((segdat2[2]&0x1A00)!=0x1200)
{
ESP = oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmodeiret(): New SS bad type",newss&~3);
return;
}
if (DPL2 != (seg & 3))
{
ESP = oldsp;
x86gpf(NULL,newss&~3);
x86gpf("pmodeiret(): New SS DPL != CS RPL",newss&~3);
return;
}
if (!(segdat2[2]&0x8000))

25
src/cpu_common/386.c
View File

@@ -280,33 +280,14 @@ exec386(int cycs)
}
}
if ((in_smm == 0) && smi_line) {
#ifdef ENABLE_386_LOG
x386_log("SMI while not in SMM\n");
#endif
enter_smm();
smi_line = 0;
} else if ((in_smm == 1) && smi_line) {
/* Mark this so that we don't latch more than one SMI. */
#ifdef ENABLE_386_LOG
x386_log("SMI while in unlatched SMM\n");
#endif
smi_latched = 1;
smi_line = 0;
} else if ((in_smm == 2) && smi_line) {
/* Mark this so that we don't latch more than one SMI. */
#ifdef ENABLE_386_LOG
x386_log("SMI while in latched SMM\n");
#endif
smi_line = 0;
}
ins_cycles -= cycles;
tsc += ins_cycles;
cycdiff = oldcyc - cycles;
if (trap) {
if (smi_line)
enter_smm_check(0);
else if (trap) {
flags_rebuild();
if (msw&1)
pmodeint(1,0);

1822
src/cpu_common/386_common.c
View File

File diff suppressed because it is too large Load Diff

1144
src/cpu_common/386_dynarec.c
View File

File diff suppressed because it is too large Load Diff

6
src/cpu_common/386_dynarec_ops.c
View File

@@ -26,6 +26,8 @@
#include "386_common.h"
#define SYSENTER_LOG 1
static __inline void fetch_ea_32_long(uint32_t rmdat)
{
eal_r = eal_w = NULL;
@@ -66,7 +68,7 @@ static __inline void fetch_ea_16_long(uint32_t rmdat)
#define OP_TABLE(name) dynarec_ops_ ## name
#define CLOCK_CYCLES(c) in_hlt = 0
#define CLOCK_CYCLES_ALWAYS(c) do { cycles -= (c); in_hlt = 0; } while(0)
#define CLOCK_CYCLES(c)
#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
#include "386_ops.h"

14
src/cpu_common/386_ops.h
View File

@@ -167,14 +167,6 @@ static int ILLEGAL(uint32_t fetchdat)
return 0;
}
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && (defined(USE_AMD_K) || defined(USE_I686)))
static int internal_illegal(char *s)
{
cpu_state.pc = cpu_state.oldpc;
x86gpf(s, 0);
return cpu_state.abrt;
}
#endif
#ifdef ENABLE_386_DYNAREC_LOG
extern void x386_dynarec_log(const char *fmt, ...);
@@ -224,9 +216,7 @@ extern void x386_dynarec_log(const char *fmt, ...);
#include "x86_ops_xchg.h"
#include "x86_ops_call.h"
#include "x86_ops_shift.h"
#ifdef USE_NEW_DYNAREC
#include "x86_ops_amd.h"
#endif
#include "x86_ops_3dnow.h"
@@ -909,7 +899,6 @@ const OpFn OP_TABLE(pentiummmx_0f)[1024] =
/*f0*/ ILLEGAL, opPSLLW_a32, opPSLLD_a32, opPSLLQ_a32, ILLEGAL, opPMADDWD_a32, ILLEGAL, ILLEGAL, opPSUBB_a32, opPSUBW_a32, opPSUBD_a32, ILLEGAL, opPADDB_a32, opPADDW_a32, opPADDD_a32, ILLEGAL,
};
#ifdef USE_NEW_DYNAREC
const OpFn OP_TABLE(k6_0f)[1024] =
{
/*16-bit data, 16-bit addr*/
@@ -1091,9 +1080,8 @@ const OpFn OP_TABLE(k62_0f)[1024] =
/*e0*/ ILLEGAL, opPSRAW_a32, opPSRAD_a32, ILLEGAL, ILLEGAL, opPMULHW_a32, ILLEGAL, ILLEGAL, opPSUBSB_a32, opPSUBSW_a32, NULL, opPOR_a32, opPADDSB_a32, opPADDSW_a32, NULL, opPXOR_a32,
/*f0*/ ILLEGAL, opPSLLW_a32, opPSLLD_a32, opPSLLQ_a32, ILLEGAL, opPMADDWD_a32, ILLEGAL, ILLEGAL, opPSUBB_a32, opPSUBW_a32, opPSUBD_a32, ILLEGAL, opPADDB_a32, opPADDW_a32, opPADDD_a32, ILLEGAL,
};
#endif
#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
const OpFn OP_TABLE(c6x86mx_0f)[1024] =
{
/*16-bit data, 16-bit addr*/

3
src/cpu_common/808x.c
View File

@@ -972,10 +972,11 @@ reset_common(int hard)
cpu_alu_op = 0;
in_smm = smi_latched = 0;
smi_line = in_hlt = 0;
smi_line = smm_in_hlt = 0;
if (hard)
smbase = 0x00030000;
in_sys = 0;
}

131
src/cpu_common/cpu.c
View File

@@ -71,6 +71,7 @@ enum {
CPUID_PSE = (1 << 3),
CPUID_TSC = (1 << 4),
CPUID_MSR = (1 << 5),
CPUID_PAE = (1 << 6),
CPUID_CMPXCHG8B = (1 << 8),
CPUID_AMDSEP = (1 << 10),
CPUID_SEP = (1 << 11),
@@ -108,10 +109,8 @@ const OpFn *x86_dynarec_opcodes_df_a16;
const OpFn *x86_dynarec_opcodes_df_a32;
const OpFn *x86_dynarec_opcodes_REPE;
const OpFn *x86_dynarec_opcodes_REPNE;
#ifdef USE_NEW_DYNAREC
const OpFn *x86_dynarec_opcodes_3DNOW;
#endif
#endif
const OpFn *x86_opcodes;
const OpFn *x86_opcodes_0f;
@@ -135,7 +134,7 @@ const OpFn *x86_opcodes_REPE;
const OpFn *x86_opcodes_REPNE;
const OpFn *x86_opcodes_3DNOW;
int in_smm = 0, smi_line = 0, smi_latched = 0, in_hlt = 0;
int in_smm = 0, smi_line = 0, smi_latched = 0, smm_in_hlt = 0;
uint32_t smbase = 0x30000;
CPU *cpu_s;
@@ -178,7 +177,7 @@ uint64_t pmc[2] = {0, 0};
uint16_t temp_seg_data[4] = {0, 0, 0, 0};
uint64_t mtrr_cap_msr = 0;
uint64_t mtrr_cap_msr = 0x00000508;
uint64_t mtrr_physbase_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0};
uint64_t mtrr_physmask_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0};
uint64_t mtrr_fix64k_8000_msr = 0;
@@ -206,21 +205,13 @@ uint64_t ecx1e0_msr = 0;
uint64_t ecx570_msr = 0;
#endif
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
uint64_t ecx83_msr = 0; /* AMD K5 and K6 MSR's. */
#ifdef USE_NEW_DYNAREC
uint64_t star = 0; /* AMD K6-2+. */
#endif
#ifdef USE_NEW_DYNAREC
uint64_t amd_efer = 0, amd_whcr = 0,
amd_uwccr = 0, amd_epmr = 0, /* AMD K6-2+ registers. */
amd_psor = 0, amd_pfir = 0,
amd_l2aar = 0;
#else
uint64_t amd_efer = 0, amd_whcr = 0;
#endif
#endif
int timing_rr;
int timing_mr, timing_mrl;
@@ -317,21 +308,15 @@ cpu_set(void)
is486dx2 = (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_iDX4);
isdx4 = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP);
is_pentium = (cpu_s->cpu_type == CPU_PENTIUM) || (cpu_s->cpu_type == CPU_PENTIUMMMX);
#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)))
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
is_k5 = (cpu_s->cpu_type == CPU_K5) || (cpu_s->cpu_type == CPU_5K86);
#else
is_k5 = 0;
is_k5 = 0;
#endif
#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)))
is_k6 = (cpu_s->cpu_type == CPU_K6);
#else
is_k6 = 0;
#endif
#ifdef USE_NEW_DYNAREC
is_k6 = is_k6 || (cpu_s->cpu_type == CPU_K6_2) || (cpu_s->cpu_type == CPU_K6_2C) ||
(cpu_s->cpu_type == CPU_K6_3) || (cpu_s->cpu_type == CPU_K6_2P) ||
(cpu_s->cpu_type == CPU_K6_3P);
#endif
is_k6 = (cpu_s->cpu_type == CPU_K6) || (cpu_s->cpu_type == CPU_K6_2) ||
(cpu_s->cpu_type == CPU_K6_2C) || (cpu_s->cpu_type == CPU_K6_3) ||
(cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P);
#if defined(DEV_BRANCH) && defined(USE_I686)
is_p6 = (cpu_s->cpu_type == CPU_PENTIUMPRO) || (cpu_s->cpu_type == CPU_PENTIUM2) ||
(cpu_s->cpu_type == CPU_PENTIUM2D);
@@ -340,7 +325,7 @@ cpu_set(void)
#endif
hasfpu = (cpu_s->cpu_type >= CPU_i486DX) || (cpu_s->cpu_type == CPU_RAPIDCAD);
hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL);
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1);
#else
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86);
@@ -402,10 +387,8 @@ cpu_set(void)
#ifdef USE_DYNAREC
x86_dynarec_opcodes_REPE = dynarec_ops_REPE;
x86_dynarec_opcodes_REPNE = dynarec_ops_REPNE;
#ifdef USE_NEW_DYNAREC
x86_dynarec_opcodes_3DNOW = dynarec_ops_3DNOW;
#endif
#endif
#ifdef USE_DYNAREC
if (hasfpu)
@@ -965,7 +948,6 @@ cpu_set(void)
cpu_cyrix_alignment = 1;
break;
#ifdef USE_NEW_DYNAREC
case CPU_WINCHIP2:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_winchip2_0f, dynarec_ops_386, dynarec_ops_winchip2_0f);
@@ -1009,7 +991,6 @@ cpu_set(void)
codegen_timing_set(&codegen_timing_winchip2);
#endif
break;
#endif
case CPU_PENTIUM:
#ifdef USE_DYNAREC
@@ -1097,7 +1078,7 @@ cpu_set(void)
#endif
break;
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
case CPU_Cx6x86:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
@@ -1268,7 +1249,7 @@ cpu_set(void)
break;
#endif
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
case CPU_K5:
case CPU_5K86:
#ifdef USE_DYNAREC
@@ -1308,16 +1289,17 @@ cpu_set(void)
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_MMX;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
#if defined(USE_NEW_DYNAREC) && defined(USE_DYNAREC)
#ifdef USE_DYNAREC
codegen_timing_set(&codegen_timing_k6);
#endif
break;
#endif
case CPU_K6:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_pentiummmx_0f, dynarec_ops_386, dynarec_ops_pentiummmx_0f);
x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f);
#else
x86_setopcodes(ops_386, ops_pentiummmx_0f);
x86_setopcodes(ops_386, ops_k6_0f);
#endif
timing_rr = 1; /*register dest - register src*/
timing_rm = 2; /*register dest - memory src*/
@@ -1352,16 +1334,10 @@ cpu_set(void)
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
#ifdef USE_DYNAREC
#ifdef USE_NEW_DYNAREC
codegen_timing_set(&codegen_timing_k6);
#else
codegen_timing_set(&codegen_timing_pentium);
#endif
#endif
break;
#endif
#ifdef USE_NEW_DYNAREC
case CPU_K6_2:
case CPU_K6_2C:
case CPU_K6_3:
@@ -1406,7 +1382,6 @@ cpu_set(void)
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE;
codegen_timing_set(&codegen_timing_k6);
break;
#endif
#if defined(DEV_BRANCH) && defined(USE_I686)
case CPU_PENTIUMPRO:
@@ -1458,13 +1433,9 @@ cpu_set(void)
timing_misaligned = 3;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_PAE | CR4_MCE | CR4_PCE;
#ifdef USE_DYNAREC
#ifdef USE_NEW_DYNAREC
codegen_timing_set(&codegen_timing_p6);
#else
codegen_timing_set(&codegen_timing_686);
#endif
#endif
break;
@@ -1517,13 +1488,9 @@ cpu_set(void)
timing_misaligned = 3;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_MMX;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_PAE | CR4_MCE | CR4_PCE;
#ifdef USE_DYNAREC
#ifdef USE_NEW_DYNAREC
codegen_timing_set(&codegen_timing_p6);
#else
codegen_timing_set(&codegen_timing_686);
#endif
#endif
break;
@@ -1576,13 +1543,9 @@ cpu_set(void)
timing_misaligned = 3;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_VME | CPU_FEATURE_MMX;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE | CR4_OSFXSR;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PAE | CR4_PCE | CR4_OSFXSR;
#ifdef USE_DYNAREC
#ifdef USE_NEW_DYNAREC
codegen_timing_set(&codegen_timing_p6);
#else
codegen_timing_set(&codegen_timing_686);
#endif
#endif
break;
#endif
@@ -1763,7 +1726,6 @@ cpu_CPUID(void)
EAX = EBX = ECX = EDX = 0;
break;
#ifdef USE_NEW_DYNAREC
case CPU_WINCHIP2:
switch (EAX)
{
@@ -1823,7 +1785,6 @@ cpu_CPUID(void)
break;
}
break;
#endif
case CPU_PENTIUM:
if (!EAX)
@@ -1843,7 +1804,7 @@ cpu_CPUID(void)
EAX = EBX = ECX = EDX = 0;
break;
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
case CPU_K5:
if (!EAX)
{
@@ -1913,6 +1874,7 @@ cpu_CPUID(void)
else
EAX = EBX = ECX = EDX = 0;
break;
#endif
case CPU_K6:
if (!EAX)
@@ -1975,9 +1937,7 @@ cpu_CPUID(void)
else
EAX = EBX = ECX = EDX = 0;
break;
#endif
#ifdef USE_NEW_DYNAREC
case CPU_K6_2:
case CPU_K6_2C:
switch (EAX)
@@ -1998,7 +1958,7 @@ cpu_CPUID(void)
break;
case 0x80000001:
EAX = CPUID+0x100;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_3DNOW;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP | CPUID_MMX | CPUID_3DNOW;
break;
case 0x80000002: /*Processor name string*/
@@ -2046,7 +2006,7 @@ cpu_CPUID(void)
break;
case 0x80000001:
EAX = CPUID+0x100;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_3DNOW;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP | CPUID_MMX | CPUID_3DNOW;
break;
case 0x80000002: /*Processor name string*/
@@ -2099,7 +2059,7 @@ cpu_CPUID(void)
break;
case 0x80000001:
EAX = CPUID+0x100;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_3DNOW;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP | CPUID_MMX | CPUID_3DNOW;
break;
case 0x80000002: /*Processor name string*/
@@ -2138,7 +2098,6 @@ cpu_CPUID(void)
break;
}
break;
#endif
case CPU_PENTIUMMMX:
if (!EAX)
@@ -2159,7 +2118,7 @@ cpu_CPUID(void)
break;
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
case CPU_Cx6x86:
if (!EAX)
{
@@ -2251,7 +2210,7 @@ cpu_CPUID(void)
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_SEP | CPUID_CMOV;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MTRR/* | CPUID_SEP*/ | CPUID_CMOV;
}
else if (EAX == 2)
{
@@ -2272,7 +2231,7 @@ cpu_CPUID(void)
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_SEP | CPUID_CMOV;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR/* | CPUID_SEP*/ | CPUID_CMOV;
}
else if (EAX == 2)
{
@@ -2296,7 +2255,7 @@ cpu_CPUID(void)
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR/* | CPUID_SEP*/ | CPUID_FXSR | CPUID_CMOV;
}
else if (EAX == 2)
{
@@ -2366,15 +2325,15 @@ cpu_CPUID(void)
void cpu_ven_reset(void)
{
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
{
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
case CPU_K5:
case CPU_5K86:
#endif
case CPU_K6:
amd_efer = amd_whcr = 0ULL;
break;
#ifdef USE_NEW_DYNAREC
case CPU_K6_2:
amd_efer = amd_whcr = 0ULL;
star = 0ULL;
@@ -2401,9 +2360,7 @@ void cpu_ven_reset(void)
amd_pfir = amd_l2aar = 0ULL;
amd_epmr = 0ULL;
break;
#endif
}
#endif
}
void cpu_RDMSR()
@@ -2412,9 +2369,7 @@ void cpu_RDMSR()
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
{
case CPU_WINCHIP:
#ifdef USE_NEW_DYNAREC
case CPU_WINCHIP2:
#endif
EAX = EDX = 0;
switch (ECX)
{
@@ -2517,9 +2472,10 @@ void cpu_RDMSR()
}
break;
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
case CPU_K5:
case CPU_5K86:
#endif
case CPU_K6:
EAX = EDX = 0;
switch (ECX)
@@ -2548,9 +2504,7 @@ void cpu_RDMSR()
break;
}
break;
#endif
#ifdef USE_NEW_DYNAREC
case CPU_K6_2:
EAX = EDX = 0;
switch (ECX)
@@ -2731,7 +2685,6 @@ void cpu_RDMSR()
break;
}
break;
#endif
case CPU_PENTIUM:
case CPU_PENTIUMMMX:
@@ -2744,7 +2697,7 @@ void cpu_RDMSR()
break;
}
break;
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
case CPU_Cx6x86:
case CPU_Cx6x86L:
case CPU_CxGX1:
@@ -2779,6 +2732,7 @@ void cpu_RDMSR()
case 0x1B:
EAX = apic_base_msr & 0xffffffff;
EDX = apic_base_msr >> 32;
/* pclog("APIC_BASE read : %08X%08X\n", EDX, EAX); */
break;
case 0x2A:
EAX = 0xC5800000;
@@ -2892,17 +2846,13 @@ i686_invalid_rdmsr:
void cpu_WRMSR()
{
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
uint64_t temp;
#endif
cpu_log("WRMSR %08X %08X%08X\n", ECX, EDX, EAX);
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
{
case CPU_WINCHIP:
#ifdef USE_NEW_DYNAREC
case CPU_WINCHIP2:
#endif
switch (ECX)
{
case 0x02:
@@ -2927,12 +2877,10 @@ void cpu_WRMSR()
cpu_features |= CPU_FEATURE_CX8;
else
cpu_features &= ~CPU_FEATURE_CX8;
#ifdef USE_NEW_DYNAREC
if ((EAX & (1 << 20)) && machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpu_type >= CPU_WINCHIP2)
cpu_features |= CPU_FEATURE_3DNOW;
else
cpu_features &= ~CPU_FEATURE_3DNOW;
#endif
if (EAX & (1 << 29))
CPUID = 0;
else
@@ -2990,9 +2938,10 @@ void cpu_WRMSR()
}
break;
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
case CPU_K5:
case CPU_5K86:
#endif
case CPU_K6:
switch (ECX)
{
@@ -3020,9 +2969,7 @@ void cpu_WRMSR()
break;
}
break;
#endif
#ifdef USE_NEW_DYNAREC
case CPU_K6_2:
switch (ECX)
{
@@ -3183,7 +3130,6 @@ void cpu_WRMSR()
break;
}
break;
#endif
case CPU_PENTIUM:
case CPU_PENTIUMMMX:
@@ -3194,7 +3140,7 @@ void cpu_WRMSR()
break;
}
break;
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
case CPU_Cx6x86:
case CPU_Cx6x86L:
case CPU_CxGX1:
@@ -3223,7 +3169,8 @@ void cpu_WRMSR()
ecx17_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0x1B:
apic_base_msr = EAX | ((uint64_t)EDX << 32);
/* pclog("APIC_BASE write: %08X%08X\n", EDX, EAX); */
// apic_base_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0x79:
ecx79_msr = EAX | ((uint64_t)EDX << 32);
@@ -3341,7 +3288,7 @@ static void cpu_write(uint16_t addr, uint8_t val, void *priv)
if ((ccr3 & 0xf0) == 0x10)
{
ccr4 = val;
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type >= CPU_Cx6x86)
{
if (val & 0x80)

36
src/cpu_common/cpu.h
View File

@@ -53,9 +53,7 @@ enum {
CPU_Am5x86,
CPU_Cx5x86,
CPU_WINCHIP, /* 586 class CPUs */
#ifdef USE_NEW_DYNAREC
CPU_WINCHIP2,
#endif
CPU_PENTIUM,
CPU_PENTIUMMMX,
#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)))
@@ -64,18 +62,16 @@ enum {
CPU_Cx6x86L,
CPU_CxGX1,
#endif
#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)))
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
CPU_K5,
CPU_5K86,
CPU_K6,
#endif
#ifdef USE_NEW_DYNAREC
CPU_K6,
CPU_K6_2,
CPU_K6_2C,
CPU_K6_3,
CPU_K6_2P,
CPU_K6_3P,
#endif
CPU_CYRIX3S,
#if defined(DEV_BRANCH) && defined(USE_I686)
CPU_PENTIUMPRO, /* 686 class CPUs */
@@ -131,28 +127,24 @@ extern CPU cpus_i486[];
extern CPU cpus_Am486[];
extern CPU cpus_Cx486[];
extern CPU cpus_WinChip[];
#ifdef USE_NEW_DYNAREC
extern CPU cpus_WinChip_SS7[];
#endif
extern CPU cpus_Pentium5V[];
extern CPU cpus_Pentium5V50[];
extern CPU cpus_PentiumS5[];
extern CPU cpus_Pentium3V[];
extern CPU cpus_Pentium[];
#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)))
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
extern CPU cpus_K5[];
#endif
extern CPU cpus_K56[];
#endif
#ifdef USE_NEW_DYNAREC
extern CPU cpus_K56_SS7[];
#endif
#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
extern CPU cpus_6x863V[];
extern CPU cpus_6x86[];
#endif
#ifdef USE_NEW_DYNAREC
extern CPU cpus_6x86SS7[];
#endif
#endif
extern CPU cpus_Cyrix3[];
#if defined(DEV_BRANCH) && defined(USE_I686)
extern CPU cpus_PentiumPro[];
@@ -172,14 +164,17 @@ extern CPU cpus_Celeron[];
#define V_FLAG 0x0800
#define NT_FLAG 0x4000
#define RF_FLAG 0x0001 /* in EFLAGS */
#define VM_FLAG 0x0002 /* in EFLAGS */
#define VIF_FLAG 0x0008 /* in EFLAGS */
#define VIP_FLAG 0x0010 /* in EFLAGS */
#define VID_FLAG 0x0020 /* in EFLAGS */
#define WP_FLAG 0x10000 /* in CR0 */
#define CR4_VME (1 << 0)
#define CR4_PVI (1 << 1)
#define CR4_PSE (1 << 4)
#define CR4_PAE (1 << 5)
#define CPL ((cpu_state.seg_cs.access>>5)&3)
@@ -400,7 +395,7 @@ extern int hasfpu;
extern uint32_t cpu_features;
extern int in_smm, smi_line, smi_latched, in_hlt;
extern int in_smm, smi_line, smi_latched, smm_in_hlt;
extern uint32_t smbase;
#ifdef USE_NEW_DYNAREC
@@ -486,6 +481,7 @@ extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
extern int timing_misaligned;
extern int in_sys;
extern CPU cpus_pcjr[]; // FIXME: should be in machine file!
extern CPU cpus_europc[]; // FIXME: should be in machine file!
@@ -526,8 +522,9 @@ extern void codegen_reset(void);
extern void cpu_set_edx(void);
extern int divl(uint32_t val);
extern void execx86(int cycs);
extern void enter_smm();
extern void leave_smm();
extern void enter_smm(int in_hlt);
extern void enter_smm_check(int in_hlt);
extern void leave_smm(void);
extern void exec386(int cycs);
extern void exec386_dynarec(int cycs);
extern int idivl(int32_t val);
@@ -568,5 +565,10 @@ extern void cpu_dynamic_switch(int new_cpu);
extern void cpu_ven_reset(void);
extern int sysenter(uint32_t fetchdat);
extern int sysexit(uint32_t fetchdat);
extern int syscall(uint32_t fetchdat);
extern int sysret(uint32_t fetchdat);
#endif /*EMU_CPU_H*/

728
src/cpu_common/cpu_table.c
View File

@@ -259,199 +259,193 @@ CPU cpus_Am486S1[] = {
};
CPU cpus_Cx486S1[] = {
/*Cyrix 486*/
{"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
{"Cx486S/25", CPU_Cx486S, 25000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"Cx486S/33", CPU_Cx486S, 33333333, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486S/40", CPU_Cx486S, 40000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX/33", CPU_Cx486DX, 33333333, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486DX/40", CPU_Cx486DX, 40000000, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2.0, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2.0, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2.0, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"", -1, 0, 0.0, 0, 0, 0x0000, 0, 0, 0, 0, 0, 0}
};
CPU cpus_i486[] = {
/*i486/P24T*/
{"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
{"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
{"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
{"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
{"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"iDX4/75", CPU_iDX4, 75000000, 3, 0x480, 0x480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*CPUID available on DX4, >= 75 MHz*/
{"iDX4/100", CPU_iDX4, 100000000, 3, 0x483, 0x483, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9},
{"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 5/2, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 5/2, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0}
{"i486SX/16", CPU_i486SX, 16000000, 1.0, 0x420, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 3, 3, 3, 3, 2},
{"i486SX/20", CPU_i486SX, 20000000, 1.0, 0x420, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"i486SX/25", CPU_i486SX, 25000000, 1.0, 0x422, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"i486SX/33", CPU_i486SX, 33333333, 1.0, 0x42a, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"i486SX2/50", CPU_i486SX, 50000000, 2.0, 0x45b, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2.0, 0x45b, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 8},
{"i486DX/25", CPU_i486DX, 25000000, 1.0, 0x404, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"i486DX/33", CPU_i486DX, 33333333, 1.0, 0x414, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"i486DX/50", CPU_i486DX, 50000000, 1.0, 0x411, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 6},
{"i486DX2/40", CPU_i486DX, 40000000, 2.0, 0x430, 0x430, 0x0000, CPU_SUPPORTS_DYNAREC, 7, 7, 6, 6, 5},
{"i486DX2/50", CPU_i486DX, 50000000, 2.0, 0x433, 0x433, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"i486DX2/66", CPU_i486DX, 66666666, 2.0, 0x435, 0x435, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"iDX4/75", CPU_iDX4, 75000000, 3.0, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, /*CPUID available on DX4, >= 75 MHz*/
{"iDX4/100", CPU_iDX4, 100000000, 3.0, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3.0, 0x1480, 0x1480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3.0, 0x1480, 0x1480, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12},
{"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 2.5, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 2.5, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"", -1, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0, 0}
};
CPU cpus_Am486[] = {
/*Am486/5x86*/
{"Am486SX/33", CPU_Am486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Am486SX/40", CPU_Am486SX, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Am486SX2/50", CPU_Am486SX2, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
{"Am486SX2/66", CPU_Am486SX2, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"Am486DX/33", CPU_Am486DX, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Am486DX/40", CPU_Am486DX, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Am486DX2/50", CPU_Am486DX2, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"Am486DX2/66", CPU_Am486DX2, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"Am486DX2/80", CPU_Am486DX2, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"Am486DX4/75", CPU_Am486DX4, 75000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"Am486DX4/90", CPU_Am486DX4, 90000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"Am486DX4/100", CPU_Am486DX4, 100000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"Am486DX4/120", CPU_Am486DX4, 120000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
{"Am5x86/P75", CPU_Am5x86, 133333333, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
{"Am5x86/P75+", CPU_Am5x86, 150000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
{"Am5x86/P90", CPU_Am5x86, 160000000, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/
{"Am486SX/33", CPU_Am486SX, 33333333, 1.0, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Am486SX/40", CPU_Am486SX, 40000000, 1.0, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Am486SX2/50", CPU_Am486SX2, 50000000, 2.0, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
{"Am486SX2/66", CPU_Am486SX2, 66666666, 2.0, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"Am486DX/33", CPU_Am486DX, 33333333, 1.0, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Am486DX/40", CPU_Am486DX, 40000000, 1.0, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Am486DX2/50", CPU_Am486DX2, 50000000, 2.0, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"Am486DX2/66", CPU_Am486DX2, 66666666, 2.0, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"Am486DX2/80", CPU_Am486DX2, 80000000, 2.0, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"Am486DX4/75", CPU_Am486DX4, 75000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"Am486DX4/90", CPU_Am486DX4, 90000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"Am486DX4/100", CPU_Am486DX4, 100000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"Am486DX4/120", CPU_Am486DX4, 120000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
{"Am5x86/P75", CPU_Am5x86, 133333333, 4.0, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
{"Am5x86/P75+", CPU_Am5x86, 150000000, 3.0, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
{"Am5x86/P90", CPU_Am5x86, 160000000, 4.0, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_Cx486[] = {
/*Cyrix 486*/
{"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"Cx486DX4/75", CPU_Cx486DX4, 75000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"Cx486DX4/100", CPU_Cx486DX4, 100000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"Cx486S/25", CPU_Cx486S, 25000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"Cx486S/33", CPU_Cx486S, 33333333, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486S/40", CPU_Cx486S, 40000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX/33", CPU_Cx486DX, 33333333, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486DX/40", CPU_Cx486DX, 40000000, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2.0, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2.0, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2.0, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"Cx486DX4/75", CPU_Cx486DX4, 75000000, 3.0, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
{"Cx486DX4/100", CPU_Cx486DX4, 100000000, 3.0, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
/*Cyrix 5x86*/
{"Cx5x86/80", CPU_Cx5x86, 80000000, 2, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/
{"Cx5x86/100", CPU_Cx5x86, 100000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"Cx5x86/120", CPU_Cx5x86, 120000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
{"Cx5x86/133", CPU_Cx5x86, 133333333, 4, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
{"Cx5x86/80", CPU_Cx5x86, 80000000, 2.0, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/
{"Cx5x86/100", CPU_Cx5x86, 100000000, 3.0, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
{"Cx5x86/120", CPU_Cx5x86, 120000000, 3.0, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
{"Cx5x86/133", CPU_Cx5x86, 133333333, 4.0, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
CPU cpus_6x863V[] = {
/*Cyrix 6x86*/
{"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
{"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
{"Cx6x86/P90", CPU_Cx6x86, 80000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
{"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_6x86[] = {
/*Cyrix 6x86*/
{"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
{"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
{"Cx6x86/P90", CPU_Cx6x86, 80000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
{"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
/*Cyrix 6x86L*/
{"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
{"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
/*Cyrix 6x86MX/MII*/
{"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
{"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
{"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28},
{"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30},
{"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2.0, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
{"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
{"MII/PR300", CPU_Cx6x86MX, 233333333, 3.5, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28},
{"MII/PR333", CPU_Cx6x86MX, 250000000, 3.0, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
#ifdef USE_NEW_DYNAREC
CPU cpus_6x86SS7[] = {
/*Cyrix 6x86*/
{"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
{"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
{"Cx6x86/P90", CPU_Cx6x86, 80000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
{"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2.0, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
/*Cyrix 6x86L*/
{"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
{"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
{"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2.0, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
/*Cyrix 6x86MX/MII*/
{"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
{"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
{"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28},
{"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30},
{"MII/PR366", CPU_Cx6x86MX, 250000000, 5/2, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30},
{"MII/PR400", CPU_Cx6x86MX, 285000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34},
{"MII/PR433", CPU_Cx6x86MX, 300000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36},
{"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2.0, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
{"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 2.5, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
{"MII/PR300", CPU_Cx6x86MX, 233333333, 3.5, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28},
{"MII/PR333", CPU_Cx6x86MX, 250000000, 3.0, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30},
{"MII/PR366", CPU_Cx6x86MX, 250000000, 2.5, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30},
{"MII/PR400", CPU_Cx6x86MX, 285000000, 3.0, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34},
{"MII/PR433", CPU_Cx6x86MX, 300000000, 3.0, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
CPU cpus_WinChip[] = {
/*IDT WinChip*/
{"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9},
{"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2},
{"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12},
{"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14},
{"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16},
{"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2},
{"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40},
{"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21},
{"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24},
{"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27},
{"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28},
#ifdef USE_NEW_DYNAREC
{"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24},
{"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27},
{"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
{"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
{"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24},
{"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, (7*8)/2},
#endif
{"WinChip 75", CPU_WINCHIP, 75000000, 1.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9},
{"WinChip 90", CPU_WINCHIP, 90000000, 1.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2},
{"WinChip 100", CPU_WINCHIP, 100000000, 1.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12},
{"WinChip 120", CPU_WINCHIP, 120000000, 2.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14},
{"WinChip 133", CPU_WINCHIP, 133333333, 2.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16},
{"WinChip 150", CPU_WINCHIP, 150000000, 2.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2},
{"WinChip 166", CPU_WINCHIP, 166666666, 2.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40},
{"WinChip 180", CPU_WINCHIP, 180000000, 3.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21},
{"WinChip 200", CPU_WINCHIP, 200000000, 3.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24},
{"WinChip 225", CPU_WINCHIP, 225000000, 3.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27},
{"WinChip 240", CPU_WINCHIP, 240000000, 4.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28},
{"WinChip 2/200", CPU_WINCHIP2, 200000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24},
{"WinChip 2/225", CPU_WINCHIP2, 225000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27},
{"WinChip 2/240", CPU_WINCHIP2, 240000000, 4.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
{"WinChip 2/250", CPU_WINCHIP2, 250000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
{"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3.0, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24},
{"WinChip 2A/233", CPU_WINCHIP2, 233333333, 3.5, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, (7*8)/2},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#ifdef USE_NEW_DYNAREC
CPU cpus_WinChip_SS7[] = {
/*IDT WinChip*/
{"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9},
{"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2},
{"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12},
{"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14},
{"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16},
{"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2},
{"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40},
{"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21},
{"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24},
{"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27},
{"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28},
{"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8},
{"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9},
{"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
{"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
{"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8},
{"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2},
{"WinChip 2A/266", CPU_WINCHIP2, 233333333, 7/3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28},
{"WinChip 2A/300", CPU_WINCHIP2, 250000000, 5/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
{"WinChip 75", CPU_WINCHIP, 75000000, 1.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9},
{"WinChip 90", CPU_WINCHIP, 90000000, 1.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2},
{"WinChip 100", CPU_WINCHIP, 100000000, 1.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12},
{"WinChip 120", CPU_WINCHIP, 120000000, 2.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14},
{"WinChip 133", CPU_WINCHIP, 133333333, 2.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16},
{"WinChip 150", CPU_WINCHIP, 150000000, 2.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2},
{"WinChip 166", CPU_WINCHIP, 166666666, 2.5, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40},
{"WinChip 180", CPU_WINCHIP, 180000000, 3.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21},
{"WinChip 200", CPU_WINCHIP, 200000000, 3.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24},
{"WinChip 225", CPU_WINCHIP, 225000000, 3.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27},
{"WinChip 240", CPU_WINCHIP, 240000000, 4.0, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28},
{"WinChip 2/200", CPU_WINCHIP2, 200000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8},
{"WinChip 2/225", CPU_WINCHIP2, 225000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9},
{"WinChip 2/240", CPU_WINCHIP2, 240000000, 4.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
{"WinChip 2/250", CPU_WINCHIP2, 250000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30},
{"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3.0, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8},
{"WinChip 2A/233", CPU_WINCHIP2, 233333333, 3.5, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2},
{"WinChip 2A/266", CPU_WINCHIP2, 233333333, 7.0/3.0, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28},
{"WinChip 2A/300", CPU_WINCHIP2, 250000000, 2.5, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
CPU cpus_Pentium5V[] = {
/*Intel Pentium (5V, socket 4)*/
@@ -475,282 +469,288 @@ CPU cpus_Pentium5V50[] = {
CPU cpus_PentiumS5[] = {
/*Intel Pentium (Socket 5)*/
{"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12},
{"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
{"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
{"Pentium 75", CPU_PENTIUM, 75000000, 1.5, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 1.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"Pentium 90", CPU_PENTIUM, 90000000, 1.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"Pentium 100/50", CPU_PENTIUM, 100000000, 2.0, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12},
{"Pentium 100/66", CPU_PENTIUM, 100000000, 1.5, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
{"Pentium 120", CPU_PENTIUM, 120000000, 2.0, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
/*Intel Pentium OverDrive*/
{"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 16},
{"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
{"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 40},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 15},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 21},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
/*Intel Pentium OverDrive*/
{"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 3.0, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 16},
{"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
{"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 40},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 15},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 21},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
{"", -1, 0, 0.0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_Pentium3V[] = {
/*Intel Pentium*/
{"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"Pentium 75", CPU_PENTIUM, 75000000, 1.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 1.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium 90", CPU_PENTIUM, 90000000, 1.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"Pentium 100/50", CPU_PENTIUM, 100000000, 2.0, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Pentium 100/66", CPU_PENTIUM, 100000000, 1.5, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"Pentium 120", CPU_PENTIUM, 120000000, 2.0, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Pentium 133", CPU_PENTIUM, 133333333, 2.0, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Pentium 150", CPU_PENTIUM, 150000000, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium 166", CPU_PENTIUM, 166666666, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium 200", CPU_PENTIUM, 200000000, 3.0, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
/*Intel Pentium OverDrive*/
{"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
{"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
{"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_Pentium[] = {
/*Intel Pentium*/
{"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"Pentium 75", CPU_PENTIUM, 75000000, 1.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 1.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium 90", CPU_PENTIUM, 90000000, 1.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"Pentium 100/50", CPU_PENTIUM, 100000000, 2.0, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Pentium 100/66", CPU_PENTIUM, 100000000, 1.5, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"Pentium 120", CPU_PENTIUM, 120000000, 2.0, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Pentium 133", CPU_PENTIUM, 133333333, 2.0, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Pentium 150", CPU_PENTIUM, 150000000, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium 166", CPU_PENTIUM, 166666666, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium 200", CPU_PENTIUM, 200000000, 3.0, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
/*Intel Pentium MMX*/
{"Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 2.5, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3.0, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 3.5, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
/*Mobile Pentium*/
{"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 120000000, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 133333333, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 150000000, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 266666666, 4, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
{"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 300000000, 9/2, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
{"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 120000000, 2.0, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 133333333, 2.0, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 150000000, 2.5, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 2.5, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3.0, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 3.5, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 266666666, 4.0, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
{"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 300000000, 4.5, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
/*Intel Pentium OverDrive*/
{"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
{"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
{"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
{"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 2.5, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15},
{"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 2.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
{"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3.0, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"", -1, 0, 0.0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
CPU cpus_K5[] = {
/*AMD K5 (Socket 5)*/
{"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
{"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
{"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
{"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16},
{"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
{"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
{"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
{"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
{"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
{"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
{"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
{"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2.0, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
{"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2.0, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16},
{"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
{"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
{"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3.0, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
{"", -1, 0, 0.0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
CPU cpus_K56[] = {
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
/*AMD K5 (Socket 7)*/
{"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2.0, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2.0, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3.0, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
#endif
/*AMD K6 (Socket 7*/
{"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28},
{"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28},
{"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32},
{"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36},
#ifdef USE_NEW_DYNAREC
{"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28},
{"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32},
{"K6-2/300 AFR-66", CPU_K6_2, 300000000, 9/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36},
{"K6-2/366", CPU_K6_2, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33, 17, 17, 44},
#endif
{"K6 (Model 6) 166", CPU_K6, 166666666, 2.5, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"K6 (Model 6) 200", CPU_K6, 200000000, 3.0, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"K6 (Model 6) 233", CPU_K6, 233333333, 3.5, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28},
{"K6 (Model 7) 200", CPU_K6, 200000000, 3.0, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"K6 (Model 7) 233", CPU_K6, 233333333, 3.5, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28},
{"K6 (Model 7) 266", CPU_K6, 266666666, 4.0, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32},
{"K6 (Model 7) 300", CPU_K6, 300000000, 4.5, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36},
/*AMD K6-2 (Socket 7)*/
{"K6-2/233", CPU_K6_2, 233333333, 3.5, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28},
{"K6-2/266", CPU_K6_2, 266666666, 4.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32},
{"K6-2/300 AFR-66", CPU_K6_2, 300000000, 4.5, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36},
{"K6-2/366", CPU_K6_2, 366666666, 5.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33, 17, 17, 44},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_K56_SS7[] = {
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
/*AMD K5 (Socket 7)*/
{"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 1.5, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 1.5, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2.0, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2.0, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 2.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3.0, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
#endif
#ifdef USE_NEW_DYNAREC
CPU cpus_K56_SS7[] = {
/*AMD K5 (Socket 7)*/
{"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12},
{"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
{"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
{"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
/*AMD K6 (Socket 7)*/
{"K6 (Model 6) 166", CPU_K6, 166666666, 2.5, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"K6 (Model 6) 200", CPU_K6, 200000000, 3.0, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"K6 (Model 6) 233", CPU_K6, 233333333, 3.5, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"K6 (Model 7) 200", CPU_K6, 200000000, 3.0, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"K6 (Model 7) 233", CPU_K6, 233333333, 3.5, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"K6 (Model 7) 266", CPU_K6, 266666666, 4.0, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
{"K6 (Model 7) 300", CPU_K6, 300000000, 4.5, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
/*AMD K6 (Socket 7)*/
{"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
{"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
/*AMD K6-2 (Socket 7/Super Socket 7)*/
{"K6-2/233", CPU_K6_2, 233333333, 3.5, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28},
{"K6-2/266", CPU_K6_2, 266666666, 4.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32},
{"K6-2/300", CPU_K6_2, 300000000, 3.0, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36},
{"K6-2/333", CPU_K6_2, 332500000, 3.5, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40},
{"K6-2/350", CPU_K6_2C, 350000000, 3.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42},
{"K6-2/366", CPU_K6_2C, 366666666, 5.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44},
{"K6-2/380", CPU_K6_2C, 380000000, 4.0, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46},
{"K6-2/400", CPU_K6_2C, 400000000, 4.0, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"K6-2/450", CPU_K6_2C, 450000000, 4.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"K6-2/475", CPU_K6_2C, 475000000, 5.0, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57},
{"K6-2/500", CPU_K6_2C, 500000000, 5.0, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60},
{"K6-2/533", CPU_K6_2C, 533333333, 5.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64},
{"K6-2/550", CPU_K6_2C, 550000000, 5.5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66},
/*AMD K6-2 (Socket 7/Super Socket 7)*/
{"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28},
{"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32},
{"K6-2/300", CPU_K6_2, 300000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36},
{"K6-2/333", CPU_K6_2, 332500000, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40},
{"K6-2/350", CPU_K6_2C, 350000000, 7/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42},
{"K6-2/366", CPU_K6_2C, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44},
{"K6-2/380", CPU_K6_2C, 380000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46},
{"K6-2/400", CPU_K6_2C, 400000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"K6-2/450", CPU_K6_2C, 450000000, 9/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"K6-2/475", CPU_K6_2C, 475000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57},
{"K6-2/500", CPU_K6_2C, 500000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60},
{"K6-2/533", CPU_K6_2C, 533333333, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64},
{"K6-2/550", CPU_K6_2C, 550000000, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66},
/*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/
{"K6-2+/450", CPU_K6_2P, 450000000, 9/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"K6-2+/475", CPU_K6_2P, 475000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57},
{"K6-2+/500", CPU_K6_2P, 500000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60},
{"K6-2+/533", CPU_K6_2P, 533333333, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64},
{"K6-2+/550", CPU_K6_2P, 550000000, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66},
{"K6-III/400", CPU_K6_3, 400000000, 4, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"K6-III/450", CPU_K6_3, 450000000, 9/2, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"K6-III+/400", CPU_K6_3P, 400000000, 4, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"K6-III+/450", CPU_K6_3P, 450000000, 9/2, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"K6-III+/475", CPU_K6_3P, 475000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57},
{"K6-III+/500", CPU_K6_3P, 500000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60},
/*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/
{"K6-2+/450", CPU_K6_2P, 450000000, 4.5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"K6-2+/475", CPU_K6_2P, 475000000, 5.0, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57},
{"K6-2+/500", CPU_K6_2P, 500000000, 5.0, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60},
{"K6-2+/533", CPU_K6_2P, 533333333, 5.5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64},
{"K6-2+/550", CPU_K6_2P, 550000000, 5.5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66},
{"K6-III/400", CPU_K6_3, 400000000, 4.0, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"K6-III/450", CPU_K6_3, 450000000, 4.5, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"K6-III+/75", CPU_K6_3P, 75000000, 1.5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"K6-III+/400", CPU_K6_3P, 400000000, 4.0, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"K6-III+/450", CPU_K6_3P, 450000000, 4.5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"K6-III+/475", CPU_K6_3P, 475000000, 5.0, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57},
{"K6-III+/500", CPU_K6_3P, 500000000, 5.0, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
#ifdef DEV_BRANCH
#ifdef USE_I686
CPU cpus_PentiumPro[] = {
/*Intel Pentium Pro*/
{"Pentium Pro 50", CPU_PENTIUMPRO, 50000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium Pro 60" , CPU_PENTIUMPRO, 60000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"Pentium Pro 66" , CPU_PENTIUMPRO, 66666666, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Pentium Pro 75", CPU_PENTIUMPRO, 75000000, 3/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium Pro 150", CPU_PENTIUMPRO, 150000000, 5/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium Pro 166", CPU_PENTIUMPRO, 166666666, 5/2, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium Pro 180", CPU_PENTIUMPRO, 180000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
{"Pentium Pro 200", CPU_PENTIUMPRO, 200000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
{"Pentium Pro 50", CPU_PENTIUMPRO, 50000000, 1.0, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium Pro 60" , CPU_PENTIUMPRO, 60000000, 1.0, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"Pentium Pro 66" , CPU_PENTIUMPRO, 66666666, 1.0, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Pentium Pro 75", CPU_PENTIUMPRO, 75000000, 1.5, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium Pro 150", CPU_PENTIUMPRO, 150000000, 2.5, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2},
{"Pentium Pro 166", CPU_PENTIUMPRO, 166666666, 2.5, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
{"Pentium Pro 180", CPU_PENTIUMPRO, 180000000, 3.0, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21},
{"Pentium Pro 200", CPU_PENTIUMPRO, 200000000, 3.0, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24},
/*Intel Pentium II OverDrive*/
{"Pentium II Overdrive 50", CPU_PENTIUM2D, 50000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium II Overdrive 60", CPU_PENTIUM2D, 60000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"Pentium II Overdrive 66", CPU_PENTIUM2D, 66666666, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Pentium II Overdrive 75", CPU_PENTIUM2D, 75000000, 3/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium II Overdrive 210", CPU_PENTIUM2D, 210000000, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
{"Pentium II Overdrive 233", CPU_PENTIUM2D, 233333333, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"Pentium II Overdrive 240", CPU_PENTIUM2D, 240000000, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
{"Pentium II Overdrive 266", CPU_PENTIUM2D, 266666666, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
{"Pentium II Overdrive 270", CPU_PENTIUM2D, 270000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 33},
{"Pentium II Overdrive 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
{"Pentium II Overdrive 300/60", CPU_PENTIUM2D, 300000000, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
{"Pentium II Overdrive 333", CPU_PENTIUM2D, 333333333, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
/*Intel Pentium II OverDrive*/
{"Pentium II Overdrive 50", CPU_PENTIUM2D, 50000000, 1.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium II Overdrive 60", CPU_PENTIUM2D, 60000000, 1.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"Pentium II Overdrive 66", CPU_PENTIUM2D, 66666666, 1.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Pentium II Overdrive 75", CPU_PENTIUM2D, 75000000, 1.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium II Overdrive 210", CPU_PENTIUM2D, 210000000, 3.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
{"Pentium II Overdrive 233", CPU_PENTIUM2D, 233333333, 3.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"Pentium II Overdrive 240", CPU_PENTIUM2D, 240000000, 4.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
{"Pentium II Overdrive 266", CPU_PENTIUM2D, 266666666, 4.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32},
{"Pentium II Overdrive 270", CPU_PENTIUM2D, 270000000, 4.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 33},
{"Pentium II Overdrive 300/66", CPU_PENTIUM2D, 300000000, 4.5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
{"Pentium II Overdrive 300/60", CPU_PENTIUM2D, 300000000, 5.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36},
{"Pentium II Overdrive 333", CPU_PENTIUM2D, 333333333, 5.0, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_PentiumII[] = {
/*Intel Pentium II Klamath*/
{"Pentium II Klamath 50", CPU_PENTIUM2, 50000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium II Klamath 60", CPU_PENTIUM2, 60000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"Pentium II Klamath 66", CPU_PENTIUM2, 66666666, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Pentium II Klamath 75", CPU_PENTIUM2, 75000000, 3/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium II Klamath 233", CPU_PENTIUM2, 233333333, 7/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"Pentium II Klamath 266", CPU_PENTIUM2, 266666666, 4, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
{"Pentium II Klamath 300/66", CPU_PENTIUM2, 300000000, 9/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
{"Pentium II Klamath 50", CPU_PENTIUM2, 50000000, 1.0, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium II Klamath 60", CPU_PENTIUM2, 60000000, 1.0, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"Pentium II Klamath 66", CPU_PENTIUM2, 66666666, 1.0, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Pentium II Klamath 75", CPU_PENTIUM2, 75000000, 1.5, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium II Klamath 233", CPU_PENTIUM2, 233333333, 3.5, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28},
{"Pentium II Klamath 266", CPU_PENTIUM2, 266666666, 4.0, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
{"Pentium II Klamath 300/66", CPU_PENTIUM2, 300000000, 4.5, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
/*Intel Pentium II Deschutes*/
{"Pentium II Deschutes 50", CPU_PENTIUM2D, 50000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium II Deschutes 60", CPU_PENTIUM2D, 60000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"Pentium II Deschutes 66", CPU_PENTIUM2D, 66666666, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Pentium II Deschutes 75", CPU_PENTIUM2D, 75000000, 3/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium II Deschutes 266", CPU_PENTIUM2D, 266666666, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
{"Pentium II Deschutes 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
{"Pentium II Deschutes 333", CPU_PENTIUM2D, 333333333, 5, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
{"Pentium II Deschutes 350", CPU_PENTIUM2D, 350000000, 7/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42},
{"Pentium II Deschutes 400", CPU_PENTIUM2D, 400000000, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
{"Pentium II Deschutes 450", CPU_PENTIUM2D, 450000000, 9/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54},
/*Intel Pentium II Deschutes*/
{"Pentium II Deschutes 50", CPU_PENTIUM2D, 50000000, 1.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Pentium II Deschutes 60", CPU_PENTIUM2D, 60000000, 1.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7},
{"Pentium II Deschutes 66", CPU_PENTIUM2D, 66666666, 1.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Pentium II Deschutes 75", CPU_PENTIUM2D, 75000000, 1.5, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium II Deschutes 266", CPU_PENTIUM2D, 266666666, 4.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29},
{"Pentium II Deschutes 300/66", CPU_PENTIUM2D, 300000000, 4.5, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
{"Pentium II Deschutes 333", CPU_PENTIUM2D, 333333333, 5.0, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
{"Pentium II Deschutes 350", CPU_PENTIUM2D, 350000000, 3.5, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42},
{"Pentium II Deschutes 400", CPU_PENTIUM2D, 400000000, 4.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
{"Pentium II Deschutes 450", CPU_PENTIUM2D, 450000000, 4.5, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_Celeron[] = { // Mendocino Celerons. Exact architecture as the P2D series. Intended for
// the PGA370 boards but they were capable to fit on a PGA 370 to Slot 1
// adaptor card so they work on Slot 1 motherboards too!.
// The 100Mhz Mendocino is only meant to not cause any struggle
// to the recompiler.
{"Celeron Mendocino 66", CPU_PENTIUM2D, 66666666, 1, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 3/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Celeron Mendocino 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
{"Celeron Mendocino 333", CPU_PENTIUM2D, 333333333, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
{"Celeron Mendocino 366", CPU_PENTIUM2D, 366666666, 11/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33,17,17, 44},
{"Celeron Mendocino 400", CPU_PENTIUM2D, 400000000, 4, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
{"Celeron Mendocino 433", CPU_PENTIUM2D, 433333333, 9/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 39,39,13,13, 51},
{"Celeron Mendocino 466", CPU_PENTIUM2D, 466666666, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43,43,15,15, 57},
{"Celeron Mendocino 500", CPU_PENTIUM2D, 500000000, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45,45,15,15, 60},
{"Celeron Mendocino 533", CPU_PENTIUM2D, 533333333, 11/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48,48,17,17, 64},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
CPU cpus_Celeron[] = {
/* Mendocino Celerons. Exact architecture as the P2D series. Intended for
the PGA370 boards but they were capable to fit on a PGA 370 to Slot 1
adaptor card so they work on Slot 1 motherboards too!.
The 100Mhz Mendocino is only meant to not cause any struggle
to the recompiler. */
{"Celeron Mendocino 25", CPU_PENTIUM2D, 25000000, 1.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 3},
{"Celeron Mendocino 50", CPU_PENTIUM2D, 50000000, 1.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6},
{"Celeron Mendocino 66", CPU_PENTIUM2D, 66666666, 1.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8},
{"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 1.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Celeron Mendocino 300/66", CPU_PENTIUM2D, 300000000, 4.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36},
{"Celeron Mendocino 333", CPU_PENTIUM2D, 333333333, 5.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
{"Celeron Mendocino 366", CPU_PENTIUM2D, 366666666, 5.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33,17,17, 44},
{"Celeron Mendocino 400", CPU_PENTIUM2D, 400000000, 4.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
{"Celeron Mendocino 433", CPU_PENTIUM2D, 433333333, 4.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 39,39,13,13, 51},
{"Celeron Mendocino 466", CPU_PENTIUM2D, 466666666, 5.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43,43,15,15, 57},
{"Celeron Mendocino 500", CPU_PENTIUM2D, 500000000, 5.0, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45,45,15,15, 60},
{"Celeron Mendocino 533", CPU_PENTIUM2D, 533333333, 5.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48,48,17,17, 64},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
#endif
CPU cpus_Cyrix3[] = {
/*VIA Cyrix III (Samuel)*/
{"Cyrix III 66", CPU_CYRIX3S, 66666666, 1, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/
{"Cyrix III 233", CPU_CYRIX3S, 233333333, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, 28},
{"Cyrix III 266", CPU_CYRIX3S, 266666666, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32},
{"Cyrix III 300", CPU_CYRIX3S, 300000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36},
{"Cyrix III 333", CPU_CYRIX3S, 333333333, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40},
{"Cyrix III 350", CPU_CYRIX3S, 350000000, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42},
{"Cyrix III 400", CPU_CYRIX3S, 400000000, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48},
{"Cyrix III 450", CPU_CYRIX3S, 450000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/
{"Cyrix III 500", CPU_CYRIX3S, 500000000, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60},
{"Cyrix III 550", CPU_CYRIX3S, 550000000, 5.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66},
{"Cyrix III 600", CPU_CYRIX3S, 600000000, 6, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72},
{"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78},
{"Cyrix III 700", CPU_CYRIX3S, 700000000, 7, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
{"Cyrix III 66", CPU_CYRIX3S, 66666666, 1.0, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/
{"Cyrix III 233", CPU_CYRIX3S, 233333333, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, 28},
{"Cyrix III 266", CPU_CYRIX3S, 266666666, 4.0, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32},
{"Cyrix III 300", CPU_CYRIX3S, 300000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36},
{"Cyrix III 333", CPU_CYRIX3S, 333333333, 5.0, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40},
{"Cyrix III 350", CPU_CYRIX3S, 350000000, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42},
{"Cyrix III 400", CPU_CYRIX3S, 400000000, 4.0, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48},
{"Cyrix III 450", CPU_CYRIX3S, 450000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/
{"Cyrix III 500", CPU_CYRIX3S, 500000000, 5.0, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60},
{"Cyrix III 550", CPU_CYRIX3S, 550000000, 5.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66},
{"Cyrix III 600", CPU_CYRIX3S, 600000000, 6.0, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72},
{"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78},
{"Cyrix III 700", CPU_CYRIX3S, 700000000, 7.0, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84},
{"", -1, 0, 0.0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};

8
src/cpu_common/x86_ops.h
View File

@@ -86,14 +86,12 @@ extern const OpFn dynarec_ops_winchip2_0f[1024];
extern const OpFn dynarec_ops_pentium_0f[1024];
extern const OpFn dynarec_ops_pentiummmx_0f[1024];
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
extern const OpFn dynarec_ops_c6x86mx_0f[1024];
#endif
#ifdef USE_NEW_DYNAREC
extern const OpFn dynarec_ops_k6_0f[1024];
extern const OpFn dynarec_ops_k62_0f[1024];
#endif
#if defined(DEV_BRANCH) && defined(USE_I686)
extern const OpFn dynarec_ops_pentiumpro_0f[1024];
@@ -185,14 +183,12 @@ extern const OpFn ops_winchip2_0f[1024];
extern const OpFn ops_pentium_0f[1024];
extern const OpFn ops_pentiummmx_0f[1024];
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
extern const OpFn ops_c6x86mx_0f[1024];
#endif
#ifdef USE_NEW_DYNAREC
extern const OpFn ops_k6_0f[1024];
extern const OpFn ops_k62_0f[1024];
#endif
#if defined(DEV_BRANCH) && defined(USE_I686)
extern const OpFn ops_pentiumpro_0f[1024];

181
src/cpu_common/x86_ops_amd.h
View File

@@ -13,180 +13,33 @@
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016-2018 Miran Grca.
*/
/* 0 = Limit 0-15
1 = Base 0-15
2 = Base 16-23 (bits 0-7), Access rights
8-11 Type
12 S
13, 14 DPL
15 P
3 = Limit 16-19 (bits 0-3), Base 24-31 (bits 8-15), granularity, etc.
4 A
6 DB
7 G */
#define AMD_SYSCALL_EIP (star & 0xFFFFFFFF)
#define AMD_SYSCALL_SB ((star >> 32) & 0xFFFF)
#define AMD_SYSRET_SB ((star >> 48) & 0xFFFF)
/* 0F 05 */
static int opSYSCALL(uint32_t fetchdat)
static int
opSYSCALL(uint32_t fetchdat)
{
uint16_t syscall_cs_seg_data[4] = {0, 0, 0, 0};
uint16_t syscall_ss_seg_data[4] = {0, 0, 0, 0};
if (!(cr0 & 1)) return internal_illegal("SYSCALL: CPU not in protected mode");
if (!AMD_SYSCALL_SB) return internal_illegal("SYSCALL: AMD SYSCALL SB MSR is zero");
/* Set VM, IF, RF to 0. */
/* cpu_state.eflags &= ~0x00030200;
cpu_state.flags &= ~0x0200; */
/* Let's do this by the AMD spec. */
ECX = cpu_state.pc;
cpu_state.eflags &= ~0x0002;
cpu_state.flags &= ~0x0200;
/* CS */
cpu_state.seg_cs.seg = AMD_SYSCALL_SB & ~7;
if (AMD_SYSCALL_SB & 4)
{
if (cpu_state.seg_cs.seg >= ldt.limit)
{
x386_dynarec_log("Bigger than LDT limit %04X %04X CS\n",AMD_SYSCALL_SB,ldt.limit);
x86gpf(NULL, AMD_SYSCALL_SB & ~3);
return 1;
}
cpu_state.seg_cs.seg +=ldt.base;
}
else
{
if (cpu_state.seg_cs.seg >= gdt.limit)
{
x386_dynarec_log("Bigger than GDT limit %04X %04X CS\n",AMD_SYSCALL_SB,gdt.limit);
x86gpf(NULL, AMD_SYSCALL_SB & ~3);
return 1;
}
cpu_state.seg_cs.seg += gdt.base;
}
cpl_override = 1;
syscall_cs_seg_data[0] = 0xFFFF;
syscall_cs_seg_data[1] = 0;
syscall_cs_seg_data[2] = 0x9B00;
syscall_cs_seg_data[3] = 0xC0;
cpl_override = 0;
use32 = 0x300;
CS = (AMD_SYSCALL_SB & ~3) | 0;
do_seg_load(&cpu_state.seg_cs, syscall_cs_seg_data);
use32 = 0x300;
CS = (CS & 0xFFFC) | 0;
cpu_state.seg_cs.limit = 0xFFFFFFFF;
cpu_state.seg_cs.limit_high = 0xFFFFFFFF;
/* SS */
syscall_ss_seg_data[0] = 0xFFFF;
syscall_ss_seg_data[1] = 0;
syscall_ss_seg_data[2] = 0x9300;
syscall_ss_seg_data[3] = 0xC0;
do_seg_load(&cpu_state.seg_ss, syscall_ss_seg_data);
cpu_state.seg_ss.seg = (AMD_SYSCALL_SB + 8) & 0xFFFC;
stack32 = 1;
cpu_state.seg_ss.limit = 0xFFFFFFFF;
cpu_state.seg_ss.limit_high = 0xFFFFFFFF;
cpu_state.seg_ss.checked = 0;
cpu_state.pc = AMD_SYSCALL_EIP;
int ret = syscall(fetchdat);
if (ret <= 1) {
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
CPU_BLOCK_END();
}
return 0;
return ret;
}
/* 0F 07 */
static int opSYSRET(uint32_t fetchdat)
static int
opSYSRET(uint32_t fetchdat)
{
uint16_t sysret_cs_seg_data[4] = {0, 0, 0, 0};
uint16_t sysret_ss_seg_data[4] = {0, 0, 0, 0};
if (!AMD_SYSRET_SB) return internal_illegal("SYSRET: CS MSR is zero");
if (!(cr0 & 1)) return internal_illegal("SYSRET: CPU not in protected mode");
cpu_state.pc = ECX;
cpu_state.eflags |= (1 << 1);
/* CS */
cpu_state.seg_cs.seg = AMD_SYSRET_SB & ~7;
if (AMD_SYSRET_SB & 4)
{
if (cpu_state.seg_cs.seg >= ldt.limit)
{
x386_dynarec_log("Bigger than LDT limit %04X %04X CS\n",AMD_SYSRET_SB,ldt.limit);
x86gpf(NULL, AMD_SYSRET_SB & ~3);
return 1;
}
cpu_state.seg_cs.seg +=ldt.base;
}
else
{
if (cpu_state.seg_cs.seg >= gdt.limit)
{
x386_dynarec_log("Bigger than GDT limit %04X %04X CS\n",AMD_SYSRET_SB,gdt.limit);
x86gpf(NULL, AMD_SYSRET_SB & ~3);
return 1;
}
cpu_state.seg_cs.seg += gdt.base;
}
cpl_override = 1;
sysret_cs_seg_data[0] = 0xFFFF;
sysret_cs_seg_data[1] = 0;
sysret_cs_seg_data[2] = 0xFB00;
sysret_cs_seg_data[3] = 0xC0;
cpl_override = 0;
use32 = 0x300;
CS = (AMD_SYSRET_SB & ~3) | 3;
do_seg_load(&cpu_state.seg_cs, sysret_cs_seg_data);
flushmmucache_cr3();
use32 = 0x300;
CS = (CS & 0xFFFC) | 3;
cpu_state.seg_cs.limit = 0xFFFFFFFF;
cpu_state.seg_cs.limit_high = 0xFFFFFFFF;
/* SS */
sysret_ss_seg_data[0] = 0xFFFF;
sysret_ss_seg_data[1] = 0;
sysret_ss_seg_data[2] = 0xF300;
sysret_ss_seg_data[3] = 0xC0;
do_seg_load(&cpu_state.seg_ss, sysret_ss_seg_data);
cpu_state.seg_ss.seg = ((AMD_SYSRET_SB + 8) & 0xFFFC) | 3;
stack32 = 1;
cpu_state.seg_ss.limit = 0xFFFFFFFF;
cpu_state.seg_ss.limit_high = 0xFFFFFFFF;
cpu_state.seg_ss.checked = 0;
int ret = sysret(fetchdat);
if (ret <= 1) {
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
CPU_BLOCK_END();
}
return 0;
return ret;
}

149
src/cpu_common/x86_ops_i686.h
View File

@@ -13,145 +13,40 @@
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016-2020 Miran Grca.
*/
/* 0 = Limit 0-15
1 = Base 0-15
2 = Base 16-23 (bits 0-7), Access rights
8-11 Type
12 S
13, 14 DPL
15 P
3 = Limit 16-19 (bits 0-3), Base 24-31 (bits 8-15), granularity, etc.
4 A
6 DB
7 G */
static void make_seg_data(uint16_t *seg_data, uint32_t base, uint32_t limit, uint8_t type, uint8_t s, uint8_t dpl, uint8_t p, uint8_t g, uint8_t db, uint8_t a)
static int
opSYSENTER(uint32_t fetchdat)
{
seg_data[0] = limit & 0xFFFF;
seg_data[1] = base & 0xFFFF;
seg_data[2] = ((base >> 16) & 0xFF) | (type << 8) | (p << 15) | (dpl << 13) | (s << 12);
seg_data[3] = ((limit >> 16) & 0xF) | (a << 4) | (db << 6) | (g << 7) | ((base >> 16) & 0xFF00);
}
static int opSYSENTER(uint32_t fetchdat)
{
uint16_t sysenter_cs_seg_data[4];
uint16_t sysenter_ss_seg_data[4];
#ifdef SYSENTER_LOG
x386_dynarec_log("SYSENTER called\n");
#endif
if (!(msw & 1)) return internal_illegal("SYSENTER: CPU not in protected mode");
if (!(cs_msr & 0xFFFC)) return internal_illegal("SYSENTER: CS MSR is zero");
#ifdef SYSENTER_LOG
x386_dynarec_log("SYSENTER started:\n");
x386_dynarec_log("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.access, cpu_state.seg_cs.seg, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.checked);
x386_dynarec_log("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.access, cpu_state.seg_ss.seg, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.checked);
x386_dynarec_log("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
x386_dynarec_log("Other information: eip=%08X esp=%08X cpu_state.eflags=%04X cpu_state.flags=%04X use32=%04X stack32=%i\n", cpu_state.pc, ESP, cpu_state.eflags, cpu_state.flags, use32, stack32);
#endif
if (cpu_state.abrt) return 1;
ESP = esp_msr;
cpu_state.pc = eip_msr;
optype = CALL; \
cgate16 = cgate32 = 0; \
/* Set VM, RF, and IF to 0. */
cpu_state.eflags &= ~0x0003;
cpu_state.flags &= ~0x0200;
CS = (cs_msr & 0xFFFC);
make_seg_data(sysenter_cs_seg_data, 0, 0xFFFFF, 11, 1, 0, 1, 1, 1, 0);
do_seg_load(&cpu_state.seg_cs, sysenter_cs_seg_data);
use32 = 0x300;
SS = ((cs_msr + 8) & 0xFFFC);
make_seg_data(sysenter_ss_seg_data, 0, 0xFFFFF, 3, 1, 0, 1, 1, 1, 0);
do_seg_load(&cpu_state.seg_ss, sysenter_ss_seg_data);
stack32 = 1;
cycles -= timing_call_pm;
optype = 0;
int ret = sysenter(fetchdat);
if (ret <= 1) {
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
CPU_BLOCK_END();
}
#ifdef SYSENTER_LOG
x386_dynarec_log("SYSENTER completed:\n");
x386_dynarec_log("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.access, cpu_state.seg_cs.seg, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.checked);
x386_dynarec_log("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.access, cpu_state.seg_ss.seg, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.checked);
x386_dynarec_log("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
x386_dynarec_log("Other information: eip=%08X esp=%08X cpu_state.eflags=%04X cpu_state.flags=%04X use32=%04X stack32=%i\n", cpu_state.pc, ESP, cpu_state.eflags, cpu_state.flags, use32, stack32);
#endif
return 0;
return ret;
}
static int opSYSEXIT(uint32_t fetchdat)
static int
opSYSEXIT(uint32_t fetchdat)
{
uint16_t sysexit_cs_seg_data[4];
uint16_t sysexit_ss_seg_data[4];
#ifdef SYSEXIT_LOG
x386_dynarec_log("SYSEXIT called\n");
#endif
if (!(cs_msr & 0xFFFC)) return internal_illegal("SYSEXIT: CS MSR is zero");
if (!(msw & 1)) return internal_illegal("SYSEXIT: CPU not in protected mode");
if (CPL) return internal_illegal("SYSEXIT: CPL not 0");
#ifdef SYSEXIT_LOG
x386_dynarec_log("SYSEXIT start:\n");
x386_dynarec_log("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.access, cpu_state.seg_cs.seg, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.checked);
x386_dynarec_log("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.access, cpu_state.seg_ss.seg, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.checked);
x386_dynarec_log("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
x386_dynarec_log("Other information: eip=%08X esp=%08X cpu_state.eflags=%04X cpu_state.flags=%04X use32=%04X stack32=%i ECX=%08X EDX=%08X\n", cpu_state.pc, ESP, cpu_state.eflags, cpu_state.flags, use32, stack32, ECX, EDX);
#endif
if (cpu_state.abrt) return 1;
ESP = ECX;
cpu_state.pc = EDX;
optype = CALL; \
cgate16 = cgate32 = 0; \
CS = ((cs_msr + 16) & 0xFFFC) | 3;
make_seg_data(sysexit_cs_seg_data, 0, 0xFFFFF, 11, 1, 3, 1, 1, 1, 0);
do_seg_load(&cpu_state.seg_cs, sysexit_cs_seg_data);
use32 = 0x300;
SS = CS + 8;
make_seg_data(sysexit_ss_seg_data, 0, 0xFFFFF, 3, 1, 3, 1, 1, 1, 0);
do_seg_load(&cpu_state.seg_ss, sysexit_ss_seg_data);
stack32 = 1;
flushmmucache();
cycles -= timing_call_pm;
optype = 0;
int ret = sysexit(fetchdat);
if (ret <= 1) {
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 7, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
CPU_BLOCK_END();
}
#ifdef SYSEXIT_LOG
x386_dynarec_log("SYSEXIT completed:\n");
x386_dynarec_log("CS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", CS, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.access, cpu_state.seg_cs.seg, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.checked);
x386_dynarec_log("SS (%04X): base=%08X, limit=%08X, access=%02X, seg=%04X, limit_low=%08X, limit_high=%08X, checked=%i\n", SS, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.access, cpu_state.seg_ss.seg, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.checked);
x386_dynarec_log("Model specific registers: cs_msr=%04X, esp_msr=%08X, eip_msr=%08X\n", cs_msr, esp_msr, eip_msr);
x386_dynarec_log("Other information: eip=%08X esp=%08X cpu_state.eflags=%04X cpu_state.flags=%04X use32=%04X stack32=%i ECX=%08X EDX=%08X\n", cpu_state.pc, ESP, cpu_state.eflags, cpu_state.flags, use32, stack32, ECX, EDX);
#endif
return 0;
return ret;
}
static int opFXSAVESTOR_a16(uint32_t fetchdat)
static int
opFXSAVESTOR_a16(uint32_t fetchdat)
{
uint8_t fxinst = 0;
uint16_t twd = x87_gettag();

12
src/cpu_common/x86_ops_misc.h
View File

@@ -607,20 +607,18 @@ static int opF7_l_a32(uint32_t fetchdat)
static int opHLT(uint32_t fetchdat)
{
in_hlt = 0;
if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
{
x86gpf(NULL,0);
return 1;
}
if (!((cpu_state.flags & I_FLAG) && pic_intpending))
if (smi_line)
enter_smm_check(1);
else if (!((cpu_state.flags & I_FLAG) && pic_intpending))
{
CLOCK_CYCLES_ALWAYS(100);
if (!((cpu_state.flags & I_FLAG) && pic_intpending)) {
in_hlt = 1;
if (!((cpu_state.flags & I_FLAG) && pic_intpending))
cpu_state.pc--;
}
}
else
CLOCK_CYCLES(5);
@@ -959,7 +957,7 @@ static int opRSM(uint32_t fetchdat)
{
leave_smm();
if (smi_latched)
enter_smm();
enter_smm(smm_in_hlt);
CPU_BLOCK_END();
return 0;
}

2
src/cpu_common/x86_ops_mmx_arith.h
View File

@@ -491,6 +491,7 @@ static int opPSUBD_a32(uint32_t fetchdat)
static int opPSUBSB_a16(uint32_t fetchdat)
{
MMX_REG src;
pclog("opPSUBSB_a16(%08X)\n", fetchdat);
MMX_ENTER();
fetch_ea_16(fetchdat);
@@ -510,6 +511,7 @@ static int opPSUBSB_a16(uint32_t fetchdat)
static int opPSUBSB_a32(uint32_t fetchdat)
{
MMX_REG src;
pclog("opPSUBSB_a32(%08X)\n", fetchdat);
MMX_ENTER();
fetch_ea_32(fetchdat);

2
src/cpu_common/x86_ops_mov_ctrl.h
View File

@@ -139,6 +139,8 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
case 4:
if (cpu_has_feature(CPU_FEATURE_CR4))
{
if (cpu_state.regs[cpu_rm].l & 0x00000020)
fatal("PAE enable\n");
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
break;
}

2
src/cpu_common/x87.h
View File

@@ -51,7 +51,7 @@ void x87_settag(uint16_t new_tag);
void codegen_set_rounding_mode(int mode);
#else
#define TAG_EMPTY 0
#define TAG_EMPTY 3
#define TAG_VALID (1 << 0)
/*Hack for FPU copy. If set then MM[].q contains the 64-bit integer loaded by FILD*/
#define TAG_UINT64 (1 << 2)

5
src/cpu_common/x87_ops.h
View File

@@ -483,8 +483,8 @@ typedef union
} while (0)
#endif
// #ifdef USE_NEW_DYNAREC
#if 1
#ifdef USE_NEW_DYNAREC
#define FP_CHECKTOP64 cpu_state.tag[cpu_state.TOP&7] & TAG_UINT64
#define FP_TAG() cpu_state.tag[cpu_state.TOP&7] = TAG_VALID;
#define FP_FTAG() cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] = TAG_VALID;
#define FP_LSTAG() cpu_state.tag[cpu_state.TOP&7] = TAG_VALID | TAG_UINT64;
@@ -512,6 +512,7 @@ typedef union
#define FP_686
#endif
#else
#define FP_CHECKTOP64 cpu_state.tag[cpu_state.TOP] & TAG_UINT64
#define FP_TAG() cpu_state.tag[cpu_state.TOP] &= ~TAG_UINT64;
#define FP_FTAG() cpu_state.tag[(cpu_state.TOP + fetchdat) & 7] &= ~TAG_UINT64;
#define FP_LSTAG() cpu_state.tag[cpu_state.TOP] |= TAG_UINT64;

4
src/cpu_common/x87_ops_loadstore.h
View File

@@ -185,7 +185,7 @@ static int FISTPiq_a16(uint32_t fetchdat)
FP_ENTER();
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
if (FP_CHECKTOP64)
FP_LSRETQ()
else
temp64 = x87_fround(ST(0));
@@ -201,7 +201,7 @@ static int FISTPiq_a32(uint32_t fetchdat)
FP_ENTER();
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
if (cpu_state.tag[cpu_state.TOP] & TAG_UINT64)
if (FP_CHECKTOP64)
FP_LSRETQ()
else
temp64 = x87_fround(ST(0));

24
src/cpu_new/x86seg.c
View File

@@ -382,12 +382,17 @@ int loadseg(uint16_t seg, x86seg *s)
{
if (!(seg&~3))
{
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Zero stack segment",seg&~3);
return 1;
}
if ((seg&3)!=CPL || dpl!=CPL)
if ((seg&3)!=CPL)
{
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Stack segment RPL != CPL",seg&~3);
return 1;
}
if (dpl!=CPL)
{
x86gpf("loadseg(): Stack segment DPL != CPL",seg&~3);
return 1;
}
switch ((segdat[2]>>8)&0x1F)
@@ -395,7 +400,7 @@ int loadseg(uint16_t seg, x86seg *s)
case 0x12: case 0x13: case 0x16: case 0x17: /*r/w*/
break;
default:
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Unknown stack segment type",seg&~3);
return 1;
}
if (!(segdat[2]&0x8000))
@@ -414,16 +419,21 @@ int loadseg(uint16_t seg, x86seg *s)
case 0x10: case 0x11: case 0x12: case 0x13: /*Data segments*/
case 0x14: case 0x15: case 0x16: case 0x17:
case 0x1A: case 0x1B: /*Readable non-conforming code*/
if ((seg&3)>dpl || (CPL)>dpl)
if ((seg&3)>dpl)
{
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Normal segment RPL > DPL",seg&~3);
return 1;
}
if ((CPL)>dpl)
{
x86gpf("loadseg(): Normal segment DPL < CPL",seg&~3);
return 1;
}
break;
case 0x1E: case 0x1F: /*Readable conforming code*/
break;
default:
x86gpf(NULL,seg&~3);
x86gpf("loadseg(): Unknown normal segment type",seg&~3);
return 1;
}
}

32
src/include/86box/mem.h
View File

@@ -63,6 +63,7 @@
#define MEM_GRANULARITY_MASK (MEM_GRANULARITY_SIZE - 1)
#define MEM_GRANULARITY_HMASK ((1 << (MEM_GRANULARITY_BITS - 1)) - 1)
#define MEM_GRANULARITY_QMASK ((1 << (MEM_GRANULARITY_BITS - 2)) - 1)
#define MEM_GRANULARITY_PMASK ((1 << (MEM_GRANULARITY_BITS - 3)) - 1)
#define MEM_MAPPINGS_NO ((0x100000 >> MEM_GRANULARITY_BITS) << 12)
#define MEM_GRANULARITY_PAGE (MEM_GRANULARITY_MASK & ~0xfff)
#else
@@ -73,6 +74,7 @@
#define MEM_GRANULARITY_MASK (MEM_GRANULARITY_SIZE - 1)
#define MEM_GRANULARITY_HMASK ((1 << (MEM_GRANULARITY_BITS - 1)) - 1)
#define MEM_GRANULARITY_QMASK ((1 << (MEM_GRANULARITY_BITS - 2)) - 1)
#define MEM_GRANULARITY_PMASK ((1 << (MEM_GRANULARITY_BITS - 3)) - 1)
#define MEM_MAPPINGS_NO ((0x100000 >> MEM_GRANULARITY_BITS) << 12)
#define MEM_GRANULARITY_PAGE (MEM_GRANULARITY_MASK & ~0xfff)
#endif
@@ -233,7 +235,8 @@ void writememql(uint32_t addr, uint64_t val);
#endif
extern uint8_t *getpccache(uint32_t a);
extern uint32_t mmutranslatereal(uint32_t addr, int rw);
extern uint64_t mmutranslatereal(uint32_t addr, int rw);
extern uint32_t mmutranslatereal32(uint32_t addr, int rw);
extern void addreadlookup(uint32_t virt, uint32_t phys);
extern void addwritelookup(uint32_t virt, uint32_t phys);
@@ -300,7 +303,7 @@ extern void mem_write_nulll(uint32_t addr, uint32_t val, void *p);
extern int mem_addr_is_ram(uint32_t addr);
extern uint32_t mmutranslate_noabrt(uint32_t addr, int rw);
extern uint64_t mmutranslate_noabrt(uint32_t addr, int rw);
extern void mem_invalidate_range(uint32_t start_addr, uint32_t end_addr);
@@ -331,6 +334,8 @@ extern void mem_remap_top(int kb);
#ifdef EMU_CPU_H
static __inline uint32_t get_phys(uint32_t addr)
{
uint64_t pa64;
if (!((addr ^ get_phys_virt) & ~0xfff))
return get_phys_phys | (addr & 0xfff);
@@ -344,7 +349,12 @@ static __inline uint32_t get_phys(uint32_t addr)
if (((int) (readlookup2[addr >> 12])) != -1)
get_phys_phys = ((uintptr_t)readlookup2[addr >> 12] + (addr & ~0xfff)) - (uintptr_t)ram;
else {
get_phys_phys = (mmutranslatereal(addr, 0) & rammask) & ~0xfff;
pa64 = mmutranslatereal(addr, 0);
if (pa64 > 0xffffffffULL)
get_phys_phys = 0xffffffff;
else
get_phys_phys = (uint32_t) pa64;
get_phys_phys = (get_phys_phys & rammask) & ~0xfff;
if (!cpu_state.abrt && mem_addr_is_ram(get_phys_phys))
addreadlookup(get_phys_virt, get_phys_phys);
}
@@ -355,7 +365,8 @@ static __inline uint32_t get_phys(uint32_t addr)
static __inline uint32_t get_phys_noabrt(uint32_t addr)
{
uint32_t phys_addr;
uint64_t phys_addr;
uint32_t phys_addr32;
if (!(cr0 >> 31))
return addr & rammask;
@@ -363,11 +374,16 @@ static __inline uint32_t get_phys_noabrt(uint32_t addr)
if (((int) (readlookup2[addr >> 12])) != -1)
return ((uintptr_t)readlookup2[addr >> 12] + addr) - (uintptr_t)ram;
phys_addr = mmutranslate_noabrt(addr, 0) & rammask;
if (phys_addr != 0xffffffff && mem_addr_is_ram(phys_addr))
addreadlookup(addr, phys_addr);
phys_addr = mmutranslate_noabrt(addr, 0);
phys_addr32 = (uint32_t) phys_addr;
if ((phys_addr != 0xffffffffffffffffULL) && (phys_addr <= 0xffffffffULL) &&
mem_addr_is_ram(phys_addr32 & rammask))
addreadlookup(addr, phys_addr32 & rammask);
return phys_addr;
if (phys_addr > 0xffffffffULL)
phys_addr32 = 0xffffffff;
return phys_addr32;
}
#endif

399
src/mem.c
View File

@@ -288,14 +288,16 @@ mem_flush_write_page(uint32_t addr, uint32_t virt)
#define mmutranslate_read(addr) mmutranslatereal(addr,0)
#define mmutranslate_write(addr) mmutranslatereal(addr,1)
#define rammap(x) ((uint32_t *)(_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 2) & MEM_GRANULARITY_QMASK]
#define rammap64(x) ((uint64_t *)(_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 3) & MEM_GRANULARITY_PMASK]
uint32_t
mmutranslatereal(uint32_t addr, int rw)
static uint64_t
mmutranslatereal_normal(uint32_t addr, int rw)
{
uint32_t temp,temp2,temp3;
uint32_t addr2;
if (cpu_state.abrt) return -1;
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc));
temp = temp2 = rammap(addr2);
@@ -306,7 +308,7 @@ mmutranslatereal(uint32_t addr, int rw)
if (rw) temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return -1;
return 0xffffffffffffffffULL;
}
if ((temp & 0x80) && (cr4 & CR4_PSE)) {
@@ -321,7 +323,7 @@ mmutranslatereal(uint32_t addr, int rw)
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return -1;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
@@ -339,36 +341,129 @@ mmutranslatereal(uint32_t addr, int rw)
if (rw) temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return -1;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
rammap(addr2) |= 0x20;
rammap((temp2 & ~0xfff) + ((addr >> 10) & 0xffc)) |= (rw?0x60:0x20);
return (temp&~0xfff)+(addr&0xfff);
return (uint64_t) ((temp&~0xfff)+(addr&0xfff));
}
static uint64_t
mmutranslatereal_pae(uint32_t addr, int rw)
{
uint64_t temp,temp2,temp3;
uint64_t addr2,addr3,addr4;
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18);
temp = temp2 = rammap64(addr2);
if (! (temp&1)) {
cr2 = addr;
temp &= 1;
if (CPL == 3) temp |= 4;
if (rw) temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
addr3 = (temp & ~0xfff) + ((addr >> 18) & 0xff8);
temp = rammap64(addr3);
temp3 = temp & temp2;
if (! (temp&1)) {
cr2 = addr;
temp &= 1;
if (CPL == 3) temp |= 4;
if (rw) temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
if (temp & 0x80) {
/*4MB page*/
if ((CPL == 3 && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3 && !cpl_override) || cr0 & WP_FLAG))) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
rammap64(addr3) |= 0x20;
return ((temp & ~0x1fffff) + (addr & 0x1fffff)) & 0x0000000fffffffffULL;
}
addr4 = (temp & ~0xfff) + ((addr >> 9) & 0xff8);
temp = rammap64(addr4);
temp3 = temp3 & temp2;
if (!(temp&1) || (CPL==3 && !(temp3&4) && !cpl_override) || (rw && !(temp3&2) && ((CPL == 3 && !cpl_override) || cr0&WP_FLAG))) {
cr2 = addr;
temp &= 1;
if (CPL == 3) temp |= 4;
if (rw) temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
rammap64(addr3) |= 0x20;
rammap64(addr4) |= (rw? 0x60 : 0x20);
return ((temp & ~0xfff) + ((uint64_t) (addr & 0xfff)))& 0x0000000fffffffffULL;
}
uint64_t
mmutranslatereal(uint32_t addr, int rw)
{
if (cr4 & CR4_PAE)
return mmutranslatereal_pae(addr, rw);
else
return mmutranslatereal_normal(addr, rw);
}
/* This is needed because the old recompiler calls this to check for page fault. */
uint32_t
mmutranslate_noabrt(uint32_t addr, int rw)
mmutranslatereal32(uint32_t addr, int rw)
{
return (uint32_t) mmutranslatereal(addr, rw);
}
static uint64_t
mmutranslate_noabrt_normal(uint32_t addr, int rw)
{
uint32_t temp,temp2,temp3;
uint32_t addr2;
if (cpu_state.abrt)
return -1;
return 0xffffffffffffffffULL;
addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc));
temp = temp2 = rammap(addr2);
if (! (temp & 1))
return -1;
return 0xffffffffffffffffULL;
if ((temp & 0x80) && (cr4 & CR4_PSE)) {
/*4MB page*/
if ((CPL == 3 && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (CPL == 3 || cr0 & WP_FLAG)))
return -1;
return 0xffffffffffffffffULL;
return (temp & ~0x3fffff) + (addr & 0x3fffff);
}
@@ -377,9 +472,60 @@ mmutranslate_noabrt(uint32_t addr, int rw)
temp3 = temp & temp2;
if (!(temp&1) || (CPL==3 && !(temp3&4) && !cpl_override) || (rw && !(temp3&2) && (CPL==3 || cr0&WP_FLAG)))
return -1;
return 0xffffffffffffffffULL;
return (temp & ~0xfff) + (addr & 0xfff);
return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff));
}
static uint64_t
mmutranslate_noabrt_pae(uint32_t addr, int rw)
{
uint32_t temp,temp2,temp3;
uint32_t addr2,addr3,addr4;
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18);
temp = temp2 = rammap64(addr2);
if (! (temp & 1))
return 0xffffffffffffffffULL;
addr3 = (temp & ~0xfff) + ((addr >> 18) & 0xff8);
temp = rammap64(addr3);
temp3 = temp & temp2;
if (! (temp & 1))
return 0xffffffffffffffffULL;
if (temp & 0x80) {
/*2MB page*/
if ((CPL == 3 && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (CPL == 3 || cr0 & WP_FLAG)))
return 0xffffffffffffffffULL;
return ((temp & ~0x1fffff) + (addr & 0x1fffff)) & 0x0000000fffffffffULL;
}
addr4 = (temp & ~0xfff) + ((addr >> 9) & 0xff8);
temp = rammap64(addr4);
temp3 = temp3 & temp2;
if (!(temp&1) || (CPL==3 && !(temp3&4) && !cpl_override) || (rw && !(temp3&2) && (CPL==3 || cr0&WP_FLAG)))
return 0xffffffffffffffffULL;
return ((temp & ~0xfff) + ((uint64_t) (addr & 0xfff))) & 0x0000000fffffffffULL;
}
uint64_t
mmutranslate_noabrt(uint32_t addr, int rw)
{
if (cr4 & CR4_PAE)
return mmutranslate_noabrt_pae(addr, rw);
else
return mmutranslate_noabrt_normal(addr, rw);
}
@@ -467,29 +613,30 @@ addwritelookup(uint32_t virt, uint32_t phys)
uint8_t *
getpccache(uint32_t a)
{
uint64_t a64 = (uint64_t) a;
uint32_t a2;
a2 = a;
if (cr0 >> 31) {
a = mmutranslate_read(a);
a64 = mmutranslate_read(a64);
if (a == 0xffffffff) return ram;
if (a64 == 0xffffffffffffffffULL) return ram;
}
a &= rammask;
a64 &= rammask;
if (_mem_exec[a >> MEM_GRANULARITY_BITS]) {
if (_mem_exec[a64 >> MEM_GRANULARITY_BITS]) {
if (is286) {
if (read_mapping[a >> MEM_GRANULARITY_BITS] && (read_mapping[a >> MEM_GRANULARITY_BITS]->flags & MEM_MAPPING_ROM))
if (read_mapping[a64 >> MEM_GRANULARITY_BITS] && (read_mapping[a64 >> MEM_GRANULARITY_BITS]->flags & MEM_MAPPING_ROM))
cpu_prefetch_cycles = cpu_rom_prefetch_cycles;
else
cpu_prefetch_cycles = cpu_mem_prefetch_cycles;
}
return &_mem_exec[a >> MEM_GRANULARITY_BITS][(uintptr_t)(a & MEM_GRANULARITY_PAGE) - (uintptr_t)(a2 & ~0xfff)];
return &_mem_exec[a64 >> MEM_GRANULARITY_BITS][(uintptr_t)(a64 & MEM_GRANULARITY_PAGE) - (uintptr_t)(a2 & ~0xfff)];
}
mem_log("Bad getpccache %08X\n", a);
mem_log("Bad getpccache %08X%08X\n", (uint32_t) (a >> 32), (uint32_t) (a & 0xffffffff));
#if FIXME
return &ff_array[0-(uintptr_t)(a2 & ~0xfff)];
@@ -502,15 +649,19 @@ getpccache(uint32_t a)
uint8_t
readmembl(uint32_t addr)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
mem_logical_addr = addr;
if (cr0 >> 31) {
addr = mmutranslate_read(addr);
if (addr == 0xffffffff) return 0xff;
addr64 = mmutranslate_read(addr);
if (addr64 == 0xffffffffffffffffULL)
return 0xff;
if (addr64 > 0xffffffffULL)
return 0xff;
}
addr &= rammask;
addr = (uint32_t) (addr64 & rammask);
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_b)
@@ -523,6 +674,7 @@ readmembl(uint32_t addr)
void
writemembl(uint32_t addr, uint8_t val)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
mem_logical_addr = addr;
@@ -532,11 +684,13 @@ writemembl(uint32_t addr, uint8_t val)
}
if (cr0 >> 31) {
addr = mmutranslate_write(addr);
if (addr == 0xffffffff)
addr64 = mmutranslate_write(addr);
if (addr64 == 0xffffffffffffffffULL)
return;
if (addr64 > 0xffffffffULL)
return;
}
addr &= rammask;
addr = (uint32_t) (addr64 & rammask);
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_b)
@@ -548,18 +702,19 @@ writemembl(uint32_t addr, uint8_t val)
uint16_t
readmemwl(uint32_t addr)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
mem_logical_addr = addr;
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
if (addr64 & 1) {
if (!cpu_cyrix_alignment || (addr64 & 7) == 7)
sub_cycles(timing_misaligned);
if ((addr & 0xfff) > 0xffe) {
if ((addr64 & 0xfff) > 0xffe) {
if (cr0 >> 31) {
if (mmutranslate_read(addr) == 0xffffffff)
if (mmutranslate_read(addr) == 0xffffffffffffffffULL)
return 0xffff;
if (mmutranslate_read(addr+1) == 0xffffffff)
if (mmutranslate_read(addr+1) == 0xffffffffffffffffULL)
return 0xffff;
}
return readmembl(addr)|(readmembl(addr+1)<<8);
@@ -567,12 +722,14 @@ readmemwl(uint32_t addr)
return *(uint16_t *)(readlookup2[addr >> 12] + addr);
}
if (cr0>>31) {
addr = mmutranslate_read(addr);
if (addr == 0xffffffff)
addr64 = mmutranslate_read(addr);
if (addr64 == 0xffffffffffffffffULL)
return 0xffff;
if (addr64 > 0xffffffffULL)
return 0xffff;
}
addr &= rammask;
addr = (uint32_t) (addr64 & rammask);
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
@@ -589,6 +746,7 @@ readmemwl(uint32_t addr)
void
writememwl(uint32_t addr, uint16_t val)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
mem_logical_addr = addr;
@@ -617,12 +775,14 @@ writememwl(uint32_t addr, uint16_t val)
return;
}
if (cr0>>31) {
addr = mmutranslate_write(addr);
if (addr==0xFFFFFFFF)
addr64 = mmutranslate_write(addr);
if (addr64 == 0xffffffffffffffffULL)
return;
if (addr64 > 0xffffffffULL)
return;
}
addr &= rammask;
addr = (uint32_t) (addr64 & rammask);
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map) {
@@ -639,6 +799,7 @@ writememwl(uint32_t addr, uint16_t val)
uint32_t
readmemll(uint32_t addr)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
mem_logical_addr = addr;
@@ -646,11 +807,11 @@ readmemll(uint32_t addr)
if (addr & 3) {
if (!cpu_cyrix_alignment || (addr & 7) > 4)
sub_cycles(timing_misaligned);
if ((addr&0xFFF)>0xFFC) {
if ((addr & 0xfff) > 0xffc) {
if (cr0>>31) {
if (mmutranslate_read(addr) == 0xffffffff)
if (mmutranslate_read(addr) == 0xffffffffffffffffULL)
return 0xffffffff;
if (mmutranslate_read(addr+3) == 0xffffffff)
if (mmutranslate_read(addr+3) == 0xffffffffffffffffULL)
return 0xffffffff;
}
return readmemwl(addr)|(readmemwl(addr+2)<<16);
@@ -658,13 +819,15 @@ readmemll(uint32_t addr)
return *(uint32_t *)(readlookup2[addr >> 12] + addr);
}
if (cr0>>31) {
addr = mmutranslate_read(addr);
if (addr==0xFFFFFFFF)
return 0xFFFFFFFF;
if (cr0 >> 31) {
addr64 = mmutranslate_read(addr);
if (addr64 == 0xffffffffffffffffULL)
return 0xffffffff;
if (addr64 > 0xffffffffULL)
return 0xffffffff;
}
addr&=rammask;
addr = (uint32_t) (addr64 & rammask);
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map) {
@@ -686,6 +849,7 @@ readmemll(uint32_t addr)
void
writememll(uint32_t addr, uint32_t val)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
mem_logical_addr = addr;
@@ -695,9 +859,9 @@ writememll(uint32_t addr, uint32_t val)
sub_cycles(timing_misaligned);
if ((addr & 0xFFF) > 0xFFC) {
if (cr0>>31) {
if (mmutranslate_write(addr) == 0xffffffff)
if (mmutranslate_write(addr) == 0xffffffffffffffffULL)
return;
if (mmutranslate_write(addr+3) == 0xffffffff)
if (mmutranslate_write(addr+3) == 0xffffffffffffffffULL)
return;
}
writememwl(addr,val);
@@ -713,12 +877,14 @@ writememll(uint32_t addr, uint32_t val)
return;
}
if (cr0>>31) {
addr = mmutranslate_write(addr);
if (addr==0xFFFFFFFF)
addr64 = mmutranslate_write(addr);
if (addr64 == 0xffffffffffffffffULL)
return;
if (addr64 > 0xffffffffULL)
return;
}
addr&=rammask;
addr = (uint32_t) (addr64 & rammask);
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map) {
@@ -740,6 +906,7 @@ writememll(uint32_t addr, uint32_t val)
uint64_t
readmemql(uint32_t addr)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
mem_logical_addr = addr;
@@ -748,10 +915,10 @@ readmemql(uint32_t addr)
sub_cycles(timing_misaligned);
if ((addr & 0xFFF) > 0xFF8) {
if (cr0>>31) {
if (mmutranslate_read(addr) == 0xffffffff)
return 0xffffffff;
if (mmutranslate_read(addr+7) == 0xffffffff)
return 0xffffffff;
if (mmutranslate_read(addr) == 0xffffffffffffffffULL)
return 0xffffffffffffffffULL;
if (mmutranslate_read(addr+7) == 0xffffffffffffffffULL)
return 0xffffffffffffffffULL;
}
return readmemll(addr)|((uint64_t)readmemll(addr+4)<<32);
} else if (readlookup2[addr >> 12] != -1)
@@ -759,12 +926,14 @@ readmemql(uint32_t addr)
}
if (cr0>>31) {
addr = mmutranslate_read(addr);
if (addr==0xFFFFFFFF)
return 0xFFFFFFFF;
addr64 = mmutranslate_read(addr);
if (addr64 == 0xffffffffffffffffULL)
return 0xffffffffffffffffULL;
if (addr64 > 0xffffffffULL)
return 0xffffffffffffffffULL;
}
addr&=rammask;
addr = (uint32_t) (addr64 & rammask);
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_l)
@@ -777,6 +946,7 @@ readmemql(uint32_t addr)
void
writememql(uint32_t addr, uint64_t val)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
mem_logical_addr = addr;
@@ -785,9 +955,9 @@ writememql(uint32_t addr, uint64_t val)
sub_cycles(timing_misaligned);
if ((addr & 0xFFF) > 0xFF8) {
if (cr0>>31) {
if (mmutranslate_write(addr) == 0xffffffff)
if (mmutranslate_write(addr) == 0xffffffffffffffffULL)
return;
if (mmutranslate_write(addr+7) == 0xffffffff)
if (mmutranslate_write(addr+7) == 0xffffffffffffffffULL)
return;
}
writememll(addr, val);
@@ -804,12 +974,14 @@ writememql(uint32_t addr, uint64_t val)
return;
}
if (cr0>>31) {
addr = mmutranslate_write(addr);
if (addr==0xFFFFFFFF)
addr64 = mmutranslate_write(addr);
if (addr64 == 0xffffffffffffffffULL)
return;
if (addr64 > 0xffffffffULL)
return;
}
addr&=rammask;
addr = (uint32_t) (addr64 & rammask);
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map) {
@@ -851,6 +1023,7 @@ writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
uint16_t
readmemwl(uint32_t seg, uint32_t addr)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
uint32_t addr2 = mem_logical_addr = seg + addr;
@@ -859,9 +1032,9 @@ readmemwl(uint32_t seg, uint32_t addr)
sub_cycles(timing_misaligned);
if ((addr2 & 0xfff) > 0xffe) {
if (cr0 >> 31) {
if (mmutranslate_read(addr2) == 0xffffffff)
if (mmutranslate_read(addr2) == 0xffffffffffffffffULL)
return 0xffff;
if (mmutranslate_read(addr2+1) == 0xffffffff)
if (mmutranslate_read(addr2+1) == 0xffffffffffffffffULL)
return 0xffff;
}
if (is386) return readmemb386l(seg,addr)|(((uint16_t) readmemb386l(seg,addr+1))<<8);
@@ -872,12 +1045,15 @@ readmemwl(uint32_t seg, uint32_t addr)
}
if (cr0 >> 31) {
addr2 = mmutranslate_read(addr2);
if (addr2 == 0xffffffff)
addr64 = mmutranslate_read(addr2);
if (addr64 == 0xffffffffffffffffULL)
return 0xffff;
}
if (addr64 > 0xffffffffULL)
return 0xffff;
} else
addr64 = (uint64_t) addr2;
addr2 &= rammask;
addr2 = (uint32_t) (addr64 & rammask);
map = read_mapping[addr2 >> MEM_GRANULARITY_BITS];
@@ -900,6 +1076,7 @@ readmemwl(uint32_t seg, uint32_t addr)
void
writememwl(uint32_t seg, uint32_t addr, uint16_t val)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
uint32_t addr2 = mem_logical_addr = seg + addr;
@@ -908,8 +1085,8 @@ writememwl(uint32_t seg, uint32_t addr, uint16_t val)
sub_cycles(timing_misaligned);
if ((addr2 & 0xFFF) > 0xffe) {
if (cr0 >> 31) {
if (mmutranslate_write(addr2) == 0xffffffff) return;
if (mmutranslate_write(addr2+1) == 0xffffffff) return;
if (mmutranslate_write(addr2) == 0xffffffffffffffffULL) return;
if (mmutranslate_write(addr2+1) == 0xffffffffffffffffULL) return;
}
if (is386) {
writememb386l(seg,addr,val);
@@ -931,11 +1108,15 @@ writememwl(uint32_t seg, uint32_t addr, uint16_t val)
}
if (cr0 >> 31) {
addr2 = mmutranslate_write(addr2);
if (addr2 == 0xffffffff) return;
}
addr64 = mmutranslate_write(addr2);
if (addr64 == 0xffffffffffffffffULL)
return;
if (addr64 > 0xffffffffULL)
return;
} else
addr64 = (uint64_t) addr2;
addr2 &= rammask;
addr2 = (uint32_t) (addr64 & rammask);
map = write_mapping[addr2 >> MEM_GRANULARITY_BITS];
@@ -955,6 +1136,7 @@ writememwl(uint32_t seg, uint32_t addr, uint16_t val)
uint32_t
readmemll(uint32_t seg, uint32_t addr)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
uint32_t addr2 = mem_logical_addr = seg + addr;
@@ -963,8 +1145,8 @@ readmemll(uint32_t seg, uint32_t addr)
sub_cycles(timing_misaligned);
if ((addr2 & 0xfff) > 0xffc) {
if (cr0 >> 31) {
if (mmutranslate_read(addr2) == 0xffffffff) return 0xffffffff;
if (mmutranslate_read(addr2+3) == 0xffffffff) return 0xffffffff;
if (mmutranslate_read(addr2) == 0xffffffffffffffffULL) return 0xffffffff;
if (mmutranslate_read(addr2+3) == 0xffffffffffffffffULL) return 0xffffffff;
}
return readmemwl(seg,addr)|(readmemwl(seg,addr+2)<<16);
} else if (readlookup2[addr2 >> 12] != (uintptr_t) -1)
@@ -972,12 +1154,15 @@ readmemll(uint32_t seg, uint32_t addr)
}
if (cr0 >> 31) {
addr2 = mmutranslate_read(addr2);
if (addr2 == 0xffffffff)
addr64 = mmutranslate_read(addr2);
if (addr64 == 0xffffffffffffffffULL)
return 0xffffffff;
}
if (addr64 > 0xffffffffULL)
return 0xffffffff;
} else
addr64 = (uint64_t) addr2;
addr2 &= rammask;
addr2 = (uint32_t) (addr64 & rammask);
map = read_mapping[addr2 >> MEM_GRANULARITY_BITS];
@@ -1001,6 +1186,7 @@ readmemll(uint32_t seg, uint32_t addr)
void
writememll(uint32_t seg, uint32_t addr, uint32_t val)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
uint32_t addr2 = mem_logical_addr = seg + addr;
@@ -1009,8 +1195,8 @@ writememll(uint32_t seg, uint32_t addr, uint32_t val)
sub_cycles(timing_misaligned);
if ((addr2 & 0xfff) > 0xffc) {
if (cr0 >> 31) {
if (mmutranslate_write(addr2) == 0xffffffff) return;
if (mmutranslate_write(addr2+3) == 0xffffffff) return;
if (mmutranslate_write(addr2) == 0xffffffffffffffffULL) return;
if (mmutranslate_write(addr2+3) == 0xffffffffffffffffULL) return;
}
writememwl(seg,addr,val);
writememwl(seg,addr+2,val>>16);
@@ -1027,11 +1213,15 @@ writememll(uint32_t seg, uint32_t addr, uint32_t val)
}
if (cr0 >> 31) {
addr2 = mmutranslate_write(addr2);
if (addr2 == 0xffffffff) return;
}
addr64 = mmutranslate_write(addr2);
if (addr64 == 0xffffffffffffffffULL)
return;
if (addr64 > 0xffffffffULL)
return;
} else
addr64 = (uint32_t) addr2;
addr2 &= rammask;
addr2 = (uint32_t) (addr64 & rammask);
map = write_mapping[addr2 >> MEM_GRANULARITY_BITS];
@@ -1057,6 +1247,7 @@ writememll(uint32_t seg, uint32_t addr, uint32_t val)
uint64_t
readmemql(uint32_t seg, uint32_t addr)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
uint32_t addr2 = mem_logical_addr = seg + addr;
@@ -1064,8 +1255,8 @@ readmemql(uint32_t seg, uint32_t addr)
sub_cycles(timing_misaligned);
if ((addr2 & 0xfff) > 0xff8) {
if (cr0 >> 31) {
if (mmutranslate_read(addr2) == 0xffffffff) return 0xffffffff;
if (mmutranslate_read(addr2+7) == 0xffffffff) return 0xffffffff;
if (mmutranslate_read(addr2) == 0xffffffffffffffffULL) return 0xffffffffffffffffULL;
if (mmutranslate_read(addr2+7) == 0xffffffffffffffffULL) return 0xffffffffffffffffULL;
}
return readmemll(seg,addr)|((uint64_t)readmemll(seg,addr+4)<<32);
} else if (readlookup2[addr2 >> 12] != (uintptr_t) -1)
@@ -1073,12 +1264,15 @@ readmemql(uint32_t seg, uint32_t addr)
}
if (cr0 >> 31) {
addr2 = mmutranslate_read(addr2);
if (addr2 == 0xffffffff)
return -1;
}
addr64 = mmutranslate_read(addr2);
if (addr64 == 0xffffffffffffffffULL)
return 0xffffffffffffffffULL;
if (addr64 > 0xffffffffULL)
return 0xffffffffffffffffULL;
} else
addr64 = (uint64_t) addr2;
addr2 &= rammask;
addr2 = (uint32_t) (addr64 & rammask);
map = read_mapping[addr2 >> MEM_GRANULARITY_BITS];
if (map && map->read_l)
@@ -1091,6 +1285,7 @@ readmemql(uint32_t seg, uint32_t addr)
void
writememql(uint32_t seg, uint32_t addr, uint64_t val)
{
uint64_t addr64 = (uint64_t) addr;
mem_mapping_t *map;
uint32_t addr2 = mem_logical_addr = seg + addr;
@@ -1098,8 +1293,8 @@ writememql(uint32_t seg, uint32_t addr, uint64_t val)
sub_cycles(timing_misaligned);
if ((addr2 & 0xfff) > 0xff8) {
if (cr0 >> 31) {
if (mmutranslate_write(addr2) == 0xffffffff) return;
if (mmutranslate_write(addr2+7) == 0xffffffff) return;
if (mmutranslate_write(addr2) == 0xffffffffffffffffULL) return;
if (mmutranslate_write(addr2+7) == 0xffffffffffffffffULL) return;
}
writememll(seg, addr, val);
writememll(seg, addr+4, val >> 32);
@@ -1117,11 +1312,15 @@ writememql(uint32_t seg, uint32_t addr, uint64_t val)
}
if (cr0 >> 31) {
addr2 = mmutranslate_write(addr2);
if (addr2 == 0xffffffff) return;
}
addr64 = mmutranslate_write(addr2);
if (addr64 == 0xffffffffffffffffULL)
return;
if (addr64 > 0xffffffffULL)
return;
} else
addr64 = (uint64_t) addr2;
addr2 &= rammask;
addr2 = (uint32_t) (addr64 & rammask);
map = write_mapping[addr2 >> MEM_GRANULARITY_BITS];

30
src/win/Makefile.mingw
View File

@@ -38,8 +38,8 @@ ifeq ($(DEV_BUILD), y)
ifndef DEV_BRANCH
DEV_BRANCH := y
endif
ifndef AMD_K
AMD_K := y
ifndef AMD_K5
AMD_K5 := y
endif
ifndef CL5422
CL5422 := y
@@ -108,8 +108,8 @@ else
ifndef DEV_BRANCH
DEV_BRANCH := n
endif
ifndef AMD_K
AMD_K := n
ifndef AMD_K5
AMD_K5 := n
endif
ifndef CL5422
CL5422 := n
@@ -377,10 +377,9 @@ OPTS += -DUSE_DYNAREC
RFLAGS += -DUSE_DYNAREC
DYNARECOBJ := 386_dynarec_ops.o \
codegen.o \
codegen_ops.o \
codegen_timing_common.o codegen_timing_486.o \
codegen_timing_686.o codegen_timing_pentium.o \
codegen_timing_winchip.o $(PLATCG)
codegen_ops.o codegen_timing_486.o \
codegen_timing_686.o codegen_timing_common.o codegen_timing_k6.o codegen_timing_pentium.o \
codegen_timing_p6.o codegen_timing_winchip.o codegen_timing_winchip2.o $(PLATCG)
endif
ifneq ($(WX), n)
@@ -453,8 +452,8 @@ ifeq ($(DEV_BRANCH), y)
OPTS += -DDEV_BRANCH
DEVBROBJ :=
ifeq ($(AMD_K), y)
OPTS += -DUSE_AMD_K
ifeq ($(AMD_K5), y)
OPTS += -DUSE_AMD_K5
endif
ifeq ($(CL5422), y)
@@ -548,7 +547,11 @@ CFLAGS := $(WX_FLAGS) $(OPTS) $(DFLAGS) $(COPTIM) $(AOPTIM) \
# -funroll-loops
# Add freetyp2 references through pkgconfig
ifeq ($(DEBUG), y)
CFLAGS := $(CFLAGS) -fstack-protector-all `pkg-config --cflags freetype2`
else
CFLAGS := $(CFLAGS) `pkg-config --cflags freetype2`
endif
CXXFLAGS := $(CFLAGS)
@@ -738,6 +741,9 @@ endif
LIBS := -mwindows -lcomctl32 \
-lopenal -lole32
ifeq ($(DEBUG), y)
LIBS += -lssp
endif
ifeq ($(D2D), y)
LIBS += $(D2DLIB)
@@ -821,8 +827,10 @@ pcap_if.res: pcap_if.rc
pcap_if.exe: pcap_if.o win_dynld.o pcap_if.res
@echo Linking pcap_if.exe ..
ifeq ($(DEBUG), y)
@$(CC) $(LDFLAGS) -o pcap_if.exe pcap_if.o win_dynld.o pcap_if.res -lssp
else
@$(CC) $(LDFLAGS) -o pcap_if.exe pcap_if.o win_dynld.o pcap_if.res
ifneq ($(DEBUG), y)
@$(STRIP) pcap_if.exe
endif

12
src/win/Makefile_ndr.mingw
View File

@@ -38,8 +38,8 @@ ifeq ($(DEV_BUILD), y)
ifndef DEV_BRANCH
DEV_BRANCH := y
endif
ifndef AMD_K
AMD_K := y
ifndef AMD_K5
AMD_K5 := y
endif
ifndef CL5422
CL5422 := y
@@ -108,8 +108,8 @@ else
ifndef DEV_BRANCH
DEV_BRANCH := n
endif
ifndef AMD_K
AMD_K := n
ifndef AMD_K5
AMD_K5 := n
endif
ifndef CL5422
CL5422 := n
@@ -461,8 +461,8 @@ ifeq ($(DEV_BRANCH), y)
OPTS += -DDEV_BRANCH
DEVBROBJ :=
ifeq ($(AMD_K), y)
OPTS += -DUSE_AMD_K
ifeq ($(AMD_K5), y)
OPTS += -DUSE_AMD_K5
endif
ifeq ($(CL5422), y)

4
src/win/win_new_floppy.c
View File

@@ -51,8 +51,8 @@ typedef struct {
} disk_size_t;
static const disk_size_t disk_sizes[14] = { { 0, 1, 2, 1, 0, 40, 8, 2, 0xfe, 2, 2, 1, 112 }, /* 160k */
{ 0, 1, 2, 1, 0, 40, 9, 2, 0xfc, 2, 2, 1, 112 }, /* 180k */
static const disk_size_t disk_sizes[14] = { { 0, 1, 2, 1, 0, 40, 8, 2, 0xfe, 2, 2, 1, 64 }, /* 160k */
{ 0, 1, 2, 1, 0, 40, 9, 2, 0xfc, 2, 2, 1, 64 }, /* 180k */
{ 0, 2, 2, 1, 0, 40, 8, 2, 0xff, 2, 2, 1, 112 }, /* 320k */
{ 0, 2, 2, 1, 0, 40, 9, 2, 0xfd, 2, 2, 2, 112 }, /* 360k */
{ 0, 2, 2, 1, 0, 80, 8, 2, 0xfb, 2, 2, 2, 112 }, /* 640k */