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Redirect all PRMCIO/PRMVIO writes to SVGA subsystem, not just a few random ones.

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This commit is contained in:
starfrost013
2025-03-29 16:23:18 +00:00
parent 03709d2735
commit 2829669740
6 changed files with 11 additions and 14 deletions
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doc/nvidia_notes/status.xlsx
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7
src/include/86box/nv/vid_nv3.h
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@@ -14,7 +14,7 @@
* Also check the doc folder for some more notres
*
* vid_nv3.h: NV3 Architecture Hardware Reference (open-source)
* Last updated: 22 March 2025 (STILL WORKING ON IT!!!)
* Last updated: 26 March 2025 (STILL WORKING ON IT!!!)
*
* Authors: Connor Hyde <mario64crashed@gmail.com>
*
@@ -671,9 +671,10 @@ extern const device_config_t nv3_config[];
#define NV3_PGRAPH_REGISTER_END 0x401FFF // end of pgraph registers
#define NV3_PGRAPH_REAL_END 0x5C1FFF
// PRMCIO is redirected to SVGA subsystem
#define NV3_PRMCIO_START 0x601000
// Following four are CRTC+I2C access registers
// and get redirected to VGA
#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO 0x6013B4 // Current CRTC Register Index - Monochrome
#define NV3_PRMCIO_CRTC_REGISTER_CUR_MONO 0x6013B5 // Currently Selected CRTC Register - Monochrome
#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR 0x6013D4 // Current CRTC Register Index - Colour

10
src/video/nv/nv3/nv3_core.c
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@@ -41,13 +41,9 @@ void nv3_svga_out(uint16_t addr, uint8_t val, void* priv);
bool nv3_is_svga_redirect_address(uint32_t addr)
{
return (addr >= NV3_PRMVIO_START
&& addr <= NV3_PRMVIO_END
|| addr == NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR
|| addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR
|| addr == NV3_PRMCIO_CRTC_REGISTER_CUR_MONO
|| addr == NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO
|| (addr >= NV3_VGA_DAC_START && addr <= NV3_VGA_DAC_END));
return (addr >= NV3_PRMVIO_START && addr <= NV3_PRMVIO_END) // VGA
|| (addr >= NV3_PRMCIO_START && addr <= NV3_PRMCIO_END) // CRTC
|| (addr >= NV3_VGA_DAC_START && addr <= NV3_VGA_DAC_END); // Legacy RAMDAC support(?)
}
// All MMIO regs are 32-bit i believe internally

4
src/video/nv/nv3/subsystems/nv3_pmc.c
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@@ -88,11 +88,11 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now)
if (nv3->pfifo.interrupt_status & nv3->pfifo.interrupt_enable)
new_intr_value |= (NV3_PMC_INTERRUPT_PFIFO_PENDING << NV3_PMC_INTERRUPT_PFIFO);
// PFB interrupt is VBLANK PGRAPH interrupt...what nvidia...clean this up once we verify it
// PFB interrupt is VBLANK PGRAPH interrupt...what nvidia...
if (nv3->pgraph.interrupt_status_0 & (1 << 8)
&& nv3->pgraph.interrupt_enable_0 & (1 << 8))
new_intr_value |= (NV3_PMC_INTERRUPT_PFB_PENDING << NV3_PMC_INTERRUPT_PFB);
if (nv3->pgraph.interrupt_status_0 & ~(1 << 8)
&& nv3->pgraph.interrupt_enable_0 & ~(1 << 8)) // otherwise PGRAPH-0 interurpt
new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH0_PENDING << NV3_PMC_INTERRUPT_PGRAPH0);

2
src/video/nv/nv3/subsystems/nv3_ptimer.c
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@@ -84,7 +84,7 @@ void nv3_ptimer_tick(double real_time)
// Check if the alarm has actually triggered...
if (nv3->ptimer.time >= nv3->ptimer.alarm)
{
nv_log("PTIMER alarm interrupt fired because we reached TIME value 0x%08x\n", nv3->ptimer.alarm);
nv_log("PTIMER alarm interrupt fired (if interrupts enabled) because we reached TIME value 0x%08x\n", nv3->ptimer.alarm);
nv3_ptimer_interrupt(NV3_PTIMER_INTR_ALARM);
}
}

2
src/video/nv/nv3/subsystems/nv3_user.c
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@@ -37,7 +37,7 @@ uint32_t nv3_user_read(uint32_t address)
//todo: print out the subchannel
uint8_t method_offset = (address & 0x1FFC);
#ifndef RELEASE_BUILD
#ifdef ENABLE_NV_LOG_ULTRA
uint8_t channel = (address - NV3_USER_START) / 0x10000;
uint8_t subchannel = ((address - NV3_USER_START)) / 0x2000 % NV3_DMA_SUBCHANNELS_PER_CHANNEL;