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WARNING: CONFIGS MIGHT PARTIALLY BREAK WHERE DEVICE NAMES HAVE CHANGED.

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Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite;
Added device.c/h API to obtain name from the device_t struct;
Significant changes to win/win_settings.c to clean up the code a bit and fix bugs;
Ported all the CPU and AudioPCI commits from PCem;
Added an API call to allow ACPI soft power off to gracefully stop the emulator;
Removed the Siemens PCD-2L from the Dev branch because it now works;
Removed the Socket 5 HP Vectra from the Dev branch because it now works;
Fixed the Compaq Presario and the Micronics Spitfire;
Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470;
SMM fixes;
Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions;
Changed IDE reset period to match the specification, fixes #929;
The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset;
Added the Intel AN430TX but Dev branched because it does not work;
The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full);
Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types;
USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it);
Fixed NVR on the the SMC FDC37C932QF and APM variants;
A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX;
Some ACPI changes.
This commit is contained in:
OBattler
2020-11-16 00:01:21 +01:00
parent 745460f64b
commit 0faf6692c9
260 changed files with 5122 additions and 4471 deletions
Download Patch File Download Diff File Expand all files Collapse all files

55
src/acpi.c
View File

@@ -82,25 +82,34 @@ acpi_update_irq(void *priv)
static void
acpi_raise_smi(void *priv)
acpi_raise_smi_common(void *priv)
{
acpi_t *dev = (acpi_t *) priv;
if ((dev->vendor == VEN_VIA) || (dev->vendor == VEN_VIA_596B)) {
if ((dev->regs.glbctl & 0x01) && (!dev->regs.smi_lock || !dev->regs.smi_active)) {
if ((!dev->regs.smi_lock || !dev->regs.smi_active)) {
smi_line = 1;
dev->regs.smi_active = 1;
}
} else if (dev->vendor == VEN_INTEL) {
if (dev->regs.glbctl & 0x01) {
smi_line = 1;
/* Clear bit 16 of GLBCTL. */
dev->regs.glbctl &= ~0x00010000;
}
} else if (dev->vendor == VEN_SMC) {
if (dev->regs.glbctl & 0x01)
smi_line = 1;
}
smi_line = 1;
/* Clear bit 16 of GLBCTL. */
dev->regs.glbctl &= ~0x00010000;
} else if (dev->vendor == VEN_SMC)
smi_line = 1;
}
static void
acpi_raise_smi(void *priv)
{
acpi_t *dev = (acpi_t *) priv;
if ((dev->vendor == VEN_INTEL) && !(dev->regs.glbctl & 0x00010000))
return;
if (dev->regs.glbctl & 0x01)
acpi_raise_smi_common(dev);
}
@@ -449,7 +458,7 @@ acpi_reg_write_common_regs(int size, uint16_t addr, uint8_t val, void *p)
switch (sus_typ) {
case 0:
/* Soft power off. */
quited = 1;
plat_power_off();
break;
case 1:
/* Suspend to RAM. */
@@ -1081,6 +1090,14 @@ acpi_set_irq_line(acpi_t *dev, int irq_line)
}
void
acpi_set_gpireg2_default(acpi_t *dev, uint8_t gpireg2_default)
{
dev->gpireg2_default = gpireg2_default;
dev->regs.gpireg[2] = dev->gpireg2_default;
}
void
acpi_set_nvr(acpi_t *dev, nvr_t *nvr)
{
@@ -1093,7 +1110,7 @@ acpi_apm_out(uint16_t port, uint8_t val, void *p)
{
acpi_t *dev = (acpi_t *) p;
acpi_log("[%04X:%08X] APM write: %04X = %02X (BX = %04X, CX = %04X)\n", CS, cpu_state.pc, port, val, BX, CX);
acpi_log("[%04X:%08X] APM write: %04X = %02X (AX = %04X, BX = %04X, CX = %04X)\n", CS, cpu_state.pc, port, val, AX, BX, CX);
port &= 0x0001;
@@ -1102,7 +1119,7 @@ acpi_apm_out(uint16_t port, uint8_t val, void *p)
if (dev->apm->do_smi) {
if (dev->vendor == VEN_INTEL)
dev->regs.glbsts |= 0x20;
acpi_raise_smi(dev);
acpi_raise_smi_common(dev);
}
} else
dev->apm->stat = val;
@@ -1141,7 +1158,7 @@ acpi_reset(void *priv)
- Bit 2: 80-conductor cable on primary IDE channel (active low)
Gigabyte GA-686BX:
- Bit 1: CMOS battery low (active high) */
dev->regs.gpireg[2] = 0xf1;
dev->regs.gpireg[2] = dev->gpireg2_default;
for (i = 0; i < 4; i++)
dev->regs.gporeg[i] = dev->gporeg_default[i];
if (dev->vendor == VEN_VIA_596B) {
@@ -1212,7 +1229,7 @@ const device_t acpi_intel_device =
acpi_init,
acpi_close,
acpi_reset,
NULL,
{ NULL },
acpi_speed_changed,
NULL,
NULL
@@ -1227,7 +1244,7 @@ const device_t acpi_via_device =
acpi_init,
acpi_close,
acpi_reset,
NULL,
{ NULL },
acpi_speed_changed,
NULL,
NULL
@@ -1242,7 +1259,7 @@ const device_t acpi_via_596b_device =
acpi_init,
acpi_close,
acpi_reset,
NULL,
{ NULL },
acpi_speed_changed,
NULL,
NULL
@@ -1257,7 +1274,7 @@ const device_t acpi_smc_device =
acpi_init,
acpi_close,
acpi_reset,
NULL,
{ NULL },
acpi_speed_changed,
NULL,
NULL

6
src/apm.c
View File

@@ -131,7 +131,7 @@ const device_t apm_device =
apm_init,
apm_close,
NULL,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -146,7 +146,7 @@ const device_t apm_pci_device =
apm_init,
apm_close,
apm_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -161,7 +161,7 @@ const device_t apm_pci_acpi_device =
apm_init,
apm_close,
apm_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

2
src/chipset/acc2168.c
View File

@@ -106,6 +106,6 @@ const device_t acc2168_device = {
0,
0,
acc2168_init, acc2168_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/ali1429.c
View File

@@ -189,6 +189,6 @@ const device_t ali1429_device = {
0,
0,
ali1429_init, ali1429_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

4
src/chipset/ali1489.c
View File

@@ -512,7 +512,7 @@ ali1489_init(const device_t *info)
io_sethandler(0x0fc, 0x0001, ali1489_ide_read, NULL, NULL, ali1489_ide_write, NULL, NULL, dev);
/* Dummy M1489 PCI device */
pci_add_card(0, ali1489_pci_read, ali1489_pci_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1489_pci_read, ali1489_pci_write, dev);
ide_pri_disable();
ide_sec_disable();
@@ -540,7 +540,7 @@ const device_t ali1489_device = {
ali1489_init,
ali1489_close,
ali1489_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

2
src/chipset/ali6117.c
View File

@@ -336,7 +336,7 @@ const device_t ali6117d_device =
ali6117_init,
ali6117_close,
ali6117_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

2
src/chipset/cs4031.c
View File

@@ -195,6 +195,6 @@ const device_t cs4031_device = {
0,
0,
cs4031_init, cs4031_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/cs8230.c
View File

@@ -155,6 +155,6 @@ const device_t cs8230_device = {
0,
0,
cs8230_init, cs8230_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

8
src/chipset/headland.c
View File

@@ -694,7 +694,7 @@ const device_t headland_gc10x_device = {
0,
0,
headland_init, headland_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -703,7 +703,7 @@ const device_t headland_ht18a_device = {
0,
1,
headland_init, headland_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -712,7 +712,7 @@ const device_t headland_ht18b_device = {
0,
2,
headland_init, headland_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -721,6 +721,6 @@ const device_t headland_ht18c_device = {
0,
8,
headland_init, headland_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/intel_420ex.c
View File

@@ -546,7 +546,7 @@ const device_t i420ex_device =
i420ex_init,
i420ex_close,
i420ex_reset,
NULL,
{ NULL },
i420ex_speed_changed,
NULL,
NULL

463
src/chipset/intel_4x0.c
View File

File diff suppressed because it is too large Load Diff

2
src/chipset/intel_82335.c
View File

@@ -206,6 +206,6 @@ const device_t intel_82335_device = {
0,
0,
intel_82335_init, intel_82335_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

48
src/chipset/intel_piix.c
View File

@@ -539,6 +539,9 @@ piix_write(int func, int addr, uint8_t val, void *priv)
fregs[addr] = (fregs[addr] & 0x8c) | (val & 0x73);
else if (dev->type == 5)
fregs[addr] = val & 0x7f;
if (dev->type >= 4)
alt_access = !!(val & 0x20);
break;
case 0xb1:
if (dev->type > 3)
@@ -1069,7 +1072,7 @@ piix_reset_hard(piix_t *dev)
if (dev->type == 4)
fregs[0x08] = dev->rev & 0x07;
else if (dev->type < 4)
fregs[0x08] = dev->rev;
fregs[0x08] = 0x01;
else
fregs[0x08] = 0x02;
if (dev->type > 4)
@@ -1096,7 +1099,7 @@ piix_reset_hard(piix_t *dev)
if (dev->type > 4)
fregs[0x08] = 0x02;
else
fregs[0x08] = (dev->rev & 0x08) ? 0x02 : (dev->rev & 0x07);
fregs[0x08] = (dev->rev & 0x08) ? 0x02 : 0x01 /*(dev->rev & 0x07)*/;
fregs[0x0a] = 0x80; fregs[0x0b] = 0x06;
/* NOTE: The Specification Update says this should default to 0x00 and be read-only. */
#ifdef WRONG_SPEC
@@ -1192,6 +1195,32 @@ piix_reset(void *p)
ide_pri_disable();
ide_sec_disable();
if (dev->type >= 3) {
piix_write(2, 0x04, 0x00, p);
if (dev->type == 5) {
piix_write(2, 0x10, 0x00, p);
piix_write(2, 0x11, 0x00, p);
piix_write(2, 0x12, 0x00, p);
piix_write(2, 0x13, 0x00, p);
} else {
piix_write(2, 0x20, 0x01, p);
piix_write(2, 0x21, 0x00, p);
piix_write(2, 0x22, 0x00, p);
piix_write(2, 0x23, 0x00, p);
}
}
if (dev->type >= 4) {
piix_write(0, 0xb0, (is_pentium) ? 0x00 : 0x04, p);
piix_write(3, 0x40, 0x01, p);
piix_write(3, 0x41, 0x00, p);
piix_write(3, 0x5b, 0x00, p);
piix_write(3, 0x80, 0x00, p);
piix_write(3, 0x90, 0x01, p);
piix_write(3, 0x91, 0x00, p);
piix_write(3, 0xd2, 0x00, p);
}
}
@@ -1253,6 +1282,7 @@ static void
dev->acpi = device_add(&acpi_intel_device);
acpi_set_slot(dev->acpi, dev->pci_slot);
acpi_set_nvr(dev->acpi, dev->nvr);
acpi_set_gpireg2_default(dev->acpi, (dev->type > 4) ? 0xf1 : 0xfd);
dev->ddma = device_add(&ddma_device);
} else
@@ -1283,7 +1313,9 @@ static void
if (dev->type < 3)
pci_enable_mirq(1);
dev->readout_regs[0] = 0xff;
dev->readout_regs[1] = 0x40;
dev->readout_regs[2] = 0xff;
/* Port E1 register 01 (TODO: Find how multipliers > 3.0 are defined):
@@ -1356,7 +1388,7 @@ const device_t piix_device =
piix_init,
piix_close,
piix_reset,
NULL,
{ NULL },
piix_speed_changed,
NULL,
NULL
@@ -1370,7 +1402,7 @@ const device_t piix_rev02_device =
piix_init,
piix_close,
piix_reset,
NULL,
{ NULL },
piix_speed_changed,
NULL,
NULL
@@ -1384,7 +1416,7 @@ const device_t piix3_device =
piix_init,
piix_close,
piix_reset,
NULL,
{ NULL },
piix_speed_changed,
NULL,
NULL
@@ -1398,7 +1430,7 @@ const device_t piix4_device =
piix_init,
piix_close,
piix_reset,
NULL,
{ NULL },
piix_speed_changed,
NULL,
NULL
@@ -1412,7 +1444,7 @@ const device_t piix4e_device =
piix_init,
piix_close,
piix_reset,
NULL,
{ NULL },
piix_speed_changed,
NULL,
NULL
@@ -1426,7 +1458,7 @@ const device_t slc90e66_device =
piix_init,
piix_close,
piix_reset,
NULL,
{ NULL },
piix_speed_changed,
NULL,
NULL

5
src/chipset/intel_sio.c
View File

@@ -218,6 +218,7 @@ sio_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x60: case 0x61: case 0x62: case 0x63:
if (dev->id == 0x03) {
pclog("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val);
sio_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val);
dev->regs[addr] = val & 0x8f;
if (val & 0x80)
@@ -551,7 +552,7 @@ const device_t sio_device =
sio_init,
sio_close,
sio_reset,
NULL,
{ NULL },
sio_speed_changed,
NULL,
NULL
@@ -566,7 +567,7 @@ const device_t sio_zb_device =
sio_init,
sio_close,
sio_reset,
NULL,
{ NULL },
sio_speed_changed,
NULL,
NULL

2
src/chipset/neat.c
View File

@@ -856,6 +856,6 @@ const device_t neat_device = {
0,
0,
neat_init, neat_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/opti283.c
View File

@@ -166,6 +166,6 @@ const device_t opti283_device = {
0,
0,
opti283_init, opti283_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/opti291.c
View File

@@ -151,6 +151,6 @@ const device_t opti291_device = {
0,
0,
opti291_init, opti291_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

4
src/chipset/opti495.c
View File

@@ -246,7 +246,7 @@ const device_t opti493_device = {
0,
0,
opti495_init, opti495_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -256,6 +256,6 @@ const device_t opti495_device = {
0,
1,
opti495_init, opti495_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/opti5x7.c
View File

@@ -171,6 +171,6 @@ const device_t opti5x7_device = {
0,
0,
opti5x7_init, opti5x7_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

4
src/chipset/opti895.c
View File

@@ -273,7 +273,7 @@ const device_t opti802g_device = {
0,
0,
opti895_init, opti895_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -283,6 +283,6 @@ const device_t opti895_device = {
0,
0,
opti895_init, opti895_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/scamp.c
View File

@@ -770,6 +770,6 @@ const device_t vlsi_scamp_device = {
0,
0,
scamp_init, scamp_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

6
src/chipset/scat.c
View File

@@ -1600,7 +1600,7 @@ const device_t scat_device = {
0,
0,
scat_init, scat_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -1609,7 +1609,7 @@ const device_t scat_4_device = {
0,
4,
scat_init, scat_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -1618,6 +1618,6 @@ const device_t scat_sx_device = {
0,
32,
scat_init, scat_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/sis_85c310.c
View File

@@ -145,6 +145,6 @@ const device_t rabbit_device = {
0,
0,
rabbit_init, rabbit_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

4
src/chipset/sis_85c496.c
View File

@@ -618,7 +618,7 @@ const device_t sis_85c496_device =
sis_85c496_init,
sis_85c496_close,
sis_85c496_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -633,7 +633,7 @@ const device_t sis_85c496_ls486e_device =
sis_85c496_init,
sis_85c496_close,
sis_85c496_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

8
src/chipset/sis_85c4xx.c
View File

@@ -419,7 +419,7 @@ const device_t sis_85c401_device = {
0,
0x060,
sis_85c4xx_init, sis_85c4xx_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -428,7 +428,7 @@ const device_t sis_85c460_device = {
0,
0x050,
sis_85c4xx_init, sis_85c4xx_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -438,7 +438,7 @@ const device_t sis_85c461_device = {
0,
0x050,
sis_85c4xx_init, sis_85c4xx_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -447,6 +447,6 @@ const device_t sis_85c471_device = {
0,
0x150,
sis_85c4xx_init, sis_85c4xx_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/sis_85c50x.c
View File

@@ -434,7 +434,7 @@ const device_t sis_85c50x_device =
sis_85c50x_init,
sis_85c50x_close,
sis_85c50x_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

20
src/chipset/stpc.c
View File

@@ -910,13 +910,13 @@ stpc_init(const device_t *info)
dev->local = info->local;
pci_add_card(0x0B, stpc_nb_read, stpc_nb_write, dev);
dev->ide_slot = pci_add_card(0x0C, stpc_isab_read, stpc_isab_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, stpc_nb_read, stpc_nb_write, dev);
dev->ide_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_isab_read, stpc_isab_write, dev);
if (dev->local & STPC_IDE_ATLAS)
dev->ide_slot = pci_add_card(0x0D, stpc_ide_read, stpc_ide_write, dev);
dev->ide_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_ide_read, stpc_ide_write, dev);
if (dev->local & STPC_USB) {
dev->usb = device_add(&usb_device);
pci_add_card(0x0E, stpc_usb_read, stpc_usb_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_usb_read, stpc_usb_write, dev);
}
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
@@ -1096,7 +1096,7 @@ const device_t stpc_client_device =
stpc_init,
stpc_close,
stpc_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -1110,7 +1110,7 @@ const device_t stpc_consumer2_device =
stpc_init,
stpc_close,
stpc_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -1124,7 +1124,7 @@ const device_t stpc_elite_device =
stpc_init,
stpc_close,
stpc_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -1138,7 +1138,7 @@ const device_t stpc_atlas_device =
stpc_init,
stpc_close,
stpc_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -1153,7 +1153,7 @@ const device_t stpc_serial_device =
stpc_serial_init,
stpc_serial_close,
NULL,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -1167,7 +1167,7 @@ const device_t stpc_lpt_device =
stpc_lpt_init,
stpc_lpt_close,
stpc_lpt_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

2
src/chipset/umc491.c
View File

@@ -174,6 +174,6 @@ const device_t umc491_device = {
0,
0,
umc491_init, umc491_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

16
src/chipset/via_apollo.c
View File

@@ -715,7 +715,7 @@ const device_t via_vpx_device =
via_apollo_init,
via_apollo_close,
via_apollo_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -729,7 +729,7 @@ const device_t amd640_device =
via_apollo_init,
via_apollo_close,
via_apollo_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -743,7 +743,7 @@ const device_t via_vp3_device =
via_apollo_init,
via_apollo_close,
via_apollo_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -757,7 +757,7 @@ const device_t via_mvp3_device =
via_apollo_init,
via_apollo_close,
via_apollo_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -770,7 +770,7 @@ const device_t via_apro_device = {
via_apollo_init,
via_apollo_close,
via_apollo_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -783,7 +783,7 @@ const device_t via_apro133_device = {
via_apollo_init,
via_apollo_close,
via_apollo_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -796,7 +796,7 @@ const device_t via_apro133a_device = {
via_apollo_init,
via_apollo_close,
via_apollo_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -809,7 +809,7 @@ const device_t via_vt8601_device = {
via_apollo_init,
via_apollo_close,
via_apollo_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

10
src/chipset/via_pipc.c
View File

@@ -923,7 +923,7 @@ const device_t via_vt82c586b_device =
pipc_init,
pipc_close,
pipc_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -937,7 +937,7 @@ const device_t via_vt82c596_device =
pipc_init,
pipc_close,
pipc_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -952,7 +952,7 @@ const device_t via_vt82c596b_device =
pipc_init,
pipc_close,
pipc_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -967,7 +967,7 @@ const device_t via_vt82c686a_device =
pipc_init,
pipc_close,
pipc_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -982,7 +982,7 @@ const device_t via_vt82c686b_device =
pipc_init,
pipc_close,
pipc_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

4
src/chipset/via_vt82c49x.c
View File

@@ -311,7 +311,7 @@ const device_t via_vt82c49x_device = {
0,
0,
vt82c49x_init, vt82c49x_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -321,6 +321,6 @@ const device_t via_vt82c49x_ide_device = {
0,
1,
vt82c49x_init, vt82c49x_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

4
src/chipset/via_vt82c505.c
View File

@@ -124,7 +124,7 @@ vt82c505_init(const device_t *info)
vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
memset(dev, 0, sizeof(vt82c505_t));
pci_add_card(0, vt82c505_read, vt82c505_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, vt82c505_read, vt82c505_write, dev);
dev->pci_conf[0x00] = 0x06;
dev->pci_conf[0x01] = 0x11;
@@ -152,7 +152,7 @@ const device_t via_vt82c505_device = {
vt82c505_init,
vt82c505_close,
vt82c505_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

2
src/chipset/vl82c480.c
View File

@@ -183,6 +183,6 @@ const device_t vl82c480_device = {
0,
0,
vl82c480_init, vl82c480_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/chipset/wd76c10.c
View File

@@ -287,6 +287,6 @@ const device_t wd76c10_device = {
0,
0,
wd76c10_init, wd76c10_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/codegen_new/codegen.c
View File

@@ -32,7 +32,7 @@ int codegen_get_instruction_uop(codeblock_t *block, uint32_t pc, int *first_inst
{
int c;
for (c = 0; c < block->ins; c++)
for (c = 0; c <= block->ins; c++)
{
if (codegen_instructions[c].pc == pc)
{

2
src/codegen_new/codegen_backend_x86-64.h
View File

@@ -10,3 +10,5 @@
#define HASH(l) ((l) & 0x1ffff)
#define BLOCK_MAX 0x3c0
#define CODEGEN_BACKEND_HAS_MOV_IMM

44
src/codegen_new/codegen_backend_x86-64_ops.c
View File

@@ -521,6 +521,26 @@ void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
codegen_addbyte(block, imm_data);
}
}
void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data)
{
int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
if (offset >= -128 && offset < 127)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte4(block, 0x66, 0xc7, 0x45, offset); /*MOV offset[RBP], imm_data*/
codegen_addword(block, imm_data);
}
else
{
if ((uintptr_t)p >> 32)
fatal("host_x86_MOV32_ABS_IMM - out of range %p\n", p);
codegen_alloc_bytes(block, 10);
codegen_addbyte4(block, 0x66, 0xc7, 0x04, 0x25); /*MOV p, imm_data*/
codegen_addlong(block, (uint32_t)(uintptr_t)p);
codegen_addword(block, imm_data);
}
}
void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
{
int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
@@ -945,6 +965,30 @@ void host_x86_MOV64_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset
fatal("MOV64_BASE_OFFSET_REG - offset %i\n", offset);
}
void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data)
{
if (base_reg & 8)
fatal("host_x86_MOV32_BASE_OFFSET_IMM reg & 8\n");
if (offset >= -128 && offset < 127)
{
if (base_reg == REG_RSP)
{
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0xc7, 0x40 | base_reg, 0x24, offset);
codegen_addlong(block, imm_data);
}
else
{
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0xc7, 0x40 | base_reg, offset);
codegen_addlong(block, imm_data);
}
}
else
fatal("MOV32_BASE_OFFSET_IMM - offset %i\n", offset);
}
void host_x86_MOV8_REG_IMM(codeblock_t *block, int reg, uint16_t imm_data)
{
if (reg >= 8)

3
src/codegen_new/codegen_backend_x86-64_ops.h
View File

@@ -56,6 +56,7 @@ void host_x86_LEA_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int sr
void host_x86_LEA_REG_REG_SHIFT(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b, int shift);
void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data);
void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
void host_x86_MOV8_ABS_REG(codeblock_t *block, void *p, int src_reg);
@@ -72,6 +73,8 @@ void host_x86_MOV32_BASE_INDEX_REG(codeblock_t *block, int dst_reg, int base_reg
void host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg);
void host_x86_MOV64_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg);
void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data);
void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p);

17
src/codegen_new/codegen_backend_x86-64_uops.c
View File

@@ -3145,4 +3145,21 @@ void codegen_set_jump_dest(codeblock_t *block, void *p)
*(uint32_t *)p = (uintptr_t)&block_write_data[block_pos] - ((uintptr_t)p + 4);
}
void codegen_direct_write_8_imm(codeblock_t *block, void *p, uint8_t imm_data)
{
host_x86_MOV8_ABS_IMM(block, p, imm_data);
}
void codegen_direct_write_16_imm(codeblock_t *block, void *p, uint16_t imm_data)
{
host_x86_MOV16_ABS_IMM(block, p, imm_data);
}
void codegen_direct_write_32_imm(codeblock_t *block, void *p, uint32_t imm_data)
{
host_x86_MOV32_ABS_IMM(block, p, imm_data);
}
void codegen_direct_write_32_imm_stack(codeblock_t *block, int stack_offset, uint32_t imm_data)
{
host_x86_MOV32_BASE_OFFSET_IMM(block, REG_ESP, stack_offset, imm_data);
}
#endif

2
src/codegen_new/codegen_backend_x86.h
View File

@@ -10,3 +10,5 @@
#define HASH(l) ((l) & 0x1ffff)
#define BLOCK_MAX 0x3c0
#define CODEGEN_BACKEND_HAS_MOV_IMM

39
src/codegen_new/codegen_backend_x86_ops.c
View File

@@ -449,6 +449,24 @@ void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
codegen_addbyte(block, imm_data);
}
}
void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data)
{
int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
if (offset >= -128 && offset < 127)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte4(block, 0x66, 0xc7, 0x45, offset); /*MOV offset[EBP], imm_data*/
codegen_addword(block, imm_data);
}
else
{
codegen_alloc_bytes(block, 9);
codegen_addbyte3(block, 0x66, 0xc7, 0x05); /*MOV p, imm_data*/
codegen_addlong(block, (uint32_t)p);
codegen_addword(block, imm_data);
}
}
void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
{
int offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
@@ -705,6 +723,27 @@ void host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset
fatal("MOV32_BASE_OFFSET_REG - offset %i\n", offset);
}
void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data)
{
if (offset >= -128 && offset < 127)
{
if (base_reg == REG_ESP)
{
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0xc7, 0x40 | base_reg, 0x24, offset);
codegen_addlong(block, imm_data);
}
else
{
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0xc7, 0x40 | base_reg, offset);
codegen_addlong(block, imm_data);
}
}
else
fatal("MOV32_BASE_OFFSET_IMM - offset %i\n", offset);
}
void host_x86_MOV8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
codegen_alloc_bytes(block, 2);

3
src/codegen_new/codegen_backend_x86_ops.h
View File

@@ -60,6 +60,7 @@ void host_x86_LEA_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int sr
void host_x86_LEA_REG_REG_SHIFT(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b, int shift);
void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data);
void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
void host_x86_MOV8_ABS_REG(codeblock_t *block, void *p, int src_reg);
@@ -75,6 +76,8 @@ void host_x86_MOV32_BASE_INDEX_REG(codeblock_t *block, int base_reg, int idx_reg
void host_x86_MOV16_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int dst_reg);
void host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int dst_reg);
void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data);
void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p);

23
src/codegen_new/codegen_backend_x86_uops.c
View File

@@ -2643,6 +2643,11 @@ static int codegen_STORE_PTR_IMM_8(codeblock_t *block, uop_t *uop)
host_x86_MOV8_ABS_IMM(block, uop->p, uop->imm_data);
return 0;
}
static int codegen_STORE_PTR_IMM_16(codeblock_t *block, uop_t *uop)
{
host_x86_MOV16_ABS_IMM(block, uop->p, uop->imm_data);
return 0;
}
static int codegen_SUB(codeblock_t *block, uop_t *uop)
{
@@ -2838,6 +2843,7 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_STORE_P_IMM & UOP_MASK] = codegen_STORE_PTR_IMM,
[UOP_STORE_P_IMM_8 & UOP_MASK] = codegen_STORE_PTR_IMM_8,
[UOP_STORE_P_IMM_16 & UOP_MASK] = codegen_STORE_PTR_IMM_16,
[UOP_MEM_LOAD_ABS & UOP_MASK] = codegen_MEM_LOAD_ABS,
[UOP_MEM_LOAD_REG & UOP_MASK] = codegen_MEM_LOAD_REG,
@@ -3138,4 +3144,21 @@ void codegen_set_jump_dest(codeblock_t *block, void *p)
*(uint32_t *)p = (uintptr_t)&block_write_data[block_pos] - ((uintptr_t)p + 4);
}
void codegen_direct_write_8_imm(codeblock_t *block, void *p, uint8_t imm_data)
{
host_x86_MOV8_ABS_IMM(block, p, imm_data);
}
void codegen_direct_write_16_imm(codeblock_t *block, void *p, uint16_t imm_data)
{
host_x86_MOV16_ABS_IMM(block, p, imm_data);
}
void codegen_direct_write_32_imm(codeblock_t *block, void *p, uint32_t imm_data)
{
host_x86_MOV32_ABS_IMM(block, p, imm_data);
}
void codegen_direct_write_32_imm_stack(codeblock_t *block, int stack_offset, uint32_t imm_data)
{
host_x86_MOV32_BASE_OFFSET_IMM(block, REG_ESP, stack_offset, imm_data);
}
#endif

44
src/codegen_new/codegen_block.c
View File

@@ -67,8 +67,10 @@ static int dirty_list_size = 0;
static void block_free_list_add(codeblock_t *block)
{
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
fatal("block_free_list_add: block=%p in dirty list\n", block);
#endif
if (block_free_list)
block->next = block_free_list;
else
@@ -79,8 +81,10 @@ static void block_free_list_add(codeblock_t *block)
static void block_dirty_list_add(codeblock_t *block)
{
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
fatal("block_dirty_list_add: block=%p already in dirty list\n", block);
#endif
if (block_dirty_list_head != BLOCK_INVALID)
{
codeblock_t *old_head = &codeblock[block_dirty_list_head];
@@ -102,12 +106,14 @@ static void block_dirty_list_add(codeblock_t *block)
/*Evict oldest block to the free list*/
codeblock_t *evict_block = &codeblock[block_dirty_list_tail];
#ifndef RELEASE_BUILD
if (!(evict_block->flags & CODEBLOCK_IN_DIRTY_LIST))
fatal("block_dirty_list_add: evict_block=%p %x %x not in dirty list\n", evict_block, evict_block->phys, evict_block->flags);
if (!block_dirty_list_tail)
fatal("block_dirty_list_add - !block_dirty_list_tail\n");
if (evict_block->prev == BLOCK_INVALID)
fatal("block_dirty_list_add - evict_block->prev == BLOCK_INVALID\n");
#endif
block_dirty_list_tail = evict_block->prev;
codeblock[evict_block->prev].next = BLOCK_INVALID;
@@ -123,8 +129,10 @@ static void block_dirty_list_remove(codeblock_t *block)
codeblock_t *prev_block = &codeblock[block->prev];
codeblock_t *next_block = &codeblock[block->next];
#ifndef RELEASE_BUILD
if (!(block->flags & CODEBLOCK_IN_DIRTY_LIST))
fatal("block_dirty_list_remove: block=%p not in dirty list\n", block);
#endif
/*Is block head of list*/
if (block->prev == BLOCK_INVALID)
@@ -139,8 +147,10 @@ static void block_dirty_list_remove(codeblock_t *block)
next_block->prev = block->prev;
dirty_list_size--;
#ifndef RELEASE_BUILD
if (dirty_list_size < 0)
fatal("remove - dirty_list_size < 0!\n");
#endif
block->flags &= ~CODEBLOCK_IN_DIRTY_LIST;
}
@@ -170,9 +180,10 @@ static codeblock_t *block_free_list_get()
/*Free list is empty, check the dirty list*/
if (block_dirty_list_tail)
{
#ifndef RELEASE_BUILD
if (dirty_list_size <= 0)
fatal("get - dirty_list_size <= 0!\n");
#endif
/*Reuse oldest block*/
block = &codeblock[block_dirty_list_tail];
@@ -296,8 +307,10 @@ static void add_to_block_list(codeblock_t *block)
uint16_t block_prev_nr = pages[block->phys >> 12].block;
uint16_t block_nr = get_block_nr(block);
#ifndef RELEASE_BUILD
if (!block->page_mask)
fatal("add_to_block_list - mask = 0 %llx %llx\n", block->page_mask,block->page_mask2);
#endif
if (block_prev_nr)
{
@@ -313,8 +326,10 @@ static void add_to_block_list(codeblock_t *block)
if (block->next)
{
#ifndef RELEASE_BUILD
if (codeblock[block->next].pc == BLOCK_PC_INVALID)
fatal("block->next->pc=BLOCK_PC_INVALID %p %p %x %x\n", (void *)&codeblock[block->next], (void *)codeblock, block_current, block_pos);
#endif
}
if (block->page_mask2)
@@ -341,9 +356,10 @@ static void remove_from_block_list(codeblock_t *block, uint32_t pc)
{
if (!block->page_mask)
return;
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
fatal("remove_from_block_list: in dirty list\n");
#endif
if (block->prev)
{
codeblock[block->prev].next = block->next;
@@ -361,8 +377,10 @@ static void remove_from_block_list(codeblock_t *block, uint32_t pc)
if (!(block->flags & CODEBLOCK_HAS_PAGE2))
{
#ifndef RELEASE_BUILD
if (block->prev_2 || block->next_2)
fatal("Invalid block_2 %x %p %08x\n", block->flags, block, block->phys);
#endif
return;
}
block->flags &= ~CODEBLOCK_HAS_PAGE2;
@@ -387,11 +405,12 @@ static void invalidate_block(codeblock_t *block)
{
uint32_t old_pc = block->pc;
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
fatal("invalidate_block: already in dirty list\n");
if (block->pc == BLOCK_PC_INVALID)
fatal("Invalidating deleted block\n");
#endif
remove_from_block_list(block, old_pc);
block_dirty_list_add(block);
if (block->head_mem_block)
@@ -406,8 +425,10 @@ static void delete_block(codeblock_t *block)
if (block == &codeblock[codeblock_hash[HASH(block->phys)]])
codeblock_hash[HASH(block->phys)] = BLOCK_INVALID;
#ifndef RELEASE_BUILD
if (block->pc == BLOCK_PC_INVALID)
fatal("Deleting deleted block\n");
#endif
block->pc = BLOCK_PC_INVALID;
codeblock_tree_delete(block);
@@ -426,8 +447,10 @@ static void delete_dirty_block(codeblock_t *block)
if (block == &codeblock[codeblock_hash[HASH(block->phys)]])
codeblock_hash[HASH(block->phys)] = BLOCK_INVALID;
#ifndef RELEASE_BUILD
if (block->pc == BLOCK_PC_INVALID)
fatal("Deleting deleted block\n");
#endif
block->pc = BLOCK_PC_INVALID;
codeblock_tree_delete(block);
@@ -475,8 +498,10 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
{
invalidate_block(block);
}
#ifndef RELEASE_BUILD
if (block_nr == next_block)
fatal("Broken 1\n");
#endif
block_nr = next_block;
}
@@ -491,8 +516,10 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
{
invalidate_block(block);
}
#ifndef RELEASE_BUILD
if (block_nr == next_block)
fatal("Broken 2\n");
#endif
block_nr = next_block;
}
@@ -520,8 +547,10 @@ void codegen_block_init(uint32_t phys_addr)
if (!page->block)
mem_flush_write_page(phys_addr, cs+cpu_state.pc);
block = block_free_list_get();
#ifndef RELEASE_BUILD
if (!block)
fatal("codegen_block_init: block_free_list_get() returned NULL\n");
#endif
block_current = get_block_nr(block);
block_num = HASH(phys_addr);
@@ -560,8 +589,10 @@ void codegen_block_start_recompile(codeblock_t *block)
block_num = HASH(block->phys);
block_current = get_block_nr(block);//block->pnt;
#ifndef RELEASE_BUILD
if (block->pc != cs + cpu_state.pc || (block->flags & CODEBLOCK_WAS_RECOMPILED))
fatal("Recompile to used block!\n");
#endif
block->head_mem_block = codegen_allocator_allocate(NULL, block_current);
block->data = codeblock_allocator_get_ptr(block->head_mem_block);
@@ -668,6 +699,7 @@ void codegen_block_generate_end_mask_recompile()
if (!pages[block->phys_2 >> 12].block_2)
mem_flush_write_page(block->phys_2, codegen_endpc);
#ifndef RELEASE_BUILD
if (!block->page_mask2)
fatal("!page_mask2\n");
if (block->next_2)
@@ -675,6 +707,7 @@ void codegen_block_generate_end_mask_recompile()
if (codeblock[block->next_2].pc == BLOCK_PC_INVALID)
fatal("block->next_2->pc=BLOCK_PC_INVALID %p\n", (void *)&codeblock[block->next_2]);
}
#endif
}
else
{
@@ -695,8 +728,10 @@ void codegen_block_generate_end_mask_mark()
uint32_t end_pc;
page_t *p;
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_BYTE_MASK)
fatal("codegen_block_generate_end_mask2() - BYTE_MASK\n");
#endif
block->page_mask = 0;
start_pc = (block->pc & 0xfff) & ~63;
@@ -741,6 +776,7 @@ void codegen_block_generate_end_mask_mark()
if (!pages[block->phys_2 >> 12].block_2)
mem_flush_write_page(block->phys_2, codegen_endpc);
#ifndef RELEASE_BUILD
if (!block->page_mask2)
fatal("!page_mask2\n");
if (block->next_2)
@@ -748,7 +784,7 @@ void codegen_block_generate_end_mask_mark()
if (codeblock[block->next_2].pc == BLOCK_PC_INVALID)
fatal("block->next_2->pc=BLOCK_PC_INVALID %p\n", (void *)&codeblock[block->next_2]);
}
#endif
block->dirty_mask2 = &page_2->dirty_mask;
}
else

78
src/codegen_new/codegen_ir.c
View File

@@ -71,8 +71,10 @@ void codegen_ir_compile(ir_data_t *ir, codeblock_t *block)
for (unroll_count = 1; unroll_count < codegen_unroll_count; unroll_count++)
{
int offset = ir->wr_pos - codegen_unroll_start;
// pclog("Unroll from %i to %i, offset %i - iteration %i\n", codegen_unroll_start, ir->wr_pos, offset, unroll_count);
for (c = codegen_unroll_start; c < unroll_end; c++)
{
// pclog(" Duplicate uop %i\n", c);
duplicate_uop(ir, &ir->uops[c], offset);
}
}
@@ -87,6 +89,8 @@ void codegen_ir_compile(ir_data_t *ir, codeblock_t *block)
for (c = 0; c < ir->wr_pos; c++)
{
uop_t *uop = &ir->uops[c];
// pclog("uOP %i : %08x\n", c, uop->type);
if (uop->type & UOP_TYPE_BARRIER)
codegen_reg_flush_invalidate(ir, block);
@@ -105,37 +109,61 @@ void codegen_ir_compile(ir_data_t *ir, codeblock_t *block)
if ((uop->type & UOP_MASK) == UOP_INVALID)
continue;
if (uop->type & UOP_TYPE_PARAMS_REGS)
#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
if ((uop->type & UOP_MASK) == (UOP_MOV_IMM & UOP_MASK) && reg_is_native_size(uop->dest_reg_a) && !codegen_reg_is_loaded(uop->dest_reg_a) && reg_version[IREG_GET_REG(uop->dest_reg_a.reg)][uop->dest_reg_a.version].refcount <= 0)
{
codegen_reg_alloc_register(uop->dest_reg_a, uop->src_reg_a, uop->src_reg_b, uop->src_reg_c);
if (uop->src_reg_a.reg != IREG_INVALID)
{
uop->src_reg_a_real = codegen_reg_alloc_read_reg(block, uop->src_reg_a, NULL);
}
if (uop->src_reg_b.reg != IREG_INVALID)
{
uop->src_reg_b_real = codegen_reg_alloc_read_reg(block, uop->src_reg_b, NULL);
}
if (uop->src_reg_c.reg != IREG_INVALID)
{
uop->src_reg_c_real = codegen_reg_alloc_read_reg(block, uop->src_reg_c, NULL);
}
/*Special case for UOP_MOV_IMM - if destination not already in host register
and won't be used again then just store directly to memory*/
codegen_reg_write_imm(block, uop->dest_reg_a, uop->imm_data);
}
if (uop->type & UOP_TYPE_ORDER_BARRIER)
codegen_reg_flush(ir, block);
else
#endif
if ((uop->type & UOP_MASK) == (UOP_MOV & UOP_MASK) && reg_version[IREG_GET_REG(uop->src_reg_a.reg)][uop->src_reg_a.version].refcount <= 1 &&
reg_is_native_size(uop->src_reg_a) && reg_is_native_size(uop->dest_reg_a))
{
/*Special case for UOP_MOV - if source register won't be used again then
just rename it to dest register instead of moving*/
codegen_reg_alloc_register(invalid_ir_reg, uop->src_reg_a, invalid_ir_reg, invalid_ir_reg);
uop->src_reg_a_real = codegen_reg_alloc_read_reg(block, uop->src_reg_a, NULL);
codegen_reg_rename(block, uop->src_reg_a, uop->dest_reg_a);
if (uop->type & UOP_TYPE_ORDER_BARRIER)
codegen_reg_flush(ir, block);
}
else
{
if (uop->type & UOP_TYPE_PARAMS_REGS)
{
codegen_reg_alloc_register(uop->dest_reg_a, uop->src_reg_a, uop->src_reg_b, uop->src_reg_c);
if (uop->src_reg_a.reg != IREG_INVALID)
{
uop->src_reg_a_real = codegen_reg_alloc_read_reg(block, uop->src_reg_a, NULL);
}
if (uop->src_reg_b.reg != IREG_INVALID)
{
uop->src_reg_b_real = codegen_reg_alloc_read_reg(block, uop->src_reg_b, NULL);
}
if (uop->src_reg_c.reg != IREG_INVALID)
{
uop->src_reg_c_real = codegen_reg_alloc_read_reg(block, uop->src_reg_c, NULL);
}
}
if (uop->type & UOP_TYPE_PARAMS_REGS)
{
if (uop->dest_reg_a.reg != IREG_INVALID)
if (uop->type & UOP_TYPE_ORDER_BARRIER)
codegen_reg_flush(ir, block);
if (uop->type & UOP_TYPE_PARAMS_REGS)
{
uop->dest_reg_a_real = codegen_reg_alloc_write_reg(block, uop->dest_reg_a);
if (uop->dest_reg_a.reg != IREG_INVALID)
{
uop->dest_reg_a_real = codegen_reg_alloc_write_reg(block, uop->dest_reg_a);
}
}
#ifndef RELEASE_BUILD
if (!uop_handlers[uop->type & UOP_MASK])
fatal("!uop_handlers[uop->type & UOP_MASK] %08x\n", uop->type);
#endif
uop_handlers[uop->type & UOP_MASK](block, uop);
}
if (!uop_handlers[uop->type & UOP_MASK])
fatal("!uop_handlers[uop->type & UOP_MASK] %08x\n", uop->type);
uop_handlers[uop->type & UOP_MASK](block, uop);
if (uop->type & UOP_TYPE_JUMP)
{

7
src/codegen_new/codegen_ir_defs.h
View File

@@ -55,6 +55,7 @@
/*UOP_JMP_DEST - jump to ptr*/
#define UOP_JMP_DEST (UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x17 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_NOP_BARRIER (UOP_TYPE_BARRIER | 0x18)
#define UOP_STORE_P_IMM_16 (UOP_TYPE_PARAMS_IMM | 0x19)
#ifdef DEBUG_EXTRA
/*UOP_LOG_INSTR - log non-recompiled instruction in imm_data*/
@@ -765,6 +766,7 @@ static inline void uop_gen_reg_src2_pointer(uint32_t uop_type, ir_data_t *ir, in
#define uop_STORE_PTR_IMM(ir, p, imm) uop_gen_pointer_imm(UOP_STORE_P_IMM, ir, p, imm)
#define uop_STORE_PTR_IMM_8(ir, p, imm) uop_gen_pointer_imm(UOP_STORE_P_IMM_8, ir, p, imm)
#define uop_STORE_PTR_IMM_16(ir, p, imm) uop_gen_pointer_imm(UOP_STORE_P_IMM_16, ir, p, imm)
#define uop_TEST_JNS_DEST(ir, src_reg) uop_gen_reg_src1(UOP_TEST_JNS_DEST, ir, src_reg)
#define uop_TEST_JS_DEST(ir, src_reg) uop_gen_reg_src1(UOP_TEST_JS_DEST, ir, src_reg)
@@ -807,4 +809,9 @@ void codegen_direct_write_double_stack(codeblock_t *block, int stack_offset, int
void codegen_set_jump_dest(codeblock_t *block, void *p);
void codegen_direct_write_8_imm(codeblock_t *block, void *p, uint8_t imm_data);
void codegen_direct_write_16_imm(codeblock_t *block, void *p, uint16_t imm_data);
void codegen_direct_write_32_imm(codeblock_t *block, void *p, uint32_t imm_data);
void codegen_direct_write_32_imm_stack(codeblock_t *block, int stack_offset, uint32_t imm_data);
#endif

155
src/codegen_new/codegen_reg.c
View File

@@ -277,8 +277,10 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
switch (ireg_data[IREG_GET_REG(ir_reg.reg)].native_size)
{
case REG_WORD:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
fatal("codegen_reg_load - REG_WORD !REG_INTEGER\n");
#endif
if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
codegen_direct_read_16_stack(block, reg_set->reg_list[c].reg, (int)(uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
else
@@ -286,8 +288,10 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
break;
case REG_DWORD:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
fatal("codegen_reg_load - REG_DWORD !REG_INTEGER\n");
#endif
if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
codegen_direct_read_32_stack(block, reg_set->reg_list[c].reg, (int)(uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
else
@@ -295,8 +299,10 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
break;
case REG_QWORD:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_FP)
fatal("codegen_reg_load - REG_QWORD !REG_FP\n");
#endif
if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
codegen_direct_read_64_stack(block, reg_set->reg_list[c].reg, (int)(uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
else
@@ -304,8 +310,10 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
break;
case REG_POINTER:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
fatal("codegen_reg_load - REG_POINTER !REG_INTEGER\n");
#endif
if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
codegen_direct_read_pointer_stack(block, reg_set->reg_list[c].reg, (int)(uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
else
@@ -313,8 +321,10 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
break;
case REG_DOUBLE:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_FP)
fatal("codegen_reg_load - REG_DOUBLE !REG_FP\n");
#endif
if ((uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p < 256)
codegen_direct_read_double_stack(block, reg_set->reg_list[c].reg, (int)(uintptr_t)ireg_data[IREG_GET_REG(ir_reg.reg)].p);
else
@@ -322,8 +332,10 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
break;
case REG_FPU_ST_BYTE:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
fatal("codegen_reg_load - REG_FPU_ST_BYTE !REG_INTEGER\n");
#endif
if (block->flags & CODEBLOCK_STATIC_TOP)
codegen_direct_read_8(block, reg_set->reg_list[c].reg, &cpu_state.tag[ir_reg.reg & 7]);
else
@@ -331,8 +343,10 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
break;
case REG_FPU_ST_QWORD:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_FP)
fatal("codegen_reg_load - REG_FPU_ST_QWORD !REG_FP\n");
#endif
if (block->flags & CODEBLOCK_STATIC_TOP)
codegen_direct_read_64(block, reg_set->reg_list[c].reg, &cpu_state.MM[ir_reg.reg & 7]);
else
@@ -340,8 +354,10 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
break;
case REG_FPU_ST_DOUBLE:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_FP)
fatal("codegen_reg_load - REG_FPU_ST_DOUBLE !REG_FP\n");
#endif
if (block->flags & CODEBLOCK_STATIC_TOP)
codegen_direct_read_double(block, reg_set->reg_list[c].reg, &cpu_state.ST[ir_reg.reg & 7]);
else
@@ -366,24 +382,30 @@ static void codegen_reg_writeback(host_reg_set_t *reg_set, codeblock_t *block, i
switch (ireg_data[ir_reg].native_size)
{
case REG_BYTE:
#ifndef RELEASE_BUILD
if (ireg_data[ir_reg].type != REG_INTEGER)
fatal("codegen_reg_writeback - REG_BYTE !REG_INTEGER\n");
if ((uintptr_t)p < 256)
fatal("codegen_reg_writeback - REG_BYTE %p\n", p);
#endif
codegen_direct_write_8(block, p, reg_set->reg_list[c].reg);
break;
case REG_WORD:
#ifndef RELEASE_BUILD
if (ireg_data[ir_reg].type != REG_INTEGER)
fatal("codegen_reg_writeback - REG_WORD !REG_INTEGER\n");
if ((uintptr_t)p < 256)
fatal("codegen_reg_writeback - REG_WORD %p\n", p);
#endif
codegen_direct_write_16(block, p, reg_set->reg_list[c].reg);
break;
case REG_DWORD:
#ifndef RELEASE_BUILD
if (ireg_data[ir_reg].type != REG_INTEGER)
fatal("codegen_reg_writeback - REG_DWORD !REG_INTEGER\n");
#endif
if ((uintptr_t)p < 256)
codegen_direct_write_32_stack(block, (int)(uintptr_t)p, reg_set->reg_list[c].reg);
else
@@ -391,8 +413,10 @@ static void codegen_reg_writeback(host_reg_set_t *reg_set, codeblock_t *block, i
break;
case REG_QWORD:
#ifndef RELEASE_BUILD
if (ireg_data[ir_reg].type != REG_FP)
fatal("codegen_reg_writeback - REG_QWORD !REG_FP\n");
#endif
if ((uintptr_t)p < 256)
codegen_direct_write_64_stack(block, (int)(uintptr_t)p, reg_set->reg_list[c].reg);
else
@@ -400,16 +424,20 @@ static void codegen_reg_writeback(host_reg_set_t *reg_set, codeblock_t *block, i
break;
case REG_POINTER:
#ifndef RELEASE_BUILD
if (ireg_data[ir_reg].type != REG_INTEGER)
fatal("codegen_reg_writeback - REG_POINTER !REG_INTEGER\n");
if ((uintptr_t)p < 256)
fatal("codegen_reg_writeback - REG_POINTER %p\n", p);
#endif
codegen_direct_write_ptr(block, p, reg_set->reg_list[c].reg);
break;
case REG_DOUBLE:
#ifndef RELEASE_BUILD
if (ireg_data[ir_reg].type != REG_FP)
fatal("codegen_reg_writeback - REG_DOUBLE !REG_FP\n");
#endif
if ((uintptr_t)p < 256)
codegen_direct_write_double_stack(block, (int)(uintptr_t)p, reg_set->reg_list[c].reg);
else
@@ -417,8 +445,10 @@ static void codegen_reg_writeback(host_reg_set_t *reg_set, codeblock_t *block, i
break;
case REG_FPU_ST_BYTE:
#ifndef RELEASE_BUILD
if (ireg_data[ir_reg].type != REG_INTEGER)
fatal("codegen_reg_writeback - REG_FPU_ST_BYTE !REG_INTEGER\n");
#endif
if (block->flags & CODEBLOCK_STATIC_TOP)
codegen_direct_write_8(block, &cpu_state.tag[reg_set->regs[c].reg & 7], reg_set->reg_list[c].reg);
else
@@ -426,8 +456,10 @@ static void codegen_reg_writeback(host_reg_set_t *reg_set, codeblock_t *block, i
break;
case REG_FPU_ST_QWORD:
#ifndef RELEASE_BUILD
if (ireg_data[ir_reg].type != REG_FP)
fatal("codegen_reg_writeback - REG_FPU_ST_QWORD !REG_FP\n");
#endif
if (block->flags & CODEBLOCK_STATIC_TOP)
codegen_direct_write_64(block, &cpu_state.MM[reg_set->regs[c].reg & 7], reg_set->reg_list[c].reg);
else
@@ -435,8 +467,10 @@ static void codegen_reg_writeback(host_reg_set_t *reg_set, codeblock_t *block, i
break;
case REG_FPU_ST_DOUBLE:
#ifndef RELEASE_BUILD
if (ireg_data[ir_reg].type != REG_FP)
fatal("codegen_reg_writeback - REG_FPU_ST_DOUBLE !REG_FP\n");
#endif
if (block->flags & CODEBLOCK_STATIC_TOP)
codegen_direct_write_double(block, &cpu_state.ST[reg_set->regs[c].reg & 7], reg_set->reg_list[c].reg);
else
@@ -452,6 +486,49 @@ static void codegen_reg_writeback(host_reg_set_t *reg_set, codeblock_t *block, i
reg_set->dirty[c] = 0;
}
#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
void codegen_reg_write_imm(codeblock_t *block, ir_reg_t ir_reg, uint32_t imm_data)
{
int reg_idx = IREG_GET_REG(ir_reg.reg);
void *p = ireg_data[reg_idx].p;
switch (ireg_data[reg_idx].native_size)
{
case REG_BYTE:
#ifndef RELEASE_BUILD
if ((uintptr_t)p < 256)
fatal("codegen_reg_write_imm - REG_BYTE %p\n", p);
#endif
codegen_direct_write_8_imm(block, p, imm_data);
break;
case REG_WORD:
#ifndef RELEASE_BUILD
if ((uintptr_t)p < 256)
fatal("codegen_reg_write_imm - REG_WORD %p\n", p);
#endif
codegen_direct_write_16_imm(block, p, imm_data);
break;
case REG_DWORD:
if ((uintptr_t)p < 256)
codegen_direct_write_32_imm_stack(block, (int)p, imm_data);
else
codegen_direct_write_32_imm(block, p, imm_data);
break;
case REG_POINTER:
case REG_QWORD:
case REG_DOUBLE:
case REG_FPU_ST_BYTE:
case REG_FPU_ST_QWORD:
case REG_FPU_ST_DOUBLE:
default:
fatal("codegen_reg_write_imm - native_size=%i\n", ireg_data[reg_idx].native_size);
}
}
#endif
static void alloc_reg(ir_reg_t ir_reg)
{
host_reg_set_t *reg_set = get_reg_set(ir_reg);
@@ -462,8 +539,10 @@ static void alloc_reg(ir_reg_t ir_reg)
{
if (IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(ir_reg.reg))
{
#ifndef RELEASE_BUILD
if (reg_set->regs[c].version != ir_reg.version)
fatal("alloc_reg - host_regs[c].version != ir_reg.version %i %p %p %i %i\n", c, reg_set, &host_reg_set, reg_set->regs[c].reg, ir_reg.reg);
#endif
reg_set->locked |= (1 << c);
return;
}
@@ -551,8 +630,10 @@ ir_host_reg_t codegen_reg_alloc_read_reg(codeblock_t *block, ir_reg_t ir_reg, in
break;
}
#ifndef RELEASE_BUILD
if (!ir_reg_is_invalid(reg_set->regs[c]) && IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(ir_reg.reg) && reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount)
fatal("codegen_reg_alloc_read_reg - version mismatch!\n");
#endif
}
if (c == reg_set->nr_regs)
@@ -571,8 +652,10 @@ ir_host_reg_t codegen_reg_alloc_read_reg(codeblock_t *block, ir_reg_t ir_reg, in
if (!(reg_set->locked & (1 << c)))
break;
}
#ifndef RELEASE_BUILD
if (c == reg_set->nr_regs)
fatal("codegen_reg_alloc_read_reg - out of registers\n");
#endif
}
if (reg_set->dirty[c])
codegen_reg_writeback(reg_set, block, c, 1);
@@ -582,8 +665,10 @@ ir_host_reg_t codegen_reg_alloc_read_reg(codeblock_t *block, ir_reg_t ir_reg, in
}
reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount--;
#ifndef RELEASE_BUILD
if (reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount == (uint8_t)-1)
fatal("codegen_reg_alloc_read_reg - refcount < 0\n");
#endif
if (host_reg_idx)
*host_reg_idx = c;
@@ -606,11 +691,13 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
codegen_reg_alloc_read_reg(block, parent_reg, &c);
#ifndef RELEASE_BUILD
if (IREG_GET_REG(reg_set->regs[c].reg) != IREG_GET_REG(ir_reg.reg) || reg_set->regs[c].version > ir_reg.version-1)
fatal("codegen_reg_alloc_write_reg sub_reg - doesn't match %i %02x.%i %02x.%i\n", c,
reg_set->regs[c].reg,reg_set->regs[c].version,
ir_reg.reg,ir_reg.version);
#endif
reg_set->regs[c].reg = ir_reg.reg;
reg_set->regs[c].version = ir_reg.version;
reg_set->dirty[c] = 1;
@@ -624,8 +711,10 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
{
if (reg_set->regs[c].version <= ir_reg.version-1)
{
#ifndef RELEASE_BUILD
if (reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount != 0)
fatal("codegen_reg_alloc_write_reg - previous version refcount != 0\n");
#endif
break;
}
}
@@ -648,8 +737,10 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
if (!(reg_set->locked & (1 << c)))
break;
}
#ifndef RELEASE_BUILD
if (c == reg_set->nr_regs)
fatal("codegen_reg_alloc_write_reg - out of registers\n");
#endif
if (reg_set->dirty[c])
codegen_reg_writeback(reg_set, block, c, 1);
}
@@ -661,6 +752,68 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
return reg_set->reg_list[c].reg | IREG_GET_SIZE(ir_reg.reg);
}
#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
int codegen_reg_is_loaded(ir_reg_t ir_reg)
{
host_reg_set_t *reg_set = get_reg_set(ir_reg);
int c;
/*Search for previous version in host register*/
for (c = 0; c < reg_set->nr_regs; c++)
{
if (!ir_reg_is_invalid(reg_set->regs[c]) && IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(ir_reg.reg))
{
if (reg_set->regs[c].version <= ir_reg.version-1)
{
#ifndef RELEASE_BUILD
if (reg_version[IREG_GET_REG(reg_set->regs[c].reg)][reg_set->regs[c].version].refcount != 0)
fatal("codegen_reg_alloc_write_reg - previous version refcount != 0\n");
#endif
return 1;
}
}
}
return 0;
}
#endif
void codegen_reg_rename(codeblock_t *block, ir_reg_t src, ir_reg_t dst)
{
host_reg_set_t *reg_set = get_reg_set(src);
int c;
int target;
// pclog("rename: %i.%i -> %i.%i\n", src.reg,src.version, dst.reg, dst.version);
/*Search for required register*/
for (c = 0; c < reg_set->nr_regs; c++)
{
if (!ir_reg_is_invalid(reg_set->regs[c]) && IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(src.reg) && reg_set->regs[c].version == src.version)
break;
}
#ifndef RELEASE_BUILD
if (c == reg_set->nr_regs)
fatal("codegen_reg_rename: Can't find register to rename\n");
#endif
target = c;
if (reg_set->dirty[target])
codegen_reg_writeback(reg_set, block, target, 0);
reg_set->regs[target] = dst;
reg_set->dirty[target] = 1;
// pclog("renamed reg %i dest=%i.%i\n", target, dst.reg, dst.version);
/*Invalidate any stale copies of the dest register*/
for (c = 0; c < reg_set->nr_regs; c++)
{
if (c == target)
continue;
if (!ir_reg_is_invalid(reg_set->regs[c]) && IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(dst.reg))
{
reg_set->regs[c] = invalid_ir_reg;
reg_set->dirty[c] = 0;
}
}
}
void codegen_reg_flush(ir_data_t *ir, codeblock_t *block)
{
host_reg_set_t *reg_set;

23
src/codegen_new/codegen_reg.h
View File

@@ -325,17 +325,21 @@ static inline ir_reg_t codegen_reg_read(int reg)
ir_reg_t ireg;
reg_version_t *version;
#ifndef RELEASE_BUILD
if (IREG_GET_REG(reg) == IREG_INVALID)
fatal("codegen_reg_read - IREG_INVALID\n");
#endif
ireg.reg = reg;
ireg.version = reg_last_version[IREG_GET_REG(reg)];
version = &reg_version[IREG_GET_REG(ireg.reg)][ireg.version];
version->flags = 0;
version->refcount++;
#ifndef RELEASE_BUILD
if (!version->refcount)
fatal("codegen_reg_read - refcount overflow\n");
else if (version->refcount > REG_REFCOUNT_MAX)
else
#endif
if (version->refcount > REG_REFCOUNT_MAX)
CPU_BLOCK_END();
if (version->refcount > max_version_refcount)
max_version_refcount = version->refcount;
@@ -350,9 +354,10 @@ static inline ir_reg_t codegen_reg_write(int reg, int uop_nr)
int last_version = reg_last_version[IREG_GET_REG(reg)];
reg_version_t *version;
#ifndef RELEASE_BUILD
if (IREG_GET_REG(reg) == IREG_INVALID)
fatal("codegen_reg_write - IREG_INVALID\n");
#endif
ireg.reg = reg;
ireg.version = last_version + 1;
@@ -364,9 +369,12 @@ static inline ir_reg_t codegen_reg_write(int reg, int uop_nr)
}
reg_last_version[IREG_GET_REG(reg)]++;
#ifndef RELEASE_BUILD
if (!reg_last_version[IREG_GET_REG(reg)])
fatal("codegen_reg_write - version overflow\n");
else if (reg_last_version[IREG_GET_REG(reg)] > REG_VERSION_MAX)
else
#endif
if (reg_last_version[IREG_GET_REG(reg)] > REG_VERSION_MAX)
CPU_BLOCK_END();
if (reg_last_version[IREG_GET_REG(reg)] > max_version_refcount)
max_version_refcount = reg_last_version[IREG_GET_REG(reg)];
@@ -394,9 +402,16 @@ void codegen_reg_flush_invalidate(struct ir_data_t *ir, codeblock_t *block);
/*Register ir_reg usage for this uOP. This ensures that required registers aren't evicted*/
void codegen_reg_alloc_register(ir_reg_t dest_reg_a, ir_reg_t src_reg_a, ir_reg_t src_reg_b, ir_reg_t src_reg_c);
#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
int codegen_reg_is_loaded(ir_reg_t ir_reg);
void codegen_reg_write_imm(codeblock_t *block, ir_reg_t ir_reg, uint32_t imm_data);
#endif
ir_host_reg_t codegen_reg_alloc_read_reg(codeblock_t *block, ir_reg_t ir_reg, int *host_reg_idx);
ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg);
void codegen_reg_rename(codeblock_t *block, ir_reg_t src, ir_reg_t dst);
void codegen_reg_mark_as_required();
void codegen_reg_process_dead_list(struct ir_data_t *ir);
#endif

3
src/config.c
View File

@@ -668,6 +668,9 @@ load_sound(void)
char *p;
p = config_get_string(cat, "sndcard", NULL);
/* FIXME: Hack to not break configs with the Sound Blaster 128 PCI set. */
if ((p != NULL) && (!strcmp(p, "sbpci128") || !strcmp(p, "sb128pci")))
p = "es1371";
if (p != NULL)
sound_card_current = sound_card_get_from_internal_name(p);
else

52
src/cpu/386.c
View File

@@ -199,10 +199,10 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
#include "x86_ops.h"
void
exec386(int cycs)
{
// uint8_t opcode;
int vector, tempi, cycdiff, oldcyc;
int cycle_period, ins_cycles;
uint32_t addr;
@@ -257,30 +257,6 @@ exec386(int cycs)
if (!use32) cpu_state.pc &= 0xffff;
#endif
if (cpu_state.abrt) {
flags_rebuild();
tempi = cpu_state.abrt;
cpu_state.abrt = 0;
x86_doabrt(tempi);
if (cpu_state.abrt) {
cpu_state.abrt = 0;
#ifndef USE_NEW_DYNAREC
CS = oldcs;
#endif
cpu_state.pc = cpu_state.oldpc;
x386_log("Double fault %i\n", ins);
pmodeint(8, 0);
if (cpu_state.abrt) {
cpu_state.abrt = 0;
softresetx86();
cpu_set_edx();
#ifdef ENABLE_386_LOG
x386_log("Triple fault - reset\n");
#endif
}
}
}
ins_cycles -= cycles;
tsc += ins_cycles;
@@ -314,7 +290,7 @@ exec386(int cycs)
nmi_auto_clear = 0;
nmi = 0;
}
} else if ((cpu_state.flags & I_FLAG) && pic.int_pending) {
} else if ((cpu_state.flags & I_FLAG) && pic.int_pending && !cpu_end_block_after_ins) {
vector = picinterrupt();
if (vector != -1) {
flags_rebuild();
@@ -332,8 +308,32 @@ exec386(int cycs)
loadcs(readmemw(0, addr + 2));
}
}
} else if (cpu_state.abrt) {
flags_rebuild();
tempi = cpu_state.abrt & ABRT_MASK;
cpu_state.abrt = 0;
x86_doabrt(tempi);
if (cpu_state.abrt) {
cpu_state.abrt = 0;
#ifndef USE_NEW_DYNAREC
CS = oldcs;
#endif
cpu_state.pc = cpu_state.oldpc;
x386_log("Double fault %i\n", ins);
pmodeint(8, 0);
if (cpu_state.abrt) {
cpu_state.abrt = 0;
softresetx86();
cpu_set_edx();
#ifdef ENABLE_386_LOG
x386_log("Triple fault - reset\n");
#endif
}
}
}
cpu_end_block_after_ins = 0;
if (timetolive) {
timetolive--;
if (!timetolive)

394
src/cpu/386_common.c
View File

@@ -46,7 +46,7 @@ uint32_t *eal_r, *eal_w;
int nmi_enable = 1;
int cpl_override=0;
int alt_access, cpl_override = 0;
#ifdef USE_NEW_DYNAREC
uint16_t cpu_cur_status = 0;
@@ -322,7 +322,10 @@ x386_common_log(const char *fmt, ...)
static __inline void
set_stack32(int s)
{
stack32 = s;
if ((cr0 & 1) && ! (cpu_state.eflags & VM_FLAG))
stack32 = s;
else
stack32 = 0;
if (stack32)
cpu_cur_status |= CPU_STATUS_STACK32;
@@ -334,13 +337,15 @@ set_stack32(int s)
static __inline void
set_use32(int u)
{
if (u) {
use32 = 0x300;
cpu_cur_status |= CPU_STATUS_USE32;
} else {
if ((cr0 & 1) && ! (cpu_state.eflags & VM_FLAG))
use32 = u ? 0x300 : 0;
else
use32 = 0;
if (use32)
cpu_cur_status |= CPU_STATUS_USE32;
else
cpu_cur_status &= ~CPU_STATUS_USE32;
}
}
@@ -984,6 +989,30 @@ smram_restore_state_amd_k(uint32_t *saved_state)
}
static void
smram_save_state_cyrix(uint32_t *saved_state, int in_hlt)
{
saved_state[0] = dr[7];
saved_state[1] = cpu_state.flags | (cpu_state.eflags << 16);
saved_state[2] = cr0;
saved_state[3] = cpu_state.oldpc;
saved_state[4] = cpu_state.pc;
saved_state[5] = CS | (CPL << 21);
saved_state[6] = 0x00000000;
}
static void
smram_restore_state_cyrix(uint32_t *saved_state)
{
dr[7] = saved_state[0];
cpu_state.flags = saved_state[1] & 0xffff;
cpu_state.eflags = saved_state[1] >> 16;
cr0 = saved_state[2];
cpu_state.pc = saved_state[4];
}
void
enter_smm(int in_hlt)
{
@@ -991,9 +1020,15 @@ enter_smm(int in_hlt)
uint32_t smram_state = smbase + 0x10000;
/* If it's a CPU on which SMM is not supporter, do nothing. */
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6)
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cx6x86)
return;
if (cpu_iscyrix) {
if (!cyrix.smhr & SMHR_VALID)
cyrix.smhr = (cyrix.arr[3].base + cyrix.arr[3].size) | SMHR_VALID;
smram_state = cyrix.smhr & SMHR_ADDR_MASK;
}
x386_common_log("enter_smm(): smbase = %08X\n", smbase);
x386_common_log("CS : seg = %04X, base = %08X, limit = %08X, limit_low = %08X, limit_high = %08X, access = %02X, ar_high = %02X\n",
cpu_state.seg_cs.seg, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low,
@@ -1030,8 +1065,16 @@ enter_smm(int in_hlt)
smram_backup_all();
smram_recalc_all(0);
if (cpu_iscyrix) {
if (!cyrix.smhr & SMHR_VALID)
cyrix.smhr = (cyrix.arr[3].base + cyrix.arr[3].size) | SMHR_VALID;
smram_state = cyrix.smhr & SMHR_ADDR_MASK;
}
memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
if (cpu_iscyrix) /* Cx6x86 */
smram_save_state_cyrix(saved_state, in_hlt);
if (is_pentium || is_am486) /* Am486 / 5x86 / Intel P5 (Pentium) */
smram_save_state_p5(saved_state, in_hlt);
else if (is_k5 || is_k6) /* AMD K5 and K6 */
@@ -1046,44 +1089,69 @@ enter_smm(int in_hlt)
cr4 = 0;
dr[7] = 0x400;
cpu_state.pc = 0x8000;
cpu_state.seg_ds.seg = 0x00000000;
cpu_state.seg_ds.base = 0x00000000;
cpu_state.seg_ds.limit = 0xffffffff;
cpu_state.seg_ds.access = 0x93;
cpu_state.seg_ds.ar_high = 0x80;
if (cpu_iscyrix) {
cpu_state.pc = 0x0000;
cpu_state.seg_cs.seg = (cyrix.arr[3].base >> 4);
cpu_state.seg_cs.base = cyrix.arr[3].base;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.access = 0x93;
cpu_state.seg_cs.ar_high = 0x80;
cpu_state.seg_cs.checked = 1;
memcpy(&cpu_state.seg_es, &cpu_state.seg_ds, sizeof(x86seg));
memcpy(&cpu_state.seg_ss, &cpu_state.seg_ds, sizeof(x86seg));
memcpy(&cpu_state.seg_fs, &cpu_state.seg_ds, sizeof(x86seg));
memcpy(&cpu_state.seg_gs, &cpu_state.seg_ds, sizeof(x86seg));
smm_seg_load(&cpu_state.seg_cs);
} else {
cpu_state.pc = 0x8000;
cpu_state.seg_ds.seg = 0x00000000;
cpu_state.seg_ds.base = 0x00000000;
cpu_state.seg_ds.limit = 0xffffffff;
cpu_state.seg_ds.access = 0x93;
cpu_state.seg_ds.ar_high = 0x80;
if (is_p6)
cpu_state.seg_cs.seg = (smbase >> 4);
else
cpu_state.seg_cs.seg = 0x3000;
memcpy(&cpu_state.seg_es, &cpu_state.seg_ds, sizeof(x86seg));
memcpy(&cpu_state.seg_ss, &cpu_state.seg_ds, sizeof(x86seg));
memcpy(&cpu_state.seg_fs, &cpu_state.seg_ds, sizeof(x86seg));
memcpy(&cpu_state.seg_gs, &cpu_state.seg_ds, sizeof(x86seg));
/* On Pentium, CS selector in SMM is always 3000, regardless of SMBASE. */
cpu_state.seg_cs.base = smbase;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.access = 0x93;
cpu_state.seg_cs.ar_high = 0x80;
cpu_state.seg_cs.checked = 1;
if (is_p6)
cpu_state.seg_cs.seg = (smbase >> 4);
else
cpu_state.seg_cs.seg = 0x3000;
smm_seg_load(&cpu_state.seg_es);
smm_seg_load(&cpu_state.seg_cs);
smm_seg_load(&cpu_state.seg_ds);
smm_seg_load(&cpu_state.seg_ss);
smm_seg_load(&cpu_state.seg_fs);
smm_seg_load(&cpu_state.seg_gs);
/* On Pentium, CS selector in SMM is always 3000, regardless of SMBASE. */
cpu_state.seg_cs.base = smbase;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.access = 0x93;
cpu_state.seg_cs.ar_high = 0x80;
cpu_state.seg_cs.checked = 1;
smm_seg_load(&cpu_state.seg_es);
smm_seg_load(&cpu_state.seg_cs);
smm_seg_load(&cpu_state.seg_ds);
smm_seg_load(&cpu_state.seg_ss);
smm_seg_load(&cpu_state.seg_fs);
smm_seg_load(&cpu_state.seg_gs);
}
cpu_state.op32 = use32;
for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
smram_state -= 4;
writememl(0, smram_state, saved_state[n]);
cpl_override = 1;
if (cpu_iscyrix) {
writememl(0, smram_state - 0x04, saved_state[0]);
writememl(0, smram_state - 0x08, saved_state[1]);
writememl(0, smram_state - 0x0c, saved_state[2]);
writememl(0, smram_state - 0x10, saved_state[3]);
writememl(0, smram_state - 0x14, saved_state[4]);
writememl(0, smram_state - 0x18, saved_state[5]);
cyrix_write_seg_descriptor(smram_state - 0x20, &cpu_state.seg_cs);
writememl(0, smram_state - 0x18, saved_state[6]);
} else {
for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
smram_state -= 4;
writememl(0, smram_state, saved_state[n]);
}
}
cpl_override = 0;
nmi_mask = 0;
@@ -1102,6 +1170,7 @@ enter_smm(int in_hlt)
flushmmucache();
}
cpu_cur_status &= ~(CPU_STATUS_PMODE | CPU_STATUS_V86);
CPU_BLOCK_END();
}
@@ -1142,16 +1211,30 @@ leave_smm(void)
uint32_t smram_state = smbase + 0x10000;
/* If it's a CPU on which SMM is not supported (or not implemented in 86Box), do nothing. */
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6)
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cx6x86)
return;
memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
smram_state -= 4;
saved_state[n] = readmeml(0, smram_state);
x386_common_log("Reading %08X from memory at %08X to array element %i\n", saved_state[n], smram_state, n);
cpl_override = 1;
if (cpu_iscyrix) {
smram_state = cyrix.smhr & SMHR_ADDR_MASK;
saved_state[0] = readmeml(0, smram_state - 0x04);
saved_state[1] = readmeml(0, smram_state - 0x08);
saved_state[2] = readmeml(0, smram_state - 0x0c);
saved_state[3] = readmeml(0, smram_state - 0x10);
saved_state[4] = readmeml(0, smram_state - 0x14);
saved_state[5] = readmeml(0, smram_state - 0x18);
cyrix_load_seg_descriptor(smram_state - 0x20, &cpu_state.seg_cs);
saved_state[6] = readmeml(0, smram_state - 0x24);
} else {
for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
smram_state -= 4;
saved_state[n] = readmeml(0, smram_state);
x386_common_log("Reading %08X from memory at %08X to array element %i\n", saved_state[n], smram_state, n);
}
}
cpl_override = 0;
if (unmask_a20_in_smm) {
rammask = old_rammask;
@@ -1160,17 +1243,25 @@ leave_smm(void)
}
x386_common_log("New SMBASE: %08X (%08X)\n", saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET], saved_state[66]);
if (is_pentium) /* Intel P5 (Pentium) */
if (cpu_iscyrix) /* Cx6x86 */
smram_restore_state_cyrix(saved_state);
else if (is_pentium) /* Intel P5 (Pentium) */
smram_restore_state_p5(saved_state);
else if (is_k5 || is_k6) /* AMD K5 and K6 */
smram_restore_state_amd_k(saved_state);
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
smram_restore_state_p6(saved_state);
in_smm = 0;
smram_recalc_all(1);
cpu_state.op32 = use32;
cpu_386_flags_extract();
cpu_cur_status &= ~(CPU_STATUS_PMODE | CPU_STATUS_V86);
if (cr0 & 1) {
cpu_cur_status |= CPU_STATUS_PMODE;
if (cpu_state.eflags & VM_FLAG)
cpu_cur_status |= CPU_STATUS_V86;
}
nmi_mask = 1;
@@ -1502,8 +1593,6 @@ read_seg_data(uint16_t *seg_data, uint16_t seg, x86seg *s)
int
sysenter(uint32_t fetchdat)
{
uint16_t seg_data[4];
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSENTER called\n");
#endif
@@ -1542,46 +1631,34 @@ sysenter(uint32_t fetchdat)
oldcs = CS;
#endif
cpu_state.oldpc = cpu_state.pc;
#if 0
old_pc = cpu_state.pc;
#endif
ESP = esp_msr;
cpu_state.pc = eip_msr;
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSENTER: Loading CS...\n");
#endif
CS = (cs_msr & 0xFFFC);
cpu_state.seg_cs.access &= 0x9f;
read_seg_data(seg_data, CS, &cpu_state.seg_cs);
if (cpu_state.abrt)
return 1;
do_seg_load(&cpu_state.seg_cs, seg_data);
cpu_state.seg_cs.checked = 0;
set_use32(0x40);
cpu_state.seg_cs.seg = (cs_msr & 0xfffc);
cpu_state.seg_cs.base = 0;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.limit_raw = 0x000fffff;
cpu_state.seg_cs.limit_high = 0xffffffff;
cpu_state.seg_cs.access = 0x9b;
cpu_state.seg_cs.ar_high = 0xcf;
cpu_state.seg_cs.checked = 1;
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSENTER: Loading SS...\n");
#endif
SS = ((cs_msr + 8) & 0xFFFC);
read_seg_data(seg_data, SS, &cpu_state.seg_ss);
if (cpu_state.abrt)
return 1;
do_seg_load(&cpu_state.seg_ss, seg_data);
cpu_state.seg_ss.checked = 0;
#ifdef USE_DYNAREC
codegen_flat_ss = 0;
#endif
if (cpu_state.seg_ss.base == 0 && cpu_state.seg_ss.limit_low == 0 &&
cpu_state.seg_ss.limit_high == 0xffffffff)
cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
else
cpu_cur_status |= CPU_STATUS_NOTFLATSS;
cpu_state.seg_ss.seg = ((cs_msr + 8) & 0xfffc);
cpu_state.seg_ss.base = 0;
cpu_state.seg_ss.limit_low = 0;
cpu_state.seg_ss.limit = 0xffffffff;
cpu_state.seg_ss.limit_raw = 0x000fffff;
cpu_state.seg_ss.limit_high = 0xffffffff;
cpu_state.seg_ss.access = 0x93;
cpu_state.seg_ss.ar_high = 0xcf;
cpu_state.seg_ss.checked = 1;
cpu_cur_status &= ~(CPU_STATUS_NOTFLATSS | CPU_STATUS_V86);
cpu_cur_status |= (CPU_STATUS_USE32 | CPU_STATUS_STACK32 | CPU_STATUS_PMODE);
set_use32(1);
set_stack32(1);
oldcpl = CPL;
flags_extract();
trap = 0;
in_sys = 1;
#ifdef ENABLE_386_COMMON_LOG
@@ -1599,8 +1676,6 @@ sysenter(uint32_t fetchdat)
int
sysexit(uint32_t fetchdat)
{
uint16_t seg_data[4];
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSEXIT called\n");
#endif
@@ -1644,39 +1719,33 @@ sysexit(uint32_t fetchdat)
ESP = ECX;
cpu_state.pc = EDX;
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSEXIT: Loading CS...\n");
#endif
CS = (((cs_msr + 16) & 0xFFFC) | 3);
read_seg_data(seg_data, CS, &cpu_state.seg_cs);
if (cpu_state.abrt)
return 1;
do_seg_load(&cpu_state.seg_cs, seg_data);
cpu_state.seg_cs.checked = 0;
set_use32(0x40);
cpu_state.seg_cs.seg = (((cs_msr + 16) & 0xfffc) | 3);
cpu_state.seg_cs.base = 0;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.limit_raw = 0x000fffff;
cpu_state.seg_cs.limit_high = 0xffffffff;
cpu_state.seg_cs.access = 0xfb;
cpu_state.seg_cs.ar_high = 0xcf;
cpu_state.seg_cs.checked = 1;
oldcpl = 3;
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSEXIT: Loading SS...\n");
#endif
SS = (((cs_msr + 24) & 0xFFFC) | 3);
read_seg_data(seg_data, SS, &cpu_state.seg_ss);
if (cpu_state.abrt)
return 1;
do_seg_load(&cpu_state.seg_ss, seg_data);
cpu_state.seg_ss.checked = 0;
#ifdef USE_DYNAREC
codegen_flat_ss = 0;
#endif
if (cpu_state.seg_ss.base == 0 && cpu_state.seg_ss.limit_low == 0 &&
cpu_state.seg_ss.limit_high == 0xffffffff)
cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
else
cpu_cur_status |= CPU_STATUS_NOTFLATSS;
cpu_state.seg_ss.seg = (((cs_msr + 24) & 0xfffc) | 3);
cpu_state.seg_ss.base = 0;
cpu_state.seg_ss.limit_low = 0;
cpu_state.seg_ss.limit = 0xffffffff;
cpu_state.seg_ss.limit_raw = 0x000fffff;
cpu_state.seg_ss.limit_high = 0xffffffff;
cpu_state.seg_ss.access = 0xf3;
cpu_state.seg_cs.ar_high = 0xcf;
cpu_state.seg_ss.checked = 1;
cpu_cur_status &= ~(CPU_STATUS_NOTFLATSS | CPU_STATUS_V86);
cpu_cur_status |= (CPU_STATUS_USE32 | CPU_STATUS_STACK32 | CPU_STATUS_PMODE);
flushmmucache_cr3();
set_use32(1);
set_stack32(1);
flushmmucache_cr3();
oldcpl = CPL;
trap = 0;
in_sys = 0;
#ifdef ENABLE_386_COMMON_LOG
@@ -1694,8 +1763,6 @@ sysexit(uint32_t fetchdat)
int
syscall(uint32_t fetchdat)
{
uint16_t seg_data[4];
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSCALL called\n");
#endif
@@ -1719,34 +1786,32 @@ syscall(uint32_t fetchdat)
cpu_cur_status &= ~CPU_STATUS_V86;
/* CS */
CS = AMD_SYSCALL_SB & 0xFFFC;
read_seg_data(seg_data, CS, &cpu_state.seg_cs);
if (cpu_state.abrt)
return 1;
do_seg_load(&cpu_state.seg_cs, seg_data);
cpu_state.seg_cs.checked = 0;
set_use32(0x40);
CS = AMD_SYSCALL_SB & 0xfffc;
cpu_state.seg_cs.base = 0;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.limit_raw = 0x000fffff;
cpu_state.seg_cs.limit_high = 0xffffffff;
cpu_state.seg_cs.access = 0x9b;
cpu_state.seg_cs.ar_high = 0xcf;
cpu_state.seg_cs.checked = 1;
/* SS */
SS = (AMD_SYSCALL_SB + 8) & 0xFFFC;
read_seg_data(seg_data, SS, &cpu_state.seg_ss);
if (cpu_state.abrt)
return 1;
do_seg_load(&cpu_state.seg_ss, seg_data);
cpu_state.seg_ss.checked = 0;
#ifdef USE_DYNAREC
codegen_flat_ss = 0;
#endif
if (cpu_state.seg_ss.base == 0 && cpu_state.seg_ss.limit_low == 0 &&
cpu_state.seg_ss.limit_high == 0xffffffff)
cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
else
cpu_cur_status |= CPU_STATUS_NOTFLATSS;
SS = (AMD_SYSCALL_SB + 8) & 0xfffc;
cpu_state.seg_ss.base = 0;
cpu_state.seg_ss.limit_low = 0;
cpu_state.seg_ss.limit = 0xffffffff;
cpu_state.seg_ss.limit_raw = 0x000fffff;
cpu_state.seg_ss.limit_high = 0xffffffff;
cpu_state.seg_ss.access = 0x93;
cpu_state.seg_ss.ar_high = 0xcf;
cpu_state.seg_ss.checked = 1;
cpu_cur_status &= ~(CPU_STATUS_NOTFLATSS | CPU_STATUS_V86);
cpu_cur_status |= (CPU_STATUS_USE32 | CPU_STATUS_STACK32 | CPU_STATUS_PMODE);
set_use32(1);
set_stack32(1);
oldcpl = CPL;
flags_extract();
trap = 0;
in_sys = 1;
return 1;
@@ -1756,8 +1821,6 @@ syscall(uint32_t fetchdat)
int
sysret(uint32_t fetchdat)
{
uint16_t seg_data[4];
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSRET called\n");
#endif
@@ -1777,35 +1840,34 @@ sysret(uint32_t fetchdat)
cpu_state.eflags |= (1 << 1);
/* CS */
CS = (AMD_SYSRET_SB & 0xFFFC) | 3;
cpu_state.seg_cs.seg = AMD_SYSRET_SB & ~7;
read_seg_data(seg_data, CS, &cpu_state.seg_cs);
if (cpu_state.abrt)
return 1;
do_seg_load(&cpu_state.seg_cs, seg_data);
cpu_state.seg_cs.checked = 0;
set_use32(0x40);
CS = (AMD_SYSRET_SB & 0xfffc) | 3;
cpu_state.seg_cs.base = 0;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.limit_raw = 0x000fffff;
cpu_state.seg_cs.limit_high = 0xffffffff;
cpu_state.seg_cs.access = 0xfb;
cpu_state.seg_cs.ar_high = 0xcf;
cpu_state.seg_cs.checked = 1;
oldcpl = 3;
/* SS */
SS = ((AMD_SYSRET_SB + 8) & 0xFFFC) | 3;
read_seg_data(seg_data, SS, &cpu_state.seg_ss);
if (cpu_state.abrt)
return 1;
do_seg_load(&cpu_state.seg_ss, seg_data);
cpu_state.seg_ss.checked = 0;
#ifdef USE_DYNAREC
codegen_flat_ss = 0;
#endif
if (cpu_state.seg_ss.base == 0 && cpu_state.seg_ss.limit_low == 0 &&
cpu_state.seg_ss.limit_high == 0xffffffff)
cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
else
cpu_cur_status |= CPU_STATUS_NOTFLATSS;
SS = ((AMD_SYSRET_SB + 8) & 0xfffc) | 3;
cpu_state.seg_ss.base = 0;
cpu_state.seg_ss.limit_low = 0;
cpu_state.seg_ss.limit = 0xffffffff;
cpu_state.seg_ss.limit_raw = 0x000fffff;
cpu_state.seg_ss.limit_high = 0xffffffff;
cpu_state.seg_ss.access = 0xf3;
cpu_state.seg_cs.ar_high = 0xcf;
cpu_state.seg_ss.checked = 1;
cpu_cur_status &= ~(CPU_STATUS_NOTFLATSS | CPU_STATUS_V86);
cpu_cur_status |= (CPU_STATUS_USE32 | CPU_STATUS_STACK32 | CPU_STATUS_PMODE);
flushmmucache_cr3();
set_use32(1);
set_stack32(1);
flushmmucache_cr3();
oldcpl = CPL;
trap = 0;
in_sys = 0;
return 1;

10
src/cpu/386_common.h
View File

@@ -57,7 +57,10 @@ int checkio(int port);
if (cpu_state.abrt) return 1; \
if (tempi) \
{ \
x86gpf("check_io_perm(): no permission",0); \
if (cpu_state.eflags & VM_FLAG) \
x86gpf_expected(NULL,0); \
else \
x86gpf(NULL,0); \
return 1; \
} \
}
@@ -68,7 +71,10 @@ int checkio(int port);
if (cpu_state.abrt) return 1; \
if (tempi) \
{ \
x86gpf("check_io_perm(): no permission",0); \
if (cpu_state.eflags & VM_FLAG) \
x86gpf_expected(NULL,0); \
else \
x86gpf(NULL,0); \
return 1; \
} \
}

1023
src/cpu/386_dynarec.c
View File

File diff suppressed because it is too large Load Diff

110
src/cpu/386_ops.h
View File

@@ -170,6 +170,7 @@ extern void x386_dynarec_log(const char *fmt, ...);
#include "x86_ops_bcd.h"
#include "x86_ops_bit.h"
#include "x86_ops_bitscan.h"
#include "x86_ops_cyrix.h"
#include "x86_ops_flag.h"
#include "x86_ops_fpu.h"
#include "x86_ops_inc_dec.h"
@@ -996,6 +997,99 @@ const OpFn OP_TABLE(pentium_0f)[1024] =
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
};
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
const OpFn OP_TABLE(c6x86_0f)[1024] =
{
/*16-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_w_a16, opLAR_w_a16, opLSL_w_a16, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opSMINT, ILLEGAL,
/*80*/ opJO_w, opJNO_w, opJB_w, opJNB_w, opJE_w, opJNE_w, opJBE_w, opJNBE_w, opJS_w, opJNS_w, opJP_w, opJNP_w, opJL_w, opJNL_w, opJLE_w, opJNLE_w,
/*90*/ opSETO_a16, opSETNO_a16, opSETB_a16, opSETNB_a16, opSETE_a16, opSETNE_a16, opSETBE_a16, opSETNBE_a16, opSETS_a16, opSETNS_a16, opSETP_a16, opSETNP_a16, opSETL_a16, opSETNL_a16, opSETLE_a16, opSETNLE_a16,
/*a0*/ opPUSH_FS_w, opPOP_FS_w, opCPUID, opBT_w_r_a16, opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL, ILLEGAL, opPUSH_GS_w, opPOP_GS_w, opRSM, opBTS_w_r_a16, opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL, opIMUL_w_w_a16,
/*b0*/ opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16, opBTR_w_r_a16, opLFS_w_a16, opLGS_w_a16, opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL, ILLEGAL, opBA_w_a16, opBTC_w_r_a16, opBSF_w_a16, opBSR_w_a16, opMOVSX_w_b_a16,ILLEGAL,
/*c0*/ opXADD_b_a16, opXADD_w_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCMPXCHG8B_a16,opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*32-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_l_a16, opLAR_l_a16, opLSL_l_a16, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opSMINT, ILLEGAL,
/*80*/ opJO_l, opJNO_l, opJB_l, opJNB_l, opJE_l, opJNE_l, opJBE_l, opJNBE_l, opJS_l, opJNS_l, opJP_l, opJNP_l, opJL_l, opJNL_l, opJLE_l, opJNLE_l,
/*90*/ opSETO_a16, opSETNO_a16, opSETB_a16, opSETNB_a16, opSETE_a16, opSETNE_a16, opSETBE_a16, opSETNBE_a16, opSETS_a16, opSETNS_a16, opSETP_a16, opSETNP_a16, opSETL_a16, opSETNL_a16, opSETLE_a16, opSETNLE_a16,
/*a0*/ opPUSH_FS_l, opPOP_FS_l, opCPUID, opBT_l_r_a16, opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL, ILLEGAL, opPUSH_GS_l, opPOP_GS_l, opRSM, opBTS_l_r_a16, opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL, opIMUL_l_l_a16,
/*b0*/ opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16, opBTR_l_r_a16, opLFS_l_a16, opLGS_l_a16, opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL, ILLEGAL, opBA_l_a16, opBTC_l_r_a16, opBSF_l_a16, opBSR_l_a16, opMOVSX_l_b_a16,opMOVSX_l_w_a16,
/*c0*/ opXADD_b_a16, opXADD_l_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCMPXCHG8B_a16,opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*16-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_w_a32, opLAR_w_a32, opLSL_w_a32, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a32, opRSDC_a32, opSVLDT_a32, opRSLDT_a32, opSVTS_a32, opRSTS_a32, opSMINT, ILLEGAL,
/*80*/ opJO_w, opJNO_w, opJB_w, opJNB_w, opJE_w, opJNE_w, opJBE_w, opJNBE_w, opJS_w, opJNS_w, opJP_w, opJNP_w, opJL_w, opJNL_w, opJLE_w, opJNLE_w,
/*90*/ opSETO_a32, opSETNO_a32, opSETB_a32, opSETNB_a32, opSETE_a32, opSETNE_a32, opSETBE_a32, opSETNBE_a32, opSETS_a32, opSETNS_a32, opSETP_a32, opSETNP_a32, opSETL_a32, opSETNL_a32, opSETLE_a32, opSETNLE_a32,
/*a0*/ opPUSH_FS_w, opPOP_FS_w, opCPUID, opBT_w_r_a32, opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL, ILLEGAL, opPUSH_GS_w, opPOP_GS_w, opRSM, opBTS_w_r_a32, opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL, opIMUL_w_w_a32,
/*b0*/ opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32, opBTR_w_r_a32, opLFS_w_a32, opLGS_w_a32, opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL, ILLEGAL, opBA_w_a32, opBTC_w_r_a32, opBSF_w_a32, opBSR_w_a32, opMOVSX_w_b_a32,ILLEGAL,
/*c0*/ opXADD_b_a32, opXADD_w_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCMPXCHG8B_a32,opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*32-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_l_a32, opLAR_l_a32, opLSL_l_a32, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a32, opRSDC_a32, opSVLDT_a32, opRSLDT_a32, opSVTS_a32, opRSTS_a32, opSMINT, ILLEGAL,
/*80*/ opJO_l, opJNO_l, opJB_l, opJNB_l, opJE_l, opJNE_l, opJBE_l, opJNBE_l, opJS_l, opJNS_l, opJP_l, opJNP_l, opJL_l, opJNL_l, opJLE_l, opJNLE_l,
/*90*/ opSETO_a32, opSETNO_a32, opSETB_a32, opSETNB_a32, opSETE_a32, opSETNE_a32, opSETBE_a32, opSETNBE_a32, opSETS_a32, opSETNS_a32, opSETP_a32, opSETNP_a32, opSETL_a32, opSETNL_a32, opSETLE_a32, opSETNLE_a32,
/*a0*/ opPUSH_FS_l, opPOP_FS_l, opCPUID, opBT_l_r_a32, opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL, ILLEGAL, opPUSH_GS_l, opPOP_GS_l, opRSM, opBTS_l_r_a32, opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL, opIMUL_l_l_a32,
/*b0*/ opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32, opBTR_l_r_a32, opLFS_l_a32, opLGS_l_a32, opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL, ILLEGAL, opBA_l_a32, opBTC_l_r_a32, opBSF_l_a32, opBSR_l_a32, opMOVSX_l_b_a32,opMOVSX_l_w_a32,
/*c0*/ opXADD_b_a32, opXADD_l_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCMPXCHG8B_a32,opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
};
#endif
const OpFn OP_TABLE(pentiummmx_0f)[1024] =
{
/*16-bit data, 16-bit addr*/
@@ -1277,12 +1371,12 @@ const OpFn OP_TABLE(c6x86mx_0f)[1024] =
/*00*/ op0F00_a16, op0F01_w_a16, opLAR_w_a16, opLSL_w_a16, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, opRDPMC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, opRDPMC, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ opCMOVO_w_a16, opCMOVNO_w_a16, opCMOVB_w_a16, opCMOVNB_w_a16, opCMOVE_w_a16, opCMOVNE_w_a16, opCMOVBE_w_a16, opCMOVNBE_w_a16,opCMOVS_w_a16, opCMOVNS_w_a16, opCMOVP_w_a16, opCMOVNP_w_a16, opCMOVL_w_a16, opCMOVNL_w_a16, opCMOVLE_w_a16, opCMOVNLE_w_a16,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ opPUNPCKLBW_a16,opPUNPCKLWD_a16,opPUNPCKLDQ_a16,opPACKSSWB_a16, opPCMPGTB_a16, opPCMPGTW_a16, opPCMPGTD_a16, opPACKUSWB_a16, opPUNPCKHBW_a16,opPUNPCKHWD_a16,opPUNPCKHDQ_a16,opPACKSSDW_a16, ILLEGAL, ILLEGAL, opMOVD_l_mm_a16,opMOVQ_q_mm_a16,
/*70*/ ILLEGAL, opPSxxW_imm, opPSxxD_imm, opPSxxQ_imm, opPCMPEQB_a16, opPCMPEQW_a16, opPCMPEQD_a16, opEMMS, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opMOVD_mm_l_a16,opMOVQ_mm_q_a16,
/*70*/ ILLEGAL, opPSxxW_imm, opPSxxD_imm, opPSxxQ_imm, opPCMPEQB_a16, opPCMPEQW_a16, opPCMPEQD_a16, opEMMS, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opMOVD_mm_l_a16_cx,opMOVQ_mm_q_a16,
/*80*/ opJO_w, opJNO_w, opJB_w, opJNB_w, opJE_w, opJNE_w, opJBE_w, opJNBE_w, opJS_w, opJNS_w, opJP_w, opJNP_w, opJL_w, opJNL_w, opJLE_w, opJNLE_w,
/*90*/ opSETO_a16, opSETNO_a16, opSETB_a16, opSETNB_a16, opSETE_a16, opSETNE_a16, opSETBE_a16, opSETNBE_a16, opSETS_a16, opSETNS_a16, opSETP_a16, opSETNP_a16, opSETL_a16, opSETNL_a16, opSETLE_a16, opSETNLE_a16,
@@ -1299,12 +1393,12 @@ const OpFn OP_TABLE(c6x86mx_0f)[1024] =
/*00*/ op0F00_a16, op0F01_l_a16, opLAR_l_a16, opLSL_l_a16, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, opRDPMC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, opRDPMC, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ opCMOVO_l_a16, opCMOVNO_l_a16, opCMOVB_l_a16, opCMOVNB_l_a16, opCMOVE_l_a16, opCMOVNE_l_a16, opCMOVBE_l_a16, opCMOVNBE_l_a16,opCMOVS_l_a16, opCMOVNS_l_a16, opCMOVP_l_a16, opCMOVNP_l_a16, opCMOVL_l_a16, opCMOVNL_l_a16, opCMOVLE_l_a16, opCMOVNLE_l_a16,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ opPUNPCKLBW_a16,opPUNPCKLWD_a16,opPUNPCKLDQ_a16,opPACKSSWB_a16, opPCMPGTB_a16, opPCMPGTW_a16, opPCMPGTD_a16, opPACKUSWB_a16, opPUNPCKHBW_a16,opPUNPCKHWD_a16,opPUNPCKHDQ_a16,opPACKSSDW_a16, ILLEGAL, ILLEGAL, opMOVD_l_mm_a16,opMOVQ_q_mm_a16,
/*70*/ ILLEGAL, opPSxxW_imm, opPSxxD_imm, opPSxxQ_imm, opPCMPEQB_a16, opPCMPEQW_a16, opPCMPEQD_a16, opEMMS, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opMOVD_mm_l_a16,opMOVQ_mm_q_a16,
/*70*/ ILLEGAL, opPSxxW_imm, opPSxxD_imm, opPSxxQ_imm, opPCMPEQB_a16, opPCMPEQW_a16, opPCMPEQD_a16, opEMMS, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opMOVD_mm_l_a16_cx,opMOVQ_mm_q_a16,
/*80*/ opJO_l, opJNO_l, opJB_l, opJNB_l, opJE_l, opJNE_l, opJBE_l, opJNBE_l, opJS_l, opJNS_l, opJP_l, opJNP_l, opJL_l, opJNL_l, opJLE_l, opJNLE_l,
/*90*/ opSETO_a16, opSETNO_a16, opSETB_a16, opSETNB_a16, opSETE_a16, opSETNE_a16, opSETBE_a16, opSETNBE_a16, opSETS_a16, opSETNS_a16, opSETP_a16, opSETNP_a16, opSETL_a16, opSETNL_a16, opSETLE_a16, opSETNLE_a16,
@@ -1321,12 +1415,12 @@ const OpFn OP_TABLE(c6x86mx_0f)[1024] =
/*00*/ op0F00_a32, op0F01_w_a32, opLAR_w_a32, opLSL_w_a32, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, opRDPMC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, opRDPMC, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ opCMOVO_w_a32, opCMOVNO_w_a32, opCMOVB_w_a32, opCMOVNB_w_a32, opCMOVE_w_a32, opCMOVNE_w_a32, opCMOVBE_w_a32, opCMOVNBE_w_a32,opCMOVS_w_a32, opCMOVNS_w_a32, opCMOVP_w_a32, opCMOVNP_w_a32, opCMOVL_w_a32, opCMOVNL_w_a32, opCMOVLE_w_a32, opCMOVNLE_w_a32,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ opPUNPCKLBW_a32,opPUNPCKLWD_a32,opPUNPCKLDQ_a32,opPACKSSWB_a32, opPCMPGTB_a32, opPCMPGTW_a32, opPCMPGTD_a32, opPACKUSWB_a32, opPUNPCKHBW_a32,opPUNPCKHWD_a32,opPUNPCKHDQ_a32,opPACKSSDW_a32, ILLEGAL, ILLEGAL, opMOVD_l_mm_a32,opMOVQ_q_mm_a32,
/*70*/ ILLEGAL, opPSxxW_imm, opPSxxD_imm, opPSxxQ_imm, opPCMPEQB_a32, opPCMPEQW_a32, opPCMPEQD_a32, opEMMS, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opMOVD_mm_l_a32,opMOVQ_mm_q_a32,
/*70*/ ILLEGAL, opPSxxW_imm, opPSxxD_imm, opPSxxQ_imm, opPCMPEQB_a32, opPCMPEQW_a32, opPCMPEQD_a32, opEMMS, opSVDC_a32, opRSDC_a32, opSVLDT_a32, opRSLDT_a32, opSVTS_a32, opRSTS_a32, opMOVD_mm_l_a32_cx,opMOVQ_mm_q_a32,
/*80*/ opJO_w, opJNO_w, opJB_w, opJNB_w, opJE_w, opJNE_w, opJBE_w, opJNBE_w, opJS_w, opJNS_w, opJP_w, opJNP_w, opJL_w, opJNL_w, opJLE_w, opJNLE_w,
/*90*/ opSETO_a32, opSETNO_a32, opSETB_a32, opSETNB_a32, opSETE_a32, opSETNE_a32, opSETBE_a32, opSETNBE_a32, opSETS_a32, opSETNS_a32, opSETP_a32, opSETNP_a32, opSETL_a32, opSETNL_a32, opSETLE_a32, opSETNLE_a32,
@@ -1343,12 +1437,12 @@ const OpFn OP_TABLE(c6x86mx_0f)[1024] =
/*00*/ op0F00_a32, op0F01_l_a32, opLAR_l_a32, opLSL_l_a32, ILLEGAL, ILLEGAL, opCLTS, ILLEGAL, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, opRDPMC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ opWRMSR, opRDTSC, opRDMSR, opRDPMC, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ opCMOVO_l_a32, opCMOVNO_l_a32, opCMOVB_l_a32, opCMOVNB_l_a32, opCMOVE_l_a32, opCMOVNE_l_a32, opCMOVBE_l_a32, opCMOVNBE_l_a32,opCMOVS_l_a32, opCMOVNS_l_a32, opCMOVP_l_a32, opCMOVNP_l_a32, opCMOVL_l_a32, opCMOVNL_l_a32, opCMOVLE_l_a32, opCMOVNLE_l_a32,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ opPUNPCKLBW_a32,opPUNPCKLWD_a32,opPUNPCKLDQ_a32,opPACKSSWB_a32, opPCMPGTB_a32, opPCMPGTW_a32, opPCMPGTD_a32, opPACKUSWB_a32, opPUNPCKHBW_a32,opPUNPCKHWD_a32,opPUNPCKHDQ_a32,opPACKSSDW_a32, ILLEGAL, ILLEGAL, opMOVD_l_mm_a32,opMOVQ_q_mm_a32,
/*70*/ ILLEGAL, opPSxxW_imm, opPSxxD_imm, opPSxxQ_imm, opPCMPEQB_a32, opPCMPEQW_a32, opPCMPEQD_a32, opEMMS, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opMOVD_mm_l_a32,opMOVQ_mm_q_a32,
/*70*/ ILLEGAL, opPSxxW_imm, opPSxxD_imm, opPSxxQ_imm, opPCMPEQB_a32, opPCMPEQW_a32, opPCMPEQD_a32, opEMMS, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opMOVD_mm_l_a32_cx,opMOVQ_mm_q_a32,
/*80*/ opJO_l, opJNO_l, opJB_l, opJNB_l, opJE_l, opJNE_l, opJBE_l, opJNBE_l, opJS_l, opJNS_l, opJP_l, opJNP_l, opJL_l, opJNL_l, opJLE_l, opJNLE_l,
/*90*/ opSETO_a32, opSETNO_a32, opSETB_a32, opSETNB_a32, opSETE_a32, opSETNE_a32, opSETBE_a32, opSETNBE_a32, opSETS_a32, opSETNS_a32, opSETP_a32, opSETNP_a32, opSETL_a32, opSETNL_a32, opSETLE_a32, opSETNLE_a32,

1
src/cpu/808x.c
View File

@@ -964,6 +964,7 @@ reset_common(int hard)
in_sys = 0;
shadowbios = shadowbios_write = 0;
alt_access = cpu_end_block_after_ins = 0;
}

122
src/cpu/codegen_timing_common.c
View File

@@ -10,41 +10,41 @@
uint64_t opcode_deps[256] =
{
/* ADD ADD ADD ADD*/
/*00*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* ADD ADD PUSH ES POP ES*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
/* OR OR OR OR*/
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* OR OR PUSH CS*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, 0,
/* ADD ADD ADD ADD*/
/*00*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* ADD ADD PUSH ES POP ES*/
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, IMPL_ESP, IMPL_ESP,
/* OR OR OR OR*/
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* OR OR PUSH CS*/
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, IMPL_ESP, 0,
/* ADC ADC ADC ADC*/
/*10*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* ADC ADC PUSH SS POP SS*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
/* SBB SBB SBB SBB*/
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* SBB SBB PUSH DS POP DS*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
/* ADC ADC ADC ADC*/
/*10*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* ADC ADC PUSH SS POP SS*/
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, IMPL_ESP, IMPL_ESP,
/* SBB SBB SBB SBB*/
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* SBB SBB PUSH DS POP DS*/
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, IMPL_ESP, IMPL_ESP,
/* AND AND AND AND*/
/*20*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* AND AND DAA*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
/* SUB SUB SUB SUB*/
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* SUB SUB DAS*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
/* AND AND AND AND*/
/*20*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* AND AND DAA*/
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, 0, SRCDEP_EAX | DSTDEP_EAX,
/* SUB SUB SUB SUB*/
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* SUB SUB DAS*/
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, 0, SRCDEP_EAX | DSTDEP_EAX,
/* XOR XOR XOR XOR*/
/*30*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* XOR XOR AAA*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
/* CMP CMP CMP CMP*/
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | MODRM,
/* CMP CMP AAS*/
SRCDEP_EAX, SRCDEP_EAX, 0, SRCDEP_EAX | DSTDEP_EAX,
/* XOR XOR XOR XOR*/
/*30*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
/* XOR XOR AAA*/
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, 0, SRCDEP_EAX | DSTDEP_EAX,
/* CMP CMP CMP CMP*/
SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | MODRM,
/* CMP CMP AAS*/
SRCDEP_EAX | HAS_IMM8, SRCDEP_EAX | HAS_IMM1632, 0, SRCDEP_EAX | DSTDEP_EAX,
/* INC EAX INC ECX INC EDX INC EBX*/
/*40*/ SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
@@ -68,7 +68,7 @@ uint64_t opcode_deps[256] =
/*60*/ IMPL_ESP, IMPL_ESP, 0, 0,
0, 0, 0, 0,
/* PUSH imm IMUL PUSH imm IMUL*/
IMPL_ESP, DSTDEP_REG | MODRM, IMPL_ESP, DSTDEP_REG | MODRM,
IMPL_ESP | HAS_IMM1632,DSTDEP_REG | MODRM, IMPL_ESP | HAS_IMM8, DSTDEP_REG | MODRM,
/* INSB INSW OUTSB OUTSW*/
0, 0, 0, 0,
@@ -102,15 +102,15 @@ uint64_t opcode_deps[256] =
0, 0, 0, 0,
/* MOV*/
/*b0*/ DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
DSTDEP_ESP, DSTDEP_EBP, DSTDEP_ESI, DSTDEP_EDI,
/*b0*/ DSTDEP_EAX | HAS_IMM8, DSTDEP_ECX | HAS_IMM8, DSTDEP_EDX | HAS_IMM8, DSTDEP_EBX | HAS_IMM8,
DSTDEP_EAX | HAS_IMM8, DSTDEP_ECX | HAS_IMM8, DSTDEP_EDX | HAS_IMM8, DSTDEP_EBX | HAS_IMM8,
DSTDEP_EAX | HAS_IMM1632, DSTDEP_ECX | HAS_IMM1632, DSTDEP_EDX | HAS_IMM1632, DSTDEP_EBX | HAS_IMM1632,
DSTDEP_ESP | HAS_IMM1632, DSTDEP_EBP | HAS_IMM1632, DSTDEP_ESI | HAS_IMM1632, DSTDEP_EDI | HAS_IMM1632,
/* RET imm RET*/
/*c0*/ 0, 0, SRCDEP_ESP | DSTDEP_ESP, IMPL_ESP,
/* LES LDS MOV MOV*/
DSTDEP_REG | MODRM, DSTDEP_REG | MODRM, MODRM, MODRM,
DSTDEP_REG | MODRM, DSTDEP_REG | MODRM, MODRM | HAS_IMM8, MODRM | HAS_IMM1632,
/* ENTER LEAVE RETF RETF*/
IMPL_ESP, IMPL_ESP, IMPL_ESP, IMPL_ESP,
/* INT3 INT INTO IRET*/
@@ -147,38 +147,38 @@ uint64_t opcode_deps_mod3[256] =
/* ADD ADD ADD ADD*/
/*00*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
/* ADD ADD PUSH ES POP ES*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, IMPL_ESP, IMPL_ESP,
/* OR OR OR OR*/
SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
/* OR OR PUSH CS*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, 0,
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, IMPL_ESP, 0,
/* ADC ADC ADC ADC*/
/*10*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
/* ADC ADC PUSH SS POP SS*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, IMPL_ESP, IMPL_ESP,
/* SBB SBB SBB SBB*/
SRCDEP_REG |SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
/* SBB SBB PUSH DS POP DS*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, IMPL_ESP, IMPL_ESP,
/* AND AND AND AND*/
/*20*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
/* AND AND DAA*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, 0, SRCDEP_EAX | DSTDEP_EAX,
/* SUB SUB SUB SUB*/
SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
/* SUB SUB DAS*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, 0, SRCDEP_EAX | DSTDEP_EAX,
/* XOR XOR XOR XOR*/
/*30*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
/* XOR XOR AAA*/
SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
SRCDEP_EAX | DSTDEP_EAX | HAS_IMM8, SRCDEP_EAX | DSTDEP_EAX | HAS_IMM1632, 0, SRCDEP_EAX | DSTDEP_EAX,
/* CMP CMP CMP CMP*/
SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM,
/* CMP CMP AAS*/
SRCDEP_EAX, SRCDEP_EAX, 0, SRCDEP_EAX | DSTDEP_EAX,
SRCDEP_EAX | HAS_IMM8, SRCDEP_EAX | HAS_IMM1632, 0, SRCDEP_EAX | DSTDEP_EAX,
/* INC EAX INC ECX INC EDX INC EBX*/
/*40*/ SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
@@ -202,7 +202,7 @@ uint64_t opcode_deps_mod3[256] =
/*60*/ IMPL_ESP, IMPL_ESP, 0, 0,
0, 0, 0, 0,
/* PUSH imm IMUL PUSH imm IMUL*/
IMPL_ESP, DSTDEP_REG | SRCDEP_RM | MODRM, IMPL_ESP, DSTDEP_REG | SRCDEP_RM | MODRM,
IMPL_ESP | HAS_IMM1632,DSTDEP_REG | SRCDEP_RM | MODRM, IMPL_ESP | HAS_IMM8, DSTDEP_REG | SRCDEP_RM | MODRM,
/* INSB INSW OUTSB OUTSW*/
0, 0, 0, 0,
@@ -236,19 +236,19 @@ uint64_t opcode_deps_mod3[256] =
0, 0, 0, 0,
/* MOV*/
/*b0*/ DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
DSTDEP_ESP, DSTDEP_EBP, DSTDEP_ESI, DSTDEP_EDI,
/*b0*/ DSTDEP_EAX | HAS_IMM8, DSTDEP_ECX | HAS_IMM8, DSTDEP_EDX | HAS_IMM8, DSTDEP_EBX | HAS_IMM8,
DSTDEP_EAX | HAS_IMM8, DSTDEP_ECX | HAS_IMM8, DSTDEP_EDX | HAS_IMM8, DSTDEP_EBX | HAS_IMM8,
DSTDEP_EAX | HAS_IMM1632, DSTDEP_ECX | HAS_IMM1632, DSTDEP_EDX | HAS_IMM1632, DSTDEP_EBX | HAS_IMM1632,
DSTDEP_ESP | HAS_IMM1632, DSTDEP_EBP | HAS_IMM1632, DSTDEP_ESI | HAS_IMM1632, DSTDEP_EDI | HAS_IMM1632,
/* RET imm RET*/
/*c0*/ 0, 0, SRCDEP_ESP | DSTDEP_ESP, IMPL_ESP,
/* LES LDS MOV MOV*/
DSTDEP_REG | MODRM, DSTDEP_REG | MODRM, DSTDEP_RM | MODRM, DSTDEP_RM | MODRM,
/* ENTER LEAVE RETF RETF*/
IMPL_ESP, IMPL_ESP, IMPL_ESP, IMPL_ESP,
/* INT3 INT INTO IRET*/
0, 0, 0, 0,
/* RET imm RET*/
/*c0*/ 0, 0, SRCDEP_ESP | DSTDEP_ESP, IMPL_ESP,
/* LES LDS MOV MOV*/
DSTDEP_REG | MODRM, DSTDEP_REG | MODRM, DSTDEP_RM | MODRM | HAS_IMM8, DSTDEP_RM | MODRM | HAS_IMM1632,
/* ENTER LEAVE RETF RETF*/
IMPL_ESP, IMPL_ESP, IMPL_ESP, IMPL_ESP,
/* INT3 INT INTO IRET*/
0, 0, 0, 0,
/*d0*/ 0, 0, 0, 0,
@@ -331,7 +331,7 @@ uint64_t opcode_deps_0f[256] =
/*a0*/ MODRM, MODRM, MODRM, MODRM,
MODRM, MODRM, 0, 0,
MODRM, MODRM, 0, MODRM,
MODRM, MODRM, 0, MODRM,
MODRM, MODRM, MODRM, MODRM,
/*b0*/ MODRM, MODRM, MODRM, MODRM,
MODRM, MODRM, MODRM, MODRM,
@@ -413,7 +413,7 @@ uint64_t opcode_deps_0f_mod3[256] =
/*a0*/ MODRM, MODRM, MODRM, MODRM,
MODRM, MODRM, 0, 0,
MODRM, MODRM, 0, MODRM,
MODRM, MODRM, 0, MODRM,
MODRM, MODRM, MODRM, MODRM,
/*b0*/ MODRM, MODRM, MODRM, MODRM,
MODRM, MODRM, MODRM, MODRM,

82
src/cpu/cpu.c
View File

@@ -61,6 +61,18 @@
#endif
#include "x87_timings.h"
#define CCR1_USE_SMI (1 << 1)
#define CCR1_SMAC (1 << 2)
#define CCR1_SM3 (1 << 7)
#define CCR3_SMI_LOCK (1 << 0)
#define CCR3_NMI_EN (1 << 1)
cyrix_t cyrix;
static void cpu_write(uint16_t addr, uint8_t val, void *priv);
static uint8_t cpu_read(uint16_t addr, void *priv);
@@ -169,7 +181,7 @@ int is286,
hascache,
isibm486,
israpidcad,
is_am486, is_pentium, is_k5, is_k6, is_p6;
is_am486, is_pentium, is_k5, is_k6, is_p6, is_cx6x86;
int hasfpu;
@@ -251,6 +263,8 @@ int timing_misaligned;
static uint8_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6;
static int cyrix_addr;
#ifdef ENABLE_CPU_LOG
int cpu_do_log = ENABLE_CPU_LOG;
@@ -399,6 +413,13 @@ cpu_set(void)
(cpu_s->cpu_type == CPU_PENTIUM2D);
/* The Samuel 2 datasheet claims it's Celeron-compatible. */
is_p6 |= (cpu_s->cpu_type == CPU_CYRIX3S);
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
is_cx6x86 = (cpu_s->cpu_type == CPU_PENTIUMPRO) || (cpu_s->cpu_type == CPU_PENTIUM2) ||
(cpu_s->cpu_type == CPU_PENTIUM2D);
#else
is_cx6x86 = (cpu_s->cpu_type == CPU_Cx6x86) || (cpu_s->cpu_type == CPU_Cx6x86MX) ||
(cpu_s->cpu_type == CPU_Cx6x86L) || (cpu_s->cpu_type == CPU_CxGX1);
#endif
hasfpu = (fpu_type != FPU_NONE);
hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL);
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
@@ -444,10 +465,13 @@ cpu_set(void)
else
io_removehandler(0x0022, 0x0002, cpu_read, NULL, NULL, cpu_write, NULL, NULL, NULL);
if (hasfpu)
if (hasfpu) {
io_sethandler(0x00f0, 0x000f, cpu_read, NULL, NULL, cpu_write, NULL, NULL, NULL);
else
io_sethandler(0xf007, 0x0001, cpu_read, NULL, NULL, cpu_write, NULL, NULL, NULL);
} else {
io_removehandler(0x00f0, 0x000f, cpu_read, NULL, NULL, cpu_write, NULL, NULL, NULL);
io_removehandler(0xf007, 0x0001, cpu_read, NULL, NULL, cpu_write, NULL, NULL, NULL);
}
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_386_0f, dynarec_ops_386, dynarec_ops_386_0f);
@@ -548,6 +572,7 @@ cpu_set(void)
timing_misaligned = 0;
cpu_cyrix_alignment = 0;
cpu_CR4_mask = 0;
switch (cpu_s->cpu_type)
{
@@ -1191,9 +1216,9 @@ cpu_set(void)
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
case CPU_Cx6x86:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
x86_setopcodes(ops_386, ops_c6x86_0f, dynarec_ops_386, dynarec_ops_c6x86_0f);
#else
x86_setopcodes(ops_386, ops_pentium_0f);
x86_setopcodes(ops_386, ops_c6x86_0f);
#endif
timing_rr = 1; /*register dest - register src*/
timing_rm = 1; /*register dest - memory src*/
@@ -2366,10 +2391,7 @@ cpu_CPUID(void)
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR/* | CPUID_SEP*/ | CPUID_CMOV;
#ifdef USE_SEP
EDX |= CPUID_SEP;
#endif
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_SEP | CPUID_CMOV;
}
else if (EAX == 2)
{
@@ -2393,10 +2415,7 @@ cpu_CPUID(void)
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR/* | CPUID_SEP*/ | CPUID_FXSR | CPUID_CMOV;
#ifdef USE_SEP
EDX |= CPUID_SEP;
#endif
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
}
else if (EAX == 2)
{
@@ -3555,8 +3574,6 @@ i686_invalid_wrmsr:
}
}
static int cyrix_addr;
static void cpu_write(uint16_t addr, uint8_t val, void *priv)
{
if (addr == 0xf0) {
@@ -3577,14 +3594,46 @@ static void cpu_write(uint16_t addr, uint8_t val, void *priv)
ccr0 = val;
break;
case 0xc1: /*CCR1*/
if ((ccr3 & CCR3_SMI_LOCK) && !in_smm)
val = (val & ~(CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3)) | (ccr1 & (CCR1_USE_SMI | CCR1_SMAC | CCR1_SM3));
ccr1 = val;
break;
case 0xc2: /*CCR2*/
ccr2 = val;
break;
case 0xc3: /*CCR3*/
if ((ccr3 & CCR3_SMI_LOCK) && !in_smm)
val = (val & ~(CCR3_NMI_EN)) | (ccr3 & CCR3_NMI_EN) | CCR3_SMI_LOCK;
ccr3 = val;
break;
case 0xcd:
if (!(ccr3 & CCR3_SMI_LOCK) || in_smm)
{
cyrix.arr[3].base = (cyrix.arr[3].base & ~0xff000000) | (val << 24);
cyrix.smhr &= ~SMHR_VALID;
}
break;
case 0xce:
if (!(ccr3 & CCR3_SMI_LOCK) || in_smm)
{
cyrix.arr[3].base = (cyrix.arr[3].base & ~0x00ff0000) | (val << 16);
cyrix.smhr &= ~SMHR_VALID;
}
break;
case 0xcf:
if (!(ccr3 & CCR3_SMI_LOCK) || in_smm)
{
cyrix.arr[3].base = (cyrix.arr[3].base & ~0x0000f000) | ((val & 0xf0) << 8);
if ((val & 0xf) == 0xf)
cyrix.arr[3].size = 1ull << 32; /*4 GB*/
else if (val & 0xf)
cyrix.arr[3].size = 2048 << (val & 0xf);
else
cyrix.arr[3].size = 0; /*Disabled*/
cyrix.smhr &= ~SMHR_VALID;
}
break;
case 0xe8: /*CCR4*/
if ((ccr3 & 0xf0) == 0x10)
{
@@ -3613,6 +3662,9 @@ static void cpu_write(uint16_t addr, uint8_t val, void *priv)
static uint8_t cpu_read(uint16_t addr, void *priv)
{
if (addr == 0xf007)
return 0x7f;
if (addr >= 0xf0)
return 0xff; /* FPU stuff */

29
src/cpu/cpu.h
View File

@@ -150,6 +150,7 @@ extern CPU cpus_i486S1[];
extern CPU cpus_Am486S1[];
extern CPU cpus_Cx486S1[];
extern CPU cpus_i486[];
extern CPU cpus_i486_PC330[];
extern CPU cpus_Am486[];
extern CPU cpus_Cx486[];
#if defined(DEV_BRANCH) && defined(USE_STPC)
@@ -225,7 +226,8 @@ typedef struct {
uint8_t access, ar_high;
int8_t checked; /*Non-zero if selector is known to be valid*/
uint16_t seg;
uint32_t base, limit,
uint32_t base,
limit, limit_raw,
limit_low, limit_high;
} x86seg;
@@ -311,6 +313,7 @@ typedef struct {
#define CPU_STATUS_STACK32 (1 << 1)
#define CPU_STATUS_PMODE (1 << 2)
#define CPU_STATUS_V86 (1 << 3)
#define CPU_STATUS_SMM (1 << 4)
#define CPU_STATUS_FLAGS 0xffff
/*If the cpu_state.flags below are set in cpu_cur_status, they must be set in block->status.
@@ -388,7 +391,7 @@ extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
penalties when crossing 8-byte boundaries*/
extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4;
extern int is_am486, is_pentium, is_k5, is_k6, is_p6;
extern int is_am486, is_pentium, is_k5, is_k6, is_p6, is_cx6x86;
extern int hascache;
extern int isibm486;
extern int is_rapidcad;
@@ -492,7 +495,8 @@ extern uint32_t old_rammask;
extern int acycs;
#endif
extern int pic_pending, is_vpc;
extern int soft_reset_mask;
extern int soft_reset_mask, alt_access;
extern int cpu_end_block_after_ins;
extern uint16_t cpu_fast_off_count, cpu_fast_off_val;
extern uint32_t cpu_fast_off_flags;
@@ -590,4 +594,23 @@ extern const char *fpu_get_internal_name(int machine, int cpu_manufacturer, int
extern const char *fpu_get_name_from_index(int machine, int cpu_manufacturer, int cpu, int c);
extern int fpu_get_type_from_index(int machine, int cpu_manufacturer, int cpu, int c);
void cyrix_load_seg_descriptor(uint32_t addr, x86seg *seg);
void cyrix_write_seg_descriptor(uint32_t addr, x86seg *seg);
#define SMHR_VALID (1 << 0)
#define SMHR_ADDR_MASK (0xfffffffc)
typedef struct
{
struct
{
uint32_t base;
uint64_t size;
} arr[8];
uint32_t smhr;
} cyrix_t;
extern cyrix_t cyrix;
#endif /*EMU_CPU_H*/

13
src/cpu/cpu_table.c
View File

@@ -342,6 +342,17 @@ CPU cpus_i486[] = {
{"", -1, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0, 0}
};
CPU cpus_i486_PC330[] = {
/*i486/P24T*/
{"i486DX2/50", CPU_i486DX2, fpus_internal, 50000000, 2.0, 0x470, 0x470, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
{"i486DX2/66", CPU_i486DX2, fpus_internal, 66666666, 2.0, 0x470, 0x470, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"iDX4/75", CPU_iDX4, fpus_internal, 75000000, 3.0, 0x480, 0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, /*CPUID available on DX4, >= 75 MHz*/
{"iDX4/100", CPU_iDX4, fpus_internal, 100000000, 3.0, 0x483, 0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"Pentium OverDrive 63", CPU_P24T, fpus_internal, 62500000, 2.5, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"Pentium OverDrive 83", CPU_P24T, fpus_internal, 83333333, 2.5, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"", -1, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0, 0}
};
CPU cpus_Am486[] = {
/*Am486/5x86*/
{"Am486SX/33", CPU_Am486SX, fpus_486sx, 33333333, 1.0, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
@@ -579,7 +590,7 @@ CPU cpus_Pentium3V[] = {
CPU cpus_Pentium[] = {
/*Intel Pentium*/
{"Pentium 75", CPU_PENTIUM, fpus_internal, 75000000, 1.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium 75", CPU_PENTIUM, fpus_internal, 75000000, 1.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC /*| CPU_REQUIRES_DYNAREC*/, 7, 7, 4, 4, 9},
{"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, fpus_internal, 75000000, 1.5, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
{"Pentium 90", CPU_PENTIUM, fpus_internal, 90000000, 1.5, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2},
{"Pentium 100/50", CPU_PENTIUM, fpus_internal, 100000000, 2.0, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},

12
src/cpu/x86.h
View File

@@ -1,3 +1,14 @@
#define ABRT_MASK 0x7f
/*An 'expected' exception is one that would be expected to occur on every execution
of this code path; eg a GPF due to being in v86 mode. An 'unexpected' exception is
one that would be unlikely to occur on the next exception, eg a page fault may be
fixed up by the exception handler and the next execution would not hit it.
This distinction is used by the dynarec; a block that hits an 'expected' exception
would be compiled, a block that hits an 'unexpected' exception would be rejected so
that we don't end up with an unnecessarily short block*/
#define ABRT_EXPECTED 0x80
extern uint8_t opcode, opcode2;
extern uint8_t flags_p;
extern uint8_t znptable8[256];
@@ -68,3 +79,4 @@ extern void x86_doabrt(int x86_abrt);
extern void x86illegal();
extern void x86seg_reset();
extern void x86gpf(char *s, uint16_t error);
extern void x86gpf_expected(char *s, uint16_t error);

2
src/cpu/x86_ops.h
View File

@@ -88,6 +88,7 @@ extern const OpFn dynarec_ops_pentium_0f[1024];
extern const OpFn dynarec_ops_pentiummmx_0f[1024];
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
extern const OpFn dynarec_ops_c6x86_0f[1024];
extern const OpFn dynarec_ops_c6x86mx_0f[1024];
#endif
@@ -184,6 +185,7 @@ extern const OpFn ops_pentium_0f[1024];
extern const OpFn ops_pentiummmx_0f[1024];
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
extern const OpFn ops_c6x86_0f[1024];
extern const OpFn ops_c6x86mx_0f[1024];
#endif

274
src/cpu/x86_ops_cyrix.h Normal file
View File

@@ -0,0 +1,274 @@
/*Cyrix-only instructions*/
/*System Management Mode*/
static void opSVDC_common(uint32_t fetchdat)
{
switch (rmdat & 0x38)
{
case 0x00: /*ES*/
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_es);
writememw(0, easeg+cpu_state.eaaddr+8, ES);
break;
case 0x08: /*CS*/
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_cs);
writememw(0, easeg+cpu_state.eaaddr+8, CS);
break;
case 0x18: /*DS*/
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_ds);
writememw(0, easeg+cpu_state.eaaddr+8, DS);
break;
case 0x10: /*SS*/
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_ss);
writememw(0, easeg+cpu_state.eaaddr+8, SS);
break;
case 0x20: /*FS*/
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_fs);
writememw(0, easeg+cpu_state.eaaddr+8, FS);
break;
case 0x28: /*GS*/
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_gs);
writememw(0, easeg+cpu_state.eaaddr+8, GS);
break;
default:
pclog("opSVDC: unknown rmdat %02x\n", rmdat);
x86illegal();
}
}
static int opSVDC_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
opSVDC_common(fetchdat);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opSVDC_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
opSVDC_common(fetchdat);
}
else
x86illegal();
return cpu_state.abrt;
}
static void opRSDC_common(uint32_t fetchdat)
{
switch (rmdat & 0x38)
{
case 0x00: /*ES*/
cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_es);
break;
case 0x18: /*DS*/
cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_ds);
break;
case 0x10: /*SS*/
cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_ss);
break;
case 0x20: /*FS*/
cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_fs);
break;
case 0x28: /*GS*/
cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_gs);
break;
default:
pclog("opRSDC: unknown rmdat %02x\n", rmdat);
x86illegal();
}
}
static int opRSDC_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_16(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
opRSDC_common(fetchdat);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opRSDC_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_32(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
opRSDC_common(fetchdat);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opSVLDT_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &ldt);
writememw(0, easeg+cpu_state.eaaddr+8, ldt.seg);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opSVLDT_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &ldt);
writememw(0, easeg+cpu_state.eaaddr+8, ldt.seg);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opRSLDT_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_16(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &ldt);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opRSLDT_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_32(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &ldt);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opSVTS_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &tr);
writememw(0, easeg+cpu_state.eaaddr+8, tr.seg);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opSVTS_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &tr);
writememw(0, easeg+cpu_state.eaaddr+8, tr.seg);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opRSTS_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &tr);
writememw(0, easeg+cpu_state.eaaddr+8, tr.seg);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opRSTS_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
{
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &tr);
writememw(0, easeg+cpu_state.eaaddr+8, tr.seg);
}
else
x86illegal();
return cpu_state.abrt;
}
static int opSMINT(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
fatal("opSMINT\n");
else
x86illegal();
return 1;
}
static int opRDSHR_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
fatal("opRDSHR_a16\n");
else
x86illegal();
return 1;
}
static int opRDSHR_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
fatal("opRDSHR_a32\n");
else
x86illegal();
return 1;
}
static int opWRSHR_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
fatal("opWRSHR_a16\n");
else
x86illegal();
return 1;
}
static int opWRSHR_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
fatal("opWRSHR_a32\n");
else
x86illegal();
return 1;
}

6
src/cpu/x86_ops_flag.h
View File

@@ -85,8 +85,10 @@ static int opSTI(uint32_t fetchdat)
else
cpu_state.flags |= I_FLAG;
CPU_BLOCK_END();
/*First instruction after STI will always execute, regardless of whether
there is a pending interrupt*/
cpu_end_block_after_ins = 2;
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
return 0;

2
src/cpu/x86_ops_int.h
View File

@@ -59,7 +59,7 @@ static int opINT(uint32_t fetchdat)
}
}
}
x86gpf(NULL,0);
x86gpf_expected(NULL,0);
return 1;
}

48
src/cpu/x86_ops_mmx_mov.h
View File

@@ -50,7 +50,7 @@ static int opMOVD_l_mm_a32(uint32_t fetchdat)
static int opMOVD_mm_l_a16(uint32_t fetchdat)
{
MMX_ENTER();
fetch_ea_16(fetchdat);
if (cpu_mod == 3)
{
@@ -69,6 +69,52 @@ static int opMOVD_mm_l_a16(uint32_t fetchdat)
static int opMOVD_mm_l_a32(uint32_t fetchdat)
{
MMX_ENTER();
fetch_ea_32(fetchdat);
if (cpu_mod == 3)
{
cpu_state.regs[cpu_rm].l = cpu_state.MM[cpu_reg].l[0];
CLOCK_CYCLES(1);
}
else
{
SEG_CHECK_WRITE(cpu_state.ea_seg);
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
writememl(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
CLOCK_CYCLES(2);
}
return 0;
}
/*Cyrix maps both MOVD and SMINT to the same opcode*/
static int opMOVD_mm_l_a16_cx(uint32_t fetchdat)
{
if (in_smm)
return opSMINT(fetchdat);
MMX_ENTER();
fetch_ea_16(fetchdat);
if (cpu_mod == 3)
{
cpu_state.regs[cpu_rm].l = cpu_state.MM[cpu_reg].l[0];
CLOCK_CYCLES(1);
}
else
{
SEG_CHECK_WRITE(cpu_state.ea_seg);
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
writememl(easeg, cpu_state.eaaddr, cpu_state.MM[cpu_reg].l[0]); if (cpu_state.abrt) return 1;
CLOCK_CYCLES(2);
}
return 0;
}
static int opMOVD_mm_l_a32_cx(uint32_t fetchdat)
{
if (in_smm)
return opSMINT(fetchdat);
MMX_ENTER();
fetch_ea_32(fetchdat);
if (cpu_mod == 3)

8
src/cpu/x86_ops_pmode.h
View File

@@ -163,7 +163,7 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
int dpl, valid, granularity;
uint32_t addr, base, limit;
uint16_t desc, sel;
uint8_t access;
uint8_t access, ar_high;
switch (rmdat & 0x38)
{
@@ -194,10 +194,13 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
base = (readmemw(0, addr + 2)) | (readmemb(0, addr + 4) << 16) | (readmemb(0, addr + 7) << 24);
access = readmemb(0, addr + 5);
ar_high = readmemb(0, addr + 6);
granularity = readmemb(0, addr + 6) & 0x80;
if (cpu_state.abrt) return 1;
ldt.limit = limit;
ldt.limit_raw = limit;
ldt.access = access;
ldt.ar_high = ar_high;
if (granularity)
{
ldt.limit <<= 12;
@@ -221,6 +224,7 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
limit = readmemw(0, addr) + ((readmemb(0, addr + 6) & 0xf) << 16);
base = (readmemw(0, addr + 2)) | (readmemb(0, addr + 4) << 16) | (readmemb(0, addr + 7) << 24);
access = readmemb(0, addr + 5);
ar_high = readmemb(0, addr + 6);
granularity = readmemb(0, addr + 6) & 0x80;
if (cpu_state.abrt) return 1;
access |= 2;
@@ -228,7 +232,9 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
if (cpu_state.abrt) return 1;
tr.seg = sel;
tr.limit = limit;
tr.limit_raw = limit;
tr.access = access;
tr.ar_high = ar_high;
if (granularity)
{
tr.limit <<= 12;

4
src/cpu/x86_ops_ret.h
View File

@@ -175,7 +175,7 @@ static int opIRET(uint32_t fetchdat)
}
else
{
x86gpf(NULL,0);
x86gpf_expected(NULL,0);
return 1;
}
}
@@ -224,7 +224,7 @@ static int opIRETD(uint32_t fetchdat)
if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
x86gpf_expected(NULL,0);
return 1;
}
if (msw & 1)

59
src/cpu/x86seg.c
View File

@@ -168,6 +168,14 @@ x86gpf(char *s, uint16_t error)
}
void
x86gpf_expected(char *s, uint16_t error)
{
cpu_state.abrt = ABRT_GPF | ABRT_EXPECTED;
abrt_error = error;
}
void
x86ss(char *s, uint16_t error)
{
@@ -219,6 +227,7 @@ void
do_seg_load(x86seg *s, uint16_t *segdat)
{
s->limit = segdat[0] | ((segdat[3] & 0x000f) << 16);
s->limit_raw = s->limit;
if (segdat[3] & 0x0080)
s->limit = (s->limit << 12) | 0xfff;
s->base = segdat[1] | ((segdat[2] & 0x00ff) << 16);
@@ -1469,7 +1478,11 @@ pmodeint(int num, int soft)
x86seg_log("Addr %08X seg %04X %04X %04X %04X\n", addr, segdat[0], segdat[1], segdat[2], segdat[3]);
if (!(segdat[2] & 0x1f00)) {
x86gpf("pmodeint(): Vector descriptor with bad type", (num << 3) + 2);
/* This fires on all V86 interrupts in EMM386. Mark as expected to prevent code churn */
if (cpu_state.eflags & VM_FLAG)
x86gpf_expected("pmodeint(): Expected vector descriptor with bad type", (num << 3) + 2);
else
x86gpf("pmodeint(): Vector descriptor with bad type", (num << 3) + 2);
return;
}
if ((DPL < CPL) && soft) {
@@ -2364,3 +2377,47 @@ taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
tr.access = segdat[2] >> 8;
tr.ar_high = segdat[3] & 0xff;
}
void
cyrix_write_seg_descriptor(uint32_t addr, x86seg *seg)
{
writememl(0, addr, (seg->limit_raw & 0xffff) | (seg->base << 16));
writememl(0, addr + 4, ((seg->base >> 16) & 0xff) | (seg->access << 8) |
(seg->limit_raw & 0xf0000) | (seg->ar_high << 16) |
(seg->base & 0xff000000));
}
void
cyrix_load_seg_descriptor(uint32_t addr, x86seg *seg)
{
uint16_t segdat[4], selector;
segdat[0] = readmemw(0, addr);
segdat[1] = readmemw(0, addr + 2);
segdat[2] = readmemw(0, addr + 4);
segdat[3] = readmemw(0, addr + 6);
selector = readmemw(0, addr+8);
if (!cpu_state.abrt) {
do_seg_load(seg, segdat);
seg->seg = selector;
seg->checked = 0;
if (seg == &cpu_state.seg_ds) {
if (seg->base == 0 && seg->limit_low == 0 && seg->limit_high == 0xffffffff)
cpu_cur_status &= ~CPU_STATUS_NOTFLATDS;
else
cpu_cur_status |= CPU_STATUS_NOTFLATDS;
codegen_flat_ds = 0;
}
if (seg == &cpu_state.seg_ss) {
if (seg->base == 0 && seg->limit_low == 0 && seg->limit_high == 0xffffffff)
cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
else
cpu_cur_status |= CPU_STATUS_NOTFLATSS;
set_stack32((segdat[3] & 0x40) ? 1 : 0);
codegen_flat_ss = 0;
}
}
}

3
src/cpu/x86seg.h
View File

@@ -16,3 +16,6 @@
*/
extern void do_seg_load(x86seg *s, uint16_t *segdat);
extern void cyrix_write_seg_descriptor(uint32_t addr, x86seg *seg);
extern void cyrix_load_seg_descriptor(uint32_t addr, x86seg *seg);

2
src/ddma.c
View File

@@ -193,7 +193,7 @@ const device_t ddma_device =
ddma_init,
ddma_close,
NULL,
NULL,
{ NULL },
NULL,
NULL,
NULL

123
src/device.c
View File

@@ -318,6 +318,129 @@ device_available(const device_t *d)
}
int
device_poll(const device_t *d, int x, int y, int z, int b)
{
int c;
for (c = 0; c < DEVICE_MAX; c++) {
if (devices[c] != NULL) {
if (devices[c] == d) {
if (devices[c]->poll)
return(devices[c]->poll(x, y, z, b, device_priv[c]));
}
}
}
return(0);
}
void
device_register_pci_slot(const device_t *d, int device, int type, int inta, int intb, int intc, int intd)
{
int c;
for (c = 0; c < DEVICE_MAX; c++) {
if (devices[c] != NULL) {
if (devices[c] == d) {
if (devices[c]->register_pci_slot)
devices[c]->register_pci_slot(device, type, inta, intb, intc, intd, device_priv[c]);
return;
}
}
}
return;
}
void
device_get_name(const device_t *d, int bus, char *name)
{
char *sbus = NULL, *fbus;
char *tname, pbus[8] = { 0 };
if (d == NULL)
return;
name[0] = 0x00;
if (bus) {
if (d->flags & DEVICE_LPT)
sbus = "LPT";
else if (d->flags & DEVICE_ISA)
sbus = (d->flags & DEVICE_AT) ? "ISA16" : "ISA";
else if (d->flags & DEVICE_CBUS)
sbus = "C-BUS";
else if (d->flags & DEVICE_MCA)
sbus = "MCA";
else if (d->flags & DEVICE_EISA)
sbus = "EISA";
else if (d->flags & DEVICE_VLB)
sbus = "VLB";
else if (d->flags & DEVICE_PCI)
sbus = "PCI";
else if (d->flags & DEVICE_AGP)
sbus = "AGP";
if (sbus != NULL) {
/* First concatenate [<Bus>] before the device's name. */
strcat(name, "[");
strcat(name, sbus);
strcat(name, "] ");
/* Then change string from ISA16 to ISA if applicable. */
if (!strcmp(sbus, "ISA16"))
sbus = "ISA";
else if (!strcmp(sbus, "LPT")) {
sbus = NULL;
strcat(name, d->name);
return;
}
/* Generate the bus string with parentheses. */
strcat(pbus, "(");
strcat(pbus, sbus);
strcat(pbus, ")");
/* Allocate the temporary device name string and set it to all zeroes. */
tname = (char *) malloc(strlen(d->name) + 1);
memset(tname, 0x00, strlen(d->name) + 1);
/* First strip the bus string with parentheses. */
fbus = strstr(d->name, pbus);
if (fbus == d->name)
strcat(tname, d->name + strlen(pbus) + 1);
else if (fbus == NULL)
strcat(tname, d->name);
else {
strncat(tname, d->name, fbus - d->name - 1);
strcat(tname, fbus + strlen(pbus));
}
/* Then also strip the bus string with parentheses. */
fbus = strstr(tname, sbus);
if (fbus == tname)
strcat(name, tname + strlen(sbus) + 1);
/* Special case to not strip the "oPCI" from "Ensoniq AudioPCI". */
else if ((fbus == NULL) || (*(fbus - 1) == 'o'))
strcat(name, tname);
else {
strncat(name, tname, fbus - tname - 1);
strcat(name, fbus + strlen(sbus));
}
/* Free the temporary device name string. */
free(tname);
tname = NULL;
} else
strcat(name, d->name);
} else
strcat(name, d->name);
}
void
device_speed_changed(void)
{

2
src/device/bugger.c
View File

@@ -360,6 +360,6 @@ const device_t bugger_device = {
DEVICE_ISA | DEVICE_AT,
0,
bug_init, bug_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

4
src/device/hwm_gl518sm.c
View File

@@ -296,7 +296,7 @@ const device_t gl518sm_2c_device = {
DEVICE_ISA,
0x2c,
gl518sm_init, gl518sm_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -306,6 +306,6 @@ const device_t gl518sm_2d_device = {
DEVICE_ISA,
0x2d,
gl518sm_init, gl518sm_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

4
src/device/hwm_lm75.c
View File

@@ -261,7 +261,7 @@ const device_t lm75_1_4a_device = {
DEVICE_ISA,
0x14a,
lm75_init, lm75_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -273,6 +273,6 @@ const device_t lm75_w83781d_device = {
DEVICE_ISA,
0,
lm75_init, lm75_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

10
src/device/hwm_lm78.c
View File

@@ -560,7 +560,7 @@ const device_t lm78_device = {
DEVICE_ISA,
0x290 | LM78_SMBUS,
lm78_init, lm78_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -571,7 +571,7 @@ const device_t w83781d_device = {
DEVICE_ISA,
0x290 | LM78_SMBUS | LM78_W83781D,
lm78_init, lm78_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -583,7 +583,7 @@ const device_t as99127f_device = {
DEVICE_ISA,
LM78_SMBUS | LM78_AS99127F_REV1,
lm78_init, lm78_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -594,7 +594,7 @@ const device_t as99127f_rev2_device = {
DEVICE_ISA,
LM78_SMBUS | LM78_AS99127F_REV2,
lm78_init, lm78_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -605,6 +605,6 @@ const device_t w83782d_device = {
DEVICE_ISA,
0x290 | LM78_SMBUS | LM78_W83782D,
lm78_init, lm78_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/device/hwm_vt82c686.c
View File

@@ -193,6 +193,6 @@ const device_t via_vt82c686_hwm_device = {
DEVICE_ISA,
0,
vt82c686_init, vt82c686_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/device/ibm_5161.c
View File

@@ -106,7 +106,7 @@ const device_t ibm_5161_device =
ibm_5161_init,
ibm_5161_close,
NULL,
NULL,
{ NULL },
NULL,
NULL,
NULL

107
src/device/isamem.c
View File

@@ -667,16 +667,14 @@ isamem_close(void *priv)
static const device_config_t ibmxt_config[] =
{
{
"size", "Memory Size", CONFIG_SPINNER, "", 128,
{ { 0 } },
{ { 0 } },
{ 0, 512, 16 }
"size", "Memory Size", CONFIG_SPINNER, "", 128, "",
{ 0, 512, 16 },
{ { 0 } }
},
{
"start", "Start Address", CONFIG_SPINNER, "", 256,
{ { 0 } },
{ { 0 } },
{ 0, 640-64, 64 }
"start", "Start Address", CONFIG_SPINNER, "", 256, "",
{ 0, 640-64, 64 },
{ { 0 } }
},
{
"", "", -1
@@ -688,7 +686,7 @@ static const device_t ibmxt_device = {
DEVICE_ISA,
0,
isamem_init, isamem_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
ibmxt_config
};
@@ -696,16 +694,14 @@ static const device_t ibmxt_device = {
static const device_config_t ibmat_config[] =
{
{
"size", "Memory Size", CONFIG_SPINNER, "", 512,
{ { 0 } },
{ { 0 } },
{ 0, 4096, 512 }
"size", "Memory Size", CONFIG_SPINNER, "", 512, "",
{ 0, 4096, 512 },
{ { 0 } }
},
{
"start", "Start Address", CONFIG_SPINNER, "", 512,
{ { 0 } },
{ { 0 } },
{ 0, 16128, 128 }
"start", "Start Address", CONFIG_SPINNER, "", 512, "",
{ 0, 16128, 128 },
{ { 0 } }
},
{
"", "", -1
@@ -717,7 +713,7 @@ static const device_t ibmat_device = {
DEVICE_ISA,
1,
isamem_init, isamem_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
ibmat_config
};
@@ -725,16 +721,14 @@ static const device_t ibmat_device = {
static const device_config_t p5pak_config[] =
{
{
"size", "Memory Size", CONFIG_SPINNER, "", 128,
{ { 0 } },
{ { 0 } },
{ 0, 384, 64 }
"size", "Memory Size", CONFIG_SPINNER, "", 128, "",
{ 0, 384, 64 },
{ { 0 } }
},
{
"start", "Start Address", CONFIG_SPINNER, "", 512,
{ { 0 } },
{ { 0 } },
{ 64, 576, 64 }
"start", "Start Address", CONFIG_SPINNER, "", 512, "",
{ 64, 576, 64 },
{ { 0 } }
},
{
"", "", -1
@@ -746,7 +740,7 @@ static const device_t p5pak_device = {
DEVICE_ISA,
2,
isamem_init, isamem_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
p5pak_config
};
@@ -755,12 +749,12 @@ static const device_config_t ems5150_config[] =
{
{
"size", "Memory Size", CONFIG_SPINNER, "", 256,
{ { 0 } },
{ { 0 } },
{ 0, 2048, 64 }
"",
{ 0, 2048, 64 },
{ { 0 } }
},
{
"base", "Address", CONFIG_HEX16, "", 0,
"base", "Address", CONFIG_HEX16, "", 0, "", { 0 },
{
{
"Disabled", 0
@@ -792,7 +786,7 @@ static const device_t ems5150_device = {
DEVICE_ISA,
3,
isamem_init, isamem_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
ems5150_config
};
@@ -800,25 +794,22 @@ static const device_t ems5150_device = {
static const device_config_t ev159_config[] =
{
{
"size", "Memory Size", CONFIG_SPINNER, "", 512,
{ { 0 } },
{ { 0 } },
{ 0, 3072, 512 }
"size", "Memory Size", CONFIG_SPINNER, "", 512, "",
{ 0, 3072, 512 },
{ { 0 } }
},
{
"start", "Start Address", CONFIG_SPINNER, "", 0,
{ { 0 } },
{ { 0 } },
{ 0, 16128, 128 }
"start", "Start Address", CONFIG_SPINNER, "", 0, "",
{ 0, 16128, 128 },
{ { 0 } }
},
{
"length", "Contiguous Size", CONFIG_SPINNER, "", 0,
{ { 0 } },
{ { 0 } },
{ 0, 16384, 128 }
"length", "Contiguous Size", CONFIG_SPINNER, "", 0, "",
{ 0, 16384, 128 },
{ { 0 } }
},
{
"width", "I/O Width", CONFIG_SELECTION, "", 0,
"width", "I/O Width", CONFIG_SELECTION, "", 0, "", { 0 },
{
{
"8-bit", 0
@@ -832,7 +823,7 @@ static const device_config_t ev159_config[] =
},
},
{
"speed", "Transfer Speed", CONFIG_SELECTION, "", 0,
"speed", "Transfer Speed", CONFIG_SELECTION, "", 0, "", { 0 },
{
{
"Standard (150ns)", 0
@@ -846,7 +837,7 @@ static const device_config_t ev159_config[] =
}
},
{
"ems", "EMS mode", CONFIG_SELECTION, "", 0,
"ems", "EMS mode", CONFIG_SELECTION, "", 0, "", { 0 },
{
{
"Disabled", 0
@@ -860,7 +851,7 @@ static const device_config_t ev159_config[] =
},
},
{
"base", "Address", CONFIG_HEX16, "", 0x0258,
"base", "Address", CONFIG_HEX16, "", 0x0258, "", { 0 },
{
{
"208H", 0x0208
@@ -898,7 +889,7 @@ static const device_t ev159_device = {
DEVICE_ISA,
10,
isamem_init, isamem_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
ev159_config
};
@@ -907,7 +898,7 @@ static const device_t ev159_device = {
static const device_config_t rampage_config[] =
{
{
"base", "Address", CONFIG_HEX16, "", 0x0258,
"base", "Address", CONFIG_HEX16, "", 0x0258, "", { 0 },
{
{
"208H", 0x0208
@@ -936,7 +927,7 @@ static const device_config_t rampage_config[] =
},
},
{
"frame", "Frame Address", CONFIG_HEX20, "", 0,
"frame", "Frame Address", CONFIG_HEX20, "", 0, "", { 0 },
{
{
"Disabled", 0x00000
@@ -956,7 +947,7 @@ static const device_config_t rampage_config[] =
},
},
{
"width", "I/O Width", CONFIG_SELECTION, "", 8,
"width", "I/O Width", CONFIG_SELECTION, "", 8, "", { 0 },
{
{
"8-bit", 8
@@ -970,7 +961,7 @@ static const device_config_t rampage_config[] =
},
},
{
"speed", "Transfer Speed", CONFIG_SELECTION, "", 0,
"speed", "Transfer Speed", CONFIG_SELECTION, "", 0, "", { 0 },
{
{
"Standard", 0
@@ -985,9 +976,9 @@ static const device_config_t rampage_config[] =
},
{
"size", "Memory Size", CONFIG_SPINNER, "", 128,
{ { 0 } },
{ { 0 } },
{ 0, 8192, 128 }
"",
{ 0, 8192, 128 },
{ 0 }
},
{
"", "", -1
@@ -999,7 +990,7 @@ static const device_t isamem_rampage_device = {
DEVICE_ISA,
11,
isamem_init, isamem_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
rampage_config
};
#endif
@@ -1024,7 +1015,7 @@ static const struct {
#ifdef USE_ISAMEM_IAB
{ "iab", &iab_device },
#endif
{ NULL, NULL }
{ "", NULL }
};

32
src/device/isartc.c
View File

@@ -586,7 +586,7 @@ isartc_close(void *priv)
static const device_config_t ev170_config[] = {
{
"base", "Address", CONFIG_HEX16, "", 0x02C0,
"base", "Address", CONFIG_HEX16, "", 0x02C0, "", { 0 },
{
{
"240H", 0x0240
@@ -600,7 +600,7 @@ static const device_config_t ev170_config[] = {
},
},
{
"irq", "IRQ", CONFIG_SELECTION, "", -1,
"irq", "IRQ", CONFIG_SELECTION, "", -1, "", { 0 },
{
{
"Disabled", -1
@@ -629,14 +629,14 @@ static const device_t ev170_device = {
DEVICE_ISA,
0,
isartc_init, isartc_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
ev170_config
};
static const device_config_t pii147_config[] = {
{
"base", "Address", CONFIG_HEX16, "", 0x0240,
"base", "Address", CONFIG_HEX16, "", 0x0240, "", { 0 },
{
{
"Clock 1", 0x0240
@@ -659,14 +659,14 @@ static const device_t pii147_device = {
DEVICE_ISA,
1,
isartc_init, isartc_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
pii147_config
};
static const device_config_t p5pak_config[] = {
{
"irq", "IRQ", CONFIG_SELECTION, "", -1,
"irq", "IRQ", CONFIG_SELECTION, "", -1, "", { 0 },
{
{
"Disabled", -1
@@ -695,21 +695,20 @@ static const device_t p5pak_device = {
DEVICE_ISA,
2,
isartc_init, isartc_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
p5pak_config
};
static const struct {
const char *name;
const char *internal_name;
const device_t *dev;
} boards[] = {
{ "None", "none", NULL, },
{ "Everex EV-170 Magic I/O", "ev170", &ev170_device, },
{ "DTK PII-147 Hexa I/O Plus", "pii147", &pii147_device, },
{ "Paradise Systems 5-PAK", "p5pak", &p5pak_device, },
{ "", "", NULL, },
{ "none", NULL },
{ "ev170", &ev170_device },
{ "pii147", &pii147_device },
{ "p5pak", &p5pak_device },
{ "", NULL },
};
@@ -723,13 +722,6 @@ isartc_reset(void)
}
char *
isartc_get_name(int board)
{
return((char *)boards[board].name);
}
char *
isartc_get_internal_name(int board)
{

83
src/device/keyboard_at.c
View File

@@ -90,14 +90,15 @@
typedef struct {
uint8_t command, status, out, secr_phase,
uint8_t command, status, old_status, out, old_out, secr_phase,
mem_addr, input_port, output_port, old_output_port,
key_command, output_locked, ami_stat, initialized,
want60, wantirq, key_wantdata, refresh, first_write;
uint8_t mem[0x100];
int last_irq, reset_delay;
int last_irq, old_last_irq,
reset_delay;
uint32_t flags;
@@ -649,22 +650,37 @@ channel_queue_get(uint8_t channel)
static void
add_to_kbc_queue_front(atkbd_t *dev, uint8_t val)
{
dev->wantirq = 0;
picint(0x0000);
dev->out = val;
dev->status |= STAT_OFULL;
dev->status &= ~STAT_IFULL;
dev->status &= ~STAT_MFULL;
dev->last_irq = 0x0000;
}
static int
channel_queue_check(atkbd_t *dev, uint8_t channel)
{
int val;
if (channel >= 0x03)
return;
return 0;
if ((channel == 0x01) && (dev->mem[0] & 0x10))
return;
return 0;
if ((channel == 0x02) && (((dev->flags & KBC_TYPE_MASK) < KBC_TYPE_PS2_NOREF) || (dev->mem[0] & 0x20)))
return;
return 0;
val = channel_queue_get(channel);
if (val == -1)
return;
return 0;
kbc_queue_add(val & 0xff, channel);
return 1;
}
@@ -748,9 +764,10 @@ kbd_poll(void *priv)
}
}
channel_queue_check(dev, 0x00); /* Transfer the next controller byte to the controller queue if there is any. */
channel_queue_check(dev, 0x01); /* Transfer the next keyboard byte to the controller queue if there is any. */
channel_queue_check(dev, 0x02); /* Transfer the next mouse byte to the controller queue if there is any. */
for (i = 0x00; i < 0x03; i++) {
if (channel_queue_check(dev, i))
break;
}
if (dev->reset_delay > 0) {
dev->reset_delay--;
@@ -1168,16 +1185,16 @@ write64_generic(void *priv, uint8_t val)
fixed_bits |= 0x40;
if ((dev->flags & KBC_VEN_MASK) == KBC_VEN_IBM_PS1) {
current_drive = fdc_get_current_drive();
add_data(dev, dev->input_port | fixed_bits | (fdd_is_525(current_drive) ? 0x40 : 0x00));
add_to_kbc_queue_front(dev, dev->input_port | fixed_bits | (fdd_is_525(current_drive) ? 0x40 : 0x00));
dev->input_port = ((dev->input_port + 1) & 3) |
(dev->input_port & 0xfc) |
(fdd_is_525(current_drive) ? 0x40 : 0x00);
} else {
if (((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_NOREF) &&
((dev->flags & KBC_VEN_MASK) != KBC_VEN_INTEL_AMI))
add_data(dev, (dev->input_port | fixed_bits) & (((dev->flags & KBC_VEN_MASK) == KBC_VEN_ACER) ? 0xeb : 0xef));
add_to_kbc_queue_front(dev, (dev->input_port | fixed_bits) & (((dev->flags & KBC_VEN_MASK) == KBC_VEN_ACER) ? 0xeb : 0xef));
else
add_data(dev, dev->input_port | fixed_bits);
add_to_kbc_queue_front(dev, dev->input_port | fixed_bits);
dev->input_port = ((dev->input_port + 1) & 3) |
(dev->input_port & 0xfc);
}
@@ -1977,7 +1994,7 @@ kbd_write(uint16_t port, uint8_t val, void *priv)
mask &= 0xbf;
if (((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_NOREF) && (dev->mem[0] & 0x20))
mask &= 0xf7;
add_data(dev, dev->output_port & mask);
add_to_kbc_queue_front(dev, dev->output_port & mask);
break;
case 0xd1: /* write output port */
@@ -2042,6 +2059,13 @@ kbd_read(uint16_t port, void *priv)
if ((dev->last_irq == 0x0002) || (dev->last_irq == 0x1000))
picintc(dev->last_irq);
dev->last_irq = 0xffff;
if (dev->old_last_irq != 0xffff) {
dev->out = dev->old_out;
dev->last_irq = dev->old_last_irq;
dev->status = dev->old_status;
dev->old_last_irq = 0xffff;
picint(dev->last_irq);
}
break;
case 0x61:
@@ -2110,6 +2134,7 @@ kbd_reset(void *priv)
dev->wantirq = 0;
write_output(dev, 0xcf);
dev->last_irq = 0xffff;
dev->old_last_irq = 0xffff;
dev->secr_phase = 0;
dev->key_wantdata = 0;
@@ -2243,7 +2268,7 @@ const device_t keyboard_at_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_at_ami_device = {
@@ -2253,7 +2278,7 @@ const device_t keyboard_at_ami_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_at_toshiba_device = {
@@ -2263,7 +2288,7 @@ const device_t keyboard_at_toshiba_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_device = {
@@ -2273,7 +2298,7 @@ const device_t keyboard_ps2_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_ps2_device = {
@@ -2283,7 +2308,7 @@ const device_t keyboard_ps2_ps2_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_ps1_device = {
@@ -2293,7 +2318,7 @@ const device_t keyboard_ps2_ps1_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_ps1_pci_device = {
@@ -2303,7 +2328,7 @@ const device_t keyboard_ps2_ps1_pci_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_xi8088_device = {
@@ -2313,7 +2338,7 @@ const device_t keyboard_ps2_xi8088_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_ami_device = {
@@ -2323,7 +2348,7 @@ const device_t keyboard_ps2_ami_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_mca_device = {
@@ -2333,7 +2358,7 @@ const device_t keyboard_ps2_mca_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_mca_2_device = {
@@ -2343,7 +2368,7 @@ const device_t keyboard_ps2_mca_2_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_quadtel_device = {
@@ -2353,7 +2378,7 @@ const device_t keyboard_ps2_quadtel_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_pci_device = {
@@ -2363,7 +2388,7 @@ const device_t keyboard_ps2_pci_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_ami_pci_device = {
@@ -2373,7 +2398,7 @@ const device_t keyboard_ps2_ami_pci_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_intel_ami_pci_device = {
@@ -2383,7 +2408,7 @@ const device_t keyboard_ps2_intel_ami_pci_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t keyboard_ps2_acer_pci_device = {
@@ -2393,7 +2418,7 @@ const device_t keyboard_ps2_acer_pci_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};

16
src/device/keyboard_xt.c
View File

@@ -738,7 +738,7 @@ const device_t keyboard_pc_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL
{ NULL }, NULL, NULL
};
const device_t keyboard_pc82_device = {
@@ -748,7 +748,7 @@ const device_t keyboard_pc82_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL
{ NULL }, NULL, NULL
};
const device_t keyboard_xt_device = {
@@ -758,7 +758,7 @@ const device_t keyboard_xt_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL
{ NULL }, NULL, NULL
};
const device_t keyboard_xt86_device = {
@@ -768,7 +768,7 @@ const device_t keyboard_xt86_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL
{ NULL }, NULL, NULL
};
const device_t keyboard_xt_compaq_device = {
@@ -778,7 +778,7 @@ const device_t keyboard_xt_compaq_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL
{ NULL }, NULL, NULL
};
const device_t keyboard_tandy_device = {
@@ -788,7 +788,7 @@ const device_t keyboard_tandy_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL
{ NULL }, NULL, NULL
};
const device_t keyboard_xt_t1x00_device = {
@@ -798,7 +798,7 @@ const device_t keyboard_xt_t1x00_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL
{ NULL }, NULL, NULL
};
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
@@ -809,6 +809,6 @@ const device_t keyboard_xt_lxt3_device = {
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL
{ NULL }, NULL, NULL
};
#endif

10
src/device/mouse.c
View File

@@ -47,14 +47,14 @@ static const device_t mouse_none_device = {
"None",
0, MOUSE_TYPE_NONE,
NULL, NULL, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
static const device_t mouse_internal_device = {
"Internal Mouse",
0, MOUSE_TYPE_INTERNAL,
NULL, NULL, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -172,9 +172,9 @@ mouse_process(void)
mouse_poll();
if ((mouse_dev_poll != NULL) || (mouse_curr->available != NULL)) {
if (mouse_curr->available != NULL)
mouse_curr->available(mouse_x,mouse_y,mouse_z,mouse_buttons, mouse_priv);
if ((mouse_dev_poll != NULL) || (mouse_curr->poll != NULL)) {
if (mouse_curr->poll != NULL)
mouse_curr->poll(mouse_x,mouse_y,mouse_z,mouse_buttons, mouse_priv);
else
mouse_dev_poll(mouse_x,mouse_y,mouse_z,mouse_buttons, mouse_priv);

20
src/device/mouse_bus.c
View File

@@ -696,7 +696,7 @@ bm_init(const device_t *info)
static const device_config_t lt_config[] = {
{
"base", "Address", CONFIG_HEX16, "", 0x23c,
"base", "Address", CONFIG_HEX16, "", 0x23c, "", { 0 },
{
{
"0x230", 0x230
@@ -716,7 +716,7 @@ static const device_config_t lt_config[] = {
}
},
{
"irq", "IRQ", CONFIG_SELECTION, "", 5, {
"irq", "IRQ", CONFIG_SELECTION, "", 5, "", { 0 }, {
{
"IRQ 2", 2
},
@@ -735,7 +735,7 @@ static const device_config_t lt_config[] = {
}
},
{
"hz", "Hz", CONFIG_SELECTION, "", 45, {
"hz", "Hz", CONFIG_SELECTION, "", 45, "", { 0 }, {
{
"Non-timed (original)", 0
},
@@ -754,7 +754,7 @@ static const device_config_t lt_config[] = {
}
},
{
"buttons", "Buttons", CONFIG_SELECTION, "", 2, {
"buttons", "Buttons", CONFIG_SELECTION, "", 2, "", { 0 }, {
{
"Two", 2
},
@@ -774,7 +774,7 @@ static const device_config_t lt_config[] = {
static const device_config_t ms_config[] = {
{
"base", "Address", CONFIG_HEX16, "", 0x23c,
"base", "Address", CONFIG_HEX16, "", 0x23c, "", { 0 },
{
{
"0x230", 0x230
@@ -794,7 +794,7 @@ static const device_config_t ms_config[] = {
}
},
{
"irq", "IRQ", CONFIG_SELECTION, "", 5, {
"irq", "IRQ", CONFIG_SELECTION, "", 5, "", { 0 }, {
{
"IRQ 2", 2
},
@@ -813,7 +813,7 @@ static const device_config_t ms_config[] = {
}
},
{
"buttons", "Buttons", CONFIG_SELECTION, "", 2, {
"buttons", "Buttons", CONFIG_SELECTION, "", 2, "", { 0 }, {
{
"Two", 2
},
@@ -836,7 +836,7 @@ const device_t mouse_logibus_device = {
DEVICE_ISA,
MOUSE_TYPE_LOGIBUS,
bm_init, bm_close, NULL,
bm_poll, NULL, NULL,
{ .poll = bm_poll }, NULL, NULL,
lt_config
};
@@ -845,7 +845,7 @@ const device_t mouse_logibus_onboard_device = {
DEVICE_ISA,
MOUSE_TYPE_LOGIBUS | MOUSE_TYPE_ONBOARD,
bm_init, bm_close, NULL,
bm_poll, NULL, NULL
{ .poll = bm_poll }, NULL, NULL
};
const device_t mouse_msinport_device = {
@@ -853,6 +853,6 @@ const device_t mouse_msinport_device = {
DEVICE_ISA,
MOUSE_TYPE_INPORT,
bm_init, bm_close, NULL,
bm_poll, NULL, NULL,
{ .poll = bm_poll }, NULL, NULL,
ms_config
};

4
src/device/mouse_ps2.c
View File

@@ -325,7 +325,7 @@ ps2_close(void *priv)
static const device_config_t ps2_config[] = {
{
"buttons", "Buttons", CONFIG_SELECTION, "", 2, {
"buttons", "Buttons", CONFIG_SELECTION, "", 2, "", { 0 }, {
{
"Two", 2
},
@@ -351,6 +351,6 @@ const device_t mouse_ps2_device = {
DEVICE_PS2,
MOUSE_TYPE_PS2,
mouse_ps2_init, ps2_close, NULL,
ps2_poll, NULL, NULL,
{ .poll = ps2_poll }, NULL, NULL,
ps2_config
};

14
src/device/mouse_serial.c
View File

@@ -832,7 +832,7 @@ sermouse_init(const device_t *info)
static const device_config_t mssermouse_config[] = {
{
"port", "Serial Port", CONFIG_SELECTION, "", 0, {
"port", "Serial Port", CONFIG_SELECTION, "", 0, "", { 0 }, {
{
"COM1", 0
},
@@ -845,7 +845,7 @@ static const device_config_t mssermouse_config[] = {
}
},
{
"buttons", "Buttons", CONFIG_SELECTION, "", 2, {
"buttons", "Buttons", CONFIG_SELECTION, "", 2, "", { 0 }, {
{
"Two", 2
},
@@ -868,7 +868,7 @@ static const device_config_t mssermouse_config[] = {
static const device_config_t ltsermouse_config[] = {
{
"port", "Serial Port", CONFIG_SELECTION, "", 0, {
"port", "Serial Port", CONFIG_SELECTION, "", 0, "", { 0 }, {
{
"COM1", 0
},
@@ -881,7 +881,7 @@ static const device_config_t ltsermouse_config[] = {
}
},
{
"buttons", "Buttons", CONFIG_SELECTION, "", 2, {
"buttons", "Buttons", CONFIG_SELECTION, "", 2, "", { 0 }, {
{
"Two", 2
},
@@ -904,7 +904,7 @@ const device_t mouse_mssystems_device = {
0,
MOUSE_TYPE_MSYSTEMS,
sermouse_init, sermouse_close, NULL,
sermouse_poll, sermouse_speed_changed, NULL,
{ .poll = sermouse_poll }, sermouse_speed_changed, NULL,
mssermouse_config
};
@@ -913,7 +913,7 @@ const device_t mouse_msserial_device = {
0,
0,
sermouse_init, sermouse_close, NULL,
sermouse_poll, sermouse_speed_changed, NULL,
{ .poll = sermouse_poll }, sermouse_speed_changed, NULL,
mssermouse_config
};
@@ -922,6 +922,6 @@ const device_t mouse_ltserial_device = {
0,
1,
sermouse_init, sermouse_close, NULL,
sermouse_poll, sermouse_speed_changed, NULL,
{ .poll = sermouse_poll }, sermouse_speed_changed, NULL,
ltsermouse_config
};

76
src/device/pci_bridge.c
View File

@@ -41,6 +41,7 @@
#define AGP_BRIDGE_VIA_691 0x11068691
#define AGP_BRIDGE_VIA_8601 0x11068601
#define AGP_BRIDGE_INTEL(x) (((x) >> 16) == 0x8086)
#define AGP_BRIDGE_VIA(x) (((x) >> 16) == 0x1106)
#define AGP_BRIDGE(x) ((x) >= AGP_BRIDGE_VIA_597)
@@ -88,19 +89,36 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x06: case 0x07: case 0x08: case 0x09:
case 0x0a: case 0x0b: case 0x0e: case 0x1e:
case 0x1f: case 0x34: case 0x3d: case 0x67:
case 0xdc: case 0xdd: case 0xde: case 0xdf:
case 0xe0: case 0xe1: case 0xe2: case 0xe3:
case 0x06: case 0x08: case 0x09: case 0x0a:
case 0x0b: case 0x0e: case 0x1e: case 0x34:
case 0x3d: case 0x67: case 0xdc: case 0xdd:
case 0xde: case 0xdf: case 0xe0: case 0xe1:
case 0xe2: case 0xe3:
return;
case 0x04:
val &= 0x67;
if (AGP_BRIDGE_INTEL(dev->local)) {
if (dev->local == AGP_BRIDGE_INTEL_440BX)
val &= 0x1f;
} else
val &= 0x67;
break;
case 0x05:
val &= 0x03;
if (AGP_BRIDGE_INTEL(dev->local))
val &= 0x01;
else
val &= 0x03;
break;
case 0x07:
if (dev->local == AGP_BRIDGE_INTEL_440LX)
dev->regs[addr] &= ~(val & 0x40);
return;
case 0x0d:
if (AGP_BRIDGE_INTEL(dev->local))
val &= 0xf8;
break;
case 0x18:
@@ -115,6 +133,16 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
pci_remap_bus(dev->bus_index, val);
break;
case 0x1f:
if (AGP_BRIDGE_INTEL(dev->local)) {
if (dev->local == AGP_BRIDGE_INTEL_440LX)
dev->regs[addr] &= ~(val & 0xf1);
else if ((dev->local == AGP_BRIDGE_INTEL_440BX) ||
(dev->local == AGP_BRIDGE_INTEL_440GX))
dev->regs[addr] &= ~(val & 0xf0);
}
return;
case 0x1c: case 0x1d: case 0x20: case 0x22:
case 0x24: case 0x26:
val &= 0xf0;
@@ -123,16 +151,22 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x3e:
if (AGP_BRIDGE_VIA(dev->local))
val &= 0x0c;
else if (AGP_BRIDGE(dev->local))
val &= 0x0f;
else if (AGP_BRIDGE(dev->local)) {
if ((dev->local == AGP_BRIDGE_INTEL_440BX) ||
(dev->local == AGP_BRIDGE_INTEL_440GX))
val &= 0xed;
else
val &= 0x0f;
}
else if (dev->local == PCI_BRIDGE_DEC_21150)
val &= 0xef;
break;
case 0x3f:
if (dev->local == AGP_BRIDGE_INTEL_440LX)
val &= 0x02;
else if (AGP_BRIDGE(dev->local))
if (dev->local == AGP_BRIDGE_INTEL_440LX) {
dev->regs[addr] = ((dev->regs[addr] & 0x04) | (val & 0x02)) & ~(val & 0x04);
return;
} else if (AGP_BRIDGE(dev->local))
return;
else if (dev->local == PCI_BRIDGE_DEC_21150)
val &= 0x0f;
@@ -282,7 +316,7 @@ pci_bridge_init(const device_t *info)
pci_bridge_reset(dev);
dev->slot = pci_add_card(AGP_BRIDGE(dev->local) ? 0x01 : PCI_ADD_BRIDGE, pci_bridge_read, pci_bridge_write, dev);
dev->slot = pci_add_card(AGP_BRIDGE(dev->local) ? PCI_ADD_AGPBRIDGE : PCI_ADD_BRIDGE, pci_bridge_read, pci_bridge_write, dev);
interrupt_count = sizeof(interrupts);
interrupt_mask = interrupt_count - 1;
for (i = 0; i < interrupt_count; i++)
@@ -318,7 +352,7 @@ const device_t dec21150_device =
pci_bridge_init,
NULL,
pci_bridge_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -333,7 +367,7 @@ const device_t i440lx_agp_device =
pci_bridge_init,
NULL,
pci_bridge_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -347,7 +381,7 @@ const device_t i440bx_agp_device =
pci_bridge_init,
NULL,
pci_bridge_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -361,7 +395,7 @@ const device_t i440gx_agp_device =
pci_bridge_init,
NULL,
pci_bridge_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -375,7 +409,7 @@ const device_t via_vp3_agp_device =
pci_bridge_init,
NULL,
pci_bridge_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -389,7 +423,7 @@ const device_t via_mvp3_agp_device =
pci_bridge_init,
NULL,
pci_bridge_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -403,7 +437,7 @@ const device_t via_apro_agp_device =
pci_bridge_init,
NULL,
pci_bridge_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL
@@ -417,7 +451,7 @@ const device_t via_vt8601_agp_device =
pci_bridge_init,
NULL,
pci_bridge_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

2
src/device/phoenix_486_jumper.c
View File

@@ -102,6 +102,6 @@ const device_t phoenix_486_jumper_device = {
0,
0,
phoenix_486_jumper_init, phoenix_486_jumper_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/device/postcard.c
View File

@@ -143,6 +143,6 @@ const device_t postcard_device = {
DEVICE_ISA,
0,
postcard_init, postcard_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

8
src/device/serial.c
View File

@@ -739,7 +739,7 @@ const device_t i8250_device = {
0,
SERIAL_8250,
serial_init, serial_close, NULL,
NULL, serial_speed_changed, NULL,
{ NULL }, serial_speed_changed, NULL,
NULL
};
@@ -748,7 +748,7 @@ const device_t i8250_pcjr_device = {
DEVICE_PCJR,
SERIAL_8250_PCJR,
serial_init, serial_close, NULL,
NULL, serial_speed_changed, NULL,
{ NULL }, serial_speed_changed, NULL,
NULL
};
@@ -757,7 +757,7 @@ const device_t ns16450_device = {
0,
SERIAL_NS16450,
serial_init, serial_close, NULL,
NULL, serial_speed_changed, NULL,
{ NULL }, serial_speed_changed, NULL,
NULL
};
@@ -766,6 +766,6 @@ const device_t ns16550_device = {
0,
SERIAL_NS16550,
serial_init, serial_close, NULL,
NULL, serial_speed_changed, NULL,
{ NULL }, serial_speed_changed, NULL,
NULL
};

2
src/device/smbus_piix4.c
View File

@@ -249,6 +249,6 @@ const device_t piix4_smbus_device = {
DEVICE_AT,
0,
smbus_piix4_init, smbus_piix4_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/device/vpc2007.c
View File

@@ -181,6 +181,6 @@ const device_t vpc2007_device = {
DEVICE_ISA,
0,
vpc2007_init, vpc2007_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

119
src/disk/hdc.c
View File

@@ -69,7 +69,7 @@ null_close(void *priv)
static const device_t null_device = {
"Null HDC", 0, 0,
null_init, null_close, NULL,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
@@ -89,83 +89,37 @@ inthdc_close(void *priv)
static const device_t inthdc_device = {
"Internal controller", 0, 0,
inthdc_init, inthdc_close, NULL,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
static const struct {
const char *name;
const char *internal_name;
const device_t *device;
} controllers[] = {
{ "None", "none",
&null_device },
{ "Internal controller", "internal",
&inthdc_device },
{ "[ISA] [MFM] IBM PC Fixed Disk Adapter", "st506_xt",
&st506_xt_xebec_device },
{ "[ISA] [MFM] DTC-5150X Fixed Disk Adapter", "st506_xt_dtc5150x",
&st506_xt_dtc5150x_device },
{ "[ISA] [MFM] ST-11M Fixed Disk Adapter", "st506_xt_st11_m",
&st506_xt_st11_m_device },
{ "[ISA] [MFM] WD1002A-WX1 Fixed Disk Adapter", "st506_xt_wd1002a_wx1",
&st506_xt_wd1002a_wx1_device },
{ "[ISA] [MFM/RLL] IBM PC/AT Fixed Disk Adapter", "st506_at",
&st506_at_wd1003_device },
{ "[ISA] [RLL] ST-11R Fixed Disk Adapter", "st506_xt_st11_r",
&st506_xt_st11_r_device },
{ "[ISA] [RLL] WD1002A-27X Fixed Disk Adapter", "st506_xt_wd1002a_27x",
&st506_xt_wd1002a_27x_device },
{ "[ISA] [ESDI] PC/AT ESDI Fixed Disk Adapter", "esdi_at",
&esdi_at_wd1007vse1_device },
{ "[ISA] [IDE] PC/AT IDE Adapter", "ide_isa",
&ide_isa_device },
{ "[ISA] [IDE] PC/AT IDE Adapter (Dual-Channel)", "ide_isa_2ch",
&ide_isa_2ch_device },
{ "[ISA] [IDE] PC/AT XTIDE", "xtide_at",
&xtide_at_device },
{ "[ISA] [IDE] PS/2 AT XTIDE (1.1.5)", "xtide_at_ps2",
&xtide_at_ps2_device },
{ "[ISA] [IDE] WDXT-150 IDE (XTA) Adapter", "xta_wdxt150",
&xta_wdxt150_device },
{ "[ISA] [XT IDE] Acculogic XT IDE", "xtide_acculogic",
&xtide_acculogic_device },
{ "[ISA] [XT IDE] PC/XT XTIDE", "xtide",
&xtide_device },
{ "[MCA] [ESDI] IBM PS/2 ESDI Fixed Disk Adapter","esdi_mca",
&esdi_ps2_device },
{ "[PCI] [IDE] PCI IDE Adapter", "ide_pci",
&ide_pci_device },
{ "[PCI] [IDE] PCI IDE Adapter (Dual-Channel)", "ide_pci_2ch",
&ide_pci_2ch_device },
{ "[VLB] [IDE] PC/AT IDE Adapter", "vlb_isa",
&ide_vlb_device },
{ "[VLB] [IDE] PC/AT IDE Adapter (Dual-Channel)", "vlb_isa_2ch",
&ide_vlb_2ch_device },
{ "", "",
NULL }
{ "none", &null_device },
{ "internal", &inthdc_device },
{ "st506_xt", &st506_xt_xebec_device },
{ "st506_xt_dtc5150x", &st506_xt_dtc5150x_device },
{ "st506_xt_st11_m", &st506_xt_st11_m_device },
{ "st506_xt_wd1002a_wx1", &st506_xt_wd1002a_wx1_device },
{ "st506_at", &st506_at_wd1003_device },
{ "st506_xt_st11_r", &st506_xt_st11_r_device },
{ "st506_xt_wd1002a_27x", &st506_xt_wd1002a_27x_device },
{ "esdi_at", &esdi_at_wd1007vse1_device },
{ "ide_isa", &ide_isa_device },
{ "ide_isa_2ch", &ide_isa_2ch_device },
{ "xtide_at", &xtide_at_device },
{ "xtide_at_ps2", &xtide_at_ps2_device },
{ "xta_wdxt150", &xta_wdxt150_device },
{ "xtide_acculogic", &xtide_acculogic_device },
{ "xtide", &xtide_device },
{ "esdi_mca", &esdi_ps2_device },
{ "ide_pci", &ide_pci_device },
{ "ide_pci_2ch", &ide_pci_2ch_device },
{ "vlb_isa", &ide_vlb_device },
{ "vlb_isa_2ch", &ide_vlb_2ch_device },
{ "", NULL }
};
@@ -199,13 +153,6 @@ hdc_reset(void)
}
char *
hdc_get_name(int hdc)
{
return((char *) controllers[hdc].name);
}
char *
hdc_get_internal_name(int hdc)
{
@@ -213,22 +160,6 @@ hdc_get_internal_name(int hdc)
}
int
hdc_get_id(char *s)
{
int c = 0;
while (strlen((char *) controllers[c].name))
{
if (!strcmp((char *) controllers[c].name, s))
return c;
c++;
}
return 0;
}
int
hdc_get_from_internal_name(char *s)
{

2
src/disk/hdc_esdi_at.c
View File

@@ -849,7 +849,7 @@ const device_t esdi_at_wd1007vse1_device = {
DEVICE_ISA | DEVICE_AT,
0,
wd1007vse1_init, wd1007vse1_close, NULL,
wd1007vse1_available,
{ wd1007vse1_available },
NULL, NULL,
NULL
};

4
src/disk/hdc_esdi_mca.c
View File

@@ -1180,8 +1180,8 @@ esdi_available(void)
const device_t esdi_ps2_device = {
"IBM ESDI Fixed Disk Adapter (MCA)",
"IBM PS/2 ESDI Fixed Disk Adapter (MCA)",
DEVICE_MCA, 0,
esdi_init, esdi_close, NULL,
esdi_available, NULL, NULL, NULL
{ esdi_available }, NULL, NULL, NULL
};

24
src/disk/hdc_ide.c
View File

@@ -886,7 +886,7 @@ ide_set_board_callback(uint8_t board, double callback)
{
ide_board_t *dev = ide_boards[board];
ide_log("ide_set_callback(%i)\n", board);
ide_log("ide_set_board_callback(%i)\n", board);
if (!dev) {
ide_log("Set board callback failed\n");
@@ -1340,7 +1340,7 @@ ide_write_devctl(uint16_t addr, uint8_t val, void *priv)
ide->reset = 1;
ide_set_callback(ide, 0.0);
ide_set_callback(ide_other, 0.0);
ide_set_board_callback(ide->board, 500 * IDE_TIME);
ide_set_board_callback(ide->board, 1000.4); /* 1 ms + 400 ns, per the specification */
} else {
/* Currently active device is 1, simply reset the status and the active device. */
dev_reset(ide);
@@ -2848,7 +2848,7 @@ const device_t ide_isa_device = {
DEVICE_ISA | DEVICE_AT,
0,
ide_init, ide_close, ide_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t ide_isa_2ch_device = {
@@ -2856,7 +2856,7 @@ const device_t ide_isa_2ch_device = {
DEVICE_ISA | DEVICE_AT,
1,
ide_init, ide_close, ide_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t ide_vlb_device = {
@@ -2864,7 +2864,7 @@ const device_t ide_vlb_device = {
DEVICE_VLB | DEVICE_AT,
2,
ide_init, ide_close, ide_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t ide_vlb_2ch_device = {
@@ -2872,7 +2872,7 @@ const device_t ide_vlb_2ch_device = {
DEVICE_VLB | DEVICE_AT,
3,
ide_init, ide_close, ide_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t ide_pci_device = {
@@ -2880,7 +2880,7 @@ const device_t ide_pci_device = {
DEVICE_PCI | DEVICE_AT,
4,
ide_init, ide_close, ide_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
const device_t ide_pci_2ch_device = {
@@ -2888,13 +2888,13 @@ const device_t ide_pci_2ch_device = {
DEVICE_PCI | DEVICE_AT,
5,
ide_init, ide_close, ide_reset,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};
static const device_config_t ide_ter_config[] =
{
{
"irq", "IRQ", CONFIG_SELECTION, "", 10,
"irq", "IRQ", CONFIG_SELECTION, "", 10, "", { 0 },
{
{
"IRQ 2", 2
@@ -2936,7 +2936,7 @@ static const device_config_t ide_ter_config[] =
static const device_config_t ide_qua_config[] =
{
{
"irq", "IRQ", CONFIG_SELECTION, "", 11,
"irq", "IRQ", CONFIG_SELECTION, "", 11, "", { 0 },
{
{
"IRQ 2", 2
@@ -2980,7 +2980,7 @@ const device_t ide_ter_device = {
DEVICE_AT,
0,
ide_ter_init, ide_ter_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
ide_ter_config
};
@@ -2989,6 +2989,6 @@ const device_t ide_qua_device = {
DEVICE_AT,
0,
ide_qua_init, ide_qua_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
ide_qua_config
};

10
src/disk/hdc_ide_cmd640.c
View File

@@ -442,7 +442,7 @@ const device_t ide_cmd640_vlb_device = {
DEVICE_VLB,
0x0078,
cmd640_init, cmd640_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -451,7 +451,7 @@ const device_t ide_cmd640_vlb_178_device = {
DEVICE_VLB,
0x0178,
cmd640_init, cmd640_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -460,7 +460,7 @@ const device_t ide_cmd640_pci_device = {
DEVICE_PCI,
0x0a,
cmd640_init, cmd640_close, cmd640_reset,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -469,7 +469,7 @@ const device_t ide_cmd640_pci_legacy_only_device = {
DEVICE_PCI,
0x00,
cmd640_init, cmd640_close, cmd640_reset,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -478,6 +478,6 @@ const device_t ide_cmd640_pci_single_channel_device = {
DEVICE_PCI,
0x2000a,
cmd640_init, cmd640_close, cmd640_reset,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/disk/hdc_ide_opti611.c
View File

@@ -317,6 +317,6 @@ const device_t ide_opti611_vlb_device = {
0,
0,
opti611_init, opti611_close, NULL,
NULL, NULL, NULL,
{ NULL }, NULL, NULL,
NULL
};

2
src/disk/hdc_ide_sff8038i.c
View File

@@ -524,7 +524,7 @@ const device_t sff8038i_device =
sff_init,
sff_close,
sff_reset,
NULL,
{ NULL },
NULL,
NULL,
NULL

2
src/disk/hdc_st506_at.c
View File

@@ -773,5 +773,5 @@ const device_t st506_at_wd1003_device = {
DEVICE_ISA | DEVICE_AT,
0,
mfm_init, mfm_close, NULL,
NULL, NULL, NULL, NULL
{ NULL }, NULL, NULL, NULL
};

36
src/disk/hdc_st506_xt.c
View File

@@ -1617,7 +1617,7 @@ wd1002a_27x_available(void)
static const device_config_t dtc_config[] = {
{
"bios_addr", "BIOS address", CONFIG_HEX20, "", 0xc8000,
"bios_addr", "BIOS address", CONFIG_HEX20, "", 0xc8000, "", { 0 },
{
{
"Disabled", 0x00000
@@ -1646,7 +1646,7 @@ static const device_config_t dtc_config[] = {
static const device_config_t st11_config[] = {
{
"base", "Address", CONFIG_HEX16, "", 0x0320,
"base", "Address", CONFIG_HEX16, "", 0x0320, "", { 0 },
{
{
"320H", 0x0320
@@ -1666,7 +1666,7 @@ static const device_config_t st11_config[] = {
}
},
{
"irq", "IRQ", CONFIG_SELECTION, "", 5,
"irq", "IRQ", CONFIG_SELECTION, "", 5, "", { 0 },
{
{
"IRQ 2", 2
@@ -1680,7 +1680,7 @@ static const device_config_t st11_config[] = {
}
},
{
"bios_addr", "BIOS address", CONFIG_HEX20, "", 0xc8000,
"bios_addr", "BIOS address", CONFIG_HEX20, "", 0xc8000, "", { 0 },
{
{
"Disabled", 0x00000
@@ -1703,7 +1703,7 @@ static const device_config_t st11_config[] = {
}
},
{
"revision", "Board Revision", CONFIG_SELECTION, "", 19,
"revision", "Board Revision", CONFIG_SELECTION, "", 19, "", { 0 },
{
{
"Rev. 05 (v1.7)", 5
@@ -1723,7 +1723,7 @@ static const device_config_t st11_config[] = {
static const device_config_t wd_config[] = {
{
"bios_addr", "BIOS address", CONFIG_HEX20, "", 0xc8000,
"bios_addr", "BIOS address", CONFIG_HEX20, "", 0xc8000, "", { 0 },
{
{
"Disabled", 0x00000
@@ -1737,7 +1737,7 @@ static const device_config_t wd_config[] = {
}
},
{
"base", "Address", CONFIG_HEX16, "", 0x0320,
"base", "Address", CONFIG_HEX16, "", 0x0320, "", { 0 },
{
{
"320H", 0x0320
@@ -1751,7 +1751,7 @@ static const device_config_t wd_config[] = {
}
},
{
"irq", "IRQ", CONFIG_SELECTION, "", 5,
"irq", "IRQ", CONFIG_SELECTION, "", 5, "", { 0 },
{
{
"IRQ 2", 2
@@ -1771,7 +1771,7 @@ static const device_config_t wd_config[] = {
static const device_config_t wd_rll_config[] = {
{
"bios_addr", "BIOS address", CONFIG_HEX20, "", 0xc8000,
"bios_addr", "BIOS address", CONFIG_HEX20, "", 0xc8000, "", { 0 },
{
{
"Disabled", 0x00000
@@ -1785,7 +1785,7 @@ static const device_config_t wd_rll_config[] = {
}
},
{
"base", "Address", CONFIG_HEX16, "", 0x0320,
"base", "Address", CONFIG_HEX16, "", 0x0320, "", { 0 },
{
{
"320H", 0x0320
@@ -1799,7 +1799,7 @@ static const device_config_t wd_rll_config[] = {
}
},
{
"irq", "IRQ", CONFIG_SELECTION, "", 5,
"irq", "IRQ", CONFIG_SELECTION, "", 5, "", { 0 },
{
{
"IRQ 2", 2
@@ -1813,7 +1813,7 @@ static const device_config_t wd_rll_config[] = {
}
},
{
"translate", "Translate 26 -> 17", CONFIG_SELECTION, "", 0,
"translate", "Translate 26 -> 17", CONFIG_SELECTION, "", 0, "", { 0 },
{
{
"Off", 0
@@ -1837,7 +1837,7 @@ const device_t st506_xt_xebec_device = {
DEVICE_ISA,
(HDD_BUS_MFM << 8) | 0,
st506_init, st506_close, NULL,
xebec_available,
{ xebec_available },
NULL, NULL,
NULL
};
@@ -1847,7 +1847,7 @@ const device_t st506_xt_dtc5150x_device = {
DEVICE_ISA,
(HDD_BUS_MFM << 8) | 1,
st506_init, st506_close, NULL,
dtc5150x_available,
{ dtc5150x_available },
NULL, NULL,
dtc_config
};
@@ -1857,7 +1857,7 @@ const device_t st506_xt_st11_m_device = {
DEVICE_ISA,
(HDD_BUS_MFM << 8) | 11,
st506_init, st506_close, NULL,
st11_m_available,
{ st11_m_available },
NULL, NULL,
st11_config
};
@@ -1867,7 +1867,7 @@ const device_t st506_xt_st11_r_device = {
DEVICE_ISA,
(HDD_BUS_MFM << 8) | 12,
st506_init, st506_close, NULL,
st11_r_available,
{ st11_r_available },
NULL, NULL,
st11_config
};
@@ -1877,7 +1877,7 @@ const device_t st506_xt_wd1002a_wx1_device = {
DEVICE_ISA,
(HDD_BUS_MFM << 8) | 21,
st506_init, st506_close, NULL,
wd1002a_wx1_available,
{ wd1002a_wx1_available },
NULL, NULL,
wd_config
};
@@ -1887,7 +1887,7 @@ const device_t st506_xt_wd1002a_27x_device = {
DEVICE_ISA,
(HDD_BUS_MFM << 8) | 22,
st506_init, st506_close, NULL,
wd1002a_27x_available,
{ wd1002a_27x_available },
NULL, NULL,
wd_rll_config
};

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