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Merge branch 'master' into master

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This commit is contained in:
Miran Grča
2022-02-23 14:45:03 +01:00
committed by GitHub
parent cccc9db388 74e55cf134
commit 0c540ff29c
665 changed files with 13030 additions and 11568 deletions
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95
.ci/AppImageBuilder.yml Normal file
View File

@@ -0,0 +1,95 @@
#
# 86Box A hypervisor and IBM PC system emulator that specializes in
# running old operating systems and software designed for IBM
# PC systems and compatibles from 1981 through fairly recent
# system designs based on the PCI bus.
#
# This file is part of the 86Box distribution.
#
# Recipe file for appimage-builder.
#
#
# Authors: RichardG, <richardg867@gmail.com>
#
# Copyright 2022 RichardG.
#
version: 1
AppDir:
path: ./archive_tmp
app_info:
id: !ENV 'net.${project_lower}.${project_lower}'
name: !ENV '${project}'
icon: !ENV '${project_lower}'
version: !ENV '${project_version}'
exec: !ENV 'usr/local/bin/${project}'
exec_args: $@
apt:
arch: !ENV '${arch_deb}'
sources:
- sourceline: 'deb http://deb.debian.org/debian bullseye main'
key_url: 'https://ftp-master.debian.org/keys/archive-key-11.asc'
- sourceline: 'deb http://security.debian.org/debian-security bullseye-security main'
key_url: 'https://ftp-master.debian.org/keys/archive-key-11.asc'
- sourceline: 'deb http://deb.debian.org/debian bullseye-updates main'
key_url: 'https://ftp-master.debian.org/keys/archive-key-11-security.asc'
include:
- libevdev2
- libfluidsynth2
- libfreetype6
- libgbm1
- libgl1
- libgles2
- libglvnd0
- libglx0
- libgs9
- libpng16-16
- libqt5core5a
- libqt5gui5
- libqt5widgets5
- libslirp0
- libsndio7.0
- libwayland-client0
- libx11-6
- libxcb1
- zlib1g
files:
exclude:
- etc
- lib/udev
- opt/libc/usr/share
- usr/bin
- usr/include
- usr/lib/*/libasound.so.*
- usr/lib/cmake
- usr/lib/pkgconfig
- usr/sbin
- usr/share/aclocal
- usr/share/alsa
- usr/share/apport
- usr/share/bug
- usr/share/color
- usr/share/doc
- usr/share/doc-base
- usr/share/fontconfig
- usr/share/fonts
- usr/share/ghostscript
- usr/share/glib-2.0
- usr/share/info
- usr/share/libinput
- usr/share/libwacom
- usr/share/lintian
- usr/share/locale
- usr/share/man
- usr/share/metainfo
- usr/share/openal
- usr/share/pkgconfig
- usr/share/poppler
- usr/share/readline
- usr/share/rtmidi
- usr/share/sounds
- usr/share/X11
- usr/share/xml
- var
AppImage:
arch: !ENV '${arch_appimage}'

24
.ci/Jenkinsfile vendored
View File

@@ -16,6 +16,7 @@
*/
def repository = 'https://github.com/86Box/86Box.git'
def commitBrowser = 'https://github.com/86Box/86Box/commit/%s'
def branch = 'master'
def osArchs = [
@@ -23,6 +24,11 @@ def osArchs = [
'Linux': ['x86', 'x86_64', 'arm32', 'arm64']
]
def osFlags = [
'Windows': '',
'Linux': '-D QT=ON'
]
def archNames = [
'32': 'x86 (32-bit)',
'x86': 'x86 (32-bit)',
@@ -73,9 +79,9 @@ def presetSlugs = [
]
def presetFlags = [
'Regular': '-t --preset=regular',
'Debug': '--preset=debug',
'Dev': '-t --preset=experimental -D VNC=OFF'
'Regular': '-t --preset=regular -D CMAKE_BUILD_TYPE=Release',
'Debug': '--preset=debug -D CMAKE_BUILD_TYPE=Debug',
'Dev': '--preset=experimental -D CMAKE_BUILD_TYPE=Debug -D VNC=OFF'
]
def anyFailure = false
@@ -143,7 +149,7 @@ pipeline {
parameters {
string(name: 'BUILD_TYPE',
defaultValue: 'beta', /* !!! CHANGE HERE !!! for build type */
description: "Build type to pass on to CMake. Don't change this, you should instead change the default value on .ci/Jenkinsfile")
description: "Build type to pass on to CMake. Should only be changed for one-off builds, otherwise change the default on .ci/Jenkinsfile")
}
stages {
@@ -195,6 +201,9 @@ pipeline {
/* Archive resulting artifacts. */
archiveArtifacts artifacts: "$packageName*"
}
/* Clean up. */
removeDir("${env.WORKSPACE_TMP}/output")
} catch (e) {
/* Mark that a failure occurred. */
anyFailure = true
@@ -225,12 +234,15 @@ pipeline {
/* Run build process. */
def packageName = "${env.JOB_BASE_NAME}${dynarecSlugs[dynarec]}${presetSlugs[preset]}-$os-$arch-b${env.BUILD_NUMBER}"
dir("${dynarecNames[dynarec]}/$os - ${archNames[arch]}") {
runBuild("-b \"$packageName\" \"$arch\" ${presetFlags[preset]} ${dynarecFlags[dynarec]} -D \"BUILD_TYPE=$BUILD_TYPE\" -D \"EMU_BUILD=build ${env.BUILD_NUMBER}\" -D \"EMU_BUILD_NUM=${env.BUILD_NUMBER}\"")
runBuild("-b \"$packageName\" \"$arch\" ${presetFlags[preset]} ${dynarecFlags[dynarec]} ${osFlags[os]} -D \"BUILD_TYPE=$BUILD_TYPE\" -D \"EMU_BUILD=build ${env.BUILD_NUMBER}\" -D \"EMU_BUILD_NUM=${env.BUILD_NUMBER}\"")
}
/* Archive resulting artifacts. */
archiveArtifacts artifacts: "**/**/$packageName*"
}
/* Clean up. */
removeDir("${env.WORKSPACE_TMP}/output")
} catch (e) {
/* Mark that a failure occurred. */
anyFailure = true
@@ -272,7 +284,7 @@ pipeline {
description: "**Status:** ${result}\n\u2060", /* word joiner character forces a blank line */
enableArtifactsList: false,
showChangeset: true,
scmWebUrl: "https://github.com/86Box/86Box/commit/%s"
scmWebUrl: commitBrowser
/* Notify IRC, which needs a node for whatever reason. */
node {

184
.ci/build.sh
View File

@@ -12,7 +12,7 @@
#
# Authors: RichardG, <richardg867@gmail.com>
#
# Copyright 2021 RichardG.
# Copyright 2021-2022 RichardG.
#
#
@@ -85,6 +85,7 @@ make_tar() {
# Set common variables.
project=86Box
project_lower=86box
cwd=$(pwd)
# Parse arguments.
@@ -176,6 +177,15 @@ fi
echo [-] Building [$package_name] for [$arch] with flags [$cmake_flags]
# Determine CMake toolchain file for this architecture.
case $arch in
32 | x86) toolchain="flags-gcc-i686";;
64 | x86_64) toolchain="flags-gcc-x86_64";;
ARM32 | arm32) toolchain="flags-gcc-armv7";;
ARM64 | arm64) toolchain="flags-gcc-aarch64";;
*) toolchain="flags-gcc-$arch";;
esac
# Perform platform-specific setup.
strip_binary=strip
if is_windows
@@ -200,6 +210,9 @@ then
exit 2
fi
echo [-] Using MSYSTEM [$MSYSTEM]
# Point CMake to the toolchain file.
cmake_flags_extra="$cmake_flags_extra -D \"CMAKE_TOOLCHAIN_FILE=cmake/$toolchain.cmake\""
elif is_mac
then
# macOS lacks nproc, but sysctl can do the same job.
@@ -213,21 +226,26 @@ else
*) arch_deb="$arch";;
esac
# Establish general and architecture-specific dependencies.
pkgs="cmake pkg-config git tar xz-utils dpkg-dev rpm"
# Establish general dependencies.
pkgs="cmake pkg-config git imagemagick wget p7zip-full wayland-protocols tar gzip"
if [ "$(dpkg --print-architecture)" = "$arch_deb" ]
then
pkgs="$pkgs build-essential"
else
sudo dpkg --add-architecture $arch_deb
sudo dpkg --add-architecture "$arch_deb"
pkgs="$pkgs crossbuild-essential-$arch_deb"
fi
# Establish architecture-specific dependencies we don't want listed on the readme...
pkgs="$pkgs linux-libc-dev:$arch_deb extra-cmake-modules:$arch_deb qttools5-dev:$arch_deb qtbase5-private-dev:$arch_deb"
# ...and the ones we do want listed. Non-dev packages fill missing spots on the list.
libpkgs=""
longest_libpkg=0
for pkg in libc6-dev linux-libc-dev libopenal-dev libfreetype6-dev libsdl2-dev libpng-dev librtmidi-dev
for pkg in libc6-dev libstdc++6 libopenal-dev libfreetype6-dev libx11-dev libsdl2-dev libpng-dev librtmidi-dev qtdeclarative5-dev libwayland-dev libevdev-dev libglib2.0-dev libslirp-dev
do
libpkgs="$libpkgs $pkg:$arch_deb"
length=$(echo -n $pkg | sed 's/-dev$//' | wc -c)
length=$(echo -n $pkg | sed 's/-dev$//' | sed "s/qtdeclarative/qt/" | wc -c)
[ $length -gt $longest_libpkg ] && longest_libpkg=$length
done
@@ -266,6 +284,8 @@ set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
set(ENV{PKG_CONFIG_PATH} "")
set(ENV{PKG_CONFIG_LIBDIR} "/usr/lib/$libdir/pkgconfig:/usr/share/$libdir/pkgconfig")
include("$(pwd)/cmake/$toolchain.cmake")
EOF
cmake_flags_extra="$cmake_flags_extra -D CMAKE_TOOLCHAIN_FILE=toolchain.cmake"
strip_binary="$arch_gnu-strip"
@@ -275,6 +295,12 @@ EOF
sudo apt-get update
DEBIAN_FRONTEND=noninteractive sudo apt-get -y install $pkgs $libpkgs
sudo apt-get clean
# Link against the system libslirp instead of compiling ours.
cmake_flags_extra="$cmake_flags_extra -D SLIRP_EXTERNAL=ON"
# Use OpenAL for Linux builds before FAudio builds are set up.
cmake_flags_extra="$cmake_flags_extra -D OPENAL=ON"
fi
# Clean workspace.
@@ -288,11 +314,11 @@ find . \( -name Makefile -o -name CMakeCache.txt -o -name CMakeFiles \) -exec rm
# Add ARCH to skip the arch_detect process.
case $arch in
32 | x86) cmake_flags_extra="$cmake_flags_extra -D ARCH=i386";;
64 | x86_64) cmake_flags_extra="$cmake_flags_extra -D ARCH=x86_64";;
ARM32 | arm32) cmake_flags_extra="$cmake_flags_extra -D ARCH=arm";;
ARM64 | arm64) cmake_flags_extra="$cmake_flags_extra -D ARCH=arm64";;
*) cmake_flags_extra="$cmake_flags_extra -D \"ARCH=$arch\"";;
32 | x86) cmake_flags_extra="$cmake_flags_extra -D ARCH=i386";;
64 | x86_64) cmake_flags_extra="$cmake_flags_extra -D ARCH=x86_64";;
ARM32 | arm32) cmake_flags_extra="$cmake_flags_extra -D ARCH=arm";;
ARM64 | arm64) cmake_flags_extra="$cmake_flags_extra -D ARCH=arm64";;
*) cmake_flags_extra="$cmake_flags_extra -D \"ARCH=$arch\"";;
esac
# Add git hash.
@@ -333,6 +359,26 @@ then
exit 4
fi
# Download Discord Game SDK from their CDN if necessary.
if [ ! -e "discord_game_sdk.zip" ]
then
echo [-] Downloading Discord Game SDK
wget -qO discord_game_sdk.zip "https://dl-game-sdk.discordapp.net/2.5.6/discord_game_sdk.zip"
status=$?
if [ $status -ne 0 ]
then
echo [!] Discord Game SDK download failed with status [$status]
rm -f discord_game_sdk.zip
fi
fi
# Determine Discord Game SDK architecture.
case $arch in
32) arch_discord="x86";;
64) arch_discord="x86_64";;
*) arch_discord="$arch";;
esac
# Create temporary directory for archival.
echo [-] Gathering archive files
rm -rf archive_tmp
@@ -363,15 +409,9 @@ then
cp -p "$gs"/bin/gsdll*.dll archive_tmp/
done
# Archive Discord Game SDK DLL from their CDN.
discordarch=
[ "$arch" = "32" ] && discordarch=x86
[ "$arch" = "64" ] && discordarch=x86_64
if [ ! -z "$discordarch" ]
then
[ ! -e "discord_game_sdk.zip" ] && wget -qOdiscord_game_sdk.zip https://dl-game-sdk.discordapp.net/2.5.6/discord_game_sdk.zip
"$sevenzip" e -y -oarchive_tmp discord_game_sdk.zip lib/$discordarch/discord_game_sdk.dll
fi
# Archive Discord Game SDK DLL.
"$sevenzip" e -y -o"archive_tmp" discord_game_sdk.zip "lib/$arch_discord/discord_game_sdk.dll"
[ ! -e "archive_tmp/discord_game_sdk.dll" ] && echo [!] No Discord Game SDK for architecture [$arch_discord]
# Archive other DLLs from local directory.
cp -p "/home/$project/dll$arch/"* archive_tmp/
@@ -390,9 +430,62 @@ then
# TBD
:
else
cwd_root=$(pwd)
# Build openal-soft 1.21.1 manually to fix audio issues. This is a temporary
# workaround until a newer version of openal-soft trickles down to Debian repos.
if [ -d "openal-soft-1.21.1" ]
then
rm -rf openal-soft-1.21.1/build/*
else
wget -qO - https://github.com/kcat/openal-soft/archive/refs/tags/1.21.1.tar.gz | tar zxf -
fi
cd openal-soft-1.21.1/build
[ -e Makefile ] && make clean
cmake -G "Unix Makefiles" -D "CMAKE_TOOLCHAIN_FILE=$cwd_root/toolchain.cmake" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" ..
make -j$(nproc) install || exit 99
cd "$cwd_root"
# Build rtmidi without JACK support to remove the dependency on libjack.
if [ -d "rtmidi-4.0.0" ]
then
rm -rf rtmidi-4.0.0/CMakeCache.txt rtmidi-4.0.0/CMakeFiles
else
wget -qO - http://www.music.mcgill.ca/~gary/rtmidi/release/rtmidi-4.0.0.tar.gz | tar zxf -
fi
cwd_root=$(pwd)
cd rtmidi-4.0.0
[ -e Makefile ] && make clean
cmake -G "Unix Makefiles" -D RTMIDI_API_JACK=OFF -D "CMAKE_TOOLCHAIN_FILE=$cwd_root/toolchain.cmake" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" .
make -j$(nproc) install || exit 99
cd "$cwd_root"
# Build SDL2 for joystick support with most components disabled to remove the dependencies on PulseAudio and libdrm.
if [ ! -d "SDL2-2.0.20" ]
then
wget -qO - https://www.libsdl.org/release/SDL2-2.0.20.tar.gz | tar zxf -
fi
rm -rf sdlbuild
mkdir sdlbuild
cd sdlbuild
cmake -G "Unix Makefiles" -D SDL_DISKAUDIO=OFF -D SDL_DIRECTFB_SHARED=OFF -D SDL_OPENGL=OFF -D SDL_OPENGLES=OFF -D SDL_OSS=OFF -D SDL_ALSA=OFF \
-D SDL_ALSA_SHARED=OFF -D SDL_JACK=OFF -D SDL_JACK_SHARED=OFF -D SDL_ESD=OFF -D SDL_ESD_SHARED=OFF -D SDL_PIPEWIRE=OFF -D SDL_PIPEWIRE_SHARED=OFF \
-D SDL_PULSEAUDIO=OFF -D SDL_PULSEAUDIO_SHARED=OFF -D SDL_ARTS=OFF -D SDL_ARTS_SHARED=OFF -D SDL_NAS=OFF -D SDL_NAS_SHARED=OFF -D SDL_SNDIO=OFF \
-D SDL_SNDIO_SHARED=OFF -D SDL_FUSIONSOUND=OFF -D SDL_FUSIONSOUND_SHARED=OFF -D SDL_LIBSAMPLERATE=OFF -D SDL_LIBSAMPLERATE_SHARED=OFF -D SDL_X11=OFF \
-D SDL_X11_SHARED=OFF -D SDL_WAYLAND=OFF -D SDL_WAYLAND_SHARED=OFF -D SDL_WAYLAND_LIBDECOR=OFF -D SDL_WAYLAND_LIBDECOR_SHARED=OFF \
-D SDL_WAYLAND_QT_TOUCH=OFF -D SDL_RPI=OFF -D SDL_VIVANTE=OFF -D SDL_VULKAN=OFF -D SDL_KMSDRM=OFF -D SDL_KMSDRM_SHARED=OFF -D SDL_OFFSCREEN=OFF \
-D SDL_HIDAPI_JOYSTICK=ON -D SDL_VIRTUAL_JOYSTICK=ON -D SDL_SHARED=ON -D SDL_STATIC=OFF -S "$cwd_root/SDL2-2.0.20" \
-D "CMAKE_TOOLCHAIN_FILE=$cwd_root/toolchain.cmake" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr"
make -j$(nproc) install || exit 99
cd "$cwd_root"
# Archive Discord Game SDK library.
7z e -y -o"archive_tmp/usr/lib" discord_game_sdk.zip "lib/$arch_discord/discord_game_sdk.so"
[ ! -e "archive_tmp/usr/lib/discord_game_sdk.so" ] && echo [!] No Discord Game SDK for architecture [$arch_discord]
# Archive readme with library package versions.
echo Libraries used to compile this $arch build of $project: > archive_tmp/README
dpkg-query -f '${Package} ${Version}\n' -W $libpkgs | sed "s/-dev / /" | while IFS=" " read pkg version
dpkg-query -f '${Package} ${Version}\n' -W $libpkgs | sed "s/-dev / /" | sed "s/qtdeclarative/qt/" | while IFS=" " read pkg version
do
for i in $(seq $(expr $longest_libpkg - $(echo -n $pkg | wc -c)))
do
@@ -401,13 +494,20 @@ else
echo $pkg $version >> archive_tmp/README
done
# Archive icon, while also shrinking it to 512x512 if necessary.
convert src/win/assets/$project_lower.png -resize '512x512>' icon.png
icon_base="$(identify -format 'archive_tmp/usr/share/icons/%wx%h' icon.png)"
mkdir -p "$icon_base"
mv icon.png "$icon_base/$project_lower.png"
# Archive executable, while also stripping it if requested.
mkdir -p archive_tmp/usr/local/bin
if [ $strip -ne 0 ]
then
"$strip_binary" -o "archive_tmp/$project" "build/src/$project"
"$strip_binary" -o "archive_tmp/usr/local/bin/$project" "build/src/$project"
status=$?
else
mv "build/src/$project" "archive_tmp/$project"
mv "build/src/$project" "archive_tmp/usr/local/bin/$project"
status=$?
fi
fi
@@ -421,20 +521,50 @@ fi
# Produce artifact archive.
echo [-] Creating artifact archive
cd archive_tmp
if is_windows
then
# Create zip.
"$sevenzip" a -y -mx9 "$(cygpath -w "$cwd")\\$package_name.zip" *
cd archive_tmp
"$sevenzip" a -y "$(cygpath -w "$cwd")\\$package_name.zip" *
status=$?
elif is_mac
then
# TBD
:
else
# Create binary tarball.
VERBOSE=1 make_tar "$cwd/$package_name.tar"
# Determine AppImage runtime architecture.
case $arch in
x86) arch_appimage="i686";;
arm32) arch_appimage="armhf";;
arm64) arch_appimage="aarch64";;
*) arch_appimage="$arch";;
esac
# Get version for AppImage metadata.
project_version=$(grep -oP '#define\s+EMU_VERSION\s+"\K([^"]+)' "build/src/include/$project_lower/version.h" 2> /dev/null)
[ -z "$project_version" ] && project_version=unknown
build_num=$(grep -oP '#define\s+EMU_BUILD_NUM\s+\K([0-9]+)' "build/src/include/$project_lower/version.h" 2> /dev/null)
[ ! -z "$build_num" -a "$build_num" != "0" ] && project_version="$project_version-b$build_num"
# Download appimage-builder if necessary.
[ ! -e "appimage-builder.AppImage" ] && wget -qO appimage-builder.AppImage \
https://github.com/AppImageCrafters/appimage-builder/releases/download/v0.9.2/appimage-builder-0.9.2-35e3eab-x86_64.AppImage
chmod u+x appimage-builder.AppImage
# Remove any dangling AppImages which may interfere with the renaming process.
rm -rf "$project-"*".AppImage"
# Run appimage-builder in extract-and-run mode for Docker compatibility.
project="$project" project_lower="$project_lower" project_version="$project_version" arch_deb="$arch_deb" arch_appimage="$arch_appimage" \
APPIMAGE_EXTRACT_AND_RUN=1 ./appimage-builder.AppImage --recipe .ci/AppImageBuilder.yml
status=$?
# Rename AppImage to the final name if the build succeeded.
if [ $status -eq 0 ]
then
mv "$project-"*".AppImage" "$cwd/$package_name.AppImage"
status=$?
fi
fi
cd ..

4
.editorconfig
View File

@@ -32,3 +32,7 @@ indent_size = 4
[*.cmake]
indent_style = space
indent_size = 4
[*.json]
indent_style = space
indent_size = 4

115
.github/workflows/cmake.yml vendored
View File

@@ -25,20 +25,20 @@ jobs:
msys2:
name: MSYS2 ${{ matrix.build.name }} build (${{ matrix.environment.msystem }})
runs-on: windows-latest
runs-on: windows-2022
defaults:
run:
shell: msys2 {0}
strategy:
fail-fast: false
fail-fast: true
matrix:
build:
- name: Regular ODR
slug: -ODR
preset: regular
target: install/strip
# - name: Regular ODR
# slug: -ODR
# preset: regular
# target: install/strip
- name: Debug ODR
slug: -ODR-Debug
preset: debug
@@ -47,10 +47,10 @@ jobs:
slug: -ODR-Dev
preset: experimental
target: install
- name: Regular NDR
slug: -NDR
preset: regularndr
target: install/strip
# - name: Regular NDR
# slug: -NDR
# preset: regularndr
# target: install/strip
- name: Debug NDR
slug: -NDR-Debug
preset: debugndr
@@ -68,8 +68,8 @@ jobs:
prefix: mingw-w64-ucrt-x86_64
# - msystem: CLANG32
# prefix: mingw-w64-clang-i686
- msystem: CLANG64
prefix: mingw-w64-clang-x86_64
# - msystem: CLANG64
# prefix: mingw-w64-clang-x86_64
steps:
- uses: msys2/setup-msys2@v2
@@ -111,15 +111,15 @@ jobs:
VCPKG_BINARY_SOURCES: 'clear;nuget,GitHub,readwrite'
strategy:
fail-fast: false
fail-fast: true
matrix:
build:
- name: Regular ODR
slug: -ODR
type: Release
dev-build: off
new-dynarec: off
strip: --strip
# - name: Regular ODR
# slug: -ODR
# type: Release
# dev-build: off
# new-dynarec: off
# strip: --strip
- name: Debug ODR
slug: -ODR-Debug
type: Debug
@@ -130,12 +130,12 @@ jobs:
type: Debug
dev-build: on
new-dynarec: off
- name: Regular NDR
slug: -NDR
type: Release
strip: --strip
dev-build: off
new-dynarec: on
# - name: Regular NDR
# slug: -NDR
# type: Release
# strip: --strip
# dev-build: off
# new-dynarec: on
- name: Debug NDR
slug: -NDR-Debug
type: Debug
@@ -210,18 +210,18 @@ jobs:
linux:
name: "Linux GCC 11 (${{ matrix.build.name }} x86_64)"
runs-on: ubuntu-latest
runs-on: ubuntu-20.04
strategy:
fail-fast: false
fail-fast: true
matrix:
build:
- name: Regular ODR
slug: -ODR
type: Release
dev-build: off
new-dynarec: off
strip: --strip
# - name: Regular ODR
# slug: -ODR
# type: Release
# dev-build: off
# new-dynarec: off
# strip: --strip
- name: Debug ODR
slug: -ODR-Debug
type: Debug
@@ -232,12 +232,12 @@ jobs:
type: Debug
dev-build: on
new-dynarec: off
- name: Regular NDR
slug: -NDR
type: Release
strip: --strip
dev-build: off
new-dynarec: on
# - name: Regular NDR
# slug: -NDR
# type: Release
# strip: --strip
# dev-build: off
# new-dynarec: on
- name: Debug NDR
slug: -NDR-Debug
type: Debug
@@ -252,14 +252,14 @@ jobs:
steps:
- uses: actions/checkout@v2
- name: Install dependencies
run: sudo apt update && sudo apt install gcc-11 g++-11 libfreetype-dev libsdl2-dev libpng-dev libopenal-dev libc6-dev librtmidi-dev
run: sudo apt update && sudo apt install gcc-11 g++-11 libfreetype-dev libsdl2-dev libpng-dev libopenal-dev libc6-dev librtmidi-dev qtbase5-dev qttools5-dev libfaudio-dev
- name: Configure CMake
run: >-
cmake -S . -B build
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D DEV_BRANCH=${{ matrix.build.dev-build }}
-D NEW_DYNAREC=${{ matrix.build.new-dynarec }}
-D VNC=OFF
-D QT=ON
-D CMAKE_BUILD_TYPE=${{ matrix.build.type }}
-D CMAKE_C_COMPILER=gcc-11 -D CMAKE_CXX_COMPILER=g++-11
- name: Build
@@ -268,7 +268,7 @@ jobs:
run: cmake --install build --prefix ./build/artifacts ${{ matrix.build.strip }}
- uses: actions/upload-artifact@v2
with:
name: '86Box${{ matrix.build.slug }}-Linux-x86_64-gha${{ github.run_number }}'
name: '86Box${{ matrix.build.slug }}-UbuntuFocal-x86_64-gha${{ github.run_number }}'
path: build/artifacts/**
macos11:
@@ -277,15 +277,15 @@ jobs:
runs-on: macos-11
strategy:
fail-fast: false
fail-fast: true
matrix:
build:
- name: Regular ODR
slug: -ODR
type: Release
dev-build: off
new-dynarec: off
strip: --strip
# - name: Regular ODR
# slug: -ODR
# type: Release
# dev-build: off
# new-dynarec: off
# strip: --strip
- name: Debug ODR
slug: -ODR-Debug
type: Debug
@@ -296,12 +296,12 @@ jobs:
type: Debug
dev-build: on
new-dynarec: off
- name: Regular NDR
slug: -NDR
type: Release
strip: --strip
dev-build: off
new-dynarec: on
# - name: Regular NDR
# slug: -NDR
# type: Release
# strip: --strip
# dev-build: off
# new-dynarec: on
- name: Debug NDR
slug: -NDR-Debug
type: Debug
@@ -316,7 +316,7 @@ jobs:
steps:
- uses: actions/checkout@v2
- name: Install dependencies
run: brew install freetype sdl2 libpng openal-soft rtmidi
run: brew install freetype sdl2 libpng openal-soft rtmidi qt@5 faudio
- name: Configure CMake
run: >-
cmake -S . -B build
@@ -325,6 +325,9 @@ jobs:
-D NEW_DYNAREC=${{ matrix.build.new-dynarec }}
-D VNC=OFF
-D CMAKE_BUILD_TYPE=${{ matrix.build.type }}
-D QT=ON
-D Qt5_DIR=/usr/local/Cellar/qt@5/5.15.2_1/lib/cmake/Qt5
-D Qt5LinguistTools_DIR=/usr/local/Cellar/qt@5/5.15.2_1/lib/cmake/Qt5LinguistTools/
- name: Build
run: cmake --build build
- name: Generate package

2
.gitignore vendored
View File

@@ -31,6 +31,8 @@ Makefile
*.zip
*.tar
*.tar.*
*.AppImage
/appimage-builder-cache
# Visual Studio Code
/.vs

10
AUTHORS
View File

@@ -1,5 +1,5 @@
All authors of this emulator are documented in at the top of each file in the source code.
They own portions of the code, or in cases, the entirety of it.
resid-fp and slirp folders have their own exceptions.
All authors of this emulator are documented in at the top of each file in the source code.
They own portions of the code, or in cases, the entirety of it.
resid-fp and slirp folders have their own exceptions.

64
CMakeLists.txt
View File

@@ -18,12 +18,20 @@ cmake_minimum_required(VERSION 3.16)
cmake_policy(SET CMP0091 NEW)
cmake_policy(SET CMP0079 NEW)
if (QT)
if(QT)
list(APPEND VCPKG_MANIFEST_FEATURES "qt-ui")
endif()
if(SLIRP_EXTERNAL)
list(APPEND VCPKG_MANIFEST_FEATURES "slirp")
endif()
if(MUNT_EXTERNAL)
list(APPEND VCPKG_MANIFEST_FEATURES "munt")
endif()
project(86Box
VERSION 3.2
VERSION 3.3
DESCRIPTION "Emulator of x86-based systems"
HOMEPAGE_URL "https://86box.net"
LANGUAGES C CXX)
@@ -32,26 +40,26 @@ include(CPack)
include(CMakeDependentOption)
# Basic build options
if(WIN32)
if(VCPKG_TOOLCHAIN)
# For vcpkg builds we have to respect the linking method used by the
# specified triplet.
set(NO_STATIC_OPTION ON)
if(VCPKG_TARGET_TRIPLET MATCHES "-windows-static$")
# `-static` triplet, use static linking
set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded$<$<CONFIG:Debug>:Debug>")
set(STATIC_BUILD ON)
elseif(VCPKG_TARGET_TRIPLET MATCHES "-windows-static-md$")
# `-static-md` triplet, use static linking with dynamic CRT
set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded$<$<CONFIG:Debug>:Debug>DLL")
set(STATIC_BUILD ON)
elseif()
# Regular triplet, use dynamic linking
set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded$<$<CONFIG:Debug>:Debug>DLL")
set(STATIC_BUILD OFF)
endif()
if(VCPKG_TOOLCHAIN)
# For vcpkg builds we have to respect the linking method used by the
# specified triplet.
set(NO_STATIC_OPTION ON)
if(VCPKG_TARGET_TRIPLET MATCHES "-static$")
# `-static` triplet, use static linking
set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded$<$<CONFIG:Debug>:Debug>")
set(STATIC_BUILD ON)
elseif(VCPKG_TARGET_TRIPLET MATCHES "-static-md$")
# `-static-md` triplet, use static linking with dynamic CRT
set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded$<$<CONFIG:Debug>:Debug>DLL")
set(STATIC_BUILD ON)
elseif()
# Regular triplet, use dynamic linking
set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded$<$<CONFIG:Debug>:Debug>DLL")
set(STATIC_BUILD OFF)
endif()
endif()
if(WIN32)
# Prefer static builds on Windows
set(PREFER_STATIC ON)
@@ -98,6 +106,7 @@ if(WIN32)
endif()
set(CMAKE_CXX_STANDARD 11)
set(CMAKE_FIND_PACKAGE_PREFER_CONFIG ON)
# Optional features
#
@@ -105,7 +114,7 @@ set(CMAKE_CXX_STANDARD 11)
# ------ ----------- ----
option(RELEASE "Release build" OFF)
option(DYNAREC "Dynamic recompiler" ON)
option(OPENAL "OpenAL" ON)
option(OPENAL "OpenAL" OFF)
option(FLUIDSYNTH "FluidSynth" ON)
option(MUNT "MUNT" ON)
option(DINPUT "DirectInput" OFF)
@@ -113,7 +122,11 @@ option(CPPTHREADS "C++11 threads"
option(NEW_DYNAREC "Use the PCem v15 (\"new\") dynamic recompiler" OFF)
option(MINITRACE "Enable Chrome tracing using the modified minitrace library" OFF)
option(DEV_BRANCH "Development branch" OFF)
if(NOT WIN32)
option(QT "QT GUI" ON)
else()
option(QT "QT GUI" OFF)
endif()
# Development branch features
#
@@ -122,6 +135,9 @@ option(QT "QT GUI"
cmake_dependent_option(AMD_K5 "AMD K5" ON "DEV_BRANCH" OFF)
cmake_dependent_option(CYRIX_6X86 "Cyrix 6x86" ON "DEV_BRANCH" OFF)
cmake_dependent_option(GUSMAX "Gravis UltraSound MAX" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_RAMPAGE "AST Rampage" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_IAB "Intel Above Board" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_BRAT "BocaRAM/AT" ON "DEV_BRANCH" OFF)
cmake_dependent_option(LASERXT "VTech Laser XT" ON "DEV_BRANCH" OFF)
cmake_dependent_option(MGA "Matrox Mystique graphics adapters" ON "DEV_BRANCH" OFF)
cmake_dependent_option(NO_SIO "Machines without emulated Super I/O chips" ON "DEV_BRANCH" OFF)
@@ -129,12 +145,10 @@ cmake_dependent_option(OLIVETTI "Olivetti M290"
cmake_dependent_option(OPEN_AT "OpenAT" ON "DEV_BRANCH" OFF)
cmake_dependent_option(PAS16 "Pro Audio Spectrum 16" OFF "DEV_BRANCH" OFF)
cmake_dependent_option(SIO_DETECT "Super I/O Detection Helper" ON "DEV_BRANCH" OFF)
cmake_dependent_option(TANDY_ISA "Tandy PSG ISA clone boards" ON "DEV_BRANCH" OFF)
cmake_dependent_option(VGAWONDER "ATI VGA Wonder (ATI-18800)" ON "DEV_BRANCH" OFF)
cmake_dependent_option(VNC "VNC renderer" OFF "DEV_BRANCH" OFF)
cmake_dependent_option(XL24 "ATI VGA Wonder XL24 (ATI-28800-6)" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_RAMPAGE "AST Rampage" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_IAB "Intel Above Board" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_BRAT "BocaRAM/AT" ON "DEV_BRANCH" OFF)
# Ditto but for Qt
if (QT)
@@ -169,7 +183,7 @@ if(NOT EMU_BUILD_NUM)
set(EMU_BUILD_NUM 0)
endif()
if(NOT EMU_COPYRIGHT_YEAR)
set(EMU_COPYRIGHT_YEAR 2021)
set(EMU_COPYRIGHT_YEAR 2022)
endif()
add_subdirectory(src)

10
CMakePresets.json
View File

@@ -9,15 +9,7 @@
{
"name": "flags-base",
"cacheVariables": {
"CMAKE_CONFIGURATION_TYPES": "Debug;Release;Optimized",
"CMAKE_C_FLAGS": "-msse2 -mfpmath=sse -fomit-frame-pointer -mstackrealign -Wall -fno-strict-aliasing",
"CMAKE_CXX_FLAGS": "-msse2 -mfpmath=sse -fomit-frame-pointer -mstackrealign -Wall -fno-strict-aliasing",
"CMAKE_C_FLAGS_RELEASE": "-g0 -O3",
"CMAKE_CXX_FLAGS_RELEASE": "-g0 -O3",
"CMAKE_C_FLAGS_DEBUG": "-ggdb -Og",
"CMAKE_CXX_FLAGS_DEBUG": "-ggdb -Og",
"CMAKE_C_FLAGS_OPTIMIZED": "-march=native -mtune=native -O3 -ffp-contract=fast -flto",
"CMAKE_CXX_FLAGS_OPTIMIZED": "-march=native -mtune=native -O3 -ffp-contract=fast -flto"
"CMAKE_CONFIGURATION_TYPES": "Debug;Release;Optimized"
},
"hidden": true,
"binaryDir": "build"

6
README.md
View File

@@ -15,14 +15,16 @@ Features
System requirements and recommendations
---------------------------------------
* Intel Core 2 or AMD Athlon 64 processor
* Windows 7 Service Pack 1, Windows 8.1 or Windows 10
* Windows version: Windows 7 Service Pack 1, Windows 8.1 or Windows 10
* Linux version: Ubuntu 16.04, Debian 9.0 or other distributions from 2016 onwards
* 4 GB of RAM
Performance may vary depending on both host and guest configuration. Most emulation logic is executed in a single thread, therefore generally systems with better IPC (instructions per clock) should be able to emulate higher clock speeds.
It is also recommended to use a manager application with 86Box for easier handling of multiple virtual machines.
It is also recommended to use a manager application (**Windows only**) with 86Box for easier handling of multiple virtual machines.
* [WinBox for 86Box](https://github.com/86Box/WinBox-for-86Box) by Laci bá'
* The new manager with improved new user experience; installer, automatic updates of emulator files and more.
* While development is suspended and the repository is archived, the latest version is fully functional.
* [86Box Manager](https://github.com/86Box/86BoxManager) by [daviunic](https://github.com/daviunic) (Overdoze)
* The traditional 86Box manager with simple interface.

4
cmake/flags-gcc-aarch64.cmake
View File

@@ -14,7 +14,7 @@
# Copyright 2021 David Hrdlička.
#
string(APPEND CMAKE_C_FLAGS_INIT " -march=armv8-a -mfloat-abi=hard")
string(APPEND CMAKE_CXX_FLAGS_INIT " -march=armv8-a -mfloat-abi=hard")
string(APPEND CMAKE_C_FLAGS_INIT " -march=armv8-a ${CMAKE_C_FLAGS_INIT}")
string(APPEND CMAKE_CXX_FLAGS_INIT " -march=armv8-a ${CMAKE_CXX_FLAGS_INIT}")
include(${CMAKE_CURRENT_LIST_DIR}/flags-gcc.cmake)

4
cmake/flags-gcc-i686.cmake
View File

@@ -14,7 +14,7 @@
# Copyright 2021 David Hrdlička.
#
string(APPEND CMAKE_C_FLAGS_INIT " -m32 -march=i686 -msse2 -mfpmath=sse ${CMAKE_C_FLAGS_INIT}")
string(APPEND CMAKE_CXX_FLAGS_INIT " -m32 -march=i686 -msse2 -mfpmath=sse ${CMAKE_CXX_FLAGS_INIT}")
string(APPEND CMAKE_C_FLAGS_INIT " -m32 -march=i686 -msse2 -mfpmath=sse -mstackrealign ${CMAKE_C_FLAGS_INIT}")
string(APPEND CMAKE_CXX_FLAGS_INIT " -m32 -march=i686 -msse2 -mfpmath=sse -mstackrealign ${CMAKE_CXX_FLAGS_INIT}")
include(${CMAKE_CURRENT_LIST_DIR}/flags-gcc.cmake)

4
cmake/flags-gcc-x86_64.cmake
View File

@@ -14,7 +14,7 @@
# Copyright 2021 David Hrdlička.
#
string(APPEND CMAKE_C_FLAGS_INIT " -m64 -march=x86-64 -msse2 -mfpmath=sse ${CMAKE_C_FLAGS_INIT}")
string(APPEND CMAKE_CXX_FLAGS_INIT " -m64 -march=x86-64 -msse2 -mfpmath=sse ${CMAKE_CXX_FLAGS_INIT}")
string(APPEND CMAKE_C_FLAGS_INIT " -m64 -march=x86-64 -msse2 -mfpmath=sse -mstackrealign ${CMAKE_C_FLAGS_INIT}")
string(APPEND CMAKE_CXX_FLAGS_INIT " -m64 -march=x86-64 -msse2 -mfpmath=sse -mstackrealign ${CMAKE_CXX_FLAGS_INIT}")
include(${CMAKE_CURRENT_LIST_DIR}/flags-gcc.cmake)

4
cmake/flags-gcc.cmake
View File

@@ -14,8 +14,8 @@
#
# Define our flags
string(APPEND CMAKE_C_FLAGS_INIT " -fomit-frame-pointer -mstackrealign -Wall -fno-strict-aliasing")
string(APPEND CMAKE_CXX_FLAGS_INIT " -fomit-frame-pointer -mstackrealign -Wall -fno-strict-aliasing")
string(APPEND CMAKE_C_FLAGS_INIT " -fomit-frame-pointer -Wall -fno-strict-aliasing")
string(APPEND CMAKE_CXX_FLAGS_INIT " -fomit-frame-pointer -Wall -fno-strict-aliasing")
string(APPEND CMAKE_C_FLAGS_RELEASE_INIT " -g0 -O3")
string(APPEND CMAKE_CXX_FLAGS_RELEASE_INIT " -g0 -O3")
string(APPEND CMAKE_C_FLAGS_DEBUG_INIT " -ggdb -Og")

31
src/86box.c
View File

@@ -395,8 +395,8 @@ pc_init(int argc, char *argv[])
{
char path[2048], path2[2048];
char *cfg = NULL, *p;
#ifdef __APPLE__
char mac_rom_path[2048];
#if !defined(__APPLE__) && !defined(_WIN32)
char *appimage;
#endif
char temp[128];
struct tm *info;
@@ -405,7 +405,7 @@ pc_init(int argc, char *argv[])
int ng = 0, lvmp = 0;
uint32_t *uid, *shwnd;
uint32_t lang_init = 0;
/* Grab the executable's full path. */
plat_get_exe_name(exe_path, sizeof(exe_path)-1);
p = plat_get_filename(exe_path);
@@ -421,7 +421,7 @@ pc_init(int argc, char *argv[])
*/
plat_getcwd(usr_path, sizeof(usr_path) - 1);
plat_getcwd(rom_path, sizeof(rom_path) - 1);
memset(path, 0x00, sizeof(path));
memset(path2, 0x00, sizeof(path));
@@ -590,11 +590,20 @@ usage:
plat_dir_create(usr_path);
}
if (path2[0] == '\0') {
#if defined(__APPLE__)
getDefaultROMPath(path2);
#elif !defined(_WIN32)
appimage = getenv("APPIMAGE");
if (appimage && (appimage[0] != '\0')) {
plat_get_dirname(path2, appimage);
plat_path_slash(path2);
strcat(path2, "roms");
plat_path_slash(path2);
}
#endif
}
#ifdef __APPLE__
getDefaultROMPath(mac_rom_path);
strcpy(path2, mac_rom_path);
#endif
if (vmrp && (path2[0] == '\0')) {
strcpy(path2, usr_path);
plat_path_slash(path2);
@@ -718,7 +727,7 @@ usage:
/* Load the configuration file. */
config_load();
/* Load the desired language */
if (lang_init)
lang_id = lang_init;
@@ -932,9 +941,7 @@ pc_reset_hard_close(void)
scsi_disk_close();
#ifdef USE_OPENAL
closeal();
#endif
video_reset_close();
@@ -1062,7 +1069,7 @@ pc_reset_hard_init(void)
void update_mouse_msg()
{
wchar_t wcpufamily[2048], wcpu[2048], wmachine[2048], *wcp;
mbstowcs(wmachine, machine_getname(), strlen(machine_getname())+1);
if (!cpu_override)

133
src/CMakeLists.txt
View File

@@ -11,14 +11,13 @@
# Authors: David Hrdlička, <hrdlickadavid@outlook.com>
# dob205
#
# Copyright 2020,2021 David Hrdlička.
# Copyright 2020-2022 David Hrdlička.
# Copyright 2021 dob205.
#
# WIN32 marks us as a GUI app on Windows
add_executable(86Box WIN32 MACOSX_BUNDLE 86box.c config.c log.c random.c timer.c io.c acpi.c apm.c
dma.c ddma.c discord.c nmi.c pic.c pit.c port_6x.c port_92.c ppi.c pci.c mca.c usb.c fifo8.c
device.c nvr.c nvr_at.c nvr_ps2.c)
add_executable(86Box 86box.c config.c log.c random.c timer.c io.c acpi.c apm.c
dma.c ddma.c discord.c nmi.c pic.c pit.c port_6x.c port_92.c ppi.c pci.c
mca.c usb.c fifo8.c device.c nvr.c nvr_at.c nvr_ps2.c)
if(CPPTHREADS)
target_sources(86Box PRIVATE thread.cpp)
@@ -44,7 +43,7 @@ if(VNC)
add_compile_definitions(USE_VNC)
add_library(vnc OBJECT vnc.c vnc_keymap.c)
target_link_libraries(86Box vnc vncserver)
if (WIN32)
if(WIN32)
target_link_libraries(86Box ws2_32)
endif()
endif()
@@ -79,25 +78,6 @@ if(APPLE)
endif()
endif()
if(QT)
set(CMAKE_CXX_STANDARD 17)
set(CMAKE_CXX_STANDARD_REQUIRED ON)
set(CMAKE_CXX_EXTENSIONS OFF)
if (USE_QT6)
set(QT_MAJOR 6)
else()
set(QT_MAJOR 5)
endif()
# if we want to use qt5-static to eliminate need for bundling qt dlls (windows)
#set(QT_STATIC ON)
# needed to build with qt5-static if both qt5 and qt5-static are installed
#set(CMAKE_PREFIX_PATH "path/to/qt5-static")
find_package(Qt${QT_MAJOR} COMPONENTS Core Widgets OpenGL REQUIRED)
find_package(Qt${QT_MAJOR}LinguistTools REQUIRED)
endif()
find_package(Freetype REQUIRED)
include_directories(${FREETYPE_INCLUDE_DIRS})
if(APPLE)
@@ -106,12 +86,6 @@ if(APPLE)
target_link_libraries(86Box Freetype::Freetype)
endif()
if(OPENAL)
find_package(OpenAL REQUIRED)
include_directories(${OPENAL_INCLUDE_DIR})
target_link_libraries(86Box ${OPENAL_LIBRARY})
endif()
find_package(SDL2 REQUIRED)
include_directories(${SDL2_INCLUDE_DIRS})
if(STATIC_BUILD AND TARGET SDL2::SDL2-static)
@@ -174,90 +148,29 @@ else()
install(TARGETS 86Box)
endif()
# prepare everything for Qt5 bundle creation
if (APPLE AND QT)
set(prefix "86Box.app/Contents")
set(INSTALL_RUNTIME_DIR "${prefix}/MacOS")
set(INSTALL_CMAKE_DIR "${prefix}/Resources")
endif()
# loads a macro to install Qt5 plugins on macOS
# based on https://stackoverflow.com/questions/35612687/cmake-macos-x-bundle-with-bundleutiliies-for-qt-application
macro(install_qt5_plugin _qt_plugin_name _qt_plugins_var _prefix)
get_target_property(_qt_plugin_path "${_qt_plugin_name}" LOCATION)
if(EXISTS "${_qt_plugin_path}")
get_filename_component(_qt_plugin_file "${_qt_plugin_path}" NAME)
get_filename_component(_qt_plugin_type "${_qt_plugin_path}" PATH)
get_filename_component(_qt_plugin_type "${_qt_plugin_type}" NAME)
set(_qt_plugin_dest "${_prefix}/PlugIns/${_qt_plugin_type}")
install(FILES "${_qt_plugin_path}"
DESTINATION "${_qt_plugin_dest}")
set(${_qt_plugins_var}
"${${_qt_plugins_var}};\$ENV{DEST_DIR}\${CMAKE_INSTALL_PREFIX}/${_qt_plugin_dest}/${_qt_plugin_file}")
else()
message(FATAL_ERROR "QT plugin ${_qt_plugin_name} not found")
endif()
endmacro()
# Install our dependencies to the macOS bundle
if(APPLE)
if (NOT QT)
install(CODE "
include(BundleUtilities)
get_filename_component(CMAKE_INSTALL_PREFIX_ABSOLUTE \${CMAKE_INSTALL_PREFIX} ABSOLUTE)
fixup_bundle(\"\${CMAKE_INSTALL_PREFIX_ABSOLUTE}/86Box.app\" \"\" \"\")"
COMPONENT Runtime)
endif()
if(QT)
# using the install_qt5_plugin to add Qt plugins into the macOS app bundle
if (USE_QT6)
install_qt5_plugin("Qt6::QCocoaIntegrationPlugin" QT_PLUGINS ${prefix})
else()
install_qt5_plugin("Qt5::QCocoaIntegrationPlugin" QT_PLUGINS ${prefix})
install_qt5_plugin("Qt5::QMacStylePlugin" QT_PLUGINS ${prefix})
install_qt5_plugin("Qt5::QICOPlugin" QT_PLUGINS ${prefix})
install_qt5_plugin("Qt5::QICNSPlugin" QT_PLUGINS ${prefix})
endif()
file(WRITE "${CMAKE_CURRENT_BINARY_DIR}/qt.conf"
"[Paths]\nPlugins = ${_qt_plugin_dir}\n")
install(FILES "${CMAKE_CURRENT_BINARY_DIR}/qt.conf"
DESTINATION "${INSTALL_CMAKE_DIR}")
# Note Mac specific extension .app
set(APPS "\$ENV{DESTDIR}\${CMAKE_INSTALL_PREFIX}/86Box.app")
# Directories to look for dependencies
set(DIRS "${CMAKE_BINARY_DIR}")
# Path used for searching by FIND_XXX(), with appropriate suffixes added
if(CMAKE_PREFIX_PATH)
foreach(dir ${CMAKE_PREFIX_PATH})
list(APPEND DIRS "${dir}/bin" "${dir}/lib")
endforeach()
endif()
# Append Qt's lib folder which is two levels above Qt5Widgets_DIR
list(APPEND DIRS "${Qt5Widgets_DIR}/../..")
include(InstallRequiredSystemLibraries)
message(STATUS "APPS: ${APPS}")
message(STATUS "QT_PLUGINS: ${QT_PLUGINS}")
message(STATUS "DIRS: ${DIRS}")
install(CODE "include(BundleUtilities)
fixup_bundle(\"${APPS}\" \"${QT_PLUGINS}\" \"${DIRS}\")")
endif()
endif()
# Install our dependencies if using vcpkg
if(VCPKG_TOOLCHAIN)
x_vcpkg_install_local_dependencies(TARGETS 86Box DESTINATION ".")
endif()
# Install other dependencies
if(WIN32)
install(CODE "
include(BundleUtilities)
get_filename_component(CMAKE_INSTALL_PREFIX_ABSOLUTE \${CMAKE_INSTALL_PREFIX} ABSOLUTE)
fixup_bundle(\"\${CMAKE_INSTALL_PREFIX_ABSOLUTE}/$<TARGET_FILE_NAME:86Box>\" \"\" \"\")"
COMPONENT Runtime)
elseif(APPLE AND NOT QT)
install(CODE "
include(BundleUtilities)
get_filename_component(CMAKE_INSTALL_PREFIX_ABSOLUTE \${CMAKE_INSTALL_PREFIX} ABSOLUTE)
fixup_bundle(\"\${CMAKE_INSTALL_PREFIX_ABSOLUTE}/86Box.app\" \"\" \"\")"
COMPONENT Runtime)
endif()
# Install the PDB file on Windows builds
if(MSVC)
# CMake fully supports PDB files on MSVC-compatible compilers
@@ -288,7 +201,7 @@ add_subdirectory(scsi)
add_subdirectory(sound)
add_subdirectory(video)
if (APPLE)
add_subdirectory(mac)
add_subdirectory(mac)
endif()
if (QT)

222
src/acpi.c
View File

@@ -298,94 +298,6 @@ acpi_reg_read_intel(int size, uint16_t addr, void *p)
}
static uint32_t
acpi_reg_read_sis(int size, uint16_t addr, void *p)
{
acpi_t *dev = (acpi_t *) p;
uint32_t ret = 0x00000000;
int shift16, shift32;
addr &= 0x2f;
shift16 = (addr & 1) << 3;
shift32 = (addr & 3) << 3;
switch(addr)
{
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
ret = (dev->regs.pcntrl >> shift32) & 0xff;
break;
case 0x12:
ret = dev->regs.p2cntrl;
break;
case 0x13:
ret = dev->regs.gptimer;
break;
case 0x14: case 0x15:
ret = (dev->regs.gpsts >> shift16) & 0xff;
break;
case 0x16: case 0x17:
ret = (dev->regs.gpen >> shift16) & 0xff;
break;
case 0x18: case 0x19:
ret = (dev->regs.gpcntrl >> shift16) & 0xff;
break;
case 0x1a: case 0x1b:
ret = (dev->regs.gpen >> shift16) & 0xff;
break;
case 0x1c: case 0x1d:
ret = (dev->regs.gpmux >> shift16) & 0xff;
break;
case 0x1e: case 0x1f:
ret = (dev->regs.gplvl >> shift16) & 0xff;
break;
case 0x20:
ret = dev->regs.smicmd;
break;
case 0x24:
ret = dev->regs.muxcntrl;
break;
case 0x25:
ret = dev->regs.auxsts;
break;
case 0x26:
ret = dev->regs.auxen;
break;
case 0x2a:
ret = dev->regs.smireg;
break;
case 0x2b:
ret = dev->regs.acpitst;
break;
default:
acpi_reg_read_common_regs(size, addr, p);
break;
}
#ifdef ENABLE_ACPI_LOG
if (size != 1)
acpi_log("(%i) ACPI Read (%i) %02X: %02X\n", in_smm, size, addr, ret);
#endif
return ret;
}
static uint32_t
acpi_reg_read_via_common(int size, uint16_t addr, void *p)
{
@@ -835,93 +747,6 @@ acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *p)
}
}
static void
acpi_reg_write_sis(int size, uint16_t addr, uint8_t val, void *p)
{
acpi_t *dev = (acpi_t *) p;
int shift16, shift32;
addr &= 0x2f;
shift16 = (addr & 1) << 3;
shift32 = (addr & 3) << 3;
switch(addr)
{
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
dev->regs.pcntrl = ((dev->regs.pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x0000007e;
break;
case 0x12:
dev->regs.p2cntrl = val & 1;
break;
case 0x13:
dev->regs.gptimer = val;
break;
case 0x14: case 0x15:
dev->regs.gpsts &= ~((val << shift16) & 0xff9f);
break;
case 0x16: case 0x17:
dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0xef1f;
break;
case 0x18: case 0x19:
dev->regs.gpcntrl &= ~((val << shift16) & 0x07ff);
break;
case 0x1a: case 0x1b:
dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0187;
break;
case 0x1c: case 0x1d:
dev->regs.gpmux = ((dev->regs.gpmux & ~(0xff << shift16)) | (val << shift16)) & 0x3f7f;
if(dev->regs.gpmux & 0x0400)
dev->regs.pmsts |= 0x0020;
break;
case 0x1e: case 0x1f:
dev->regs.gplvl = ((dev->regs.gplvl & ~(0xff << shift16)) | (val << shift16)) & 0x0fb7;
break;
case 0x20:
dev->regs.smicmd = val;
break;
case 0x24:
dev->regs.muxcntrl = val & 0xc3;
break;
case 0x25:
dev->regs.auxsts &= val & 0x1f;
break;
case 0x26:
dev->regs.auxen = val & 0x3f;
break;
case 0x2a:
dev->regs.smireg = val;
break;
case 0x2b:
dev->regs.acpitst = val;
break;
default:
acpi_reg_write_common_regs(size, addr, val, p);
break;
}
#ifdef ENABLE_ACPI_LOG
if (size != 1)
acpi_log("(%i) ACPI Write (%i) %02X: %02X\n", in_smm, size, addr, val);
#endif
}
static void
acpi_reg_write_via_common(int size, uint16_t addr, uint8_t val, void *p)
@@ -1190,8 +1015,6 @@ acpi_reg_read_common(int size, uint16_t addr, void *p)
ret = acpi_reg_read_via_596b(size, addr, p);
else if (dev->vendor == VEN_INTEL)
ret = acpi_reg_read_intel(size, addr, p);
else if (dev->vendor == VEN_SIS)
ret = acpi_reg_read_sis(size, addr, p);
else if (dev->vendor == VEN_SMC)
ret = acpi_reg_read_smc(size, addr, p);
@@ -1212,8 +1035,6 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
acpi_reg_write_via_596b(size, addr, val, p);
else if (dev->vendor == VEN_INTEL)
acpi_reg_write_intel(size, addr, val, p);
else if (dev->vendor == VEN_SIS)
acpi_reg_write_sis(size, addr, val, p);
else if (dev->vendor == VEN_SMC)
acpi_reg_write_smc(size, addr, val, p);
}
@@ -1401,9 +1222,6 @@ acpi_update_io_mapping(acpi_t *dev, uint32_t base, int chipset_en)
default:
size = 0x040;
break;
case VEN_SIS:
size = 0x030;
break;
case VEN_SMC:
size = 0x010;
break;
@@ -1784,11 +1602,6 @@ acpi_init(const device_t *info)
dev->suspend_types[3] = SUS_SUSPEND | SUS_RESET_CACHE;
dev->suspend_types[4] = SUS_SUSPEND;
break;
case VEN_SIS:
dev->suspend_types[0] = SUS_SUSPEND;
dev->suspend_types[4] = SUS_POWER_OFF;
break;
}
timer_add(&dev->timer, acpi_timer_count, dev, 0);
@@ -1806,8 +1619,8 @@ const device_t acpi_ali_device =
"acpi_ali",
DEVICE_PCI,
VEN_ALI,
acpi_init,
acpi_close,
acpi_init,
acpi_close,
acpi_reset,
{ NULL },
acpi_speed_changed,
@@ -1821,23 +1634,8 @@ const device_t acpi_intel_device =
"acpi_intel",
DEVICE_PCI,
VEN_INTEL,
acpi_init,
acpi_close,
acpi_reset,
{ NULL },
acpi_speed_changed,
NULL,
NULL
};
const device_t acpi_sis_device =
{
"SiS ACPI",
"acpi_sis",
DEVICE_PCI,
VEN_SIS,
acpi_init,
acpi_close,
acpi_init,
acpi_close,
acpi_reset,
{ NULL },
acpi_speed_changed,
@@ -1851,8 +1649,8 @@ const device_t acpi_via_device =
"acpi_via",
DEVICE_PCI,
VEN_VIA,
acpi_init,
acpi_close,
acpi_init,
acpi_close,
acpi_reset,
{ NULL },
acpi_speed_changed,
@@ -1867,8 +1665,8 @@ const device_t acpi_via_596b_device =
"acpi_via_596b",
DEVICE_PCI,
VEN_VIA_596B,
acpi_init,
acpi_close,
acpi_init,
acpi_close,
acpi_reset,
{ NULL },
acpi_speed_changed,
@@ -1883,8 +1681,8 @@ const device_t acpi_smc_device =
"acpi_smc",
DEVICE_PCI,
VEN_SMC,
acpi_init,
acpi_close,
acpi_init,
acpi_close,
acpi_reset,
{ NULL },
acpi_speed_changed,

6
src/apm.c
View File

@@ -130,7 +130,7 @@ const device_t apm_device =
0,
0,
apm_init,
apm_close,
apm_close,
NULL,
{ NULL },
NULL,
@@ -146,7 +146,7 @@ const device_t apm_pci_device =
DEVICE_PCI,
0,
apm_init,
apm_close,
apm_close,
apm_reset,
{ NULL },
NULL,
@@ -162,7 +162,7 @@ const device_t apm_pci_acpi_device =
DEVICE_PCI,
1,
apm_init,
apm_close,
apm_close,
apm_reset,
{ NULL },
NULL,

2
src/cdrom/CMakeLists.txt
View File

@@ -13,4 +13,4 @@
# Copyright 2020,2021 David Hrdlička.
#
add_library(cdrom OBJECT cdrom.c cdrom_image_backend.c cdrom_image.c)
add_library(cdrom OBJECT cdrom.c cdrom_image_backend.c cdrom_image.c)

1122
src/cdrom/cdrom.c
View File

File diff suppressed because it is too large Load Diff

84
src/cdrom/cdrom_image.c
View File

@@ -8,8 +8,6 @@
*
* CD-ROM image support.
*
*
*
* Author: RichardG867,
* Miran Grca, <mgrca8@gmail.com>
* bit,
@@ -61,7 +59,7 @@ cdrom_image_log(const char *fmt, ...)
/* The addresses sent from the guest are absolute, ie. a LBA of 0 corresponds to a MSF of 00:00:00. Otherwise, the counter displayed by the guest is wrong:
there is a seeming 2 seconds in which audio plays but counter does not move, while a data track before audio jumps to 2 seconds before the actual start
of the audio while audio still plays. With an absolute conversion, the counter is fine. */
#define MSFtoLBA(m,s,f) ((((m * 60) + s) * 75) + f)
#define MSFtoLBA(m,s,f) ((((m * 60) + s) * 75) + f)
static void
@@ -95,7 +93,7 @@ image_get_subchannel(cdrom_t *dev, uint32_t lba, subchannel_t *subc)
TMSF rel_pos, abs_pos;
cdi_get_audio_sub(img, lba, &subc->attr, &subc->track, &subc->index,
&rel_pos, &abs_pos);
&rel_pos, &abs_pos);
subc->abs_m = abs_pos.min;
subc->abs_s = abs_pos.sec;
@@ -117,14 +115,14 @@ image_get_capacity(cdrom_t *dev)
uint32_t address = 0, lb = 0;
if (!img)
return 0;
return 0;
cdi_get_audio_tracks_lba(img, &first_track, &last_track, &lb);
for (c = 0; c <= last_track; c++) {
cdi_get_audio_track_info_lba(img, 0, c + 1, &number, &address, &attr);
if (address > lb)
lb = address;
cdi_get_audio_track_info_lba(img, 0, c + 1, &number, &address, &attr);
if (address > lb)
lb = address;
}
return lb;
@@ -141,22 +139,22 @@ image_is_track_audio(cdrom_t *dev, uint32_t pos, int ismsf)
int number, track;
if (!img || (dev->cd_status == CD_STATUS_DATA_ONLY))
return 0;
return 0;
if (ismsf) {
m = (pos >> 16) & 0xff;
s = (pos >> 8) & 0xff;
f = pos & 0xff;
pos = MSFtoLBA(m, s, f) - 150;
m = (pos >> 16) & 0xff;
s = (pos >> 8) & 0xff;
f = pos & 0xff;
pos = MSFtoLBA(m, s, f) - 150;
}
/* GetTrack requires LBA. */
track = cdi_get_track(img, pos);
if (track == -1)
return 0;
return 0;
else {
cdi_get_audio_track_info(img, 0, track, &number, &tmsf, &attr);
return attr == AUDIO_TRACK;
cdi_get_audio_track_info(img, 0, track, &number, &tmsf, &attr);
return attr == AUDIO_TRACK;
}
}
@@ -171,13 +169,13 @@ image_is_track_pre(cdrom_t *dev, uint32_t lba)
track = cdi_get_track(img, lba);
if (track != -1)
return cdi_get_audio_track_pre(img, track);
return cdi_get_audio_track_pre(img, track);
return 0;
}
static int
static int
image_sector_size(struct cdrom *dev, uint32_t lba)
{
cd_img_t *img = (cd_img_t *)dev->image;
@@ -192,18 +190,18 @@ image_read_sector(struct cdrom *dev, int type, uint8_t *b, uint32_t lba)
cd_img_t *img = (cd_img_t *)dev->image;
switch (type) {
case CD_READ_DATA:
return cdi_read_sector(img, b, 0, lba);
case CD_READ_AUDIO:
return cdi_read_sector(img, b, 1, lba);
case CD_READ_RAW:
if (cdi_get_sector_size(img, lba) == 2352)
return cdi_read_sector(img, b, 1, lba);
else
return cdi_read_sector_sub(img, b, lba);
default:
cdrom_image_log("CD-ROM %i: Unknown CD read type\n", dev->id);
return 0;
case CD_READ_DATA:
return cdi_read_sector(img, b, 0, lba);
case CD_READ_AUDIO:
return cdi_read_sector(img, b, 1, lba);
case CD_READ_RAW:
if (cdi_get_sector_size(img, lba) == 2352)
return cdi_read_sector(img, b, 1, lba);
else
return cdi_read_sector_sub(img, b, lba);
default:
cdrom_image_log("CD-ROM %i: Unknown CD read type\n", dev->id);
return 0;
}
}
@@ -214,11 +212,11 @@ image_track_type(cdrom_t *dev, uint32_t lba)
cd_img_t *img = (cd_img_t *)dev->image;
if (img) {
if (image_is_track_audio(dev, lba, 0))
return CD_TRACK_AUDIO;
else {
if (cdi_is_mode2(img, lba))
return CD_TRACK_MODE2 | cdi_get_mode2_form(img, lba);
if (image_is_track_audio(dev, lba, 0))
return CD_TRACK_AUDIO;
else {
if (cdi_is_mode2(img, lba))
return CD_TRACK_MODE2 | cdi_get_mode2_form(img, lba);
}
}
@@ -231,12 +229,12 @@ image_exit(cdrom_t *dev)
{
cd_img_t *img = (cd_img_t *)dev->image;
cdrom_image_log("CDROM: image_exit(%s)\n", dev->image_path);
cdrom_image_log("CDROM: image_exit(%s)\n", dev->image_path);
dev->cd_status = CD_STATUS_EMPTY;
if (img) {
cdi_close(img);
dev->image = NULL;
cdi_close(img);
dev->image = NULL;
}
dev->ops = NULL;
@@ -273,22 +271,22 @@ cdrom_image_open(cdrom_t *dev, const char *fn)
/* Make sure to not STRCPY if the two are pointing
at the same place. */
if (fn != dev->image_path)
strcpy(dev->image_path, fn);
strcpy(dev->image_path, fn);
/* Create new instance of the CDROM_Image class. */
img = (cd_img_t *) malloc(sizeof(cd_img_t));
/* This guarantees that if ops is not NULL, then
neither is the image pointer. */
if (!img)
return image_open_abort(dev);
if (!img)
return image_open_abort(dev);
memset(img, 0, sizeof(cd_img_t));
dev->image = img;
/* Open the image. */
if (!cdi_set_device(img, fn))
return image_open_abort(dev);
return image_open_abort(dev);
/* All good, reset state. */
if (! strcasecmp(plat_get_extension((char *) fn), "ISO"))
@@ -313,5 +311,5 @@ cdrom_image_close(cdrom_t *dev)
cdrom_image_log("CDROM: image_close(%s)\n", dev->image_path);
if (dev && dev->ops && dev->ops->exit)
dev->ops->exit(dev);
dev->ops->exit(dev);
}

689
src/cdrom/cdrom_image_backend.c
View File

File diff suppressed because it is too large Load Diff

2
src/chipset/CMakeLists.txt
View File

@@ -23,4 +23,4 @@ add_library(chipset OBJECT 82c100.c acc2168.c cs8230.c ali1429.c ali1489.c ali15
if(OLIVETTI)
target_sources(chipset PRIVATE olivetti_eva.c)
endif()
endif()

2
src/chipset/ali1543.c
View File

@@ -1355,6 +1355,8 @@ ali7101_read(int func, int addr, void *priv)
/* TODO: C4, C5 = GPIREG (masks: 0D, 0E) */
if (addr == 0x43)
ret = acpi_ali_soft_smi_status_read(dev->acpi) ? 0x10 : 0x00;
else if (addr == 0x7f)
ret = 0x80;
else if (addr == 0xbc)
ret = inb(0x70);
else

10
src/chipset/ali6117.c
View File

@@ -361,7 +361,7 @@ ali6117_init(const device_t *info)
ali6117_t *dev = (ali6117_t *) malloc(sizeof(ali6117_t));
memset(dev, 0, sizeof(ali6117_t));
dev->local = info->local;
device_add(&ide_isa_device);
@@ -382,8 +382,8 @@ const device_t ali1217_device =
"ali1217",
DEVICE_AT,
0x8,
ali6117_init,
ali6117_close,
ali6117_init,
ali6117_close,
ali6117_reset,
{ NULL },
NULL,
@@ -398,8 +398,8 @@ const device_t ali6117d_device =
"ali6117d",
DEVICE_AT,
0x2,
ali6117_init,
ali6117_close,
ali6117_init,
ali6117_close,
ali6117_reset,
{ NULL },
NULL,

2
src/chipset/cs8230.c
View File

@@ -100,7 +100,7 @@ cs8230_read(uint16_t port, void *p)
case 0x05: case 0x06: /* 82C301 registers */
case 0x09: case 0x0a: case 0x0b: case 0x0c: /* 82C302 registers */
case 0x0d: case 0x0e: case 0x0f:
case 0x0d: case 0x0e: case 0x0f:
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x28: case 0x29: case 0x2a:
ret = cs8230->regs[cs8230->idx];

14
src/chipset/gc100.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the G2 GC100/GC100A chipset.
* NOTE: As documentation is currently available only for the
* CG100 chipset, the GC100A chipset has been reverese-engineered.
* CG100 chipset, the GC100A chipset has been reverese-engineered.
* Thus, its behavior may not be fully accurate.
*
* Authors: EngiNerd, <webmaster.crrc@yahoo.it>
@@ -71,7 +71,7 @@ static uint8_t
get_fdd_switch_settings(void)
{
int i, fdd_count = 0;
for (i = 0; i < FDD_NUM; i++) {
if (fdd_get_flags(i))
fdd_count++;
@@ -80,7 +80,7 @@ get_fdd_switch_settings(void)
if (!fdd_count)
return 0x00;
else
return ((fdd_count - 1) << 6) | 0x01;
return ((fdd_count - 1) << 6) | 0x01;
}
@@ -92,7 +92,7 @@ get_videomode_switch_settings(void)
else if (video_is_cga())
return 0x20; /* 0x10 would be 40x25 */
else
return 0x00;
return 0x00;
}
@@ -124,7 +124,7 @@ gc100_write(uint16_t port, uint8_t val, void *priv)
else
cpu_dynamic_switch(cpu);
break;
/* addr 0x5
* programmable dip-switches
* bits 6-7: floppy drive number
@@ -216,7 +216,7 @@ gc100_init(const device_t *info)
dev->reg[0x5] = 0x0;
dev->reg[0x6] = 0x0;
dev->reg[0x7] = 0x0;
if (info->local) {
/* GC100A */
io_sethandler(0x0c2, 0x02, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev);
@@ -226,7 +226,7 @@ gc100_init(const device_t *info)
io_sethandler(0x022, 0x02, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev);
io_sethandler(0x025, 0x01, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev);
}
return dev;
}

66
src/chipset/intel_4x0.c
View File

@@ -718,7 +718,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
switch (dev->type) {
case INTEL_430NX: case INTEL_430HX:
case INTEL_430NX: case INTEL_430HX:
case INTEL_440FX:
case INTEL_440LX: case INTEL_440EX:
case INTEL_440BX: case INTEL_440GX:
@@ -1640,8 +1640,8 @@ const device_t i420tx_device =
"i420tx",
DEVICE_PCI,
INTEL_420TX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1656,8 +1656,8 @@ const device_t i420zx_device =
"i420zx",
DEVICE_PCI,
INTEL_420ZX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1672,8 +1672,8 @@ const device_t i430lx_device =
"i430lx",
DEVICE_PCI,
INTEL_430LX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1688,8 +1688,8 @@ const device_t i430nx_device =
"i430nx",
DEVICE_PCI,
INTEL_430NX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1704,8 +1704,8 @@ const device_t i430fx_device =
"i430fx",
DEVICE_PCI,
INTEL_430FX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1720,8 +1720,8 @@ const device_t i430fx_rev02_device =
"i430fx_rev02",
DEVICE_PCI,
0x0200 | INTEL_430FX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1736,8 +1736,8 @@ const device_t i430hx_device =
"i430hx",
DEVICE_PCI,
INTEL_430HX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1752,8 +1752,8 @@ const device_t i430vx_device =
"i430vx",
DEVICE_PCI,
INTEL_430VX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1768,8 +1768,8 @@ const device_t i430tx_device =
"i430tx",
DEVICE_PCI,
INTEL_430TX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1784,8 +1784,8 @@ const device_t i440fx_device =
"i440fx",
DEVICE_PCI,
INTEL_440FX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1799,8 +1799,8 @@ const device_t i440lx_device =
"i440lx",
DEVICE_PCI,
INTEL_440LX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1814,8 +1814,8 @@ const device_t i440ex_device =
"i440ex",
DEVICE_PCI,
INTEL_440EX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1829,8 +1829,8 @@ const device_t i440bx_device =
"i440bx",
DEVICE_PCI,
0x8000 | INTEL_440BX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1844,8 +1844,8 @@ const device_t i440bx_no_agp_device =
"i440bx_no_agp",
DEVICE_PCI,
0x8200 | INTEL_440BX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1859,8 +1859,8 @@ const device_t i440gx_device =
"i440gx",
DEVICE_PCI,
0x8000 | INTEL_440GX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,
@@ -1874,8 +1874,8 @@ const device_t i440zx_device =
"i440zx",
DEVICE_PCI,
0x8000 | INTEL_440ZX,
i4x0_init,
i4x0_close,
i4x0_init,
i4x0_close,
i4x0_reset,
{ NULL },
NULL,

2
src/chipset/intel_i450kx.c
View File

@@ -98,7 +98,7 @@ i450kx_smram_recalc(i450kx_t *dev, int bus)
addr = ((uint32_t) regs[0xb8] << 16) | ((uint32_t) regs[0xb9] << 24);
size = (((uint32_t) ((regs[0xbb] >> 4) & 0x0f)) << 16) + 0x00010000;
if ((addr != 0x00000000) && !!(regs[0x57] & 0x08)) {
if (bus)
smram_enable_ex(dev->smram[bus], addr, addr, size, 0, !!(regs[0x57] & 8), 0, 1);

32
src/chipset/intel_piix.c
View File

@@ -1281,7 +1281,7 @@ piix_reset_hard(piix_t *dev)
/* Function 3: Power Management */
if (dev->type > 3) {
fregs = (uint8_t *) dev->regs[3];
fregs = (uint8_t *) dev->regs[3];
piix_log("PIIX Function 3: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]);
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
if (dev->type > 4)
@@ -1606,8 +1606,8 @@ const device_t piix_device =
"piix",
DEVICE_PCI,
0x122e0101,
piix_init,
piix_close,
piix_init,
piix_close,
piix_reset,
{ NULL },
piix_speed_changed,
@@ -1621,8 +1621,8 @@ const device_t piix_rev02_device =
"piix_rev02",
DEVICE_PCI,
0x122e0121,
piix_init,
piix_close,
piix_init,
piix_close,
piix_reset,
{ NULL },
piix_speed_changed,
@@ -1636,8 +1636,8 @@ const device_t piix3_device =
"piix3",
DEVICE_PCI,
0x70000403,
piix_init,
piix_close,
piix_init,
piix_close,
piix_reset,
{ NULL },
piix_speed_changed,
@@ -1648,11 +1648,11 @@ const device_t piix3_device =
const device_t piix3_ioapic_device =
{
"Intel 82371SB (PIIX3) (Boards with I/O APIC)",
"piix3",
"piix3_ioapic",
DEVICE_PCI,
0x70001403,
piix_init,
piix_close,
piix_init,
piix_close,
piix_reset,
{ NULL },
piix_speed_changed,
@@ -1666,8 +1666,8 @@ const device_t piix4_device =
"piix4",
DEVICE_PCI,
0x71100004,
piix_init,
piix_close,
piix_init,
piix_close,
piix_reset,
{ NULL },
piix_speed_changed,
@@ -1681,8 +1681,8 @@ const device_t piix4e_device =
"piix4e",
DEVICE_PCI,
0x71100094,
piix_init,
piix_close,
piix_init,
piix_close,
piix_reset,
{ NULL },
piix_speed_changed,
@@ -1696,8 +1696,8 @@ const device_t slc90e66_device =
"slc90e66",
DEVICE_PCI,
0x94600005,
piix_init,
piix_close,
piix_init,
piix_close,
piix_reset,
{ NULL },
piix_speed_changed,

24
src/chipset/neat.c
View File

@@ -480,7 +480,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
#endif
break;
case REG_RB0:
case REG_RB0:
val &= RB0_MASK;
*reg = (*reg & ~RB0_MASK) | val | \
(RB0_REV_ID << RB0_REV_SH);
@@ -489,7 +489,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
#endif
break;
case REG_RB1:
case REG_RB1:
val &= RB1_MASK;
*reg = (*reg & ~RB1_MASK) | val;
#if NEAT_DEBUG > 1
@@ -497,7 +497,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
#endif
break;
case REG_RB2:
case REG_RB2:
val &= RB2_MASK;
*reg = (*reg & ~RB2_MASK) | val;
#if NEAT_DEBUG > 1
@@ -505,7 +505,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
#endif
break;
case REG_RB3:
case REG_RB3:
val &= RB3_MASK;
*reg = (*reg & ~RB3_MASK) | val;
#if NEAT_DEBUG > 1
@@ -513,7 +513,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
#endif
break;
case REG_RB4:
case REG_RB4:
val &= RB4_MASK;
*reg = (*reg & ~RB4_MASK) | val;
#if NEAT_DEBUG > 1
@@ -521,7 +521,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
#endif
break;
case REG_RB5:
case REG_RB5:
val &= RB5_MASK;
*reg = (*reg & ~RB5_MASK) | val;
#if NEAT_DEBUG > 1
@@ -529,7 +529,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
#endif
break;
case REG_RB6:
case REG_RB6:
val &= RB6_MASK;
*reg = (*reg & ~RB6_MASK) | val;
#if NEAT_DEBUG > 1
@@ -537,7 +537,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
#endif
break;
case REG_RB7:
case REG_RB7:
val &= RB7_MASK;
*reg = val;
#if NEAT_DEBUG > 1
@@ -556,7 +556,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
}
break;
case REG_RB8:
case REG_RB8:
val &= RB8_MASK;
*reg = (*reg & ~RB8_MASK) | val;
#if NEAT_DEBUG > 1
@@ -564,7 +564,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
#endif
break;
case REG_RB9:
case REG_RB9:
val &= RB9_MASK;
*reg = (*reg & ~RB9_MASK) | val;
#if NEAT_DEBUG > 1
@@ -576,7 +576,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
}
break;
case REG_RB10:
case REG_RB10:
val &= RB10_MASK;
*reg = (*reg & ~RB10_MASK) | val;
#if NEAT_DEBUG > 1
@@ -591,7 +591,7 @@ neat_write(uint16_t port, uint8_t val, void *priv)
ems_recalc(dev, &dev->ems[i]);
break;
case REG_RB11:
case REG_RB11:
val &= RB11_MASK;
*reg = (*reg & ~RB11_MASK) | val;
#if NEAT_DEBUG > 1

20
src/chipset/olivetti_eva.c
View File

@@ -73,12 +73,12 @@ olivetti_eva_write(uint16_t addr, uint8_t val, void *priv)
case 0x069:
dev->reg_069 = val;
/*
* Unfortunately, if triggered, the BIOS remapping function fails causing
* Unfortunately, if triggered, the BIOS remapping function fails causing
* a fatal error. Therefore, this code section is currently commented.
*/
// if (val & 1){
// /*
// * Set the register to 7 or above for the BIOS to trigger the
// /*
// * Set the register to 7 or above for the BIOS to trigger the
// * memory remapping function if shadowing is active.
// */
// dev->reg_069 = 0x7;
@@ -129,24 +129,24 @@ olivetti_eva_init(const device_t *info)
{
olivetti_eva_t *dev = (olivetti_eva_t *) malloc(sizeof(olivetti_eva_t));
memset(dev, 0, sizeof(olivetti_eva_t));
/* GA98 registers */
dev->reg_065 = 0x00;
/* RAM page registers: never read, only set */
dev->reg_067 = 0x00;
/* RAM enable registers */
dev->reg_069 = 0x0;
io_sethandler(0x0065, 0x0001, olivetti_eva_read, NULL, NULL, olivetti_eva_write, NULL, NULL, dev);
io_sethandler(0x0067, 0x0001, olivetti_eva_read, NULL, NULL, olivetti_eva_write, NULL, NULL, dev);
io_sethandler(0x0069, 0x0001, olivetti_eva_read, NULL, NULL, olivetti_eva_write, NULL, NULL, dev);
/* When shadowing is not enabled in BIOS, all upper memory is available as XMS */
mem_remap_top(384);
/*
/*
* Default settings when NVRAM is cleared activate shadowing.
* Thus, to avoid boot errors, remap only 256k from UMB to XMS.
* Remove this block once BIOS memory remapping works.

2
src/chipset/opti291.c
View File

@@ -7,7 +7,7 @@
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C291 chipset.
* Authors: plant/nerd73, Tiseno100
*
* Copyright 2020 plant/nerd73.

2
src/chipset/opti5x7.c
View File

@@ -7,7 +7,7 @@
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C546/82C547(Python) & 82C596/82C597(Cobra) chipsets.
* Authors: plant/nerd73,
* Miran Grca, <mgrca8@gmail.com>
* Tiseno100

44
src/chipset/scamp.c
View File

@@ -153,7 +153,7 @@ static const struct
/* The column bits masked when using 256kbit DRAMs in 4Mbit mode aren't contiguous,
so we use separate routines for that special case */
static uint8_t
static uint8_t
ram_mirrored_256k_in_4mi_read(uint32_t addr, void *priv)
{
ram_struct_t *rs = (ram_struct_t *) priv;
@@ -183,7 +183,7 @@ ram_mirrored_256k_in_4mi_read(uint32_t addr, void *priv)
}
static void
static void
ram_mirrored_256k_in_4mi_write(uint32_t addr, uint8_t val, void *priv)
{
ram_struct_t *rs = (ram_struct_t *) priv;
@@ -215,7 +215,7 @@ ram_mirrored_256k_in_4mi_write(uint32_t addr, uint8_t val, void *priv)
/*Read/write handlers for interleaved memory banks. We must keep CPU and ram array
mapping linear, otherwise we won't be able to execute code from interleaved banks*/
static uint8_t
static uint8_t
ram_mirrored_interleaved_read(uint32_t addr, void *priv)
{
ram_struct_t *rs = (ram_struct_t *) priv;
@@ -245,7 +245,7 @@ ram_mirrored_interleaved_read(uint32_t addr, void *priv)
}
static void
static void
ram_mirrored_interleaved_write(uint32_t addr, uint8_t val, void *priv)
{
ram_struct_t *rs = (ram_struct_t *) priv;
@@ -275,7 +275,7 @@ ram_mirrored_interleaved_write(uint32_t addr, uint8_t val, void *priv)
}
static uint8_t
static uint8_t
ram_mirrored_read(uint32_t addr, void *priv)
{
ram_struct_t *rs = (ram_struct_t *) priv;
@@ -293,14 +293,14 @@ ram_mirrored_read(uint32_t addr, void *priv)
}
static void
static void
ram_mirrored_write(uint32_t addr, uint8_t val, void *priv)
{
ram_struct_t *rs = (ram_struct_t *) priv;
scamp_t *dev = rs->parent;
int bank = rs->bank, byte;
int row, column;
addr -= dev->ram_virt_base[bank];
byte = addr & 1;
column = (addr >> 1) & dev->ram_mask[bank];
@@ -311,7 +311,7 @@ ram_mirrored_write(uint32_t addr, uint8_t val, void *priv)
}
static void
static void
recalc_mappings(void *priv)
{
scamp_t *dev = (scamp_t *) priv;
@@ -346,7 +346,7 @@ recalc_mappings(void *priv)
if (rammap[cur_rammap].bank[0] == BANK_NONE)
bank_nr = 1;
for (; bank_nr < 2; bank_nr++) {
old_virt_base = virt_base;
phys_bank = ram_configs[dev->ram_config].bank[bank_nr];
@@ -511,7 +511,7 @@ recalc_mappings(void *priv)
ram_mirrored_interleaved_read, NULL, NULL,
ram_mirrored_interleaved_write, NULL, NULL);
break;
case BANK_4M_INTERLEAVED:
if (phys_bank == BANK_256K || phys_bank == BANK_256K_INTERLEAVED) {
mem_mapping_set_handler(&dev->ram_mapping[bank_nr],
@@ -577,14 +577,14 @@ scamp_ems_write(uint32_t addr, uint8_t val, void *priv)
ems_struct_t *ems = (ems_struct_t *) priv;
scamp_t *dev = ems->parent;
int segment = ems->segment;
addr = (addr & 0x3fff) | dev->mappings[segment];
ram[addr] = val;
}
static void
recalc_ems(scamp_t *dev)
{
{
int segment;
const uint32_t ems_base[12] =
{
@@ -633,7 +633,7 @@ recalc_ems(scamp_t *dev)
}
}
static void
static void
shadow_control(uint32_t addr, uint32_t size, int state, int ems_enable)
{
if (ems_enable)
@@ -706,7 +706,7 @@ shadow_recalc(scamp_t *dev)
shadow_control(0xf8000, 0x8000, (feaxs >> 6) & 3, 0);
}
static void
static void
scamp_write(uint16_t addr, uint8_t val, void *priv)
{
scamp_t *dev = (scamp_t *) priv;
@@ -729,9 +729,9 @@ scamp_write(uint16_t addr, uint8_t val, void *priv)
recalc_ems(dev);
}
if (dev->ems_autoinc)
dev->ems_index = (dev->ems_index + 1) & 0x1f;
dev->ems_index = (dev->ems_index + 1) & 0x3f;
break;
case 0xec:
if (dev->cfg_enable)
dev->cfg_index = val;
@@ -778,7 +778,7 @@ scamp_write(uint16_t addr, uint8_t val, void *priv)
}
static uint8_t
static uint8_t
scamp_read(uint16_t addr, void *priv)
{
scamp_t *dev = (scamp_t *) priv;
@@ -795,10 +795,10 @@ scamp_read(uint16_t addr, void *priv)
break;
case 0xeb:
if (dev->ems_index < 0x24)
ret = dev->ems[dev->ems_index] = (dev->ems[dev->ems_index] >> 8) & 0xfc;
ret = (dev->ems[dev->ems_index] >> 8) | 0xfc;
if (dev->ems_autoinc)
dev->ems_index = (dev->ems_index + 1) & 0x1f;
break;
dev->ems_index = (dev->ems_index + 1) & 0x3f;
break;
case 0xed:
if (dev->cfg_enable && (dev->cfg_index >= 0x00) && (dev->cfg_index <= 0x16))
@@ -839,7 +839,7 @@ scamp_init(const device_t *info)
int c;
scamp_t *dev = (scamp_t *)malloc(sizeof(scamp_t));
memset(dev, 0x00, sizeof(scamp_t));
dev->cfg_regs[CFG_ID] = ID_VL82C311;
dev->cfg_enable = 1;
@@ -852,7 +852,7 @@ scamp_init(const device_t *info)
io_sethandler(0x00f9, 0x0001,
scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev);
io_sethandler(0x00fb, 0x0001,
scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev);
scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev);
dev->ram_config = 0;

2
src/chipset/scat.c
View File

@@ -384,7 +384,7 @@ get_addr(scat_t *dev, uint32_t addr, ems_page_t *p)
if (mem_size <= ((dev->regs[SCAT_VERSION] & 0x0f) > 3 ? 2048 : 4096) && (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) < 8) || dev->external_is_RAS)) {
nbanks_2048k = 0;
nbanks_512k = mem_size >> 9;
} else {
} else {
nbanks_2048k = mem_size >> 11;
nbanks_512k = (mem_size & 1536) >> 9;
}

2
src/chipset/sis_85c310.c
View File

@@ -144,4 +144,4 @@ const device_t rabbit_device = {
rabbit_init, rabbit_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
};

10
src/chipset/sis_85c496.c
View File

@@ -468,7 +468,7 @@ sis_85c49x_pci_read(int func, int addr, void *priv)
return ret;
}
static void
sis_85c496_rmsmiblk_count(void *priv)
@@ -625,8 +625,8 @@ const device_t sis_85c496_device =
"sis_85c496",
DEVICE_PCI,
0,
sis_85c496_init,
sis_85c496_close,
sis_85c496_init,
sis_85c496_close,
sis_85c496_reset,
{ NULL },
NULL,
@@ -641,8 +641,8 @@ const device_t sis_85c496_ls486e_device =
"sis_85c496_ls486e",
DEVICE_PCI,
1,
sis_85c496_init,
sis_85c496_close,
sis_85c496_init,
sis_85c496_close,
sis_85c496_reset,
{ NULL },
NULL,

2
src/chipset/sis_85c50x.c
View File

@@ -304,7 +304,7 @@ sis_85c50x_isa_read(uint16_t addr, void *priv)
ret = dev->regs[dev->index];
break;
}
sis_85c50x_log("85C501-ISA: dev->regs[%02x] (%02x)\n", dev->index, ret);
return ret;

22
src/chipset/stpc.c
View File

@@ -835,7 +835,7 @@ stpc_setup(stpc_t *dev)
dev->pci_conf[3][0x01] = dev->local >> 24;
dev->pci_conf[3][0x02] = 0x30;
dev->pci_conf[3][0x03] = 0x02;
dev->pci_conf[3][0x06] = 0x80;
dev->pci_conf[3][0x07] = 0x02;
@@ -877,7 +877,7 @@ stpc_init(const device_t *info)
stpc_t *dev = (stpc_t *) malloc(sizeof(stpc_t));
memset(dev, 0, sizeof(stpc_t));
dev->local = info->local;
pci_add_card(PCI_ADD_NORTHBRIDGE, stpc_nb_read, stpc_nb_write, dev);
@@ -1002,7 +1002,7 @@ stpc_lpt_write(uint16_t addr, uint8_t val, void *priv)
} else if (addr == 0x3f0) {
if (val == 0xaa)
dev->unlocked = 0;
else
else
dev->offset = val;
} else if (dev->offset == 1) {
/* dev->reg1 is set by stpc_lpt_handlers */
@@ -1063,8 +1063,8 @@ const device_t stpc_client_device =
"stpc_client",
DEVICE_PCI,
STPC_CLIENT,
stpc_init,
stpc_close,
stpc_init,
stpc_close,
stpc_reset,
{ NULL },
NULL,
@@ -1078,8 +1078,8 @@ const device_t stpc_consumer2_device =
"stpc_consumer2",
DEVICE_PCI,
STPC_CONSUMER2,
stpc_init,
stpc_close,
stpc_init,
stpc_close,
stpc_reset,
{ NULL },
NULL,
@@ -1093,8 +1093,8 @@ const device_t stpc_elite_device =
"stpc_elite",
DEVICE_PCI,
STPC_ELITE,
stpc_init,
stpc_close,
stpc_init,
stpc_close,
stpc_reset,
{ NULL },
NULL,
@@ -1108,8 +1108,8 @@ const device_t stpc_atlas_device =
"stpc_atlas",
DEVICE_PCI,
STPC_ATLAS,
stpc_init,
stpc_close,
stpc_init,
stpc_close,
stpc_reset,
{ NULL },
NULL,

2
src/chipset/umc_8886.c
View File

@@ -18,7 +18,7 @@
* Copyright 2021 Miran Grca.
*/
/*
/*
UMC 8886xx Configuration Registers
Note: PMU functionality is quite basic. There may be Enable/Disable bits, IRQ/SMI picks and it also

4
src/chipset/umc_hb4.c
View File

@@ -10,7 +10,7 @@
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
* Note 2: Additional information were also used from all
* around the web.
*
@@ -81,7 +81,7 @@
Register 56h & 57h: DRAM Bank 0 Configuration
Register 58h & 59h: DRAM Bank 1 Configuration
Register 60:
Bit 5: If set and SMRAM is enabled, data cycles go to PCI and code cycles go to DRAM
Bit 0: SMRAM Local Access Enable - if set, SMRAM is also enabled outside SMM

20
src/chipset/via_apollo.c
View File

@@ -232,7 +232,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
via_apollo_t *dev = (via_apollo_t *) priv;
if (func)
return;
/*Read-only addresses*/
if ((addr < 4) || ((addr > 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) ||
((addr >= 0xe) && (addr != 0x0f) && (addr < 0x12)) || ((addr >= 0x14) && (addr < 0x50)) ||
@@ -259,7 +259,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
else
dev->pci_conf[0x05] = val;
break;
case 0x07:
dev->pci_conf[0x07] &= ~(val & 0xb0);
break;
@@ -766,8 +766,8 @@ const device_t via_vpx_device =
"via_vpx",
DEVICE_PCI,
VIA_585, /*VT82C585*/
via_apollo_init,
via_apollo_close,
via_apollo_init,
via_apollo_close,
via_apollo_reset,
{ NULL },
NULL,
@@ -781,8 +781,8 @@ const device_t amd640_device =
"amd640",
DEVICE_PCI,
VIA_595, /*VT82C595*/
via_apollo_init,
via_apollo_close,
via_apollo_init,
via_apollo_close,
via_apollo_reset,
{ NULL },
NULL,
@@ -796,8 +796,8 @@ const device_t via_vp3_device =
"via_vp3",
DEVICE_PCI,
VIA_597, /*VT82C597*/
via_apollo_init,
via_apollo_close,
via_apollo_init,
via_apollo_close,
via_apollo_reset,
{ NULL },
NULL,
@@ -811,8 +811,8 @@ const device_t via_mvp3_device =
"via_mvp3",
DEVICE_PCI,
VIA_598, /*VT82C598MVP*/
via_apollo_init,
via_apollo_close,
via_apollo_init,
via_apollo_close,
via_apollo_reset,
{ NULL },
NULL,

4
src/chipset/via_pipc.c
View File

@@ -980,7 +980,7 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
if ((dev->local <= VIA_PIPC_586B) && (addr >= 0x74))
return;
if ((dev->local <= VIA_PIPC_596A) && ((addr == 0x51) || (addr == 0x52) || (addr == 0x5f) || (addr == 0x85) ||
if ((dev->local <= VIA_PIPC_596A) && ((addr == 0x51) || (addr == 0x52) || (addr == 0x5f) || (addr == 0x85) ||
(addr == 0x86) || ((addr >= 0x8a) && (addr < 0x90))))
return;
@@ -1577,7 +1577,7 @@ pipc_init(const device_t *info)
dev->ac97 = device_add(&ac97_via_device);
ac97_via_set_slot(dev->ac97, dev->slot, PCI_INTC);
dev->sb = device_add(&sb_pro_compat_device);
dev->sb = device_add_inst(&sb_pro_compat_device, 2);
#ifndef VIA_PIPC_FM_EMULATION
dev->sb->opl_enabled = 1;
#endif

2
src/chipset/via_vt82c49x.c
View File

@@ -354,7 +354,7 @@ vt82c49x_init(const device_t *info)
pic_elcr_set_enabled(1);
vt82c49x_recalc(dev);
return dev;
}

4
src/chipset/vl82c480.c
View File

@@ -58,7 +58,7 @@ vl82c480_shflags(uint8_t access)
}
static void
static void
vl82c480_recalc(vl82c480_t *dev)
{
int i, j;
@@ -127,7 +127,7 @@ vl82c480_write(uint16_t addr, uint8_t val, void *p)
}
static uint8_t
static uint8_t
vl82c480_read(uint16_t addr, void *p)
{
vl82c480_t *dev = (vl82c480_t *)p;

2
src/codegen/CMakeLists.txt
View File

@@ -28,4 +28,4 @@ if(DYNAREC)
endif()
target_link_libraries(86Box dynarec cgt)
endif()
endif()

30
src/codegen/codegen.h
View File

@@ -56,18 +56,18 @@
added to the page_lookup for this purpose. When in the page_lookup, each write
will go through the mem_write_ram*_page() functions and set the dirty mask
appropriately.
Each codeblock also contains a code mask (actually two masks, one for each
page the block is/may be in), again with each bit representing 64 bytes.
Each page has a list of codeblocks present in it. As each codeblock can span
up to two pages, two lists are present.
When a codeblock is about to be executed, the code masks are compared with the
dirty masks for the relevant pages. If either intersect, then
codegen_check_flush() is called on the affected page(s), and all affected
blocks are evicted.
The 64 byte granularity appears to work reasonably well for most cases,
avoiding most unnecessary evictions (eg when code & data are stored in the
same page).
@@ -78,17 +78,17 @@ typedef struct codeblock_t
uint64_t page_mask, page_mask2;
uint64_t *dirty_mask, *dirty_mask2;
uint64_t cmp;
/*Previous and next pointers, for the codeblock list associated with
each physical page. Two sets of pointers, as a codeblock can be
present in two pages.*/
struct codeblock_t *prev, *next;
struct codeblock_t *prev_2, *next_2;
/*Pointers for codeblock tree, used to search for blocks when hash lookup
fails.*/
struct codeblock_t *parent, *left, *right;
int pnt;
int ins;
@@ -116,7 +116,7 @@ static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
{
codeblock_t *block = pages[phys >> 12].head;
uint64_t a = _cs | ((uint64_t)phys << 32);
while (block)
{
if (a == block->cmp)
@@ -130,7 +130,7 @@ static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
else
block = block->right;
}
return block;
}
@@ -139,7 +139,7 @@ static inline void codeblock_tree_add(codeblock_t *new_block)
codeblock_t *block = pages[new_block->phys >> 12].head;
uint64_t a = new_block->_cs | ((uint64_t)new_block->phys << 32);
new_block->cmp = a;
if (!block)
{
pages[new_block->phys >> 12].head = new_block;
@@ -148,7 +148,7 @@ static inline void codeblock_tree_add(codeblock_t *new_block)
else
{
codeblock_t *old_block = NULL;
while (block)
{
old_block = block;
@@ -157,12 +157,12 @@ static inline void codeblock_tree_add(codeblock_t *new_block)
else
block = block->right;
}
if (a < old_block->cmp)
old_block->left = new_block;
else
old_block->right = new_block;
new_block->parent = old_block;
new_block->left = new_block->right = NULL;
}
@@ -237,7 +237,7 @@ static inline void codeblock_tree_delete(codeblock_t *block)
/*Difficult case - node has two children. Walk right child to find lowest node*/
codeblock_t *lowest = block->right, *highest;
codeblock_t *old_parent;
while (lowest->left)
lowest = lowest->left;
@@ -260,7 +260,7 @@ static inline void codeblock_tree_delete(codeblock_t *block)
lowest->left->parent = lowest;
old_parent->left = NULL;
highest = lowest->right;
if (!highest)
{

2
src/codegen/codegen_accumulate.h
View File

@@ -1,7 +1,7 @@
enum
{
ACCREG_cycles = 0,
ACCREG_COUNT
};

48
src/codegen/codegen_ops.c
View File

@@ -35,7 +35,7 @@
RecompOpFn recomp_opcodes[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropADD_b_rmw, ropADD_w_rmw, ropADD_b_rm, ropADD_w_rm, ropADD_AL_imm, ropADD_AX_imm, ropPUSH_ES_16, ropPOP_ES_16, ropOR_b_rmw, ropOR_w_rmw, ropOR_b_rm, ropOR_w_rm, ropOR_AL_imm, ropOR_AX_imm, ropPUSH_CS_16, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_SS_16, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_DS_16, ropPOP_DS_16,
/*20*/ ropAND_b_rmw, ropAND_w_rmw, ropAND_b_rm, ropAND_w_rm, ropAND_AL_imm, ropAND_AX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_w_rmw, ropSUB_b_rm, ropSUB_w_rm, ropSUB_AL_imm, ropSUB_AX_imm, NULL, NULL,
@@ -57,7 +57,7 @@ RecompOpFn recomp_opcodes[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, ropF6, ropF7_w, NULL, NULL, ropCLI, ropSTI, ropCLD, ropSTD, ropFE, ropFF_16,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropADD_b_rmw, ropADD_l_rmw, ropADD_b_rm, ropADD_l_rm, ropADD_AL_imm, ropADD_EAX_imm, ropPUSH_ES_32, ropPOP_ES_32, ropOR_b_rmw, ropOR_l_rmw, ropOR_b_rm, ropOR_l_rm, ropOR_AL_imm, ropOR_EAX_imm, ropPUSH_CS_32, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_SS_32, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropPUSH_DS_32, ropPOP_DS_32,
/*20*/ ropAND_b_rmw, ropAND_l_rmw, ropAND_b_rm, ropAND_l_rm, ropAND_AL_imm, ropAND_EAX_imm, NULL, NULL, ropSUB_b_rmw, ropSUB_l_rmw, ropSUB_b_rm, ropSUB_l_rm, ropSUB_AL_imm, ropSUB_EAX_imm, NULL, NULL,
@@ -82,7 +82,7 @@ RecompOpFn recomp_opcodes[512] =
RecompOpFn recomp_opcodes_0f[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -104,7 +104,7 @@ RecompOpFn recomp_opcodes_0f[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -130,7 +130,7 @@ RecompOpFn recomp_opcodes_0f[512] =
RecompOpFn recomp_opcodes_d8[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*10*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*20*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
@@ -152,7 +152,7 @@ RecompOpFn recomp_opcodes_d8[512] =
/*f0*/ ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIV, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR, ropFDIVR,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFADDs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs, ropFMULs,
/*10*/ ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs, ropFCOMPs,
/*20*/ ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs, ropFSUBRs,
@@ -177,7 +177,7 @@ RecompOpFn recomp_opcodes_d8[512] =
RecompOpFn recomp_opcodes_d9[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
@@ -199,7 +199,7 @@ RecompOpFn recomp_opcodes_d9[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, ropFLDs, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs, ropFSTPs,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW, ropFLDCW,
@@ -224,7 +224,7 @@ RecompOpFn recomp_opcodes_d9[512] =
RecompOpFn recomp_opcodes_da[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*10*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*20*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
@@ -246,7 +246,7 @@ RecompOpFn recomp_opcodes_da[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFADDil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil, ropFMULil,
/*10*/ ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil, ropFCOMPil,
/*20*/ ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil, ropFSUBRil,
@@ -271,7 +271,7 @@ RecompOpFn recomp_opcodes_da[512] =
RecompOpFn recomp_opcodes_db[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -293,7 +293,7 @@ RecompOpFn recomp_opcodes_db[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*80*/ ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, ropFILDl, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl, ropFISTPl,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -318,7 +318,7 @@ RecompOpFn recomp_opcodes_db[512] =
RecompOpFn recomp_opcodes_dc[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*10*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*20*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
@@ -340,7 +340,7 @@ RecompOpFn recomp_opcodes_dc[512] =
/*f0*/ ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVRr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr, ropFDIVr,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFADDd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd, ropFMULd,
/*10*/ ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd, ropFCOMPd,
/*20*/ ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd, ropFSUBRd,
@@ -365,7 +365,7 @@ RecompOpFn recomp_opcodes_dc[512] =
RecompOpFn recomp_opcodes_dd[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -387,7 +387,7 @@ RecompOpFn recomp_opcodes_dd[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, ropFLDd, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd, ropFSTPd,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -412,7 +412,7 @@ RecompOpFn recomp_opcodes_dd[512] =
RecompOpFn recomp_opcodes_de[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*10*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*20*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
@@ -434,7 +434,7 @@ RecompOpFn recomp_opcodes_de[512] =
/*f0*/ ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVRP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP, ropFDIVP,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFADDiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw, ropFMULiw,
/*10*/ ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw, ropFCOMPiw,
/*20*/ ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw, ropFSUBRiw,
@@ -459,7 +459,7 @@ RecompOpFn recomp_opcodes_de[512] =
RecompOpFn recomp_opcodes_df[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
@@ -481,7 +481,7 @@ RecompOpFn recomp_opcodes_df[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, ropFILDw, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw, ropFISTPw,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq, ropFILDq,
@@ -506,7 +506,7 @@ RecompOpFn recomp_opcodes_df[512] =
RecompOpFn recomp_opcodes_REPE[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -528,7 +528,7 @@ RecompOpFn recomp_opcodes_REPE[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -553,7 +553,7 @@ RecompOpFn recomp_opcodes_REPE[512] =
RecompOpFn recomp_opcodes_REPNE[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -575,7 +575,7 @@ RecompOpFn recomp_opcodes_REPNE[512] =
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

112
src/codegen/codegen_ops_arith.h
View File

@@ -1,11 +1,11 @@
static uint32_t ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
// ADD_HOST_REG_IMM_W(host_reg, 1);
INC_HOST_REG_W(host_reg);
@@ -13,7 +13,7 @@ static uint32_t ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc;
@@ -23,9 +23,9 @@ static uint32_t ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
int host_reg;
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
// ADD_HOST_REG_IMM(host_reg, 1);
INC_HOST_REG(host_reg);
@@ -41,11 +41,11 @@ static uint32_t ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
// SUB_HOST_REG_IMM_W(host_reg, 1);
DEC_HOST_REG_W(host_reg);
@@ -61,11 +61,11 @@ static uint32_t ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
// SUB_HOST_REG_IMM(host_reg, 1);
DEC_HOST_REG(host_reg);
@@ -474,10 +474,10 @@ static uint32_t ropADD_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
ADD_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -488,9 +488,9 @@ static uint32_t ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
ADD_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -503,9 +503,9 @@ static uint32_t ropADD_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
ADD_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 4;
}
@@ -518,23 +518,23 @@ static uint32_t ropCMP_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
host_reg = CMP_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t ropCMP_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -547,9 +547,9 @@ static uint32_t ropCMP_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = CMP_HOST_REG_IMM_L(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 4;
}
@@ -562,9 +562,9 @@ static uint32_t ropSUB_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
SUB_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
@@ -576,9 +576,9 @@ static uint32_t ropSUB_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
SUB_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -591,9 +591,9 @@ static uint32_t ropSUB_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
SUB_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
return op_pc + 4;
}
@@ -603,7 +603,7 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
@@ -629,7 +629,7 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
host_reg = LOAD_REG_B(fetchdat & 7);
imm = (fetchdat >> 8) & 0xff;
}
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -663,8 +663,8 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
break;
}
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -679,7 +679,7 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
}
else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -689,10 +689,10 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -715,7 +715,7 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
host_reg = LOAD_REG_W(fetchdat & 7);
imm = (fetchdat >> 8) & 0xffff;
}
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -749,8 +749,8 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -765,7 +765,7 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 3;
}
@@ -774,10 +774,10 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -799,7 +799,7 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
host_reg = LOAD_REG_L(fetchdat & 7);
}
imm = fastreadl(cs + op_pc + 1);
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -833,8 +833,8 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -849,7 +849,7 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 5;
}
@@ -859,10 +859,10 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
int host_reg;
uint32_t imm;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -888,7 +888,7 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
if (imm & 0x80)
imm |= 0xff80;
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -922,8 +922,8 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -938,7 +938,7 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
else
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
return op_pc + 2;
}
@@ -950,7 +950,7 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
if ((fetchdat & 0x30) == 0x10)
return 0;
if ((fetchdat & 0xc0) != 0xc0)
{
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -976,7 +976,7 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
if (imm & 0x80)
imm |= 0xffffff80;
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -1010,8 +1010,8 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)

132
src/codegen/codegen_ops_fpu.h
View File

@@ -3,7 +3,7 @@ static uint32_t ropFXCH(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
FP_ENTER();
FP_FXCH(opcode & 7);
return op_pc;
}
@@ -12,7 +12,7 @@ static uint32_t ropFLD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32
FP_ENTER();
FP_FLD(opcode & 7);
return op_pc;
}
@@ -21,7 +21,7 @@ static uint32_t ropFST(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32
FP_ENTER();
FP_FST(opcode & 7);
return op_pc;
}
static uint32_t ropFSTP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -30,7 +30,7 @@ static uint32_t ropFSTP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
FP_FST(opcode & 7);
FP_POP();
return op_pc;
}
@@ -38,13 +38,13 @@ static uint32_t ropFSTP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropFLDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -55,13 +55,13 @@ static uint32_t ropFLDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropFLDd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_Q(target_seg);
@@ -73,13 +73,13 @@ static uint32_t ropFLDd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropFILDw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
@@ -90,13 +90,13 @@ static uint32_t ropFILDw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFILDl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -107,20 +107,20 @@ static uint32_t ropFILDl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFILDq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_Q(target_seg);
FP_LOAD_IQ();
codegen_fpu_loaded_iq[(cpu_state.TOP - 1) & 7] = 1;
return op_pc + 1;
}
@@ -128,7 +128,7 @@ static uint32_t ropFSTs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
x86seg *target_seg;
int host_reg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -138,7 +138,7 @@ static uint32_t ropFSTs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
return op_pc + 1;
@@ -147,7 +147,7 @@ static uint32_t ropFSTd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
x86seg *target_seg;
int host_reg1, host_reg2 = 0;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
@@ -158,7 +158,7 @@ static uint32_t ropFSTd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 7);
MEM_STORE_ADDR_EA_Q(target_seg, host_reg1, host_reg2);
return op_pc + 1;
@@ -167,17 +167,17 @@ static uint32_t ropFSTd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropFSTPs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFSTs(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
static uint32_t ropFSTPd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFSTd(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
@@ -260,13 +260,13 @@ ropFcompare(COM, il, MEM_LOAD_ADDR_EA_L, FP_COMPARE_IL);
/*static uint32_t ropFADDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -277,13 +277,13 @@ ropFcompare(COM, il, MEM_LOAD_ADDR_EA_L, FP_COMPARE_IL);
static uint32_t ropFDIVs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -294,13 +294,13 @@ static uint32_t ropFDIVs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFMULs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -311,13 +311,13 @@ static uint32_t ropFMULs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFSUBs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
FP_ENTER();
op_pc--;
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_L(target_seg);
@@ -331,49 +331,49 @@ static uint32_t ropFADD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
FP_ENTER();
FP_OP_REG(FPU_ADD, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFCOM(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_COMPARE_REG(0, opcode & 7);
return op_pc;
}
static uint32_t ropFDIV(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIV, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFDIVR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFMUL(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_MUL, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFSUB(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUB, 0, opcode & 7);
return op_pc;
}
static uint32_t ropFSUBR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, 0, opcode & 7);
return op_pc;
}
@@ -381,42 +381,42 @@ static uint32_t ropFADDr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
{
FP_ENTER();
FP_OP_REG(FPU_ADD, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFDIVr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIV, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFDIVRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFMULr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_MUL, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFSUBr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUB, opcode & 7, 0);
return op_pc;
}
static uint32_t ropFSUBRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, opcode & 7, 0);
return op_pc;
}
@@ -425,7 +425,7 @@ static uint32_t ropFADDP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_OP_REG(FPU_ADD, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFCOMP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -433,7 +433,7 @@ static uint32_t ropFCOMP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_COMPARE_REG(0, opcode & 7);
FP_POP();
return op_pc;
}
static uint32_t ropFDIVP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -441,7 +441,7 @@ static uint32_t ropFDIVP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_OP_REG(FPU_DIV, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFDIVRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -449,7 +449,7 @@ static uint32_t ropFDIVRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
FP_ENTER();
FP_OP_REG(FPU_DIVR, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFMULP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -457,7 +457,7 @@ static uint32_t ropFMULP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_OP_REG(FPU_MUL, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFSUBP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -465,7 +465,7 @@ static uint32_t ropFSUBP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
FP_ENTER();
FP_OP_REG(FPU_SUB, opcode & 7, 0);
FP_POP();
return op_pc;
}
static uint32_t ropFSUBRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -473,7 +473,7 @@ static uint32_t ropFSUBRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
FP_ENTER();
FP_OP_REG(FPU_SUBR, opcode & 7, 0);
FP_POP();
return op_pc;
}
@@ -482,18 +482,18 @@ static uint32_t ropFCOMPP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
FP_ENTER();
FP_COMPARE_REG(0, 1);
FP_POP2();
return op_pc;
}
static uint32_t ropFSTSW_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
FP_ENTER();
host_reg = LOAD_VAR_W((uintptr_t)&cpu_state.npxs);
STORE_REG_TARGET_W_RELEASE(host_reg, REG_AX);
return op_pc;
}
@@ -512,7 +512,7 @@ static uint32_t ropFISTw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
return op_pc + 1;
@@ -531,7 +531,7 @@ static uint32_t ropFISTl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
return op_pc + 1;
@@ -540,17 +540,17 @@ static uint32_t ropFISTl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropFISTPw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFISTw(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
static uint32_t ropFISTPl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint32_t new_pc = ropFISTl(opcode, fetchdat, op_32, op_pc, block);
FP_POP();
return new_pc;
}
static uint32_t ropFISTPq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -567,11 +567,11 @@ static uint32_t ropFISTPq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
MEM_STORE_ADDR_EA_Q(target_seg, host_reg1, host_reg2);
FP_POP();
return op_pc + 1;
}
@@ -585,11 +585,11 @@ static uint32_t ropFLDCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
STORE_HOST_REG_ADDR_W((uintptr_t)&cpu_state.npxc, 0);
UPDATE_NPXC(0);
return op_pc + 1;
}
static uint32_t ropFSTCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -605,7 +605,7 @@ static uint32_t ropFSTCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
host_reg = LOAD_VAR_W((uintptr_t)&cpu_state.npxc);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
return op_pc + 1;
}
@@ -614,7 +614,7 @@ static uint32_t ropFCHS(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
FP_ENTER();
FP_FCHS();
return op_pc;
}

28
src/codegen/codegen_ops_jump.h
View File

@@ -6,7 +6,7 @@ static uint32_t ropJMP_r8(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
offset |= 0xffffff00;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+1+offset);
return -1;
}
@@ -15,7 +15,7 @@ static uint32_t ropJMP_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
uint16_t offset = fetchdat & 0xffff;
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, (op_pc+2+offset) & 0xffff);
return -1;
}
@@ -24,7 +24,7 @@ static uint32_t ropJMP_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
uint32_t offset = fastreadl(cs + op_pc);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+4+offset);
return -1;
}
@@ -42,11 +42,11 @@ static uint32_t ropJCXZ(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
TEST_ZERO_JUMP_L(host_reg, op_pc+1+offset, 0);
}
else
{
{
int host_reg = LOAD_REG_W(REG_CX);
TEST_ZERO_JUMP_W(host_reg, op_pc+1+offset, 0);
}
return op_pc+1;
}
@@ -56,7 +56,7 @@ static uint32_t ropLOOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
if (offset & 0x80)
offset |= 0xffffff00;
if (op_32 & 0x200)
{
int host_reg = LOAD_REG_L(REG_ECX);
@@ -71,7 +71,7 @@ static uint32_t ropLOOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_REG_W_RELEASE(host_reg);
TEST_NONZERO_JUMP_W(host_reg, op_pc+1+offset, 0);
}
return op_pc+1;
}
@@ -87,10 +87,10 @@ static void BRANCH_COND_B(int pc_offset, uint32_t op_pc, uint32_t offset, int no
static void BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
int host_reg;
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_ZN8:
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:
case FLAGS_ADD8:
@@ -120,7 +120,7 @@ static void BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int no
else
TEST_ZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);
break;
case FLAGS_UNKNOWN:
CALL_FUNC((uintptr_t)ZF_SET);
if (not)
@@ -152,10 +152,10 @@ static void BRANCH_COND_P(int pc_offset, uint32_t op_pc, uint32_t offset, int no
static void BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
int host_reg;
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_ZN8:
case FLAGS_ZN8:
case FLAGS_ADD8:
case FLAGS_SUB8:
case FLAGS_SHL8:
@@ -186,7 +186,7 @@ static void BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int no
else
TEST_NONZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);
break;
case FLAGS_ZN32:
case FLAGS_ADD32:
case FLAGS_SUB32:
@@ -202,7 +202,7 @@ static void BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int no
else
TEST_NONZERO_JUMP_L(host_reg, op_pc+pc_offset+offset, timing_bt);
break;
case FLAGS_UNKNOWN:
CALL_FUNC((uintptr_t)NF_SET);
if (not)

72
src/codegen/codegen_ops_logic.h
View File

@@ -275,9 +275,9 @@ static uint32_t ropAND_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
AND_HOST_REG_IMM(host_reg, (fetchdat & 0xff) | 0xffffff00);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
}
static uint32_t ropAND_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -286,9 +286,9 @@ static uint32_t ropAND_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
AND_HOST_REG_IMM(host_reg, (fetchdat & 0xffff) | 0xffff0000);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
}
static uint32_t ropAND_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -298,9 +298,9 @@ static uint32_t ropAND_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
fetchdat = fastreadl(cs + op_pc);
AND_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
}
@@ -310,9 +310,9 @@ static uint32_t ropOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
OR_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
}
static uint32_t ropOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -321,9 +321,9 @@ static uint32_t ropOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
OR_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
}
static uint32_t ropOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -333,9 +333,9 @@ static uint32_t ropOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
fetchdat = fastreadl(cs + op_pc);
OR_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
}
@@ -345,9 +345,9 @@ static uint32_t ropTEST_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 1;
}
static uint32_t ropTEST_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -356,9 +356,9 @@ static uint32_t ropTEST_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 2;
}
static uint32_t ropTEST_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -368,9 +368,9 @@ static uint32_t ropTEST_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
fetchdat = fastreadl(cs + op_pc);
host_reg = TEST_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 4;
}
@@ -380,9 +380,9 @@ static uint32_t ropXOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
XOR_HOST_REG_IMM(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
return op_pc + 1;
}
static uint32_t ropXOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -391,9 +391,9 @@ static uint32_t ropXOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
XOR_HOST_REG_IMM(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
return op_pc + 2;
}
static uint32_t ropXOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -403,9 +403,9 @@ static uint32_t ropXOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
fetchdat = fastreadl(cs + op_pc);
XOR_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
return op_pc + 4;
}
@@ -414,7 +414,7 @@ static uint32_t ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
x86seg *target_seg;
int host_reg;
uint8_t imm;
switch (fetchdat & 0x38)
{
case 0x00: /*TEST b,#8*/
@@ -433,7 +433,7 @@ static uint32_t ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
}
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 2;
@@ -457,7 +457,7 @@ static uint32_t ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
return op_pc + 1;
}
return 0;
}
static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -465,7 +465,7 @@ static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
x86seg *target_seg;
int host_reg;
uint16_t imm;
switch (fetchdat & 0x38)
{
case 0x00: /*TEST w,#*/
@@ -484,7 +484,7 @@ static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 3;
@@ -508,7 +508,7 @@ static uint32_t ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
return op_pc + 1;
}
return 0;
}
static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -516,7 +516,7 @@ static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
x86seg *target_seg;
int host_reg;
uint32_t imm;
switch (fetchdat & 0x38)
{
case 0x00: /*TEST l,#*/
@@ -535,7 +535,7 @@ static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
host_reg = TEST_HOST_REG_IMM(host_reg, imm);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
return op_pc + 5;
@@ -559,6 +559,6 @@ static uint32_t ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
return op_pc + 1;
}
return 0;
}

20
src/codegen/codegen_ops_misc.h
View File

@@ -41,7 +41,7 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
return 0;
CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_B(fetchdat & 7);
else
@@ -53,7 +53,7 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
MEM_CHECK_WRITE(target_seg);
host_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg);
}
switch (fetchdat & 0x38)
{
case 0x00: /*INC*/
@@ -80,7 +80,7 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
MEM_STORE_ADDR_EA_B_NO_ABRT(target_seg, host_reg);
}
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t codegen_temp;
@@ -88,7 +88,7 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
{
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0;
@@ -114,7 +114,7 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
host_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg);
}
}
switch (fetchdat & 0x38)
{
case 0x00: /*INC*/
@@ -159,7 +159,7 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
SP_MODIFY(-2);
host_reg = LOAD_VAR_W((uintptr_t)&codegen_temp);
STORE_HOST_REG_ADDR_W((uintptr_t)&cpu_state.pc, host_reg);
STORE_HOST_REG_ADDR_W((uintptr_t)&cpu_state.pc, host_reg);
return -1;
case 0x20: /*JMP*/
@@ -181,13 +181,13 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
{
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0;
if ((fetchdat & 0x30) == 0x00)
CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_L(fetchdat & 7);
else
@@ -207,7 +207,7 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
host_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg);
}
}
switch (fetchdat & 0x38)
{
case 0x00: /*INC*/
@@ -252,7 +252,7 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
SP_MODIFY(-4);
host_reg = LOAD_VAR_L((uintptr_t)&codegen_temp);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, host_reg);
return -1;
case 0x20: /*JMP*/

42
src/codegen/codegen_ops_mmx.h
View File

@@ -3,9 +3,9 @@ static uint32_t ropMOVQ_q_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg1, host_reg2 = 0;
MMX_ENTER();
LOAD_MMX_Q((fetchdat >> 3) & 7, &host_reg1, &host_reg2);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_MMX_Q(fetchdat & 7, host_reg1, host_reg2);
@@ -15,10 +15,10 @@ static uint32_t ropMOVQ_q_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 7);
MEM_STORE_ADDR_EA_Q(target_seg, host_reg1, host_reg2);
}
@@ -28,11 +28,11 @@ static uint32_t ropMOVQ_q_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
static uint32_t ropMOVQ_mm_q(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
MMX_ENTER();
if ((fetchdat & 0xc0) == 0xc0)
{
int host_reg1, host_reg2;
LOAD_MMX_Q(fetchdat & 7, &host_reg1, &host_reg2);
STORE_MMX_Q((fetchdat >> 3) & 7, host_reg1, host_reg2);
}
@@ -56,9 +56,9 @@ static uint32_t ropMOVD_l_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
int host_reg;
MMX_ENTER();
host_reg = LOAD_MMX_D((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_REG_TARGET_L_RELEASE(host_reg, fetchdat & 7);
@@ -68,10 +68,10 @@ static uint32_t ropMOVD_l_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 3);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
}
@@ -80,7 +80,7 @@ static uint32_t ropMOVD_l_mm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
static uint32_t ropMOVD_mm_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
MMX_ENTER();
if ((fetchdat & 0xc0) == 0xc0)
{
int host_reg = LOAD_REG_L(fetchdat & 7);
@@ -192,9 +192,9 @@ static uint32_t ropPSxxW_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
return 0;
if ((fetchdat & 0x08) || !(fetchdat & 0x30))
return 0;
MMX_ENTER();
xmm_dst = LOAD_MMX_Q_MMX(fetchdat & 7);
switch (fetchdat & 0x38)
{
@@ -209,7 +209,7 @@ static uint32_t ropPSxxW_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
break;
}
STORE_MMX_Q_MMX(fetchdat & 7, xmm_dst);
return op_pc + 2;
}
static uint32_t ropPSxxD_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -220,9 +220,9 @@ static uint32_t ropPSxxD_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
return 0;
if ((fetchdat & 0x08) || !(fetchdat & 0x30))
return 0;
MMX_ENTER();
xmm_dst = LOAD_MMX_Q_MMX(fetchdat & 7);
switch (fetchdat & 0x38)
{
@@ -237,7 +237,7 @@ static uint32_t ropPSxxD_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
break;
}
STORE_MMX_Q_MMX(fetchdat & 7, xmm_dst);
return op_pc + 2;
}
static uint32_t ropPSxxQ_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -248,9 +248,9 @@ static uint32_t ropPSxxQ_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
return 0;
if ((fetchdat & 0x08) || !(fetchdat & 0x30))
return 0;
MMX_ENTER();
xmm_dst = LOAD_MMX_Q_MMX(fetchdat & 7);
switch (fetchdat & 0x38)
{
@@ -265,13 +265,13 @@ static uint32_t ropPSxxQ_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
break;
}
STORE_MMX_Q_MMX(fetchdat & 7, xmm_dst);
return op_pc + 2;
}
static uint32_t ropEMMS(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
codegen_mmx_entered = 0;
return 0;
}

104
src/codegen/codegen_ops_mov.h
View File

@@ -1,7 +1,7 @@
static uint32_t ropMOV_rb_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
STORE_IMM_REG_B(opcode & 7, fetchdat & 0xff);
return op_pc + 1;
}
static uint32_t ropMOV_rw_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -15,7 +15,7 @@ static uint32_t ropMOV_rl_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
fetchdat = fastreadl(cs + op_pc);
STORE_IMM_REG_L(opcode & 7, fetchdat);
return op_pc + 4;
}
@@ -23,7 +23,7 @@ static uint32_t ropMOV_rl_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
static uint32_t ropMOV_b_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_B((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_REG_TARGET_B_RELEASE(host_reg, fetchdat & 7);
@@ -33,20 +33,20 @@ static uint32_t ropMOV_b_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 0);
MEM_STORE_ADDR_EA_B(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t ropMOV_w_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg = LOAD_REG_W((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_REG_TARGET_W_RELEASE(host_reg, fetchdat & 7);
@@ -56,23 +56,23 @@ static uint32_t ropMOV_w_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 1);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t ropMOV_l_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int host_reg;
host_reg = LOAD_REG_L((fetchdat >> 3) & 7);
if ((fetchdat & 0xc0) == 0xc0)
{
STORE_REG_TARGET_L_RELEASE(host_reg, fetchdat & 7);
@@ -82,13 +82,13 @@ static uint32_t ropMOV_l_r(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 3);
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
@@ -106,13 +106,13 @@ static uint32_t ropMOV_r_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
STORE_REG_TARGET_B_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOV_r_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -133,7 +133,7 @@ static uint32_t ropMOV_r_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
MEM_LOAD_ADDR_EA_W(target_seg);
STORE_REG_TARGET_W_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOV_r_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -154,7 +154,7 @@ static uint32_t ropMOV_r_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
MEM_LOAD_ADDR_EA_L(target_seg);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
@@ -220,7 +220,7 @@ static uint32_t ropMOV_l_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
MEM_STORE_ADDR_EA_L(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 5;
}
@@ -239,7 +239,7 @@ static uint32_t ropMOV_AL_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
MEM_LOAD_ADDR_IMM_B(op_ea_seg, addr);
STORE_REG_TARGET_B_RELEASE(0, REG_AL);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropMOV_AX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -256,7 +256,7 @@ static uint32_t ropMOV_AX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
MEM_LOAD_ADDR_IMM_W(op_ea_seg, addr);
STORE_REG_TARGET_W_RELEASE(0, REG_AX);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropMOV_EAX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -273,7 +273,7 @@ static uint32_t ropMOV_EAX_a(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
MEM_LOAD_ADDR_IMM_L(op_ea_seg, addr);
STORE_REG_TARGET_L_RELEASE(0, REG_EAX);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
@@ -289,12 +289,12 @@ static uint32_t ropMOV_a_AL(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
CHECK_SEG_WRITE(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
host_reg = LOAD_REG_B(REG_AL);
MEM_STORE_ADDR_IMM_B(op_ea_seg, addr, host_reg);
RELEASE_REG(host_reg);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropMOV_a_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -309,12 +309,12 @@ static uint32_t ropMOV_a_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
CHECK_SEG_WRITE(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
host_reg = LOAD_REG_W(REG_AX);
MEM_STORE_ADDR_IMM_W(op_ea_seg, addr, host_reg);
RELEASE_REG(host_reg);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropMOV_a_EAX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -329,24 +329,24 @@ static uint32_t ropMOV_a_EAX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
CHECK_SEG_WRITE(op_ea_seg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
host_reg = LOAD_REG_L(REG_EAX);
MEM_STORE_ADDR_IMM_L(op_ea_seg, addr, host_reg);
RELEASE_REG(host_reg);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
static uint32_t ropLEA_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
return 0;
FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_REG_TARGET_W_RELEASE(0, dest_reg);
return op_pc + 1;
@@ -354,12 +354,12 @@ static uint32_t ropLEA_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
static uint32_t ropLEA_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
return 0;
FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_REG_TARGET_L_RELEASE(0, dest_reg);
return op_pc + 1;
@@ -378,14 +378,14 @@ static uint32_t ropMOVZX_w_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
ZERO_EXTEND_W_B(0);
STORE_REG_TARGET_W_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOVZX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -401,14 +401,14 @@ static uint32_t ropMOVZX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
ZERO_EXTEND_L_B(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOVZX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -424,14 +424,14 @@ static uint32_t ropMOVZX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
ZERO_EXTEND_L_W(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
@@ -448,14 +448,14 @@ static uint32_t ropMOVSX_w_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
SIGN_EXTEND_W_B(0);
STORE_REG_TARGET_W_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOVSX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -471,14 +471,14 @@ static uint32_t ropMOVSX_l_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_B(target_seg);
SIGN_EXTEND_L_B(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
static uint32_t ropMOVSX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -494,14 +494,14 @@ static uint32_t ropMOVSX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
SIGN_EXTEND_L_W(0);
STORE_REG_TARGET_L_RELEASE(0, (fetchdat >> 3) & 7);
}
return op_pc + 1;
}
@@ -532,7 +532,7 @@ static uint32_t ropMOV_w_seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
default:
return 0;
}
if ((fetchdat & 0xc0) == 0xc0)
{
if (op_32 & 0x100)
@@ -545,14 +545,14 @@ static uint32_t ropMOV_w_seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
CHECK_SEG_WRITE(target_seg);
CHECK_SEG_LIMITS(target_seg, 1);
MEM_STORE_ADDR_EA_W(target_seg, host_reg);
RELEASE_REG(host_reg);
}
return op_pc + 1;
}
static uint32_t ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -572,7 +572,7 @@ static uint32_t ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
}
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_W(fetchdat & 7);
else
@@ -581,10 +581,10 @@ static uint32_t ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
CHECK_SEG_READ(target_seg);
MEM_LOAD_ADDR_EA_W(target_seg);
host_reg = 0;
}
switch (fetchdat & 0x38)
{
case 0x00: /*ES*/
@@ -600,7 +600,7 @@ static uint32_t ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
LOAD_SEG(host_reg, &cpu_state.seg_gs);
break;
}
return op_pc + 1;
}

8
src/codegen/codegen_ops_shift.h
View File

@@ -67,7 +67,7 @@ static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
return 0;
SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 1);
return op_pc + 2;
}
static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -80,7 +80,7 @@ static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
return 0;
SHIFT(L, 32, STORE_HOST_REG_ADDR, 1);
return op_pc + 2;
}
@@ -107,7 +107,7 @@ static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
return 0;
SHIFT(W, 16, STORE_HOST_REG_ADDR_WL, 0);
return op_pc + 1;
}
static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -120,6 +120,6 @@ static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
return 0;
SHIFT(L, 32, STORE_HOST_REG_ADDR, 0);
return op_pc + 1;
}

28
src/codegen/codegen_ops_stack.h
View File

@@ -7,7 +7,7 @@ static uint32_t ropPUSH_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, ui
host_reg = LOAD_REG_W(opcode & 7);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc;
}
static uint32_t ropPUSH_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -33,7 +33,7 @@ static uint32_t ropPUSH_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc+2;
}
static uint32_t ropPUSH_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -46,7 +46,7 @@ static uint32_t ropPUSH_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
return op_pc+4;
}
@@ -63,7 +63,7 @@ static uint32_t ropPUSH_imm_b16(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
return op_pc+1;
}
static uint32_t ropPUSH_imm_b32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -79,7 +79,7 @@ static uint32_t ropPUSH_imm_b32(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
host_reg = LOAD_REG_IMM(imm);
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
return op_pc+1;
}
@@ -90,7 +90,7 @@ static uint32_t ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
SP_MODIFY(2);
STORE_REG_TARGET_W_RELEASE(0, opcode & 7);
return op_pc;
}
static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -100,7 +100,7 @@ static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
SP_MODIFY(4);
STORE_REG_TARGET_L_RELEASE(0, opcode & 7);
return op_pc;
}
@@ -111,7 +111,7 @@ static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(2);
return -1;
}
static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -121,7 +121,7 @@ static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(4);
return -1;
}
@@ -134,7 +134,7 @@ static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
MEM_LOAD_ADDR_EA_W(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(2+offset);
return -1;
}
static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -146,7 +146,7 @@ static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
MEM_LOAD_ADDR_EA_L(&cpu_state.seg_ss);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
SP_MODIFY(4+offset);
return -1;
}
@@ -161,7 +161,7 @@ static uint32_t ropCALL_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
MEM_STORE_ADDR_EA_W(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-2);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, (op_pc+2+offset) & 0xffff);
return -1;
}
static uint32_t ropCALL_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -175,7 +175,7 @@ static uint32_t ropCALL_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
MEM_STORE_ADDR_EA_L(&cpu_state.seg_ss, host_reg);
SP_MODIFY(-4);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+4+offset);
return -1;
}
@@ -204,7 +204,7 @@ static uint32_t ropLEAVE_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
ADD_HOST_REG_IMM(host_reg, 4);
STORE_REG_TARGET_L_RELEASE(host_reg, REG_ESP);
STORE_REG_TARGET_L_RELEASE(0, REG_EBP); /*EBP = POP_L()*/
return op_pc;
}

250
src/codegen/codegen_ops_x86-64.h
View File

@@ -16,7 +16,7 @@ static inline int find_host_xmm_reg()
if (host_reg_xmm_mapping[c] == -1)
break;
}
if (c == HOST_REG_XMM_END)
fatal("Out of host XMM regs!\n");
return c;
@@ -236,10 +236,10 @@ static inline int LOAD_REG_B(int reg)
}
codegen_reg_loaded[reg & 3] = 1;
if (reg & 4)
return host_reg | 0x18;
return host_reg | 8;
}
static inline int LOAD_REG_W(int reg)
@@ -255,7 +255,7 @@ static inline int LOAD_REG_W(int reg)
}
codegen_reg_loaded[reg & 7] = 1;
return host_reg | 8;
}
static inline int LOAD_REG_L(int reg)
@@ -271,7 +271,7 @@ static inline int LOAD_REG_L(int reg)
}
codegen_reg_loaded[reg & 7] = 1;
return host_reg | 8;
}
@@ -281,14 +281,14 @@ static inline int LOAD_REG_IMM(uint32_t imm)
addbyte(0xb8 | REG_EBX); /*MOVL EBX, imm*/
addlong(imm);
return host_reg;
}
static inline void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
{
int dest_reg = LOAD_REG_L(guest_reg & 3) & 7;
if (guest_reg & 4)
{
if (host_reg & 8)
@@ -305,7 +305,7 @@ static inline void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
addbyte(0xc0 | ((host_reg & 3) << 3));
}
if (host_reg & 0x10)
{
{
addbyte(0x66); /*AND AX, 0xff00*/
addbyte(0x25);
addword(0xff00);
@@ -382,7 +382,7 @@ static inline void STORE_REG_TARGET_B_RELEASE(int host_reg, int guest_reg)
static inline void STORE_REG_TARGET_W_RELEASE(int host_reg, int guest_reg)
{
int dest_reg = LOAD_REG_L(guest_reg & 7) & 7;
if (host_reg & 8)
{
addbyte(0x66); /*MOVW guest_reg, host_reg*/
@@ -555,8 +555,8 @@ static x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
int mod = (fetchdat >> 6) & 3;
int rm = fetchdat & 7;
if (!mod && rm == 6)
{
if (!mod && rm == 6)
{
addbyte(0xb8); /*MOVL EAX, imm*/
addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2;
@@ -564,7 +564,7 @@ static x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
else
{
int base_reg = 0, index_reg = 0;
switch (rm)
{
case 0: case 1: case 7:
@@ -589,7 +589,7 @@ static x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
}
base_reg &= 7;
index_reg &= 7;
switch (mod)
{
case 0:
@@ -658,7 +658,7 @@ static x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
}
(*op_pc) += 2;
break;
}
if (mod || !(rm & 4))
{
@@ -745,7 +745,7 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
}
}
else
{
{
switch (mod)
{
case 0:
@@ -823,7 +823,7 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
int base_reg;
if (!mod && rm == 5)
{
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL EAX, new_eaaddr*/
addlong(new_eaaddr);
@@ -831,20 +831,20 @@ static x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, u
return op_ea_seg;
}
base_reg = LOAD_REG_L(rm) & 7;
if (mod)
if (mod)
{
if (rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (mod == 1)
if (mod == 1)
{
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x40 | base_reg);
addbyte((fetchdat >> 8) & 0xff);
(*op_pc)++;
(*op_pc)++;
}
else
else
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, base_reg+imm32*/
@@ -907,7 +907,7 @@ static inline void CHECK_SEG_READ(x86seg *seg)
addbyte(0x0f); /*JE GPF_BLOCK_OFFSET*/
addbyte(0x84);
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
seg->checked = 1;
}
static inline void CHECK_SEG_WRITE(x86seg *seg)
@@ -922,7 +922,7 @@ static inline void CHECK_SEG_WRITE(x86seg *seg)
return;
if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
return;
if (IS_32_ADDR(&seg->base))
{
addbyte(0x83); /*CMP seg->base, -1*/
@@ -1740,14 +1740,14 @@ static inline void MEM_STORE_ADDR_IMM_L(x86seg *seg, uint32_t addr, int host_reg
static inline void STORE_HOST_REG_ADDR_BL(uintptr_t addr, int host_reg)
{
int temp_reg = REG_ECX;
if (host_reg_mapping[REG_ECX] != -1)
temp_reg = REG_EBX;
if (host_reg & 0x10)
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0x41);
addbyte(0x0f); /*MOVZX temp_reg, host_reg*/
addbyte(0xb7);
addbyte(0xc0 | (temp_reg << 3) | (host_reg & 7));
@@ -1758,7 +1758,7 @@ static inline void STORE_HOST_REG_ADDR_BL(uintptr_t addr, int host_reg)
else
{
if (host_reg & 8)
addbyte(0x41);
addbyte(0x41);
addbyte(0x0f); /*MOVZX temp_reg, host_reg*/
addbyte(0xb6);
addbyte(0xc0 | (temp_reg << 3) | (host_reg & 7));
@@ -1788,12 +1788,12 @@ static inline void STORE_HOST_REG_ADDR_BL(uintptr_t addr, int host_reg)
static inline void STORE_HOST_REG_ADDR_WL(uintptr_t addr, int host_reg)
{
int temp_reg = REG_ECX;
if (host_reg_mapping[REG_ECX] != -1)
temp_reg = REG_EBX;
if (host_reg & 8)
addbyte(0x41);
addbyte(0x41);
addbyte(0x0f); /*MOVZX temp_reg, host_reg*/
addbyte(0xb7);
addbyte(0xc0 | (temp_reg << 3) | (host_reg & 7));
@@ -1980,7 +1980,7 @@ static inline void AND_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*ANDB dst_reg, src_reg*/
addbyte(0x20);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
else
{
@@ -2005,7 +2005,7 @@ static inline void AND_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x20); /*ANDB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
}
static inline void AND_HOST_REG_W(int dst_reg, int src_reg)
@@ -2092,12 +2092,12 @@ static inline int TEST_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = (dst_reg & 0x10) | REG_EDX;
}
AND_HOST_REG_B(dst_reg, src_reg);
return dst_reg & ~0x10;
}
static inline int TEST_HOST_REG_W(int dst_reg, int src_reg)
@@ -2107,12 +2107,12 @@ static inline int TEST_HOST_REG_W(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
AND_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_L(int dst_reg, int src_reg)
@@ -2122,12 +2122,12 @@ static inline int TEST_HOST_REG_L(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
AND_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_IMM(int host_reg, uint32_t imm)
@@ -2152,7 +2152,7 @@ static inline int TEST_HOST_REG_IMM(int host_reg, uint32_t imm)
addbyte(0xe0 | (host_reg & 7));
addlong(imm);
}
return host_reg;
}
@@ -2250,7 +2250,7 @@ static inline void OR_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*ORB dst_reg, src_reg*/
addbyte(0x08);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
else
{
@@ -2275,7 +2275,7 @@ static inline void OR_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x08); /*ORB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
}
static inline void OR_HOST_REG_W(int dst_reg, int src_reg)
@@ -2453,7 +2453,7 @@ static inline void XOR_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*XORB dst_reg, src_reg*/
addbyte(0x30);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
else
{
@@ -2478,7 +2478,7 @@ static inline void XOR_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x30); /*XORB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
}
static inline void XOR_HOST_REG_W(int dst_reg, int src_reg)
@@ -2800,7 +2800,7 @@ static inline void SUB_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*SUBB dst_reg, src_reg*/
addbyte(0x28);
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
else
{
@@ -2825,7 +2825,7 @@ static inline void SUB_HOST_REG_B(int dst_reg, int src_reg)
{
addbyte(0x28); /*SUBB dst_reg, src_reg*/
addbyte(0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
}
}
}
static inline void SUB_HOST_REG_W(int dst_reg, int src_reg)
@@ -2892,12 +2892,12 @@ static inline int CMP_HOST_REG_B(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = (dst_reg & 0x10) | REG_EDX;
}
SUB_HOST_REG_B(dst_reg, src_reg);
return dst_reg & ~0x10;
}
static inline int CMP_HOST_REG_W(int dst_reg, int src_reg)
@@ -2907,12 +2907,12 @@ static inline int CMP_HOST_REG_W(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
SUB_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static inline int CMP_HOST_REG_L(int dst_reg, int src_reg)
@@ -2922,12 +2922,12 @@ static inline int CMP_HOST_REG_L(int dst_reg, int src_reg)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((dst_reg & 7) << 3) | REG_EDX);
dst_reg = REG_EDX;
}
SUB_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
@@ -3045,12 +3045,12 @@ static inline int CMP_HOST_REG_IMM_B(int host_reg, uint8_t imm)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3) | REG_EDX);
host_reg = (host_reg & 0x10) | REG_EDX;
}
SUB_HOST_REG_IMM_B(host_reg, imm);
return host_reg;
}
static inline int CMP_HOST_REG_IMM_W(int host_reg, uint16_t imm)
@@ -3060,12 +3060,12 @@ static inline int CMP_HOST_REG_IMM_W(int host_reg, uint16_t imm)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3) | REG_EDX);
host_reg = REG_EDX;
}
SUB_HOST_REG_IMM_W(host_reg, imm);
return host_reg;
}
static inline int CMP_HOST_REG_IMM_L(int host_reg, uint32_t imm)
@@ -3075,12 +3075,12 @@ static inline int CMP_HOST_REG_IMM_L(int host_reg, uint32_t imm)
addbyte(0x44); /*MOV EDX, dst_reg*/
addbyte(0x89);
addbyte(0xc0 | ((host_reg & 7) << 3) | REG_EDX);
host_reg = REG_EDX;
}
SUB_HOST_REG_IMM(host_reg, imm);
return host_reg;
}
@@ -3280,7 +3280,7 @@ static inline void TEST_NONZERO_JUMP_L(int host_reg, uint32_t new_pc, int taken_
static inline void BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
uint8_t *jump1;
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN)
{
addbyte(0x83); /*CMP flags_res, 0*/
@@ -3305,7 +3305,7 @@ static inline void BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(7+5+(timing_bt ? 4 : 0));
if (!not)
*jump1 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump1 - 1;
@@ -3346,7 +3346,7 @@ static inline void BRANCH_COND_L(int pc_offset, uint32_t op_pc, uint32_t offset,
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(pc));
@@ -3400,7 +3400,7 @@ static inline void BRANCH_COND_LE(int pc_offset, uint32_t op_pc, uint32_t offset
addbyte(0x75); /*JNZ +*/
else
addbyte(0x74); /*JZ +*/
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(7+5+(timing_bt ? 4 : 0));
if (!not)
*jump1 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump1 - 1;
addbyte(0xC7); /*MOVL [pc], new_pc*/
@@ -3490,7 +3490,7 @@ static inline int COPY_REG(int src_reg)
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | REG_ECX | ((src_reg & 7) << 3));
return REG_ECX | (src_reg & 0x10);
}
@@ -3500,7 +3500,7 @@ static inline int LOAD_HOST_REG(int host_reg)
addbyte(0x44);
addbyte(0x89);
addbyte(0xc0 | REG_EBX | ((host_reg & 7) << 3));
return REG_EBX | (host_reg & 0x10);
}
@@ -3514,16 +3514,16 @@ static inline int ZERO_EXTEND_W_B(int reg)
addbyte(0x0f); /*MOVZX EAX, AH*/
addbyte(0xb6);
addbyte(0xc4);
return REG_EAX;
}
if (reg & 8)
addbyte(0x41);
addbyte(0x0f); /*MOVZX regl, regb*/
addbyte(0xb6);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static inline int ZERO_EXTEND_L_B(int reg)
@@ -3536,7 +3536,7 @@ static inline int ZERO_EXTEND_L_B(int reg)
addbyte(0x0f); /*MOVZX EAX, AH*/
addbyte(0xb6);
addbyte(0xc4);
return REG_EAX;
}
@@ -3545,7 +3545,7 @@ static inline int ZERO_EXTEND_L_B(int reg)
addbyte(0x0f); /*MOVZX regl, regb*/
addbyte(0xb6);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static inline int ZERO_EXTEND_L_W(int reg)
@@ -3555,7 +3555,7 @@ static inline int ZERO_EXTEND_L_W(int reg)
addbyte(0x0f); /*MOVZX regl, regw*/
addbyte(0xb7);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
@@ -3569,7 +3569,7 @@ static inline int SIGN_EXTEND_W_B(int reg)
addbyte(0x0f); /*MOVSX EAX, AH*/
addbyte(0xbe);
addbyte(0xc4);
return REG_EAX;
}
@@ -3578,7 +3578,7 @@ static inline int SIGN_EXTEND_W_B(int reg)
addbyte(0x0f); /*MOVSX regl, regb*/
addbyte(0xbe);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static inline int SIGN_EXTEND_L_B(int reg)
@@ -3591,7 +3591,7 @@ static inline int SIGN_EXTEND_L_B(int reg)
addbyte(0x0f); /*MOVSX EAX, AH*/
addbyte(0xbe);
addbyte(0xc4);
return REG_EAX;
}
@@ -3600,7 +3600,7 @@ static inline int SIGN_EXTEND_L_B(int reg)
addbyte(0x0f); /*MOVSX regl, regb*/
addbyte(0xbe);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
static inline int SIGN_EXTEND_L_W(int reg)
@@ -3610,7 +3610,7 @@ static inline int SIGN_EXTEND_L_W(int reg)
addbyte(0x0f); /*MOVSX regl, regw*/
addbyte(0xbf);
addbyte(0xc0 | (reg & 7));
return REG_EAX;
}
@@ -3773,7 +3773,7 @@ static inline void NEG_HOST_REG_L(int reg)
addbyte(0xf7);
addbyte(0xd8 | (reg & 7));
}
static inline void FP_ENTER()
{
@@ -3806,7 +3806,7 @@ static inline void FP_ENTER()
CALL_FUNC((uintptr_t)x86_int);
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
codegen_fpu_entered = 1;
}
@@ -3844,7 +3844,7 @@ static inline void FP_FXCH(int reg)
addbyte(0x4c);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(ST));
addbyte(0x8a); /*MOV CL, tag[EAX]*/
addbyte(0x4c);
addbyte(0x05);
@@ -3910,7 +3910,7 @@ static inline void FP_FLD(int reg)
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
}
}
addbyte(0x48); /*MOV RCX, ST[EAX*8]*/
addbyte(0x8b);
@@ -4288,8 +4288,8 @@ static inline int FP_LOAD_REG(int reg)
addbyte(0x66); /*MOVD EBX, XMM0*/
addbyte(0x0f);
addbyte(0x7e);
addbyte(0xc0 | REG_EBX);
addbyte(0xc0 | REG_EBX);
return REG_EBX;
}
static inline void FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
@@ -4311,13 +4311,13 @@ static inline void FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(ST));
*host_reg1 = REG_EBX;
}
static inline int64_t x87_fround16_64(double b)
{
int16_t a, c;
switch ((cpu_state.npxc >> 10) & 3)
{
case 0: /*Nearest*/
@@ -4336,13 +4336,13 @@ static inline int64_t x87_fround16_64(double b)
case 3: /*Chop*/
return (int64_t)((int16_t)b);
}
return 0;
}
static inline int64_t x87_fround32_64(double b)
{
int32_t a, c;
switch ((cpu_state.npxc >> 10) & 3)
{
case 0: /*Nearest*/
@@ -4361,13 +4361,13 @@ static inline int64_t x87_fround32_64(double b)
case 3: /*Chop*/
return (int64_t)((int32_t)b);
}
return 0;
}
static inline int64_t x87_fround(double b)
{
int64_t a, c;
switch ((cpu_state.npxc >> 10) & 3)
{
case 0: /*Nearest*/
@@ -4386,7 +4386,7 @@ static inline int64_t x87_fround(double b)
case 3: /*Chop*/
return (int64_t)b;
}
return 0;
}
static inline int FP_LOAD_REG_INT_W(int reg)
@@ -4414,9 +4414,9 @@ static inline int FP_LOAD_REG_INT_W(int reg)
addbyte((uint8_t)cpu_state_offset(ST));
CALL_FUNC((uintptr_t)x87_fround16_64);
addbyte(0x93); /*XCHG EBX, EAX*/
return REG_EBX;
}
static inline int FP_LOAD_REG_INT(int reg)
@@ -4444,9 +4444,9 @@ static inline int FP_LOAD_REG_INT(int reg)
addbyte((uint8_t)cpu_state_offset(ST));
CALL_FUNC((uintptr_t)x87_fround32_64);
addbyte(0x93); /*XCHG EBX, EAX*/
return REG_EBX;
}
static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
@@ -4482,16 +4482,16 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte(0x93);
*host_reg1 = REG_EBX;
return;
}
addbyte(0xf6); /*TEST TAG[EAX], TAG_UINT64*/
addbyte(0x44);
addbyte(0x05);
addbyte((uint8_t)cpu_state_offset(tag));
addbyte(TAG_UINT64);
addbyte(0x74); /*JZ +*/
addbyte(5+2);
@@ -4500,7 +4500,7 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte(0x44);
addbyte(0xc5);
addbyte((uint8_t)cpu_state_offset(MM));
addbyte(0xeb); /*JMP done*/
addbyte(6+12);
@@ -4512,10 +4512,10 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte((uint8_t)cpu_state_offset(ST));
CALL_FUNC((uintptr_t)x87_fround);
addbyte(0x48); /*XCHG RBX, RAX*/
addbyte(0x93);
*host_reg1 = REG_EBX;
}
@@ -5015,7 +5015,7 @@ static inline void MMX_ENTER()
{
if (codegen_mmx_entered)
return;
if (IS_32_ADDR(&cr0))
{
addbyte(0xf6); /*TEST cr0, 0xc*/
@@ -5044,7 +5044,7 @@ static inline void MMX_ENTER()
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
addbyte(0x31); /*XOR EAX, EAX*/
addbyte(0xc0);
addbyte(0xc6); /*MOV ISMMX, 1*/
@@ -5054,7 +5054,7 @@ static inline void MMX_ENTER()
addbyte(0x89); /*MOV TOP, EAX*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(TOP));
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(tag[0]));
addbyte(0x89); /*MOV tag+4, EAX*/
@@ -5074,7 +5074,7 @@ static inline int LOAD_MMX_D(int guest_reg)
addbyte(0x44 | (host_reg << 3));
addbyte(0x25);
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].l[0]));
return host_reg;
}
static inline void LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
@@ -5089,7 +5089,7 @@ static inline void LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
addbyte(0x44 | ((host_reg & 7) << 3));
addbyte(0x25);
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].q));
*host_reg1 = host_reg;
}
static inline int LOAD_MMX_Q_MMX(int guest_reg)
@@ -5103,7 +5103,7 @@ static inline int LOAD_MMX_Q_MMX(int guest_reg)
addbyte(0x44 | ((dst_reg & 7) << 3));
addbyte(0x25);
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].q));
return dst_reg;
}
@@ -5111,7 +5111,7 @@ static inline int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
{
int dst_reg = find_host_xmm_reg();
host_reg_xmm_mapping[dst_reg] = 100;
addbyte(0x66); /*MOVQ host_reg, src_reg1*/
if (src_reg1 & 8)
addbyte(0x49);
@@ -5120,7 +5120,7 @@ static inline int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
addbyte(0x0f);
addbyte(0x6e);
addbyte(0xc0 | (dst_reg << 3) | (src_reg1 & 7));
return dst_reg;
}
@@ -5382,7 +5382,7 @@ static inline void LOAD_EA()
static inline void MEM_CHECK_WRITE(x86seg *seg)
{
uint8_t *jump1, *jump2, *jump3 = NULL;
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5408,7 +5408,7 @@ static inline void MEM_CHECK_WRITE(x86seg *seg)
/*seg = ESI, addr = EAX*/
if (IS_32_ADDR(&cr0))
{
addbyte(0x83); /*CMP cr0, 0*/
@@ -5468,7 +5468,7 @@ static inline void MEM_CHECK_WRITE(x86seg *seg)
addbyte(0);
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
*jump3 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump3 - 1;
*jump3 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump3 - 1;
/*slowpath:*/
addbyte(0x67); /*LEA EDI, [EAX+ESI]*/
addbyte(0x8d);
@@ -5497,7 +5497,7 @@ static inline void MEM_CHECK_WRITE_W(x86seg *seg)
{
uint8_t *jump1, *jump2, *jump3, *jump4 = NULL;
int jump_pos;
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5523,7 +5523,7 @@ static inline void MEM_CHECK_WRITE_W(x86seg *seg)
/*seg = ESI, addr = EAX*/
if (IS_32_ADDR(&cr0))
{
addbyte(0x83); /*CMP cr0, 0*/
@@ -5610,7 +5610,7 @@ static inline void MEM_CHECK_WRITE_W(x86seg *seg)
addbyte(0x75); /*JNE +*/
jump3 = &codeblock[block_current].data[block_pos];
addbyte(0);
/*slowpath:*/
*jump2 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump2 - 1;
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5646,7 +5646,7 @@ static inline void MEM_CHECK_WRITE_L(x86seg *seg)
{
uint8_t *jump1, *jump2, *jump3, *jump4 = NULL;
int jump_pos;
CHECK_SEG_WRITE(seg);
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5672,7 +5672,7 @@ static inline void MEM_CHECK_WRITE_L(x86seg *seg)
/*seg = ESI, addr = EAX*/
if (IS_32_ADDR(&cr0))
{
addbyte(0x83); /*CMP cr0, 0*/
@@ -5759,7 +5759,7 @@ static inline void MEM_CHECK_WRITE_L(x86seg *seg)
addbyte(0x75); /*JNE +*/
jump3 = &codeblock[block_current].data[block_pos];
addbyte(0);
/*slowpath:*/
*jump2 = (uintptr_t)&codeblock[block_current].data[block_pos] - (uintptr_t)jump2 - 1;
if (!(seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) && !(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
@@ -5861,7 +5861,7 @@ static inline int MEM_LOAD_ADDR_EA_B_NO_ABRT(x86seg *seg)
/*done:*/
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static inline int MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
@@ -5940,7 +5940,7 @@ static inline int MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
/*done:*/
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static inline int MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
@@ -6018,7 +6018,7 @@ static inline int MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
/*done:*/
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}

108
src/codegen/codegen_ops_x86.h
View File

@@ -16,7 +16,7 @@ static inline int find_host_reg()
if (host_reg_mapping[c] == -1)
break;
}
if (c == NR_HOST_REGS)
fatal("Out of host regs!\n");
return c;
@@ -29,7 +29,7 @@ static inline int find_host_xmm_reg()
if (host_reg_xmm_mapping[c] == -1)
break;
}
if (c == HOST_REG_XMM_END)
fatal("Out of host XMM regs!\n");
return c;
@@ -151,12 +151,12 @@ static inline int LOAD_VAR_WL(uintptr_t addr)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = 0;
addbyte(0x0f); /*MOVZX host_reg, [addr]*/
addbyte(0xb7);
addbyte(0x05 | (host_reg << 3));
addlong((uint32_t)addr);
return host_reg;
}
static inline int LOAD_VAR_L(uintptr_t addr)
@@ -175,11 +175,11 @@ static inline int LOAD_REG_IMM(uint32_t imm)
{
int host_reg = find_host_reg();
host_reg_mapping[host_reg] = 0;
addbyte(0xc7); /*MOVL host_reg, imm*/
addbyte(0xc0 | host_reg);
addlong(imm);
return host_reg;
}
@@ -187,10 +187,10 @@ static inline int LOAD_HOST_REG(int host_reg)
{
int new_host_reg = find_host_reg();
host_reg_mapping[new_host_reg] = 0;
addbyte(0x89); /*MOV new_host_reg, host_reg*/
addbyte(0xc0 | (host_reg << 3) | new_host_reg);
return new_host_reg;
}
@@ -366,25 +366,25 @@ static inline void AND_HOST_REG_IMM(int host_reg, uint32_t imm)
static inline int TEST_HOST_REG_B(int dst_reg, int src_reg)
{
AND_HOST_REG_B(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_W(int dst_reg, int src_reg)
{
AND_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_L(int dst_reg, int src_reg)
{
AND_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static inline int TEST_HOST_REG_IMM(int host_reg, uint32_t imm)
{
AND_HOST_REG_IMM(host_reg, imm);
return host_reg;
}
@@ -505,37 +505,37 @@ static inline void DEC_HOST_REG(int host_reg)
static inline int CMP_HOST_REG_B(int dst_reg, int src_reg)
{
SUB_HOST_REG_B(dst_reg, src_reg);
return dst_reg;
}
static inline int CMP_HOST_REG_W(int dst_reg, int src_reg)
{
SUB_HOST_REG_W(dst_reg, src_reg);
return dst_reg;
}
static inline int CMP_HOST_REG_L(int dst_reg, int src_reg)
{
SUB_HOST_REG_L(dst_reg, src_reg);
return dst_reg;
}
static inline int CMP_HOST_REG_IMM_B(int host_reg, uint8_t imm)
{
SUB_HOST_REG_IMM_B(host_reg, imm);
return host_reg;
}
static inline int CMP_HOST_REG_IMM_W(int host_reg, uint16_t imm)
{
SUB_HOST_REG_IMM_W(host_reg, imm);
return host_reg;
}
static inline int CMP_HOST_REG_IMM_L(int host_reg, uint32_t imm)
{
SUB_HOST_REG_IMM(host_reg, imm);
return host_reg;
}
@@ -647,7 +647,7 @@ static inline void CHECK_SEG_READ(x86seg *seg)
addbyte(0x0f);
addbyte(0x84); /*JE BLOCK_GPF_OFFSET*/
addlong(BLOCK_GPF_OFFSET - (block_pos + 4));
seg->checked = 1;
}
static inline void CHECK_SEG_WRITE(x86seg *seg)
@@ -662,7 +662,7 @@ static inline void CHECK_SEG_WRITE(x86seg *seg)
return;
if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
return;
addbyte(0x83); /*CMP seg->base, -1*/
addbyte(0x05|0x38);
addlong((uint32_t)&seg->base);
@@ -736,7 +736,7 @@ static inline int MEM_LOAD_ADDR_EA_B_NO_ABRT(x86seg *seg)
addlong(mem_load_addr_ea_b_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static inline void MEM_LOAD_ADDR_EA_W(x86seg *seg)
@@ -795,7 +795,7 @@ static inline int MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
addlong(mem_load_addr_ea_w_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
static inline void MEM_LOAD_ADDR_EA_L(x86seg *seg)
@@ -834,7 +834,7 @@ static inline int MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
addlong(mem_load_addr_ea_l_no_abrt - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
host_reg_mapping[REG_ECX] = 8;
return REG_ECX;
}
@@ -1053,8 +1053,8 @@ static inline x86seg *FETCH_EA_16(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
{
int mod = (fetchdat >> 6) & 3;
int rm = fetchdat & 7;
if (!mod && rm == 6)
{
if (!mod && rm == 6)
{
addbyte(0xb8); /*MOVL EAX, imm16*/
addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2;
@@ -1121,7 +1121,7 @@ static inline x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
{
uint8_t sib = fetchdat >> 8;
(*op_pc)++;
switch (mod)
{
case 0:
@@ -1139,7 +1139,7 @@ static inline x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
}
break;
case 1:
case 1:
addbyte(0x8b); /*MOVL EAX, regs[sib&7].l*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
@@ -1204,7 +1204,7 @@ static inline x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
else
{
if (!mod && rm == 5)
{
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL EAX, imm32*/
addlong(new_eaaddr);
@@ -1215,22 +1215,22 @@ static inline x86seg *FETCH_EA_32(x86seg *op_ea_seg, uint32_t fetchdat, int op_s
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(regs[rm].l));
cpu_state.eaaddr = cpu_state.regs[rm].l;
if (mod)
if (mod)
{
if (rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (mod == 1)
if (mod == 1)
{
addbyte(0x83); /*ADD EAX, imm8*/
addbyte(0xc0 | REG_EAX);
addbyte((int8_t)(fetchdat >> 8));
(*op_pc)++;
addbyte((int8_t)(fetchdat >> 8));
(*op_pc)++;
}
else
else
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x05); /*ADD EAX, imm32*/
addlong(new_eaaddr);
addlong(new_eaaddr);
(*op_pc) += 4;
}
}
@@ -1475,7 +1475,7 @@ static inline void BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset
else
addbyte(0x77); /*JNBE*/
break;
default:
if (codegen_flags_changed && cpu_state.flags_op != FLAGS_UNKNOWN)
{
@@ -1505,7 +1505,7 @@ static inline void BRANCH_COND_BE(int pc_offset, uint32_t op_pc, uint32_t offset
addbyte(0x74); /*JZ +*/
break;
}
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(7+5+(timing_bt ? 4 : 0));
addbyte(0xC7); /*MOVL [pc], new_pc*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(pc));
@@ -1706,7 +1706,7 @@ static inline void FP_ENTER()
{
if (codegen_fpu_entered)
return;
addbyte(0xf6); /*TEST cr0, 0xc*/
addbyte(0x05);
addlong((uintptr_t)&cr0);
@@ -1725,7 +1725,7 @@ static inline void FP_ENTER()
addlong((uint32_t)x86_int - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
codegen_fpu_entered = 1;
}
@@ -1788,7 +1788,7 @@ static inline void FP_FLD(int reg)
addbyte(0x83); /*SUB EBX, 1*/
addbyte(0xeb);
addbyte(0x01);
}
}
addbyte(0xdd); /*FLD [ST+EAX*8]*/
addbyte(0x44);
@@ -2425,7 +2425,7 @@ static inline int FP_LOAD_REG(int reg)
addbyte(0x8b); /*MOV EAX, [ESP]*/
addbyte(0x04 | (REG_EBX << 3));
addbyte(0x24);
return REG_EBX;
}
@@ -2466,7 +2466,7 @@ static inline void FP_LOAD_REG_D(int reg, int *host_reg1, int *host_reg2)
addbyte(0x44 | (REG_ECX << 3));
addbyte(0x24);
addbyte(0x04);
*host_reg1 = REG_EBX;
*host_reg2 = REG_ECX;
}
@@ -2489,7 +2489,7 @@ static inline int FP_LOAD_REG_INT_W(int reg)
addbyte(0x44);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(ST));
addbyte(0xd9); /*FLDCW cpu_state.new_npxc*/
addbyte(0x6d);
addbyte((uint8_t)cpu_state_offset(new_npxc));
@@ -2566,10 +2566,10 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(MM));
return;
}
addbyte(0xf6); /*TEST TAG[EBX], TAG_UINT64*/
addbyte(0x44);
addbyte(0x1d);
@@ -2586,10 +2586,10 @@ static inline void FP_LOAD_REG_INT_Q(int reg, int *host_reg1, int *host_reg2)
addbyte(0x5c);
addbyte(0xdd);
addbyte((uint8_t)cpu_state_offset(MM));
addbyte(0xeb); /*JMP done*/
addbyte(4+3+3+3+3+4);
addbyte(0xdd); /*FLD ST[EBX*8]*/
addbyte(0x44);
addbyte(0xdd);
@@ -2816,7 +2816,7 @@ static inline void FP_OP_D(int op)
addbyte(0x6d);
addbyte((uint8_t)cpu_state_offset(old_npxc));
}
}
}
}
static inline void FP_OP_IW(int op)
{
@@ -3576,7 +3576,7 @@ static inline void MMX_ENTER()
{
if (codegen_mmx_entered)
return;
addbyte(0xf6); /*TEST cr0, 0xc*/
addbyte(0x05);
addlong((uintptr_t)&cr0);
@@ -3595,7 +3595,7 @@ static inline void MMX_ENTER()
addlong((uint32_t)x86_int - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
addbyte(0xe9); /*JMP end*/
addlong(BLOCK_EXIT_OFFSET - (block_pos + 4));
addbyte(0x31); /*XOR EAX, EAX*/
addbyte(0xc0);
addbyte(0xc6); /*MOV ISMMX, 1*/
@@ -3605,7 +3605,7 @@ static inline void MMX_ENTER()
addbyte(0x89); /*MOV TOP, EAX*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(TOP));
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x89); /*MOV tag, EAX*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(tag[0]));
addbyte(0x89); /*MOV tag+4, EAX*/
@@ -3625,7 +3625,7 @@ static inline int LOAD_MMX_D(int guest_reg)
addbyte(0x8b); /*MOV EBX, reg*/
addbyte(0x45 | (host_reg << 3));
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].l[0]));
return host_reg;
}
static inline void LOAD_MMX_Q(int guest_reg, int *host_reg1, int *host_reg2)
@@ -3659,7 +3659,7 @@ static inline int LOAD_MMX_Q_MMX(int guest_reg)
addbyte(0x7e);
addbyte(0x45 | (dst_reg << 3));
addbyte((uint8_t)cpu_state_offset(MM[guest_reg].q));
return dst_reg;
}
@@ -3667,7 +3667,7 @@ static inline int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
{
int dst_reg = find_host_xmm_reg();
host_reg_xmm_mapping[dst_reg] = 100;
addbyte(0x66); /*MOVD dst_reg, src_reg1*/
addbyte(0x0f);
addbyte(0x6e);
@@ -3680,7 +3680,7 @@ static inline int LOAD_INT_TO_MMX(int src_reg1, int src_reg2)
addbyte(0x0f);
addbyte(0x62);
addbyte(0xc0 | 7 | (dst_reg << 3));
return dst_reg;
}

6
src/codegen/codegen_ops_xchg.h
View File

@@ -54,7 +54,7 @@ static uint32_t ropXCHG_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
temp_reg = COPY_REG(src_reg);
STORE_REG_TARGET_B_RELEASE(dst_reg, (fetchdat >> 3) & 7);
STORE_REG_TARGET_B_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
}
static uint32_t ropXCHG_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -69,7 +69,7 @@ static uint32_t ropXCHG_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
temp_reg = COPY_REG(src_reg);
STORE_REG_TARGET_W_RELEASE(dst_reg, (fetchdat >> 3) & 7);
STORE_REG_TARGET_W_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
}
static uint32_t ropXCHG_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
@@ -84,6 +84,6 @@ static uint32_t ropXCHG_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
temp_reg = COPY_REG(src_reg);
STORE_REG_TARGET_L_RELEASE(dst_reg, (fetchdat >> 3) & 7);
STORE_REG_TARGET_L_RELEASE(temp_reg, fetchdat & 7);
return op_pc + 1;
}

82
src/codegen/codegen_x86-64.c
View File

@@ -63,7 +63,7 @@ static int last_ssegs;
void codegen_init()
{
int c;
#if _WIN64
codeblock = VirtualAlloc(NULL, BLOCK_SIZE * sizeof(codeblock_t), MEM_COMMIT, PAGE_EXECUTE_READWRITE);
#elif defined(__unix__) || defined(__APPLE__)
@@ -83,7 +83,7 @@ void codegen_init()
void codegen_reset()
{
int c;
memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
mem_reset_page_blocks();
@@ -120,7 +120,7 @@ static void add_to_block_list(codeblock_t *block)
if (block->next->valid == 0)
fatal("block->next->valid=0 %p %p %x %x\n", (void *)block->next, (void *)codeblock, block_current, block_pos);
}
if (block->page_mask2)
{
block_prev = pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3];
@@ -212,7 +212,7 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
}
block = page->block_2[(phys_addr >> 10) & 3];
while (block)
{
if (mask & block->page_mask2)
@@ -229,7 +229,7 @@ void codegen_block_init(uint32_t phys_addr)
{
codeblock_t *block;
page_t *page = &pages[phys_addr >> 12];
if (!page->block[(phys_addr >> 10) & 3])
mem_flush_write_page(phys_addr, cs+cpu_state.pc);
@@ -256,18 +256,18 @@ void codegen_block_init(uint32_t phys_addr)
block->page_mask = 0;
block->flags = 0;
block->status = cpu_cur_status;
block->was_recompiled = 0;
recomp_page = block->phys & ~0xfff;
codeblock_tree_add(block);
}
void codegen_block_start_recompile(codeblock_t *block)
{
page_t *page = &pages[block->phys >> 12];
if (!page->block[(block->phys >> 10) & 3])
mem_flush_write_page(block->phys, cs+cpu_state.pc);
@@ -278,7 +278,7 @@ void codegen_block_start_recompile(codeblock_t *block)
fatal("Recompile to used block!\n");
block->status = cpu_cur_status;
block_pos = BLOCK_GPF_OFFSET;
#ifdef OLD_GPF
#if _WIN64
@@ -351,22 +351,22 @@ void codegen_block_start_recompile(codeblock_t *block)
last_op32 = -1;
last_ea_seg = NULL;
last_ssegs = -1;
codegen_block_cycles = 0;
codegen_timing_block_start();
codegen_block_ins = 0;
codegen_block_full_ins = 0;
recomp_page = block->phys & ~0xfff;
codegen_flags_changed = 0;
codegen_fpu_entered = 0;
codegen_mmx_entered = 0;
codegen_fpu_loaded_iq[0] = codegen_fpu_loaded_iq[1] = codegen_fpu_loaded_iq[2] = codegen_fpu_loaded_iq[3] =
codegen_fpu_loaded_iq[4] = codegen_fpu_loaded_iq[5] = codegen_fpu_loaded_iq[6] = codegen_fpu_loaded_iq[7] = 0;
cpu_state.seg_ds.checked = cpu_state.seg_es.checked = cpu_state.seg_fs.checked = cpu_state.seg_gs.checked = (cr0 & 1) ? 0 : 1;
codegen_reg_loaded[0] = codegen_reg_loaded[1] = codegen_reg_loaded[2] = codegen_reg_loaded[3] =
@@ -426,7 +426,7 @@ void codegen_block_generate_end_mask()
for (; start_pc <= end_pc; start_pc++)
block->page_mask2 |= ((uint64_t)1 << start_pc);
page_2->code_present_mask[(block->phys_2 >> 10) & 3] |= block->page_mask2;
if (!pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3])
mem_flush_write_page(block->phys_2, block->endpc);
@@ -437,7 +437,7 @@ void codegen_block_generate_end_mask()
if (block->next_2->valid == 0)
fatal("block->next_2->valid=0 %p\n", (void *)block->next_2);
}
block->dirty_mask2 = &page_2->dirty_mask[(block->phys_2 >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK];
}
}
@@ -477,7 +477,7 @@ void codegen_block_end_recompile(codeblock_t *block)
addbyte(0x5d); /*POP RBP*/
addbyte(0x5b); /*POP RDX*/
addbyte(0xC3); /*RET*/
if (block_pos > BLOCK_GPF_OFFSET)
fatal("Over limit!\n");
@@ -537,15 +537,15 @@ int opcode_0f_modrm[256] =
0, 1, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*e0*/
0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0 /*f0*/
};
void codegen_debug()
{
}
static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
{
if (!cpu_mod && cpu_rm == 6)
{
if (!cpu_mod && cpu_rm == 6)
{
addbyte(0xC7); /*MOVL $0,(ssegs)*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(eaaddr));
@@ -555,7 +555,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
else
{
int base_reg = 0, index_reg = 0;
switch (cpu_rm)
{
case 0: case 1: case 7:
@@ -580,7 +580,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
}
base_reg &= 7;
index_reg &= 7;
switch (cpu_mod)
{
case 0:
@@ -649,7 +649,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
}
(*op_pc) += 2;
break;
}
if (cpu_mod || !(cpu_rm & 4))
{
@@ -738,7 +738,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
}
}
else
{
{
switch (cpu_mod)
{
case 0:
@@ -820,7 +820,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
int base_reg;
if (!cpu_mod && cpu_rm == 5)
{
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
addbyte(0x45);
@@ -830,20 +830,20 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
return op_ea_seg;
}
base_reg = LOAD_REG_L(cpu_rm) & 7;
if (cpu_mod)
if (cpu_mod)
{
if (cpu_rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (cpu_mod == 1)
if (cpu_mod == 1)
{
addbyte(0x67); /*LEA EAX, base_reg+imm8*/
addbyte(0x41);
addbyte(0x8d);
addbyte(0x40 | base_reg);
addbyte((fetchdat >> 8) & 0xff);
(*op_pc)++;
(*op_pc)++;
}
else
else
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x67); /*LEA EAX, base_reg+imm32*/
@@ -881,16 +881,16 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
int pc_off = 0;
int test_modrm = 1;
int c;
op_ea_seg = &cpu_state.seg_ds;
op_ssegs = 0;
op_old_pc = old_pc;
for (c = 0; c < NR_HOST_REGS; c++)
host_reg_mapping[c] = -1;
for (c = 0; c < NR_HOST_XMM_REGS; c++)
host_reg_xmm_mapping[c] = -1;
codegen_timing_start();
while (!over)
@@ -902,7 +902,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
recomp_op_table = recomp_opcodes_0f;
over = 1;
break;
case 0x26: /*ES:*/
op_ea_seg = &cpu_state.seg_es;
op_ssegs = 1;
@@ -927,14 +927,14 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
op_ea_seg = &cpu_state.seg_gs;
op_ssegs = 1;
break;
case 0x66: /*Data size select*/
op_32 = ((use32 & 0x100) ^ 0x100) | (op_32 & 0x200);
break;
case 0x67: /*Address size select*/
op_32 = ((use32 & 0x200) ^ 0x200) | (op_32 & 0x100);
break;
case 0xd8:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d8_a32 : x86_dynarec_opcodes_d8_a16;
recomp_op_table = recomp_opcodes_d8;
@@ -1009,7 +1009,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xf0: /*LOCK*/
break;
@@ -1034,13 +1034,13 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
fetchdat >>= 8;
op_pc++;
}
generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
codegen_accumulate(ACCREG_cycles, -codegen_block_cycles);
codegen_block_cycles = 0;
if ((op_table == x86_dynarec_opcodes &&
((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
(opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 ||
@@ -1112,7 +1112,7 @@ generate_call:
(op_table == x86_dynarec_opcodes_0f && opcode_0f_modrm[opcode]))/* && !(op_32 & 0x200)*/)
{
int stack_offset = 0;
if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
stack_offset = (op_32 & 0x100) ? 4 : 2;
@@ -1160,10 +1160,10 @@ generate_call:
}
load_param_1_32(block, fetchdat);
call(block, (uintptr_t)op);
call(block, (uintptr_t)op);
codegen_block_ins++;
block->ins++;
#ifdef CHECK_INT

134
src/codegen/codegen_x86.c
View File

@@ -167,7 +167,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B()
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
@@ -223,7 +223,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W()
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
@@ -275,14 +275,14 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L()
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t gen_MEM_LOAD_ADDR_EA_Q()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x89); /*MOV ESI, EDX*/
addbyte(0xd6);
addbyte(0x01); /*ADDL EDX, EAX*/
@@ -331,14 +331,14 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_Q()
addbyte(0x85);
addlong(mem_abrt_rout - ((uint32_t)(&codeblock[block_current].data[block_pos]) + 4));
addbyte(0xc3); /*RET*/
return addr;
}
static uint32_t gen_MEM_STORE_ADDR_EA_B()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -387,7 +387,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B()
static uint32_t gen_MEM_STORE_ADDR_EA_W()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -442,7 +442,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W()
static uint32_t gen_MEM_STORE_ADDR_EA_L()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -496,7 +496,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L()
static uint32_t gen_MEM_STORE_ADDR_EA_Q()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = EBX/ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EDX, ESI*/
addbyte(0xf2);
@@ -605,7 +605,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
addbyte(1);
#endif
addbyte(0xc3); /*RET*/
#ifndef RELEASE_BUILD
#ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
@@ -613,7 +613,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
#endif
#endif
return addr;
}
@@ -752,7 +752,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
#endif
#endif
return addr;
}
@@ -762,7 +762,7 @@ static char gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_B_NO_
static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -805,7 +805,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
addbyte(1);
#endif
addbyte(0xc3); /*RET*/
#ifndef RELEASE_BUILD
#ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
@@ -823,7 +823,7 @@ static char gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_W_NO_
static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -890,7 +890,7 @@ static char gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_L_NO_
static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*dat = ECX, seg = ESI, addr = EAX*/
addbyte(0x89); /*MOV EBX, ESI*/
addbyte(0xf3);
@@ -953,9 +953,9 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
static uint32_t gen_MEM_CHECK_WRITE()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
@@ -982,7 +982,7 @@ static uint32_t gen_MEM_CHECK_WRITE()
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
@@ -1010,9 +1010,9 @@ static uint32_t gen_MEM_CHECK_WRITE()
static uint32_t gen_MEM_CHECK_WRITE_W()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
@@ -1054,7 +1054,7 @@ static uint32_t gen_MEM_CHECK_WRITE_W()
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x89); /*MOV EDI, EAX*/
addbyte(0xc7);
@@ -1092,9 +1092,9 @@ static uint32_t gen_MEM_CHECK_WRITE_W()
static uint32_t gen_MEM_CHECK_WRITE_L()
{
uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
/*seg = ESI, addr = EAX*/
addbyte(0x8d); /*LEA EDI, [EAX+ESI]*/
addbyte(0x3c);
addbyte(0x30);
@@ -1136,7 +1136,7 @@ static uint32_t gen_MEM_CHECK_WRITE_L()
addbyte(0x74); /*JE +*/
addbyte(1);
addbyte(0xc3); /*RET*/
/*slowpath:*/
addbyte(0x89); /*MOV EDI, EAX*/
addbyte(0xc7);
@@ -1187,7 +1187,7 @@ void codegen_init()
block_current = BLOCK_SIZE;
block_pos = 0;
mem_abrt_rout = (uint32_t)&codeblock[block_current].data[block_pos];
mem_abrt_rout = (uint32_t)&codeblock[block_current].data[block_pos];
addbyte(0x83); /*ADDL $16+4,%esp*/
addbyte(0xC4);
addbyte(0x10+4);
@@ -1230,7 +1230,7 @@ void codegen_init()
mem_check_write_w = (uint32_t)gen_MEM_CHECK_WRITE_W();
block_pos = (block_pos + 15) & ~15;
mem_check_write_l = (uint32_t)gen_MEM_CHECK_WRITE_L();
#ifndef _MSC_VER
asm(
"fstcw %0\n"
@@ -1279,7 +1279,7 @@ static void add_to_block_list(codeblock_t *block)
if (!block->next->valid)
fatal("block->next->valid=0 %p %p %x %x\n", (void *)block->next, (void *)codeblock, block_current, block_pos);
}
if (block->page_mask2)
{
block_prev = pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3];
@@ -1371,7 +1371,7 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
}
block = page->block_2[(phys_addr >> 10) & 3];
while (block)
{
if (mask & block->page_mask2)
@@ -1388,7 +1388,7 @@ void codegen_block_init(uint32_t phys_addr)
{
codeblock_t *block;
page_t *page = &pages[phys_addr >> 12];
if (!page->block[(phys_addr >> 10) & 3])
mem_flush_write_page(phys_addr, cs+cpu_state.pc);
@@ -1415,18 +1415,18 @@ void codegen_block_init(uint32_t phys_addr)
block->page_mask = 0;
block->flags = CODEBLOCK_STATIC_TOP;
block->status = cpu_cur_status;
block->was_recompiled = 0;
recomp_page = block->phys & ~0xfff;
codeblock_tree_add(block);
}
void codegen_block_start_recompile(codeblock_t *block)
{
page_t *page = &pages[block->phys >> 12];
if (!page->block[(block->phys >> 10) & 3])
mem_flush_write_page(block->phys, cs+cpu_state.pc);
@@ -1485,29 +1485,29 @@ void codegen_block_start_recompile(codeblock_t *block)
last_op32 = -1;
last_ea_seg = NULL;
last_ssegs = -1;
codegen_block_cycles = 0;
codegen_timing_block_start();
codegen_block_ins = 0;
codegen_block_full_ins = 0;
recomp_page = block->phys & ~0xfff;
codegen_flags_changed = 0;
codegen_fpu_entered = 0;
codegen_mmx_entered = 0;
codegen_fpu_loaded_iq[0] = codegen_fpu_loaded_iq[1] = codegen_fpu_loaded_iq[2] = codegen_fpu_loaded_iq[3] =
codegen_fpu_loaded_iq[4] = codegen_fpu_loaded_iq[5] = codegen_fpu_loaded_iq[6] = codegen_fpu_loaded_iq[7] = 0;
cpu_state.seg_ds.checked = cpu_state.seg_es.checked = cpu_state.seg_fs.checked = cpu_state.seg_gs.checked = (cr0 & 1) ? 0 : 1;
block->TOP = cpu_state.TOP & 7;
block->was_recompiled = 1;
codegen_flat_ds = !(cpu_cur_status & CPU_STATUS_NOTFLATDS);
codegen_flat_ss = !(cpu_cur_status & CPU_STATUS_NOTFLATSS);
codegen_flat_ss = !(cpu_cur_status & CPU_STATUS_NOTFLATSS);
codegen_accumulate_reset();
}
@@ -1539,12 +1539,12 @@ void codegen_block_generate_end_mask()
end_pc = 0x3ff;
start_pc >>= PAGE_MASK_SHIFT;
end_pc >>= PAGE_MASK_SHIFT;
for (; start_pc <= end_pc; start_pc++)
{
{
block->page_mask |= ((uint64_t)1 << start_pc);
}
pages[block->phys >> 12].code_present_mask[(block->phys >> 10) & 3] |= block->page_mask;
block->phys_2 = -1;
@@ -1562,7 +1562,7 @@ void codegen_block_generate_end_mask()
for (; start_pc <= end_pc; start_pc++)
block->page_mask2 |= ((uint64_t)1 << start_pc);
page_2->code_present_mask[(block->phys_2 >> 10) & 3] |= block->page_mask2;
if (!pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3])
mem_flush_write_page(block->phys_2, block->endpc);
@@ -1604,7 +1604,7 @@ void codegen_block_end_recompile(codeblock_t *block)
addbyte(0x5d); /*POP EBP*/
addbyte(0x5b); /*POP EDX*/
addbyte(0xC3); /*RET*/
if (block_pos > BLOCK_GPF_OFFSET)
fatal("Over limit!\n");
@@ -1674,8 +1674,8 @@ void codegen_debug()
static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
{
if (!cpu_mod && cpu_rm == 6)
{
if (!cpu_mod && cpu_rm == 6)
{
addbyte(0xC7); /*MOVL $0,(ssegs)*/
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(eaaddr));
@@ -1735,7 +1735,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
{
uint8_t sib = fetchdat >> 8;
(*op_pc)++;
switch (cpu_mod)
{
case 0:
@@ -1753,7 +1753,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
}
break;
case 1:
case 1:
new_eaaddr = (uint32_t)(int8_t)((fetchdat >> 16) & 0xff);
addbyte(0xb8); /*MOVL new_eaaddr, %eax*/
addlong(new_eaaddr);
@@ -1811,7 +1811,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
else
{
if (!cpu_mod && cpu_rm == 5)
{
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
addbyte(0x45);
@@ -1824,21 +1824,21 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addbyte(0x45);
addbyte((uint8_t)cpu_state_offset(regs[cpu_rm].l));
cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
if (cpu_mod)
if (cpu_mod)
{
if (cpu_rm == 5 && !op_ssegs)
op_ea_seg = &cpu_state.seg_ss;
if (cpu_mod == 1)
if (cpu_mod == 1)
{
addbyte(0x05);
addlong((uint32_t)(int8_t)(fetchdat >> 8));
(*op_pc)++;
addlong((uint32_t)(int8_t)(fetchdat >> 8));
(*op_pc)++;
}
else
else
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0x05);
addlong(new_eaaddr);
addlong(new_eaaddr);
(*op_pc) += 4;
}
}
@@ -1865,13 +1865,13 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
op_ea_seg = &cpu_state.seg_ds;
op_ssegs = 0;
op_old_pc = old_pc;
for (c = 0; c < NR_HOST_REGS; c++)
host_reg_mapping[c] = -1;
mmx_ebx_ecx_loaded = 0;
for (c = 0; c < NR_HOST_XMM_REGS; c++)
host_reg_xmm_mapping[c] = -1;
codegen_timing_start();
while (!over)
@@ -1883,7 +1883,7 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
recomp_op_table = recomp_opcodes_0f;
over = 1;
break;
case 0x26: /*ES:*/
op_ea_seg = &cpu_state.seg_es;
op_ssegs = 1;
@@ -1908,14 +1908,14 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
op_ea_seg = &cpu_state.seg_gs;
op_ssegs = 1;
break;
case 0x66: /*Data size select*/
op_32 = ((use32 & 0x100) ^ 0x100) | (op_32 & 0x200);
break;
case 0x67: /*Address size select*/
op_32 = ((use32 & 0x200) ^ 0x200) | (op_32 & 0x100);
break;
case 0xd8:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d8_a32 : x86_dynarec_opcodes_d8_a16;
recomp_op_table = recomp_opcodes_d8;
@@ -1990,10 +1990,10 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
test_modrm = 0;
block->flags |= CODEBLOCK_HAS_FPU;
break;
case 0xf0: /*LOCK*/
break;
case 0xf2: /*REPNE*/
op_table = x86_dynarec_opcodes_REPNE;
recomp_op_table = recomp_opcodes_REPNE;
@@ -2013,10 +2013,10 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
opcode = fetchdat & 0xff;
if (!pc_off)
fetchdat >>= 8;
op_pc++;
}
generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
@@ -2078,7 +2078,7 @@ generate_call:
return;
}
}
op = op_table[((opcode >> opcode_shift) | op_32) & opcode_mask];
if (op_ssegs != last_ssegs)
{
@@ -2095,7 +2095,7 @@ generate_call:
(op_table == x86_dynarec_opcodes_0f && opcode_0f_modrm[opcode]))
{
int stack_offset = 0;
if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
stack_offset = (op_32 & 0x100) ? 4 : 2;
@@ -2150,12 +2150,12 @@ generate_call:
addbyte(0x04);
addbyte(0x24);
addlong(fetchdat);
addbyte(0xE8); /*CALL*/
addlong(((uint8_t *)op - (uint8_t *)(&block->data[block_pos + 4])));
codegen_block_ins++;
block->ins++;
#ifdef CHECK_INT

2
src/codegen_new/CMakeLists.txt
View File

@@ -48,4 +48,4 @@ if(DYNAREC)
endif()
target_link_libraries(86Box dynarec cgt)
endif()
endif()

18
src/codegen_new/codegen.c
View File

@@ -31,7 +31,7 @@ static struct
int codegen_get_instruction_uop(codeblock_t *block, uint32_t pc, int *first_instruction, int *TOP)
{
int c;
for (c = 0; c <= block->ins; c++)
{
if (codegen_instructions[c].pc == pc)
@@ -41,7 +41,7 @@ int codegen_get_instruction_uop(codeblock_t *block, uint32_t pc, int *first_inst
return codegen_instructions[c].first_uop;
}
}
*first_instruction = block->ins;
return -1;
}
@@ -185,7 +185,7 @@ static x86seg *codegen_generate_ea_16_long(ir_data_t *ir, x86seg *op_ea_seg, uin
op_ea_seg = &cpu_state.seg_ss;
}
}
codegen_mark_code_present(ir->block, cs+old_pc, ((*op_pc)+1)-old_pc);
return op_ea_seg;
}
@@ -290,7 +290,7 @@ static x86seg *codegen_generate_ea_32_long(ir_data_t *ir, x86seg *op_ea_seg, uin
uop_MOV_IMM(ir, IREG_eaaddr, new_eaaddr);
extra_bytes = 4;
}
(*op_pc) += 4;
}
else
@@ -327,7 +327,7 @@ static x86seg *codegen_generate_ea_32_long(ir_data_t *ir, x86seg *op_ea_seg, uin
if (extra_bytes)
codegen_mark_code_present(ir->block, cs+old_pc, extra_bytes);
return op_ea_seg;
}
@@ -617,7 +617,7 @@ generate_call:
if (codegen_timing_jump_cycles)
codegen_timing_jump_cycles();
if (jump_cycles)
codegen_accumulate(ir, ACCREG_cycles, -jump_cycles);
codegen_accumulate_flush(ir);
@@ -673,7 +673,7 @@ generate_call:
if (recomp_opcodes_3DNOW[opcode_3dnow])
{
next_pc = opcode_pc + 1;
op_table = (OpFn *) x86_dynarec_opcodes_3DNOW;
recomp_op_table = recomp_opcodes_3DNOW;
opcode = opcode_3dnow;
@@ -765,14 +765,14 @@ generate_call:
last_op_ea_seg = op_ea_seg;
last_op_ssegs = op_ssegs;
//codegen_block_ins++;
block->ins++;
if (block->ins >= MAX_INSTRUCTION_COUNT)
CPU_BLOCK_END();
codegen_endpc = (cs + cpu_state.pc) + 8;
// if (has_ea)
// fatal("Has EA\n");
}

32
src/codegen_new/codegen.h
View File

@@ -13,18 +13,18 @@
added to the page_lookup for this purpose. When in the page_lookup, each write
will go through the mem_write_ram*_page() functions and set the dirty mask
appropriately.
Each codeblock also contains a code mask (actually two masks, one for each
page the block is/may be in), again with each bit representing 64 bytes.
Each page has a list of codeblocks present in it. As each codeblock can span
up to two pages, two lists are present.
When a codeblock is about to be executed, the code masks are compared with the
dirty masks for the relevant pages. If either intersect, then
codegen_check_flush() is called on the affected page(s), and all affected
blocks are evicted.
The 64 byte granularity appears to work reasonably well for most cases,
avoiding most unnecessary evictions (eg when code & data are stored in the
same page).
@@ -45,7 +45,7 @@ typedef struct codeblock_t
uint16_t parent, left, right;
uint8_t *data;
uint64_t page_mask, page_mask2;
uint64_t *dirty_mask, *dirty_mask2;
@@ -96,10 +96,10 @@ static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
{
codeblock_t *block;
uint64_t a = _cs | ((uint64_t)phys << 32);
if (!pages[phys >> 12].head)
return NULL;
block = &codeblock[pages[phys >> 12].head];
while (block)
{
@@ -115,7 +115,7 @@ static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
else
block = block->right ? &codeblock[block->right] : NULL;
}
return block;
}
@@ -133,23 +133,23 @@ static inline void codeblock_tree_add(codeblock_t *new_block)
{
codeblock_t *old_block = NULL;
uint64_t old_block_cmp = 0;
while (block)
{
old_block = block;
old_block_cmp = old_block->_cs | ((uint64_t)old_block->phys << 32);
if (a < old_block_cmp)
block = block->left ? &codeblock[block->left] : NULL;
else
block = block->right ? &codeblock[block->right] : NULL;
}
if (a < old_block_cmp)
old_block->left = get_block_nr(new_block);
else
old_block->right = get_block_nr(new_block);
new_block->parent = get_block_nr(old_block);
new_block->left = new_block->right = BLOCK_INVALID;
}
@@ -173,7 +173,7 @@ static inline void codeblock_tree_delete(codeblock_t *block)
else
{
uint16_t block_nr = get_block_nr(block);
if (parent->left == block_nr)
parent->left = BLOCK_INVALID;
if (parent->right == block_nr)
@@ -237,11 +237,11 @@ static inline void codeblock_tree_delete(codeblock_t *block)
codeblock_t *lowest = &codeblock[block->right], *highest;
codeblock_t *old_parent;
uint16_t lowest_nr;
while (lowest->left)
lowest = &codeblock[lowest->left];
lowest_nr = get_block_nr(lowest);
old_parent = &codeblock[lowest->parent];
/*Replace deleted node with lowest node*/
@@ -263,7 +263,7 @@ static inline void codeblock_tree_delete(codeblock_t *block)
codeblock[lowest->left].parent = lowest_nr;
old_parent->left = BLOCK_INVALID;
highest = &codeblock[lowest->right];
if (!lowest->right)
{

2
src/codegen_new/codegen_accumulate.h
View File

@@ -1,7 +1,7 @@
enum
{
ACCREG_cycles = 0,
ACCREG_COUNT
};

10
src/codegen_new/codegen_allocator.c
View File

@@ -60,13 +60,13 @@ mem_block_t *codegen_allocator_allocate(mem_block_t *parent, int code_block)
{
mem_block_t *block;
uint32_t block_nr;
while (!mem_block_free_list)
{
/*Pick a random memory block and free the owning code block*/
block_nr = rand() & MEM_BLOCK_MASK;
block = &mem_blocks[block_nr];
if (block->code_block && block->code_block != code_block)
codegen_delete_block(&codeblock[block->code_block]);
}
@@ -75,7 +75,7 @@ mem_block_t *codegen_allocator_allocate(mem_block_t *parent, int code_block)
block_nr = mem_block_free_list;
block = &mem_blocks[block_nr-1];
mem_block_free_list = block->next;
block->code_block = code_block;
if (parent)
{
@@ -97,12 +97,12 @@ void codegen_allocator_free(mem_block_t *block)
{
int next_block_nr = block->next;
codegen_allocator_usage--;
block->next = mem_block_free_list;
block->code_block = BLOCK_INVALID;
mem_block_free_list = block_nr;
block_nr = next_block_nr;
if (block_nr)
block = &mem_blocks[block_nr - 1];
else

4
src/codegen_new/codegen_allocator.h
View File

@@ -4,12 +4,12 @@
/*The allocator handles all allocation of executable memory. Since the two-pass
recompiler design makes applying hard limits to codeblock size difficult, the
allocator allows memory to be provided as and when required.
The allocator provides a block size of a little under 1 kB (slightly lower to
limit cache aliasing). Each generated codeblock is allocated one block by default,
and will allocate additional block(s) once the existing memory is sorted. Blocks
are chained together by jump instructions.
Due to the chaining, the total memory size is limited by the range of a jump
instruction. ARMv7 is restricted to +/- 32 MB, ARMv8 to +/- 128 MB, x86 to
+/- 2GB. As a result, total memory size is limited to 32 MB on ARMv7*/

2
src/codegen_new/codegen_backend_arm.c
View File

@@ -283,7 +283,7 @@ static void build_fp_round_routine(codeblock_t *block)
host_arm_VCVTR_IS_D(block, REG_D_TEMP, REG_D_TEMP);
host_arm_VMSR_FPSCR(block, REG_TEMP);
host_arm_MOV_REG(block, REG_PC, REG_LR);
jump_table[X87_ROUNDING_CHOP] = (uint64_t)(uintptr_t)&block_write_data[block_pos]; //zero
host_arm_VCVT_IS_D(block, REG_D_TEMP, REG_D_TEMP);
host_arm_MOV_REG(block, REG_PC, REG_LR);

2
src/codegen_new/codegen_backend_arm.h
View File

@@ -21,4 +21,4 @@ void host_arm_SUB_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm
void host_arm_call(codeblock_t *block, void *dst_addr);
void host_arm_nop(codeblock_t *block);
void codegen_alloc(codeblock_t *block, int size);
void codegen_alloc(codeblock_t *block, int size);

2
src/codegen_new/codegen_backend_arm64.c
View File

@@ -270,7 +270,7 @@ static void build_fp_round_routine(codeblock_t *block, int is_quad)
else
host_arm64_FCVTMS_W_D(block, REG_TEMP, REG_V_TEMP);
host_arm64_RET(block, REG_X30);
jump_table[X87_ROUNDING_CHOP] = (uint64_t)(uintptr_t)&block_write_data[block_pos]; //zero
if (is_quad)
host_arm64_FCVTZS_X_D(block, REG_TEMP, REG_V_TEMP);

2
src/codegen_new/codegen_backend_arm64.h
View File

@@ -28,4 +28,4 @@ void host_arm64_STRB_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int o
void host_arm64_call(codeblock_t *block, void *dst_addr);
void host_arm64_mov_imm(codeblock_t *block, int reg, uint32_t imm_data);
uint32_t host_arm64_find_imm(uint32_t data);
uint32_t host_arm64_find_imm(uint32_t data);

2
src/codegen_new/codegen_backend_arm64_defs.h
View File

@@ -132,4 +132,4 @@ extern void *codegen_fp_round;
extern void *codegen_fp_round_quad;
extern void *codegen_gpf_rout;
extern void *codegen_exit_rout;
extern void *codegen_exit_rout;

2
src/codegen_new/codegen_backend_arm64_ops.h
View File

@@ -261,4 +261,4 @@ void host_arm64_mov_imm(codeblock_t *block, int reg, uint32_t imm_data);
void codegen_direct_read_8(codeblock_t *block, int host_reg, void *p);
void codegen_alloc(codeblock_t *block, int size);
void codegen_alloc(codeblock_t *block, int size);

2
src/codegen_new/codegen_backend_arm64_uops.c
View File

@@ -1410,7 +1410,7 @@ static int codegen_MOV_INT_DOUBLE_64(codeblock_t *block, uop_t *uop)
host_arm64_FMOV_D_D(block, REG_V_TEMP, src_reg);
host_arm64_call(block, codegen_fp_round_quad);
host_arm64_FMOV_D_Q(block, dest_reg, REG_TEMP);
host_arm64_branch_set_offset(branch_offset, &block_write_data[block_pos]);
}
else

8
src/codegen_new/codegen_backend_arm_uops.c
View File

@@ -416,7 +416,7 @@ static int codegen_CMP_JNBE(codeblock_t *block, uop_t *uop)
jump_p = host_arm_BHI_(block);
*jump_p |= ((((uintptr_t)uop->p - (uintptr_t)jump_p) - 8) & 0x3fffffc) >> 2;
return 0;
}
@@ -1488,7 +1488,7 @@ static int codegen_MOV_INT_DOUBLE(codeblock_t *block, uop_t *uop)
static int64_t x87_fround64(double b)
{
int64_t a, c;
switch ((cpu_state.npxc >> 10) & 3)
{
case 0: /*Nearest*/
@@ -1507,7 +1507,7 @@ static int64_t x87_fround64(double b)
case 3: /*Chop*/
return (int64_t)b;
}
return 0;
}
static int codegen_MOV_INT_DOUBLE_64(codeblock_t *block, uop_t *uop)
@@ -1529,7 +1529,7 @@ static int codegen_MOV_INT_DOUBLE_64(codeblock_t *block, uop_t *uop)
host_arm_VMOV_D_D(block, REG_D0, src_reg);
host_arm_call(block, x87_fround64);
host_arm_VMOV_D_64(block, REG_D_TEMP, REG_R0, REG_R1);
*branch_offset |= ((((uintptr_t)&block_write_data[block_pos] - (uintptr_t)branch_offset) - 8) & 0x3fffffc) >> 2;
}
else

10
src/codegen_new/codegen_backend_x86-64_ops.c
View File

@@ -701,7 +701,7 @@ void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
if (dst_reg & 8)
fatal("host_x86_MOV8_REG_ABS reg & 8\n");
@@ -767,7 +767,7 @@ void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
if (dst_reg & 8)
fatal("host_x86_MOV32_REG_ABS reg & 8\n");
@@ -1139,7 +1139,7 @@ void host_x86_MOVZX_REG_ABS_16_8(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
if (dst_reg & 8)
fatal("host_x86_MOVZX_REG_ABS_16_8 - bad reg\n");
@@ -1170,7 +1170,7 @@ void host_x86_MOVZX_REG_ABS_32_8(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
// if (dst_reg & 8)
// fatal("host_x86_MOVZX_REG_ABS_32_8 - bad reg\n");
@@ -1214,7 +1214,7 @@ void host_x86_MOVZX_REG_ABS_32_16(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t)p - (((uintptr_t)&cpu_state) + 128);
int64_t ram_offset = (uintptr_t)p - (uintptr_t)ram;
if (dst_reg & 8)
fatal("host_x86_MOVZX_REG_ABS_32_16 - bad reg\n");

2
src/codegen_new/codegen_backend_x86-64_uops.c
View File

@@ -1449,7 +1449,7 @@ static int codegen_MOV_INT_DOUBLE_64(codeblock_t *block, uop_t *uop)
host_x86_CVTSD2SI_REG64_XREG(block, REG_RCX, src_reg);
host_x86_LDMXCSR(block, &cpu_state.old_fp_control);
host_x86_MOVQ_XREG_REG(block, dest_reg, REG_RCX);
*branch_offset = (uint32_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)branch_offset) - 4;
}
#ifdef RECOMPILER_DEBUG

8
src/codegen_new/codegen_backend_x86.c
View File

@@ -66,7 +66,7 @@ static void build_load_routine(codeblock_t *block, int size, int is_float)
{
uint8_t *branch_offset;
uint8_t *misaligned_offset = NULL;
/*In - ESI = address
Out - ECX = data, ESI = abrt*/
/*MOV ECX, ESI
@@ -111,7 +111,7 @@ static void build_load_routine(codeblock_t *block, int size, int is_float)
fatal("build_load_routine: size=%i\n", size);
host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
host_x86_RET(block);
*branch_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)branch_offset) - 1;
if (size != 1)
*misaligned_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)misaligned_offset) - 1;
@@ -155,7 +155,7 @@ static void build_store_routine(codeblock_t *block, int size, int is_float)
{
uint8_t *branch_offset;
uint8_t *misaligned_offset = NULL;
/*In - ECX = data, ESI = address
Out - ESI = abrt
Corrupts EDI*/
@@ -290,7 +290,7 @@ void codegen_backend_init()
block->data = codeblock_allocator_get_ptr(block->head_mem_block);
block_write_data = block->data;
build_loadstore_routines(block);
codegen_gpf_rout = &codeblock[block_current].data[block_pos];
host_x86_MOV32_STACK_IMM(block, STACK_ARG0, 0);
host_x86_MOV32_STACK_IMM(block, STACK_ARG1, 0);

38
src/codegen_new/codegen_backend_x86_uops.c
View File

@@ -66,7 +66,7 @@ static int codegen_ADD_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size))
{
if (uop->dest_reg_a_real != uop->src_reg_a_real)
@@ -280,7 +280,7 @@ static int codegen_CMP_IMM_JZ_DEST(codeblock_t *block, uop_t *uop)
fatal("CMP_IMM_JZ_DEST %02x\n", uop->src_reg_a_real);
#endif
uop->p = host_x86_JZ_long(block);
return 0;
}
@@ -319,7 +319,7 @@ static int codegen_CMP_JNBE(codeblock_t *block, uop_t *uop)
#endif
jump_p = host_x86_JNBE_long(block);
*jump_p = (uintptr_t)uop->p - ((uintptr_t)jump_p + 4);
return 0;
}
@@ -801,7 +801,7 @@ static int codegen_FSUB(codeblock_t *block, uop_t *uop)
static int codegen_FP_ENTER(codeblock_t *block, uop_t *uop)
{
uint32_t *branch_offset;
host_x86_MOV32_REG_ABS(block, REG_ECX, &cr0);
host_x86_TEST32_REG_IMM(block, REG_ECX, 0xc);
branch_offset = host_x86_JZ_long(block);
@@ -830,7 +830,7 @@ static int codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[4], 0x01010101);
host_x86_MOV32_ABS_IMM(block, &cpu_state.TOP, 0);
host_x86_MOV8_ABS_IMM(block, &cpu_state.ismmx, 1);
return 0;
}
@@ -1047,7 +1047,7 @@ static int codegen_MEM_LOAD_DOUBLE(codeblock_t *block, uop_t *uop)
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
host_x86_MOVQ_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
return 0;
}
@@ -1266,7 +1266,7 @@ static int codegen_MOV_REG_PTR(codeblock_t *block, uop_t *uop)
}
else
fatal("MOV_REG_PTR %02x\n", uop->dest_reg_a_real);
return 0;
}
static int codegen_MOVZX_REG_PTR_8(codeblock_t *block, uop_t *uop)
@@ -2830,7 +2830,7 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_JMP_DEST & UOP_MASK] = codegen_JMP_DEST,
[UOP_LOAD_SEG & UOP_MASK] = codegen_LOAD_SEG,
[UOP_LOAD_FUNC_ARG_0 & UOP_MASK] = codegen_LOAD_FUNC_ARG0,
[UOP_LOAD_FUNC_ARG_1 & UOP_MASK] = codegen_LOAD_FUNC_ARG1,
[UOP_LOAD_FUNC_ARG_2 & UOP_MASK] = codegen_LOAD_FUNC_ARG2,
@@ -2844,12 +2844,12 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_STORE_P_IMM & UOP_MASK] = codegen_STORE_PTR_IMM,
[UOP_STORE_P_IMM_8 & UOP_MASK] = codegen_STORE_PTR_IMM_8,
[UOP_STORE_P_IMM_16 & UOP_MASK] = codegen_STORE_PTR_IMM_16,
[UOP_MEM_LOAD_ABS & UOP_MASK] = codegen_MEM_LOAD_ABS,
[UOP_MEM_LOAD_REG & UOP_MASK] = codegen_MEM_LOAD_REG,
[UOP_MEM_LOAD_SINGLE & UOP_MASK] = codegen_MEM_LOAD_SINGLE,
[UOP_MEM_LOAD_DOUBLE & UOP_MASK] = codegen_MEM_LOAD_DOUBLE,
[UOP_MEM_STORE_ABS & UOP_MASK] = codegen_MEM_STORE_ABS,
[UOP_MEM_STORE_REG & UOP_MASK] = codegen_MEM_STORE_REG,
[UOP_MEM_STORE_IMM_8 & UOP_MASK] = codegen_MEM_STORE_IMM_8,
@@ -2857,7 +2857,7 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_MEM_STORE_IMM_32 & UOP_MASK] = codegen_MEM_STORE_IMM_32,
[UOP_MEM_STORE_SINGLE & UOP_MASK] = codegen_MEM_STORE_SINGLE,
[UOP_MEM_STORE_DOUBLE & UOP_MASK] = codegen_MEM_STORE_DOUBLE,
[UOP_MOV & UOP_MASK] = codegen_MOV,
[UOP_MOV_PTR & UOP_MASK] = codegen_MOV_PTR,
[UOP_MOV_IMM & UOP_MASK] = codegen_MOV_IMM,
@@ -2917,16 +2917,16 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_TEST_JNS_DEST & UOP_MASK] = codegen_TEST_JNS_DEST,
[UOP_TEST_JS_DEST & UOP_MASK] = codegen_TEST_JS_DEST,
[UOP_FP_ENTER & UOP_MASK] = codegen_FP_ENTER,
[UOP_MMX_ENTER & UOP_MASK] = codegen_MMX_ENTER,
[UOP_FADD & UOP_MASK] = codegen_FADD,
[UOP_FDIV & UOP_MASK] = codegen_FDIV,
[UOP_FMUL & UOP_MASK] = codegen_FMUL,
[UOP_FSUB & UOP_MASK] = codegen_FSUB,
[UOP_FCOM & UOP_MASK] = codegen_FCOM,
[UOP_FABS & UOP_MASK] = codegen_FABS,
[UOP_FCHS & UOP_MASK] = codegen_FCHS,
[UOP_FSQRT & UOP_MASK] = codegen_FSQRT,
@@ -2963,11 +2963,11 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_PFRSQRT & UOP_MASK] = codegen_PFRSQRT,
[UOP_PFSUB & UOP_MASK] = codegen_PFSUB,
[UOP_PI2FD & UOP_MASK] = codegen_PI2FD,
[UOP_PMADDWD & UOP_MASK] = codegen_PMADDWD,
[UOP_PMULHW & UOP_MASK] = codegen_PMULHW,
[UOP_PMULLW & UOP_MASK] = codegen_PMULLW,
[UOP_PSLLW_IMM & UOP_MASK] = codegen_PSLLW_IMM,
[UOP_PSLLD_IMM & UOP_MASK] = codegen_PSLLD_IMM,
[UOP_PSLLQ_IMM & UOP_MASK] = codegen_PSLLQ_IMM,
@@ -2977,7 +2977,7 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_PSRLW_IMM & UOP_MASK] = codegen_PSRLW_IMM,
[UOP_PSRLD_IMM & UOP_MASK] = codegen_PSRLD_IMM,
[UOP_PSRLQ_IMM & UOP_MASK] = codegen_PSRLQ_IMM,
[UOP_PSUBB & UOP_MASK] = codegen_PSUBB,
[UOP_PSUBW & UOP_MASK] = codegen_PSUBW,
[UOP_PSUBD & UOP_MASK] = codegen_PSUBD,
@@ -2985,7 +2985,7 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_PSUBSW & UOP_MASK] = codegen_PSUBSW,
[UOP_PSUBUSB & UOP_MASK] = codegen_PSUBUSB,
[UOP_PSUBUSW & UOP_MASK] = codegen_PSUBUSW,
[UOP_PUNPCKHBW & UOP_MASK] = codegen_PUNPCKHBW,
[UOP_PUNPCKHWD & UOP_MASK] = codegen_PUNPCKHWD,
[UOP_PUNPCKHDQ & UOP_MASK] = codegen_PUNPCKHDQ,
@@ -2994,7 +2994,7 @@ const uOpFn uop_handlers[UOP_MAX] =
[UOP_PUNPCKLDQ & UOP_MASK] = codegen_PUNPCKLDQ,
[UOP_NOP_BARRIER & UOP_MASK] = codegen_NOP,
#ifdef DEBUG_EXTRA
[UOP_LOG_INSTR & UOP_MASK] = codegen_LOG_INSTR
#endif

46
src/codegen_new/codegen_block.c
View File

@@ -58,7 +58,7 @@ static void delete_dirty_block(codeblock_t *block);
/*Temporary list of code blocks that have recently been evicted. This allows for
some historical state to be kept when a block is the target of self-modifying
code.
The size of this list is limited to DIRTY_LIST_MAX_SIZE blocks. When this is
exceeded the oldest entry will be moved to the free list.*/
static uint16_t block_dirty_list_head, block_dirty_list_tail;
@@ -88,7 +88,7 @@ static void block_dirty_list_add(codeblock_t *block)
if (block_dirty_list_head != BLOCK_INVALID)
{
codeblock_t *old_head = &codeblock[block_dirty_list_head];
block->next = block_dirty_list_head;
block->prev = BLOCK_INVALID;
block_dirty_list_head = old_head->prev = get_block_nr(block);
@@ -213,9 +213,9 @@ static codeblock_t *block_free_list_get()
void codegen_init()
{
int c;
codegen_allocator_init();
codegen_backend_init();
block_free_list = 0;
for (c = 0; c < BLOCK_SIZE; c++)
@@ -235,7 +235,7 @@ void codegen_close()
{
int c;
uint32_t highest_num = 0, highest_idx = 0;
for (c = 0; c < 256*256; c++)
{
if (instr_counts[c] > highest_num)
@@ -263,7 +263,7 @@ void codegen_reset()
for (c = 1; c < BLOCK_SIZE; c++)
{
codeblock_t *block = &codeblock[c];
if (block->pc != BLOCK_PC_INVALID)
{
block->phys = 0;
@@ -296,7 +296,7 @@ void dump_block()
pclog(" %p : %08x-%08x %08x-%08x %p %p\n", (void *)block, start_pc, end_pc, block->pc, block->endpc, (void *)block->prev, (void *)block->next);
if (!block->pc)
fatal("Dead PC=0\n");
block = block->next;
}
pclog("dump_block done\n");*/
@@ -331,11 +331,11 @@ static void add_to_block_list(codeblock_t *block)
fatal("block->next->pc=BLOCK_PC_INVALID %p %p %x %x\n", (void *)&codeblock[block->next], (void *)codeblock, block_current, block_pos);
#endif
}
if (block->page_mask2)
{
block->flags |= CODEBLOCK_HAS_PAGE2;
block_prev_nr = pages[block->phys_2 >> 12].block_2;
if (block_prev_nr)
@@ -466,7 +466,7 @@ void codegen_delete_block(codeblock_t *block)
void codegen_delete_random_block(int required_mem_block)
{
int block_nr = rand() & BLOCK_MASK;
while (1)
{
if (block_nr && block_nr != block_current)
@@ -493,7 +493,7 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
{
codeblock_t *block = &codeblock[block_nr];
uint16_t next_block = block->next;
if (*block->dirty_mask & block->page_mask)
{
invalidate_block(block);
@@ -506,7 +506,7 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
}
block_nr = page->block_2;
while (block_nr)
{
codeblock_t *block = &codeblock[block_nr];
@@ -522,12 +522,12 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
#endif
block_nr = next_block;
}
if (page->code_present_mask & page->dirty_mask)
remove_from_evict_list = 1;
page->code_present_mask &= ~page->dirty_mask;
page->dirty_mask = 0;
for (c = 0; c < 64; c++)
{
if (page->byte_code_present_mask[c] & page->byte_dirty_mask[c])
@@ -567,7 +567,7 @@ void codegen_block_init(uint32_t phys_addr)
block->page_mask = block->page_mask2 = 0;
block->flags = CODEBLOCK_STATIC_TOP;
block->status = cpu_cur_status;
recomp_page = block->phys & ~0xfff;
codeblock_tree_add(block);
}
@@ -598,7 +598,7 @@ void codegen_block_start_recompile(codeblock_t *block)
block->data = codeblock_allocator_get_ptr(block->head_mem_block);
block->status = cpu_cur_status;
block->page_mask = block->page_mask2 = 0;
block->ins = 0;
@@ -607,30 +607,30 @@ void codegen_block_start_recompile(codeblock_t *block)
last_op32 = -1;
last_ea_seg = NULL;
last_ssegs = -1;
codegen_block_cycles = 0;
codegen_timing_block_start();
codegen_block_ins = 0;
codegen_block_full_ins = 0;
recomp_page = block->phys & ~0xfff;
codegen_flags_changed = 0;
codegen_fpu_entered = 0;
codegen_mmx_entered = 0;
codegen_fpu_loaded_iq[0] = codegen_fpu_loaded_iq[1] = codegen_fpu_loaded_iq[2] = codegen_fpu_loaded_iq[3] =
codegen_fpu_loaded_iq[4] = codegen_fpu_loaded_iq[5] = codegen_fpu_loaded_iq[6] = codegen_fpu_loaded_iq[7] = 0;
cpu_state.seg_ds.checked = cpu_state.seg_es.checked = cpu_state.seg_fs.checked = cpu_state.seg_gs.checked = (cr0 & 1) ? 0 : 1;
block->TOP = cpu_state.TOP & 7;
block->flags |= CODEBLOCK_WAS_RECOMPILED;
codegen_flat_ds = !(cpu_cur_status & CPU_STATUS_NOTFLATDS);
codegen_flat_ss = !(cpu_cur_status & CPU_STATUS_NOTFLATSS);
codegen_flat_ss = !(cpu_cur_status & CPU_STATUS_NOTFLATSS);
if (block->flags & CODEBLOCK_BYTE_MASK)
{
block->dirty_mask = &page->byte_dirty_mask[(block->phys >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK];
@@ -684,7 +684,7 @@ void codegen_block_generate_end_mask_recompile()
if (block->flags & CODEBLOCK_BYTE_MASK)
{
int offset = (block->phys_2 >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
page_2->byte_code_present_mask[offset] |= block->page_mask2;
block->dirty_mask2 = &page_2->byte_dirty_mask[offset];
}

12
src/codegen_new/codegen_ir.c
View File

@@ -48,7 +48,7 @@ static void duplicate_uop(ir_data_t *ir, uop_t *uop, int offset)
new_uop->imm_data = uop->imm_data;
new_uop->p = uop->p;
new_uop->pc = uop->pc;
if (uop->jump_dest_uop != -1)
{
new_uop->jump_dest_uop = uop->jump_dest_uop + offset;
@@ -64,10 +64,10 @@ void codegen_ir_compile(ir_data_t *ir, codeblock_t *block)
{
int unroll_count;
int unroll_end;
codegen_set_loop_start(ir, codegen_unroll_first_instruction);
unroll_end = ir->wr_pos;
for (unroll_count = 1; unroll_count < codegen_unroll_count; unroll_count++)
{
int offset = ir->wr_pos - codegen_unroll_start;
@@ -89,7 +89,7 @@ void codegen_ir_compile(ir_data_t *ir, codeblock_t *block)
for (c = 0; c < ir->wr_pos; c++)
{
uop_t *uop = &ir->uops[c];
// pclog("uOP %i : %08x\n", c, uop->type);
if (uop->type & UOP_TYPE_BARRIER)
@@ -184,7 +184,7 @@ void codegen_ir_compile(ir_data_t *ir, codeblock_t *block)
else
{
uop_t *uop_dest = &ir->uops[uop->jump_dest_uop];
while (uop_dest->jump_list_next != -1)
uop_dest = &ir->uops[uop_dest->jump_list_next];
@@ -195,7 +195,7 @@ void codegen_ir_compile(ir_data_t *ir, codeblock_t *block)
}
codegen_reg_flush_invalidate(ir, block);
if (jump_target_at_end != -1)
{
uop_t *uop_dest = &ir->uops[jump_target_at_end];

26
src/codegen_new/codegen_ir_defs.h
View File

@@ -9,7 +9,7 @@
All registers must have been written back or discarded.
This should be used when calling external functions that may change any emulated
registers.*/
#define UOP_TYPE_BARRIER (1 << 31)
#define UOP_TYPE_BARRIER (1u << 31)
/*uOP is a barrier. All previous uOPs must have completed before this one executes.
All registers must have been written back, but do not have to be discarded.
@@ -361,19 +361,19 @@ typedef struct ir_data_t
static inline uop_t *uop_alloc(ir_data_t *ir, uint32_t uop_type)
{
uop_t *uop;
if (ir->wr_pos >= UOP_NR_MAX)
fatal("Exceeded uOP max\n");
uop = &ir->uops[ir->wr_pos++];
uop->dest_reg_a = invalid_ir_reg;
uop->src_reg_a = invalid_ir_reg;
uop->src_reg_b = invalid_ir_reg;
uop->src_reg_c = invalid_ir_reg;
uop->pc = cpu_state.oldpc;
uop->jump_dest_uop = -1;
uop->jump_list_next = -1;
@@ -386,7 +386,7 @@ static inline uop_t *uop_alloc(ir_data_t *ir, uint32_t uop_type)
static inline void uop_set_jump_dest(ir_data_t *ir, int jump_uop)
{
uop_t *uop = &ir->uops[jump_uop];
uop->jump_dest_uop = ir->wr_pos;
}
@@ -402,7 +402,7 @@ static inline int uop_gen(uint32_t uop_type, ir_data_t *ir)
static inline int uop_gen_reg_src1(uint32_t uop_type, ir_data_t *ir, int src_reg_a)
{
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
uop->src_reg_a = codegen_reg_read(src_reg_a);
@@ -424,7 +424,7 @@ static inline int uop_gen_reg_src1_imm(uint32_t uop_type, ir_data_t *ir, int src
uop->type = uop_type;
uop->src_reg_a = codegen_reg_read(src_reg);
uop->imm_data = imm;
return ir->wr_pos-1;
}
@@ -514,7 +514,7 @@ static inline int uop_gen_reg_src2(uint32_t uop_type, ir_data_t *ir, int src_reg
uop->type = uop_type;
uop->src_reg_a = codegen_reg_read(src_reg_a);
uop->src_reg_b = codegen_reg_read(src_reg_b);
return ir->wr_pos-1;
}
@@ -552,7 +552,7 @@ static inline void uop_gen_reg_src3_imm(uint32_t uop_type, ir_data_t *ir, int sr
static inline void uop_gen_imm(uint32_t uop_type, ir_data_t *ir, uint32_t imm)
{
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
uop->imm_data = imm;
}
@@ -560,7 +560,7 @@ static inline void uop_gen_imm(uint32_t uop_type, ir_data_t *ir, uint32_t imm)
static inline void uop_gen_pointer(uint32_t uop_type, ir_data_t *ir, void *p)
{
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
uop->p = p;
}
@@ -568,7 +568,7 @@ static inline void uop_gen_pointer(uint32_t uop_type, ir_data_t *ir, void *p)
static inline void uop_gen_pointer_imm(uint32_t uop_type, ir_data_t *ir, void *p, uint32_t imm)
{
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
uop->p = p;
uop->imm_data = imm;

30
src/codegen_new/codegen_ops_arith.c
View File

@@ -309,7 +309,7 @@ uint32_t ropADD_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32
uint32_t ropADD_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uop_MOV(ir, IREG_flags_op1, IREG_EAX);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
{
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp0, cs + op_pc);
@@ -337,7 +337,7 @@ uint32_t ropADD_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
@@ -1283,7 +1283,7 @@ uint32_t rop80(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetch
{
int dest_reg = fetchdat & 7;
uint8_t imm = fastreadb(cs + op_pc + 1);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
{
skip_immediate = 1;
@@ -1779,7 +1779,7 @@ uint32_t rop81_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int skip_immediate = 0;
codegen_mark_code_present(block, cs+op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0)
{
@@ -1836,7 +1836,7 @@ uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
@@ -1954,7 +1954,7 @@ uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp3);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
@@ -2157,7 +2157,7 @@ uint32_t rop83_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
@@ -2227,7 +2227,7 @@ uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
{
int dest_reg = fetchdat & 7;
uint32_t imm = (int32_t)(int8_t)fastreadb(cs + op_pc + 1);
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
@@ -2243,7 +2243,7 @@ uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
@@ -2299,7 +2299,7 @@ uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
{
x86seg *target_seg;
uint32_t imm;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
if ((fetchdat & 0x38) == 0x38) /*CMP*/
@@ -2326,7 +2326,7 @@ uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1, IREG_temp0, imm);
@@ -2392,7 +2392,7 @@ uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
static void rebuild_c(ir_data_t *ir)
{
int needs_rebuild = 1;
if (codegen_flags_changed)
{
switch (cpu_state.flags_op)
@@ -2403,7 +2403,7 @@ static void rebuild_c(ir_data_t *ir)
break;
}
}
if (needs_rebuild)
{
uop_CALL_FUNC(ir, flags_rebuild_c);
@@ -2426,7 +2426,7 @@ uint32_t ropINC_r16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropINC_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
rebuild_c(ir);
uop_MOV(ir, IREG_flags_op1, IREG_32(opcode & 7));
uop_ADD_IMM(ir, IREG_32(opcode & 7), IREG_32(opcode & 7), 1);
uop_MOV(ir, IREG_flags_res, IREG_32(opcode & 7));
@@ -2468,7 +2468,7 @@ uint32_t ropINCDEC(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t f
{
codegen_mark_code_present(block, cs+op_pc, 1);
rebuild_c(ir);
if ((fetchdat & 0xc0) == 0xc0)
{
uop_MOVZX(ir, IREG_flags_op1, IREG_8(fetchdat & 7));

2
src/codegen_new/codegen_ops_branch.c
View File

@@ -622,7 +622,7 @@ static int ropJNL_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr,
{
int jump_uop;
int do_unroll = ((NF_SET() ? 1 : 0) == (VF_SET() ? 1 : 0) && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN)
{
case FLAGS_ZN8:

8
src/codegen_new/codegen_ops_fpu_arith.c
View File

@@ -21,7 +21,7 @@ uint32_t ropFADD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_FP_ENTER(ir);
uop_FADD(ir, IREG_ST(0), IREG_ST(0), IREG_ST(src_reg));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t ropFADDr(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
@@ -42,7 +42,7 @@ uint32_t ropFADDP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
uop_FADD(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
fpu_POP(block, ir);
return op_pc;
}
@@ -128,7 +128,7 @@ uint32_t ropFDIVP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
uop_FDIV(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
fpu_POP(block, ir);
return op_pc;
}
uint32_t ropFDIVRP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
@@ -234,7 +234,7 @@ uint32_t ropFSUBRP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t f
uop_FSUB(ir, IREG_ST(dest_reg), IREG_ST(0), IREG_ST(dest_reg));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
fpu_POP(block, ir);
return op_pc;
}

2
src/codegen_new/codegen_ops_fpu_constant.c
View File

@@ -31,6 +31,6 @@ uint32_t ropFLDZ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uop_MOV_DOUBLE_INT(ir, IREG_ST(-1), IREG_temp0);
uop_MOV_IMM(ir, IREG_tag(-1), TAG_VALID);
fpu_PUSH(block, ir);
return op_pc;
}

2
src/codegen_new/codegen_ops_fpu_misc.c
View File

@@ -91,7 +91,7 @@ uint32_t ropFSTSW_AX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
{
uop_FP_ENTER(ir);
uop_MOV(ir, IREG_AX, IREG_NPXS);
return op_pc;
}

2
src/codegen_new/codegen_ops_helpers.c
View File

@@ -57,7 +57,7 @@ int codegen_can_unroll_full(codeblock_t *block, ir_data_t *ir, uint32_t next_pc,
TOP = cpu_state.TOP;
}
}
if (TOP != cpu_state.TOP)
return 0;

16
src/codegen_new/codegen_ops_jump.c
View File

@@ -28,7 +28,7 @@ uint32_t ropJMP_r16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
{
uint32_t offset = (int32_t)(int16_t)fastreadw(cs + op_pc);
uint32_t dest_addr = op_pc+2+offset;
dest_addr &= 0xffff;
if (offset < 0)
@@ -40,7 +40,7 @@ uint32_t ropJMP_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
{
uint32_t offset = fastreadl(cs + op_pc);
uint32_t dest_addr = op_pc+4+offset;
if (offset < 0)
codegen_can_unroll(block, ir, op_pc+1, dest_addr);
codegen_mark_code_present(block, cs+op_pc, 4);
@@ -100,13 +100,13 @@ uint32_t ropCALL_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ret_addr = op_pc + 4;
uint32_t dest_addr = ret_addr + offset;
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
uop_MEM_STORE_IMM_32(ir, IREG_SS_base, sp_reg, ret_addr);
SUB_SP(ir, 4);
uop_MOV_IMM(ir, IREG_pc, dest_addr);
codegen_mark_code_present(block, cs+op_pc, 4);
return -1;
}
@@ -114,7 +114,7 @@ uint32_t ropCALL_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropRET_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP);
else
@@ -130,7 +130,7 @@ uint32_t ropRET_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t f
uint32_t ropRET_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_pc, IREG_SS_base, IREG_ESP);
else
@@ -146,7 +146,7 @@ uint32_t ropRET_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t f
uint32_t ropRET_imm_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint16_t offset = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
@@ -267,7 +267,7 @@ uint32_t ropRETF_imm_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
if ((msw&1) && !(cpu_state.eflags&VM_FLAG))
return 0;
offset = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);

2
src/codegen_new/codegen_ops_logic.c
View File

@@ -64,7 +64,7 @@ uint32_t ropAND_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
if ((fetchdat & 0xc0) == 0xc0)
{
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
}
else

14
src/codegen_new/codegen_ops_misc.c
View File

@@ -22,13 +22,13 @@ uint32_t ropLEA_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t f
codegen_mark_code_present(block, cs+op_pc, 1);
codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
uop_MOV(ir, IREG_16(dest_reg), IREG_eaaddr_W);
return op_pc + 1;
}
uint32_t ropLEA_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
if ((fetchdat & 0xc0) == 0xc0)
return 0;
@@ -44,7 +44,7 @@ uint32_t ropF6(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetch
x86seg *target_seg = NULL;
uint8_t imm_data;
int reg;
if (fetchdat & 0x20)
return 0;
@@ -67,7 +67,7 @@ uint32_t ropF6(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetch
{
case 0x00: case 0x08: /*TEST*/
imm_data = fastreadb(cs + op_pc + 1);
uop_AND_IMM(ir, IREG_flags_res_B, reg, imm_data);
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
@@ -75,7 +75,7 @@ uint32_t ropF6(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetch
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs+op_pc+1, 1);
return op_pc+2;
case 0x10: /*NOT*/
uop_XOR_IMM(ir, reg, reg, 0xff);
if ((fetchdat & 0xc0) != 0xc0)
@@ -321,7 +321,7 @@ uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_INC16);
}
return op_pc+1;
case 0x08: /*DEC*/
rebuild_c(ir);
codegen_flags_changed = 1;
@@ -357,7 +357,7 @@ uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
case 0x20: /*JMP*/
uop_MOVZX(ir, IREG_pc, src_reg);
return -1;
case 0x28: /*JMP far*/
uop_MOVZX(ir, IREG_pc, src_reg);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2);

16
src/codegen_new/codegen_ops_mov.c
View File

@@ -242,7 +242,7 @@ uint32_t ropMOV_EAX_abs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
uop_MEM_LOAD_REG(ir, IREG_EAX, ireg_seg_base(op_ea_seg), IREG_eaaddr);
else
uop_MEM_LOAD_ABS(ir, IREG_EAX, ireg_seg_base(op_ea_seg), addr);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
@@ -421,7 +421,7 @@ uint32_t ropMOV_w_seg(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_
uint32_t ropMOV_l_seg(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg;
codegen_mark_code_present(block, cs+op_pc, 1);
switch (fetchdat & 0x38)
{
@@ -490,7 +490,7 @@ uint32_t ropMOV_seg_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_
}
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if ((fetchdat & 0xc0) == 0xc0)
{
uop_MOV(ir, IREG_temp0_W, IREG_16(fetchdat & 7));
@@ -655,11 +655,11 @@ uint32_t ropMOVZX_32_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
uint32_t ropXCHG_AX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int reg2 = IREG_16(opcode & 7);
uop_MOV(ir, IREG_temp0_W, IREG_AX);
uop_MOV(ir, IREG_AX, reg2);
uop_MOV(ir, reg2, IREG_temp0_W);
return op_pc;
}
uint32_t ropXCHG_EAX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
@@ -681,7 +681,7 @@ uint32_t ropXCHG_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t f
if ((fetchdat & 0xc0) == 0xc0)
{
int reg2 = IREG_8(fetchdat & 7);
uop_MOV(ir, IREG_temp0_B, reg1);
uop_MOV(ir, reg1, reg2);
uop_MOV(ir, reg2, IREG_temp0_B);
@@ -693,7 +693,7 @@ uint32_t ropXCHG_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t f
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg1);
uop_MOV(ir, reg1, IREG_temp0_B);
@@ -761,7 +761,7 @@ uint32_t ropXCHG_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropXLAT(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
uop_MOVZX(ir, IREG_eaaddr, IREG_AL);
uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, IREG_EBX);
if (!(op_32 & 0x200))

22
src/codegen_new/codegen_ops_shift.c
View File

@@ -58,7 +58,7 @@ static uint32_t shift_common_8(ir_data_t *ir, uint32_t fetchdat, uint32_t op_pc,
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
default:
return 0;
}
@@ -454,7 +454,7 @@ uint32_t ropC0(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetch
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs+op_pc+1, 1);
if (imm)
return shift_common_8(ir, fetchdat, op_pc, target_seg, imm) + 1;
return op_pc+1;
@@ -477,7 +477,7 @@ uint32_t ropC1_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs+op_pc+1, 1);
if (imm)
return shift_common_16(ir, fetchdat, op_pc, target_seg, imm) + 1;
return op_pc+1;
@@ -501,7 +501,7 @@ uint32_t ropC1_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
{
uint32_t new_pc;
int jump_uop;
LOAD_IMMEDIATE_FROM_RAM_8(block, ir, IREG_temp2, cs + op_pc + 1);
uop_AND_IMM(ir, IREG_temp2, IREG_temp2, 0x1f);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp2, 0);
@@ -515,7 +515,7 @@ uint32_t ropC1_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
{
uint8_t imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs+op_pc+1, 1);
if (imm)
return shift_common_32(ir, fetchdat, op_pc, target_seg, imm) + 1;
}
@@ -584,7 +584,7 @@ uint32_t ropD2(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetch
if (!(CL & 0x1f) || !block->ins)
return 0;
uop_AND_IMM(ir, IREG_temp2, REG_ECX, 0x1f);
uop_CMP_IMM_JZ(ir, IREG_temp2, 0, codegen_exit_rout);
@@ -706,7 +706,7 @@ uint32_t ropD3_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
if (!(CL & 0x1f) || !block->ins)
return 0;
uop_AND_IMM(ir, IREG_temp2, REG_ECX, 0x1f);
uop_CMP_IMM_JZ(ir, IREG_temp2, 0, codegen_exit_rout);
@@ -958,7 +958,7 @@ uint32_t ropSHLD_16_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs+op_pc+1, 1);
if (!imm)
return op_pc+2;
@@ -1006,7 +1006,7 @@ uint32_t ropSHLD_32_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs+op_pc+1, 1);
if (!imm)
return op_pc+2;
@@ -1054,7 +1054,7 @@ uint32_t ropSHRD_16_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs+op_pc+1, 1);
if (!imm)
return op_pc+2;
@@ -1102,7 +1102,7 @@ uint32_t ropSHRD_32_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs+op_pc+1, 1);
if (!imm)
return op_pc+2;

4
src/codegen_new/codegen_ops_stack.c
View File

@@ -141,7 +141,7 @@ uint32_t ropPOP_W(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
{
x86seg *target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 2);
codegen_check_seg_write(block, ir, target_seg);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP);
else
@@ -340,7 +340,7 @@ uint32_t ropPUSHA_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropPOPA_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP(ir);
uop_MEM_LOAD_REG(ir, IREG_DI, IREG_SS_base, sp_reg);

50
src/codegen_new/codegen_reg.c
View File

@@ -92,14 +92,14 @@ struct
[IREG_op32] = {REG_DWORD, &cpu_state.op32, REG_INTEGER, REG_PERMANENT},
[IREG_ssegsx] = {REG_BYTE, &cpu_state.ssegs, REG_INTEGER, REG_PERMANENT},
[IREG_rm_mod_reg] = {REG_DWORD, &cpu_state.rm_data.rm_mod_reg_data, REG_INTEGER, REG_PERMANENT},
#ifdef USE_ACYCS
[IREG_acycs] = {REG_DWORD, &acycs, REG_INTEGER, REG_PERMANENT},
#endif
[IREG_cycles] = {REG_DWORD, &cpu_state._cycles, REG_INTEGER, REG_PERMANENT},
[IREG_CS_base] = {REG_DWORD, &cpu_state.seg_cs.base, REG_INTEGER, REG_PERMANENT},
[IREG_DS_base] = {REG_DWORD, &cpu_state.seg_ds.base, REG_INTEGER, REG_PERMANENT},
[IREG_ES_base] = {REG_DWORD, &cpu_state.seg_es.base, REG_INTEGER, REG_PERMANENT},
@@ -113,7 +113,7 @@ struct
[IREG_FS_seg] = {REG_WORD, &cpu_state.seg_fs.seg, REG_INTEGER, REG_PERMANENT},
[IREG_GS_seg] = {REG_WORD, &cpu_state.seg_gs.seg, REG_INTEGER, REG_PERMANENT},
[IREG_SS_seg] = {REG_WORD, &cpu_state.seg_ss.seg, REG_INTEGER, REG_PERMANENT},
[IREG_FPU_TOP] = {REG_DWORD, &cpu_state.TOP, REG_INTEGER, REG_PERMANENT},
[IREG_ST0] = {REG_FPU_ST_DOUBLE, &cpu_state.ST[0], REG_FP, REG_PERMANENT},
@@ -124,7 +124,7 @@ struct
[IREG_ST5] = {REG_FPU_ST_DOUBLE, &cpu_state.ST[0], REG_FP, REG_PERMANENT},
[IREG_ST6] = {REG_FPU_ST_DOUBLE, &cpu_state.ST[0], REG_FP, REG_PERMANENT},
[IREG_ST7] = {REG_FPU_ST_DOUBLE, &cpu_state.ST[0], REG_FP, REG_PERMANENT},
[IREG_tag0] = {REG_FPU_ST_BYTE, &cpu_state.tag[0], REG_INTEGER, REG_PERMANENT},
[IREG_tag1] = {REG_FPU_ST_BYTE, &cpu_state.tag[0], REG_INTEGER, REG_PERMANENT},
[IREG_tag2] = {REG_FPU_ST_BYTE, &cpu_state.tag[0], REG_INTEGER, REG_PERMANENT},
@@ -151,7 +151,7 @@ struct
[IREG_MM5x] = {REG_QWORD, &cpu_state.MM[5], REG_FP, REG_PERMANENT},
[IREG_MM6x] = {REG_QWORD, &cpu_state.MM[6], REG_FP, REG_PERMANENT},
[IREG_MM7x] = {REG_QWORD, &cpu_state.MM[7], REG_FP, REG_PERMANENT},
[IREG_NPXCx] = {REG_WORD, &cpu_state.npxc, REG_INTEGER, REG_PERMANENT},
[IREG_NPXSx] = {REG_WORD, &cpu_state.npxs, REG_INTEGER, REG_PERMANENT},
@@ -179,7 +179,7 @@ struct
[IREG_temp1] = {REG_DWORD, (void *)20, REG_INTEGER, REG_VOLATILE},
[IREG_temp2] = {REG_DWORD, (void *)24, REG_INTEGER, REG_VOLATILE},
[IREG_temp3] = {REG_DWORD, (void *)28, REG_INTEGER, REG_VOLATILE},
[IREG_temp0d] = {REG_DOUBLE, (void *)40, REG_FP, REG_VOLATILE},
[IREG_temp1d] = {REG_DOUBLE, (void *)48, REG_FP, REG_VOLATILE},
};
@@ -187,11 +187,11 @@ struct
void codegen_reg_mark_as_required()
{
int reg;
for (reg = 0; reg < IREG_COUNT; reg++)
{
int last_version = reg_last_version[reg];
if (last_version > 0 && ireg_data[reg].is_volatile == REG_PERMANENT)
reg_version[reg][last_version].flags |= REG_FLAGS_REQUIRED;
}
@@ -201,7 +201,7 @@ int reg_is_native_size(ir_reg_t ir_reg)
{
int native_size = ireg_data[IREG_GET_REG(ir_reg.reg)].native_size;
int requested_size = IREG_GET_SIZE(ir_reg.reg);
switch (native_size)
{
case REG_BYTE: case REG_FPU_ST_BYTE:
@@ -216,11 +216,11 @@ int reg_is_native_size(ir_reg_t ir_reg)
if (sizeof(void *) == 4)
return (requested_size == IREG_SIZE_L);
return (requested_size == IREG_SIZE_Q);
default:
fatal("get_reg_is_native_size: unknown native size %i\n", native_size);
}
return 0;
}
@@ -254,7 +254,7 @@ void codegen_reg_reset()
host_fp_reg_set.regs[c] = invalid_ir_reg;
host_fp_reg_set.dirty[c] = 0;
}
reg_dead_list = 0;
max_version_refcount = 0;
}
@@ -308,7 +308,7 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
else
codegen_direct_read_64(block, reg_set->reg_list[c].reg, ireg_data[IREG_GET_REG(ir_reg.reg)].p);
break;
case REG_POINTER:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
@@ -330,7 +330,7 @@ static void codegen_reg_load(host_reg_set_t *reg_set, codeblock_t *block, int c,
else
codegen_direct_read_double(block, reg_set->reg_list[c].reg, ireg_data[IREG_GET_REG(ir_reg.reg)].p);
break;
case REG_FPU_ST_BYTE:
#ifndef RELEASE_BUILD
if (ireg_data[IREG_GET_REG(ir_reg.reg)].type != REG_INTEGER)
@@ -535,7 +535,7 @@ static void alloc_reg(ir_reg_t ir_reg)
host_reg_set_t *reg_set = get_reg_set(ir_reg);
int nr_regs = (reg_set == &host_reg_set) ? CODEGEN_HOST_REGS : CODEGEN_HOST_FP_REGS;
int c;
for (c = 0; c < nr_regs; c++)
{
if (IREG_GET_REG(reg_set->regs[c].reg) == IREG_GET_REG(ir_reg.reg))
@@ -591,7 +591,7 @@ static void alloc_dest_reg(ir_reg_t ir_reg, int dest_reference)
void codegen_reg_alloc_register(ir_reg_t dest_reg_a, ir_reg_t src_reg_a, ir_reg_t src_reg_b, ir_reg_t src_reg_c)
{
int dest_reference = 0;
host_reg_set.locked = 0;
host_fp_reg_set.locked = 0;
@@ -680,16 +680,16 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
{
host_reg_set_t *reg_set = get_reg_set(ir_reg);
int c;
if (!reg_is_native_size(ir_reg))
{
/*Read in parent register so we can do partial accesses to it*/
ir_reg_t parent_reg;
parent_reg.reg = IREG_GET_REG(ir_reg.reg) | IREG_SIZE_L;
parent_reg.version = ir_reg.version - 1;
reg_version[IREG_GET_REG(ir_reg.reg)][ir_reg.version - 1].refcount++;
codegen_reg_alloc_read_reg(block, parent_reg, &c);
#ifndef RELEASE_BUILD
@@ -704,7 +704,7 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
reg_set->dirty[c] = 1;
return reg_set->reg_list[c].reg | IREG_GET_SIZE(ir_reg.reg);
}
/*Search for previous version in host register*/
for (c = 0; c < reg_set->nr_regs; c++)
{
@@ -720,7 +720,7 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
}
}
}
if (c == reg_set->nr_regs)
{
/*Search for unused registers*/
@@ -729,7 +729,7 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
if (ir_reg_is_invalid(reg_set->regs[c]))
break;
}
if (c == reg_set->nr_regs)
{
/*No unused registers. Search for an unlocked register*/
@@ -746,7 +746,7 @@ ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg)
codegen_reg_writeback(reg_set, block, c, 1);
}
}
reg_set->regs[c].reg = ir_reg.reg;
reg_set->regs[c].version = ir_reg.version;
reg_set->dirty[c] = 1;
@@ -819,7 +819,7 @@ void codegen_reg_flush(ir_data_t *ir, codeblock_t *block)
{
host_reg_set_t *reg_set;
int c;
reg_set = &host_reg_set;
for (c = 0; c < reg_set->nr_regs; c++)
{
@@ -853,7 +853,7 @@ void codegen_reg_flush_invalidate(ir_data_t *ir, codeblock_t *block)
{
host_reg_set_t *reg_set;
int c;
reg_set = &host_reg_set;
for (c = 0; c < reg_set->nr_regs; c++)
{

42
src/codegen_new/codegen_reg.h
View File

@@ -38,9 +38,9 @@ enum
IREG_ea_seg = 15,
IREG_op32 = 16,
IREG_ssegsx = 17,
IREG_rm_mod_reg = 18,
IREG_acycs = 19,
IREG_cycles = 20,
@@ -70,7 +70,7 @@ enum
IREG_temp0d = 38,
IREG_temp1d = 39,
/*FPU stack registers are physical registers. Use IREG_ST() / IREG_tag()
to access.
When CODEBLOCK_STATIC_TOP is set, the physical register number will be
@@ -85,7 +85,7 @@ enum
IREG_ST5 = 45,
IREG_ST6 = 46,
IREG_ST7 = 47,
IREG_tag0 = 48,
IREG_tag1 = 49,
IREG_tag2 = 50,
@@ -103,7 +103,7 @@ enum
IREG_ST5_i64 = 61,
IREG_ST6_i64 = 62,
IREG_ST7_i64 = 63,
IREG_MM0x = 64,
IREG_MM1x = 65,
IREG_MM2x = 66,
@@ -112,13 +112,13 @@ enum
IREG_MM5x = 69,
IREG_MM6x = 70,
IREG_MM7x = 71,
IREG_NPXCx = 72,
IREG_NPXSx = 73,
IREG_flagsx = 74,
IREG_eflagsx = 75,
IREG_CS_limit_low = 76,
IREG_DS_limit_low = 77,
IREG_ES_limit_low = 78,
@@ -134,9 +134,9 @@ enum
IREG_SS_limit_high = 87,
IREG_COUNT = 88,
IREG_INVALID = 255,
IREG_AX = IREG_EAX + IREG_SIZE_W,
IREG_CX = IREG_ECX + IREG_SIZE_W,
IREG_DX = IREG_EDX + IREG_SIZE_W,
@@ -155,7 +155,7 @@ enum
IREG_CH = IREG_ECX + IREG_SIZE_BH,
IREG_DH = IREG_EDX + IREG_SIZE_BH,
IREG_BH = IREG_EBX + IREG_SIZE_BH,
IREG_flags_res_W = IREG_flags_res + IREG_SIZE_W,
IREG_flags_op1_W = IREG_flags_op1 + IREG_SIZE_W,
IREG_flags_op2_W = IREG_flags_op2 + IREG_SIZE_W,
@@ -168,7 +168,7 @@ enum
IREG_temp1_W = IREG_temp1 + IREG_SIZE_W,
IREG_temp2_W = IREG_temp2 + IREG_SIZE_W,
IREG_temp3_W = IREG_temp3 + IREG_SIZE_W,
IREG_temp0_B = IREG_temp0 + IREG_SIZE_B,
IREG_temp1_B = IREG_temp1 + IREG_SIZE_B,
IREG_temp2_B = IREG_temp2 + IREG_SIZE_B,
@@ -181,14 +181,14 @@ enum
IREG_temp1_Q = IREG_temp1d + IREG_SIZE_Q,
IREG_eaaddr_W = IREG_eaaddr + IREG_SIZE_W,
IREG_CS_seg_W = IREG_CS_seg + IREG_SIZE_W,
IREG_DS_seg_W = IREG_DS_seg + IREG_SIZE_W,
IREG_ES_seg_W = IREG_ES_seg + IREG_SIZE_W,
IREG_FS_seg_W = IREG_FS_seg + IREG_SIZE_W,
IREG_GS_seg_W = IREG_GS_seg + IREG_SIZE_W,
IREG_SS_seg_W = IREG_SS_seg + IREG_SIZE_W,
IREG_MM0 = IREG_MM0x + IREG_SIZE_Q,
IREG_MM1 = IREG_MM1x + IREG_SIZE_Q,
IREG_MM2 = IREG_MM2x + IREG_SIZE_Q,
@@ -197,12 +197,12 @@ enum
IREG_MM5 = IREG_MM5x + IREG_SIZE_Q,
IREG_MM6 = IREG_MM6x + IREG_SIZE_Q,
IREG_MM7 = IREG_MM7x + IREG_SIZE_Q,
IREG_NPXC = IREG_NPXCx + IREG_SIZE_W,
IREG_NPXS = IREG_NPXSx + IREG_SIZE_W,
IREG_ssegs = IREG_ssegsx + IREG_SIZE_B,
IREG_flags = IREG_flagsx + IREG_SIZE_W,
IREG_eflags = IREG_eflagsx + IREG_SIZE_W
};
@@ -324,7 +324,7 @@ static inline ir_reg_t codegen_reg_read(int reg)
{
ir_reg_t ireg;
reg_version_t *version;
#ifndef RELEASE_BUILD
if (IREG_GET_REG(reg) == IREG_INVALID)
fatal("codegen_reg_read - IREG_INVALID\n");
@@ -354,21 +354,21 @@ static inline ir_reg_t codegen_reg_write(int reg, int uop_nr)
ir_reg_t ireg;
int last_version = reg_last_version[IREG_GET_REG(reg)];
reg_version_t *version;
#ifndef RELEASE_BUILD
if (IREG_GET_REG(reg) == IREG_INVALID)
fatal("codegen_reg_write - IREG_INVALID\n");
#endif
ireg.reg = reg;
ireg.version = last_version + 1;
if (IREG_GET_REG(reg) > IREG_EBX && last_version && !reg_version[IREG_GET_REG(reg)][last_version].refcount &&
!(reg_version[IREG_GET_REG(reg)][last_version].flags & REG_FLAGS_REQUIRED))
{
if (reg_is_native_size(ireg)) /*Non-native size registers have an implicit dependency on the previous version, so don't add to dead list*/
add_to_dead_list(&reg_version[IREG_GET_REG(reg)][last_version], IREG_GET_REG(reg), last_version);
}
reg_last_version[IREG_GET_REG(reg)]++;
#ifndef RELEASE_BUILD
if (!reg_last_version[IREG_GET_REG(reg)])

76
src/config.c
View File

@@ -272,7 +272,7 @@ config_free(void)
ent = nent;
}
free(sec);
free(sec);
sec = ns;
}
}
@@ -318,7 +318,7 @@ config_read(char *fn)
f = plat_fopen(fn, "rt, ccs=UTF-8");
#endif
if (f == NULL) return(0);
sec = malloc(sizeof(section_t));
memset(sec, 0x00, sizeof(section_t));
memset(&config_head, 0x00, sizeof(list_t));
@@ -365,7 +365,7 @@ config_read(char *fn)
list_add(&ns->list, &config_head);
/* New section is now the current one. */
sec = ns;
sec = ns;
continue;
}
@@ -464,7 +464,7 @@ config_write(char *fn)
sec = (section_t *)sec->list.next;
}
(void)fclose(f);
}
@@ -571,14 +571,14 @@ load_general(void)
if (p != NULL)
{
lang_id = plat_language_code(p);
}
}
p = config_get_string(cat, "iconset", NULL);
if (p != NULL)
strcpy(icon_set, p);
else
strcpy(icon_set, "");
enable_discord = !!config_get_int(cat, "enable_discord", 0);
video_framerate = config_get_int(cat, "video_gl_framerate", -1);
@@ -677,7 +677,7 @@ load_machine(void)
machine = machine_get_machine_from_internal_name(p);
migrate_from = NULL;
}
} else
} else
machine = 0;
/* This is for backwards compatibility. */
@@ -833,20 +833,20 @@ load_machine(void)
p = (char *)config_get_string(cat, "fpu_type", "none");
fpu_type = fpu_get_type(cpu_f, cpu, p);
mem_size = config_get_int(cat, "mem_size", 64);
mem_size = config_get_int(cat, "mem_size", 64);
#if 0
if (mem_size < ((machine_has_bus(machine, MACHINE_AT) &&
(machines[machine].ram_granularity < 128)) ? machines[machine].min_ram*1024 : machines[machine].min_ram))
mem_size = (((machine_has_bus(machine, MACHINE_AT) && (machines[machine].ram_granularity < 128)) ? machines[machine].min_ram*1024 : machines[machine].min_ram);
#endif
if (mem_size > 2097152)
mem_size = 2097152;
cpu_use_dynarec = !!config_get_int(cat, "cpu_use_dynarec", 0);
p = config_get_string(cat, "time_sync", NULL);
if (p != NULL) {
if (p != NULL) {
if (!strcmp(p, "disabled"))
time_sync = TIME_SYNC_DISABLED;
else
@@ -977,7 +977,7 @@ load_input_devices(void)
sprintf(temp, "joystick_%i_axis_%i", c, d);
joystick_state[c].axis_mapping[d] = config_get_int(cat, temp, d);
}
for (d=0; d<joystick_get_button_count(joystick_type); d++) {
for (d=0; d<joystick_get_button_count(joystick_type); d++) {
sprintf(temp, "joystick_%i_button_%i", c, d);
joystick_state[c].button_mapping[d] = config_get_int(cat, temp, d);
}
@@ -1026,7 +1026,7 @@ load_sound(void)
SSI2001 = !!config_get_int(cat, "ssi2001", 0);
GAMEBLASTER = !!config_get_int(cat, "gameblaster", 0);
GUS = !!config_get_int(cat, "gus", 0);
memset(temp, '\0', sizeof(temp));
p = config_get_string(cat, "sound_type", "float");
if (strlen(p) > 511)
@@ -1139,7 +1139,7 @@ load_storage_controllers(void)
/* TODO: Backwards compatibility, get rid of this when enough time has passed. */
backwards_compat2 = (find_section(cat) == NULL);
/* TODO: Backwards compatibility, get rid of this when enough time has passed. */
p = config_get_string(cat, "scsicard", NULL);
if (p != NULL) {
@@ -1965,7 +1965,7 @@ load_other_removable_devices(void)
sprintf(temp, "mo_%02i_iso_path", c+1);
config_delete_var(cat, temp);
}
}
}
@@ -1978,7 +1978,7 @@ load_other_peripherals(void)
char temp[512];
int c, free_p = 0;
if (backwards_compat2) {
if (backwards_compat2) {
p = config_get_string(cat, "scsicard", NULL);
if (p != NULL)
scsi_card_current[0] = scsi_card_get_from_internal_name(p);
@@ -2041,7 +2041,7 @@ load_other_peripherals(void)
}
p = config_get_string(cat, "isartc_type", "none");
isartc_type = isartc_get_from_internal_name(p);
isartc_type = isartc_get_from_internal_name(p);
}
@@ -2258,7 +2258,7 @@ save_general(void)
if (hide_tool_bar != 0)
config_set_int(cat, "hide_tool_bar", hide_tool_bar);
else
config_delete_var(cat, "hide_tool_bar");
config_delete_var(cat, "hide_tool_bar");
if (confirm_reset != 1)
config_set_int(cat, "confirm_reset", confirm_reset);
@@ -2283,7 +2283,7 @@ save_general(void)
plat_language_code_r(lang_id, buffer, 511);
config_set_string(cat, "language", buffer);
}
if (!strcmp(icon_set, ""))
config_delete_var(cat, "iconset");
else
@@ -2354,7 +2354,7 @@ save_machine(void)
/* Match the family name, speed and multiplier. */
if (!strcmp(cpu_f->internal_name, legacy_table_entry->family)) {
if ((legacy_table_entry->rspeed == cpu_f->cpus[cpu].rspeed) &&
if ((legacy_table_entry->rspeed == cpu_f->cpus[cpu].rspeed) &&
(legacy_table_entry->multi == cpu_f->cpus[cpu].multi)) { /* exact speed/multiplier match */
legacy_cpu = i;
break;
@@ -2447,15 +2447,15 @@ save_input_devices(void)
sprintf(tmp2, "joystick_%i_nr", c);
config_delete_var(cat, tmp2);
for (d=0; d<16; d++) {
for (d=0; d<16; d++) {
sprintf(tmp2, "joystick_%i_axis_%i", c, d);
config_delete_var(cat, tmp2);
}
for (d=0; d<16; d++) {
for (d=0; d<16; d++) {
sprintf(tmp2, "joystick_%i_button_%i", c, d);
config_delete_var(cat, tmp2);
}
for (d=0; d<16; d++) {
for (d=0; d<16; d++) {
sprintf(tmp2, "joystick_%i_pov_%i", c, d);
config_delete_var(cat, tmp2);
}
@@ -2468,15 +2468,15 @@ save_input_devices(void)
config_set_int(cat, tmp2, joystick_state[c].plat_joystick_nr);
if (joystick_state[c].plat_joystick_nr) {
for (d=0; d<joystick_get_axis_count(joystick_type); d++) {
for (d=0; d<joystick_get_axis_count(joystick_type); d++) {
sprintf(tmp2, "joystick_%i_axis_%i", c, d);
config_set_int(cat, tmp2, joystick_state[c].axis_mapping[d]);
}
for (d=0; d<joystick_get_button_count(joystick_type); d++) {
for (d=0; d<joystick_get_button_count(joystick_type); d++) {
sprintf(tmp2, "joystick_%i_button_%i", c, d);
config_set_int(cat, tmp2, joystick_state[c].button_mapping[d]);
}
for (d=0; d<joystick_get_pov_count(joystick_type); d++) {
for (d=0; d<joystick_get_pov_count(joystick_type); d++) {
sprintf(tmp2, "joystick_%i_pov_%i", c, d);
sprintf(temp, "%i, %i", joystick_state[c].pov_mapping[d][0], joystick_state[c].pov_mapping[d][1]);
config_set_string(cat, tmp2, temp);
@@ -2744,8 +2744,8 @@ save_other_peripherals(void)
config_delete_var(cat, "isartc_type");
else
config_set_string(cat, "isartc_type",
isartc_get_internal_name(isartc_type));
isartc_get_internal_name(isartc_type));
delete_section_if_empty(cat);
}
@@ -2945,7 +2945,7 @@ save_other_removable_devices(void)
hdd_bus_to_string(zip_drives[c].bus_type, 1));
config_set_string(cat, temp, tmp2);
}
sprintf(temp, "zip_%02i_ide_channel", c+1);
if (zip_drives[c].bus_type != ZIP_BUS_ATAPI)
config_delete_var(cat, temp);
@@ -2985,7 +2985,7 @@ save_other_removable_devices(void)
hdd_bus_to_string(mo_drives[c].bus_type, 1));
config_set_string(cat, temp, tmp2);
}
sprintf(temp, "mo_%02i_ide_channel", c+1);
if (mo_drives[c].bus_type != MO_BUS_ATAPI)
config_delete_var(cat, temp);
@@ -3022,7 +3022,7 @@ save_other_removable_devices(void)
void
config_save(void)
{
{
save_general(); /* General */
save_machine(); /* Machine */
save_video(); /* Video */
@@ -3044,14 +3044,14 @@ void
config_dump(void)
{
section_t *sec;
sec = (section_t *)config_head.next;
while (sec != NULL) {
entry_t *ent;
if (sec->name[0])
config_log("[%s]\n", sec->name);
ent = (entry_t *)sec->entry_head.next;
while (ent != NULL) {
config_log("%s = %s\n", ent->name, ent->data);
@@ -3072,7 +3072,7 @@ config_delete_var(char *head, char *name)
section = find_section(head);
if (section == NULL) return;
entry = find_entry(section, name);
if (entry != NULL) {
list_delete(&entry->list, &section->entry_head);
@@ -3091,7 +3091,7 @@ config_get_int(char *head, char *name, int def)
section = find_section(head);
if (section == NULL)
return(def);
entry = find_entry(section, name);
if (entry == NULL)
return(def);
@@ -3112,7 +3112,7 @@ config_get_double(char *head, char *name, double def)
section = find_section(head);
if (section == NULL)
return(def);
entry = find_entry(section, name);
if (entry == NULL)
return(def);
@@ -3199,7 +3199,7 @@ config_get_string(char *head, char *name, char *def)
entry = find_entry(section, name);
if (entry == NULL)
return(def);
return(entry->data);
}
@@ -3217,7 +3217,7 @@ config_get_wstring(char *head, char *name, wchar_t *def)
entry = find_entry(section, name);
if (entry == NULL)
return(def);
return(entry->wdata);
}

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