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Merge remote-tracking branch 'origin/master' into version/4.1

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This commit is contained in:
OBattler
2023-08-07 03:18:29 +02:00
parent 83c0efa042 c30d5d90b7
commit 036dcbf2a6
92 changed files with 3015 additions and 2503 deletions
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58
src/86box.c
View File

@@ -1048,19 +1048,9 @@ pc_reset_hard_init(void)
/* Initialize the actual machine and its basic modules. */
machine_init();
/* Reset and reconfigure the serial ports. */
serial_standalone_init();
serial_passthrough_init();
/* Reset and reconfigure the Sound Card layer. */
sound_card_reset();
/* Reset any ISA RTC cards. */
isartc_reset();
fdc_card_init();
fdd_reset();
/* Reset some basic devices. */
speaker_init();
shadowbios = 0;
/*
* Once the machine has been initialized, all that remains
@@ -1071,38 +1061,49 @@ pc_reset_hard_init(void)
* that will be a call to device_reset_all() later !
*/
/* Reset some basic devices. */
speaker_init();
lpt_devices_init();
shadowbios = 0;
/*
* Reset the mouse, this will attach it to any port needed.
*/
mouse_reset();
if (joystick_type)
gameport_update_joystick_type();
/* Reset and reconfigure the Sound Card layer. */
sound_card_reset();
/* Reset and reconfigure the Network Card layer. */
network_reset();
lpt_devices_init();
/* Reset and reconfigure the serial ports. */
serial_standalone_init();
serial_passthrough_init();
/* Reset the Hard Disk Controller module. */
hdc_reset();
fdc_card_init();
fdd_reset();
/* Reset the CD-ROM Controller module. */
cdrom_interface_reset();
/* Reset and reconfigure the SCSI layer. */
scsi_card_init();
cdrom_hard_reset();
scsi_disk_hard_reset();
zip_hard_reset();
cdrom_hard_reset();
mo_hard_reset();
scsi_disk_hard_reset();
zip_hard_reset();
/* Reset and reconfigure the Network Card layer. */
network_reset();
if (joystick_type)
gameport_update_joystick_type();
/* Reset any ISA RTC cards. */
isartc_reset();
ui_sb_update_panes();
@@ -1119,6 +1120,11 @@ pc_reset_hard_init(void)
if (postcard_enabled)
device_add(&postcard_device);
if (IS_ARCH(machine, MACHINE_BUS_PCI)) {
pci_register_cards();
device_reset_all(DEVICE_PCI);
}
/* Reset the CPU module. */
resetx86();
dma_reset();

30
src/acpi.c
View File

@@ -124,29 +124,29 @@ acpi_update_irq(acpi_t *dev)
if (sci_level) {
if (dev->irq_mode == 1)
pci_set_irq(dev->slot, dev->irq_pin);
pci_set_irq(dev->slot, dev->irq_pin, &dev->irq_state);
else if (dev->irq_mode == 2)
pci_set_mirq(5, dev->mirq_is_level);
pci_set_mirq(5, dev->mirq_is_level, &dev->irq_state);
else
pci_set_mirq(0xf0 | dev->irq_line, 1);
pci_set_mirq(PCI_DIRQ_BASE | dev->irq_line, 1, &dev->irq_state);
} else {
if (dev->irq_mode == 1)
pci_clear_irq(dev->slot, dev->irq_pin);
pci_clear_irq(dev->slot, dev->irq_pin, &dev->irq_state);
else if (dev->irq_mode == 2)
pci_clear_mirq(5, dev->mirq_is_level);
pci_clear_mirq(5, dev->mirq_is_level, &dev->irq_state);
else
pci_clear_mirq(0xf0 | dev->irq_line, 1);
pci_clear_mirq(PCI_DIRQ_BASE | dev->irq_line, 1, &dev->irq_state);
}
acpi_timer_update(dev, (dev->regs.pmen & TMROF_EN) && !(dev->regs.pmsts & TMROF_STS));
}
void
acpi_raise_smi(void *priv, int do_smi)
static void
acpi_do_raise_smi(void *priv, int do_smi, int is_apm)
{
acpi_t *dev = (acpi_t *) priv;
if (dev->regs.glbctl & 0x01) {
if (is_apm || (dev->regs.glbctl & 0x01)) {
if ((dev->vendor == VEN_VIA) || (dev->vendor == VEN_VIA_596B)) {
if (!dev->regs.smi_lock || !dev->regs.smi_active) {
if (do_smi)
@@ -168,6 +168,12 @@ acpi_raise_smi(void *priv, int do_smi)
}
}
void
acpi_raise_smi(void *priv, int do_smi)
{
acpi_do_raise_smi(priv, do_smi, 0);
}
static uint32_t
acpi_reg_read_common_regs(UNUSED(int size), uint16_t addr, void *priv)
{
@@ -1582,7 +1588,7 @@ acpi_apm_out(uint16_t port, uint8_t val, void *priv)
dev->apm->cmd = val;
if (dev->vendor == VEN_INTEL)
dev->regs.glbsts |= 0x20;
acpi_raise_smi(dev, dev->apm->do_smi);
acpi_do_raise_smi(dev, dev->apm->do_smi, 1);
} else
dev->apm->stat = val;
}
@@ -1657,6 +1663,9 @@ acpi_reset(void *priv)
dev->regs.pmsts |= 0x8000;
acpi_rtc_status = 0;
acpi_update_irq(dev);
dev->irq_state = 0;
}
static void
@@ -1723,6 +1732,7 @@ acpi_init(const device_t *info)
dev->suspend_types[2] = SUS_SUSPEND | SUS_NVR | SUS_RESET_CPU | SUS_RESET_PCI;
dev->suspend_types[3] = SUS_SUSPEND;
dev->suspend_types[5] = SUS_POWER_OFF; /* undocumented, used for S4/S5 by ASUS P5A ACPI table */
dev->suspend_types[7] = SUS_POWER_OFF; /* undocumented, used for S5 by Gigabyte GA-5AX ACPI table */
break;
case VEN_VIA:

30
src/chipset/ali1435.c
View File

@@ -46,11 +46,12 @@
typedef struct ali_1435_t {
uint8_t index;
uint8_t cfg_locked;
uint8_t pci_slot;
uint8_t pad;
uint8_t regs[16];
uint8_t pci_regs[256];
} ali1435_t;
#define ENABLE_ALI1435_LOG 1
#ifdef ENABLE_ALI1435_LOG
int ali1435_do_log = ENABLE_ALI1435_LOG;
@@ -190,24 +191,20 @@ ali1435_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x23:
#if 0
#ifdef ENABLE_ALI1435_LOG
if (dev->index != 0x03)
ali1435_log("M1435: dev->regs[%02x] = %02x\n", dev->index, val);
#endif
#endif
if (dev->index == 0x03)
dev->cfg_locked = (val != 0x69);
#ifdef ENABLE_ALI1435_LOG
else
ali1435_log("M1435: dev->regs[%02x] = %02x\n", dev->index, val);
#endif
if (!dev->cfg_locked) {
pclog("M1435: dev->regs[%02x] = %02x\n", dev->index, val);
switch (dev->index) {
/* PCI Mechanism select? */
case 0x00:
dev->regs[dev->index] = val;
pclog("PMC = %i\n", val != 0xc8);
pci_set_pmc(val != 0xc8);
ali1435_log("PMC = %i\n", val != 0xc8);
pci_key_write(((val & 0xc8) == 0xc8) ? 0xf0 : 0x00);
break;
/* ???? */
@@ -253,8 +250,6 @@ ali1435_reset(void *priv)
dev->regs[0x00] = 0xff;
pci_set_pmc(0);
dev->cfg_locked = 1;
memset(dev->pci_regs, 0, 256);
@@ -298,17 +293,10 @@ ali1435_init(UNUSED(const device_t *info))
*/
io_sethandler(0x0022, 0x0002, ali1435_read, NULL, NULL, ali1435_write, NULL, NULL, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1435_pci_read, ali1435_pci_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1435_pci_read, ali1435_pci_write, dev, &dev->pci_slot);
ali1435_reset(dev);
#if 0
pci_set_irq_level(PCI_INTA, 0);
pci_set_irq_level(PCI_INTB, 0);
pci_set_irq_level(PCI_INTC, 0);
pci_set_irq_level(PCI_INTD, 0);
#endif
return dev;
}

2
src/chipset/ali1489.c
View File

@@ -622,7 +622,7 @@ ali1489_init(UNUSED(const device_t *info))
io_sethandler(0x0fc, 0x0001, ali1489_ide_read, NULL, NULL, ali1489_ide_write, NULL, NULL, dev);
/* Dummy M1489 PCI device */
dev->pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, ali1489_pci_read, ali1489_pci_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1489_pci_read, ali1489_pci_write, dev, &dev->pci_slot);
device_add(&ide_pci_2ch_device);

7
src/chipset/ali1531.c
View File

@@ -35,6 +35,11 @@
#include <86box/chipset.h>
typedef struct ali1531_t {
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pad1;
uint8_t pci_conf[256];
smram_t *smram;
@@ -374,7 +379,7 @@ ali1531_init(UNUSED(const device_t *info))
ali1531_t *dev = (ali1531_t *) malloc(sizeof(ali1531_t));
memset(dev, 0, sizeof(ali1531_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1531_read, ali1531_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1531_read, ali1531_write, dev, &dev->pci_slot);
dev->smram = smram_add();

7
src/chipset/ali1541.c
View File

@@ -35,6 +35,11 @@
#include <86box/chipset.h>
typedef struct ali1541_t {
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pad1;
uint8_t pci_conf[256];
smram_t *smram;
@@ -641,7 +646,7 @@ ali1541_init(UNUSED(const device_t *info))
ali1541_t *dev = (ali1541_t *) malloc(sizeof(ali1541_t));
memset(dev, 0, sizeof(ali1541_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1541_read, ali1541_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1541_read, ali1541_write, dev, &dev->pci_slot);
dev->smram = smram_add();

15
src/chipset/ali1543.c
View File

@@ -47,6 +47,7 @@
#include <86box/chipset.h>
typedef struct ali1543_t {
uint8_t mirq_states[8];
uint8_t pci_conf[256];
uint8_t pmu_conf[256];
uint8_t usb_conf[256];
@@ -1474,12 +1475,12 @@ ali7101_read(int func, int addr, void *priv)
static void
ali5237_usb_update_interrupt(usb_t* usb, void *priv)
{
const ali1543_t *dev = (ali1543_t *) priv;
ali1543_t *dev = (ali1543_t *) priv;
if (usb->irq_level)
pci_set_mirq(4, !!(dev->pci_conf[0x74] & 0x10));
pci_set_mirq(4, !!(dev->pci_conf[0x74] & 0x10), &dev->mirq_states[4]);
else
pci_clear_mirq(4, !!(dev->pci_conf[0x74] & 0x10));
pci_clear_mirq(4, !!(dev->pci_conf[0x74] & 0x10), &dev->mirq_states[4]);
}
static void
@@ -1595,16 +1596,16 @@ ali1543_init(const device_t *info)
memset(dev, 0, sizeof(ali1543_t));
/* Device 02: M1533 Southbridge */
dev->pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, ali1533_read, ali1533_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE, ali1533_read, ali1533_write, dev, &dev->pci_slot);
/* Device 0B: M5229 IDE Controller*/
dev->ide_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE_IDE, ali5229_read, ali5229_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE_IDE, ali5229_read, ali5229_write, dev, &dev->ide_slot);
/* Device 0C: M7101 Power Managment Controller */
dev->pmu_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE_PMU, ali7101_read, ali7101_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE_PMU, ali7101_read, ali7101_write, dev, &dev->pmu_slot);
/* Device 0F: M5237 USB */
dev->usb_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE_USB, ali5237_read, ali5237_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE_USB, ali5237_read, ali5237_write, dev, &dev->usb_slot);
/* ACPI */
dev->acpi = device_add(&acpi_ali_device);

7
src/chipset/ali1621.c
View File

@@ -36,6 +36,11 @@
#include <86box/chipset.h>
typedef struct ali1621_t {
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pad1;
uint8_t pci_conf[256];
smram_t *smram[2];
@@ -671,7 +676,7 @@ ali1621_init(UNUSED(const device_t *info))
ali1621_t *dev = (ali1621_t *) malloc(sizeof(ali1621_t));
memset(dev, 0, sizeof(ali1621_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1621_read, ali1621_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1621_read, ali1621_write, dev, &dev->pci_slot);
dev->smram[0] = smram_add();
dev->smram[1] = smram_add();

5
src/chipset/ims8848.c
View File

@@ -122,6 +122,9 @@
typedef struct ims8848_t {
uint8_t idx;
uint8_t access_data;
uint8_t pci_slot;
uint8_t pad;
uint8_t regs[256];
uint8_t pci_conf[256];
@@ -392,7 +395,7 @@ ims8848_init(UNUSED(const device_t *info))
PCI Device 0: IMS 8849 Dummy for compatibility reasons
*/
io_sethandler(0x0022, 0x0003, ims8848_read, NULL, NULL, ims8848_write, NULL, NULL, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ims8849_pci_read, ims8849_pci_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ims8849_pci_read, ims8849_pci_write, dev, &dev->pci_slot);
dev->smram = smram_add();
smram_set_separate_smram(1);

7
src/chipset/intel_420ex.c
View File

@@ -52,6 +52,9 @@
typedef struct i420ex_t {
uint8_t has_ide;
uint8_t smram_locked;
uint8_t pci_slot;
uint8_t pad;
uint8_t regs[256];
uint16_t timer_base;
@@ -167,7 +170,7 @@ i420ex_drb_recalc(i420ex_t *dev)
{
uint32_t boundary;
for (uint8_t i = 4; i >= 0; i--)
for (int8_t i = 4; i >= 0; i--)
row_disable(i);
for (uint8_t i = 0; i <= 4; i++) {
@@ -534,7 +537,7 @@ i420ex_init(const device_t *info)
dev->smram = smram_add();
pci_add_card(PCI_ADD_NORTHBRIDGE, i420ex_read, i420ex_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, i420ex_read, i420ex_write, dev, &dev->pci_slot);
dev->has_ide = info->local;

11
src/chipset/intel_4x0.c
View File

@@ -57,6 +57,9 @@ typedef struct i4x0_t {
uint8_t max_drb;
uint8_t drb_unit;
uint8_t drb_default;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t regs[256];
uint8_t regs_locked[256];
uint8_t mem_state[256];
@@ -1241,12 +1244,12 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_440FX:
regs[0x93] = (val & 0x0f);
trc_write(0x0093, val & 0x06, NULL);
pci_write(0x0cf9, val & 0x06, NULL);
break;
case INTEL_440LX:
case INTEL_440EX:
regs[0x93] = (val & 0x0e);
trc_write(0x0093, val & 0x06, NULL);
pci_write(0x0cf9, val & 0x06, NULL);
break;
default:
break;
@@ -1518,7 +1521,7 @@ i4x0_read(int func, int addr, void *priv)
/* Special behavior for 440FX register 0x93 which is basically TRC in PCI space
with the addition of bits 3 and 0. */
if ((func == 0) && (addr == 0x93) && ((dev->type == INTEL_440FX) || (dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)))
ret = (ret & 0xf9) | (trc_read(0x0093, NULL) & 0x06);
ret = (ret & 0xf9) | (pci_read(0x0cf9, NULL) & 0x06);
}
return ret;
@@ -1910,7 +1913,7 @@ i4x0_init(const device_t *info)
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev);
}
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev, &dev->pci_slot);
if ((dev->type >= INTEL_440BX) && !(regs[0x7a] & 0x02)) {
device_add((dev->type == INTEL_440GX) ? &i440gx_agp_device : &i440bx_agp_device);

12
src/chipset/intel_i450kx.c
View File

@@ -62,11 +62,15 @@ i450kx_log(const char *fmt, ...)
typedef struct i450kx_t {
smram_t *smram[2];
uint8_t bus_index;
uint8_t pb_slot;
uint8_t mc_slot;
uint8_t pad;
uint8_t pb_pci_conf[256];
uint8_t mc_pci_conf[256];
uint8_t mem_state[2][256];
uint8_t bus_index;
uint8_t mem_state[2][256];
} i450kx_t;
static void
@@ -801,8 +805,8 @@ i450kx_init(UNUSED(const device_t *info))
{
i450kx_t *dev = (i450kx_t *) malloc(sizeof(i450kx_t));
memset(dev, 0, sizeof(i450kx_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, pb_read, pb_write, dev); /* Device 19h: Intel 450KX PCI Bridge PB */
pci_add_card(PCI_ADD_AGPBRIDGE, mc_read, mc_write, dev); /* Device 14h: Intel 450KX Memory Controller MC */
pci_add_card(PCI_ADD_NORTHBRIDGE, pb_read, pb_write, dev, &dev->pb_slot); /* Device 19h: Intel 450KX PCI Bridge PB */
pci_add_card(PCI_ADD_NORTHBRIDGE_SEC, mc_read, mc_write, dev, &dev->mc_slot); /* Device 14h: Intel 450KX Memory Controller MC */
dev->smram[0] = smram_add();
dev->smram[1] = smram_add();

10
src/chipset/intel_piix.c
View File

@@ -66,7 +66,7 @@ typedef struct _piix_ {
uint8_t max_func;
uint8_t pci_slot;
uint8_t no_mirq0;
uint8_t pad;
uint8_t usb_irq_state;
uint8_t regs[4][256];
uint8_t readout_regs[256];
uint8_t board_config[2];
@@ -1446,12 +1446,12 @@ piix_fast_off_count(void *priv)
static void
piix_usb_update_interrupt(usb_t* usb, void *priv)
{
const piix_t *dev = (piix_t *) priv;
piix_t *dev = (piix_t *) priv;
if (usb->irq_level)
pci_set_irq(dev->pci_slot, PCI_INTD);
pci_set_irq(dev->pci_slot, PCI_INTD, &dev->usb_irq_state);
else
pci_clear_irq(dev->pci_slot, PCI_INTD);
pci_clear_irq(dev->pci_slot, PCI_INTD, &dev->usb_irq_state);
}
static void
@@ -1574,7 +1574,7 @@ piix_init(const device_t *info)
dev->no_mirq0 = (info->local >> 12) & 0x0f;
dev->func0_id = info->local >> 16;
dev->pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, piix_read, piix_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE, piix_read, piix_write, dev, &dev->pci_slot);
piix_log("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot);
piix_log("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot);

6
src/chipset/intel_sio.c
View File

@@ -37,6 +37,10 @@
typedef struct sio_t {
uint8_t id;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t regs[256];
uint16_t timer_base;
@@ -507,7 +511,7 @@ sio_init(const device_t *info)
sio_t *dev = (sio_t *) malloc(sizeof(sio_t));
memset(dev, 0, sizeof(sio_t));
pci_add_card(PCI_ADD_SOUTHBRIDGE, sio_read, sio_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE, sio_read, sio_write, dev, &dev->pci_slot);
dev->id = info->local;

6
src/chipset/opti822.c
View File

@@ -43,6 +43,10 @@
typedef struct opti822_t {
uint8_t irq_convert;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pci_regs[256];
} opti822_t;
@@ -393,7 +397,7 @@ opti822_init(UNUSED(const device_t *info))
opti822_t *dev = (opti822_t *) malloc(sizeof(opti822_t));
memset(dev, 0, sizeof(opti822_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, opti822_pci_read, opti822_pci_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, opti822_pci_read, opti822_pci_write, dev, &dev->pci_slot);
opti822_reset(dev);

18
src/chipset/sis_5511.c
View File

@@ -66,13 +66,15 @@ sis_5511_log(const char *fmt, ...)
#endif
typedef struct sis_5511_t {
uint8_t pci_conf[256];
uint8_t pci_conf_sb[2][256];
uint8_t index;
uint8_t nb_slot;
uint8_t sb_slot;
uint8_t pad;
uint8_t regs[16];
int nb_pci_slot;
int sb_pci_slot;
uint8_t pci_conf[256];
uint8_t pci_conf_sb[2][256];
sff8038i_t *ide_drive[2];
smram_t *smram;
@@ -713,8 +715,8 @@ sis_5511_reset(void *priv)
dev->pci_conf_sb[1][0x0a] = 1;
dev->pci_conf_sb[1][0x0b] = 1;
dev->pci_conf_sb[1][0x0e] = 0x80;
sff_set_slot(dev->ide_drive[0], dev->sb_pci_slot);
sff_set_slot(dev->ide_drive[1], dev->sb_pci_slot);
sff_set_slot(dev->ide_drive[0], dev->sb_slot);
sff_set_slot(dev->ide_drive[1], dev->sb_slot);
sff_bus_master_reset(dev->ide_drive[0], BUS_MASTER_BASE);
sff_bus_master_reset(dev->ide_drive[1], BUS_MASTER_BASE + 8);
}
@@ -734,8 +736,8 @@ sis_5511_init(UNUSED(const device_t *info))
sis_5511_t *dev = (sis_5511_t *) malloc(sizeof(sis_5511_t));
memset(dev, 0, sizeof(sis_5511_t));
dev->nb_pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5511_read, sis_5511_write, dev); /* Device 0: SiS 5511 */
dev->sb_pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5513_read, sis_5513_write, dev); /* Device 1: SiS 5513 */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5511_read, sis_5511_write, dev, &dev->nb_slot); /* Device 0: SiS 5511 */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5513_read, sis_5513_write, dev, &dev->sb_slot); /* Device 1: SiS 5513 */
io_sethandler(0x0022, 0x0002, sis_5513_isa_read, NULL, NULL, sis_5513_isa_write, NULL, NULL, dev); /* Ports 22h-23h: SiS 5513 ISA */
/* MIRQ */

22
src/chipset/sis_5571.c
View File

@@ -75,12 +75,14 @@ sis_5571_log(const char *fmt, ...)
#endif
typedef struct sis_5571_t {
uint8_t nb_slot;
uint8_t sb_slot;
uint8_t pad;
uint8_t usb_irq_state;
uint8_t pci_conf[256];
uint8_t pci_conf_sb[3][256];
int nb_pci_slot;
int sb_pci_slot;
port_92_t *port_92;
sff8038i_t *ide_drive[2];
smram_t *smram;
@@ -670,7 +672,7 @@ pci_isa_bridge_read(int func, int addr, void *priv)
static void
sis_5571_usb_update_interrupt(usb_t* usb, void* priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
sis_5571_t *dev = (sis_5571_t *) priv;
if (dev->pci_conf_sb[0][0x68] & 0x80) {
/* TODO: Is the normal PCI interrupt inhibited when USB IRQ remapping is enabled? */
@@ -691,9 +693,9 @@ sis_5571_usb_update_interrupt(usb_t* usb, void* priv)
}
} else {
if (usb->irq_level)
pci_set_irq(dev->sb_pci_slot, PCI_INTA);
pci_set_irq(dev->sb_slot, PCI_INTA, &dev->usb_irq_state);
else
pci_clear_irq(dev->sb_pci_slot, PCI_INTA);
pci_clear_irq(dev->sb_slot, PCI_INTA, &dev->usb_irq_state);
}
}
@@ -739,8 +741,8 @@ sis_5571_reset(void *priv)
dev->pci_conf_sb[1][0x0b] = 0x01;
dev->pci_conf_sb[1][0x0e] = 0x80;
dev->pci_conf_sb[1][0x4a] = 0x06;
sff_set_slot(dev->ide_drive[0], dev->sb_pci_slot);
sff_set_slot(dev->ide_drive[1], dev->sb_pci_slot);
sff_set_slot(dev->ide_drive[0], dev->sb_slot);
sff_set_slot(dev->ide_drive[1], dev->sb_slot);
sff_bus_master_reset(dev->ide_drive[0], BUS_MASTER_BASE);
sff_bus_master_reset(dev->ide_drive[1], BUS_MASTER_BASE + 8);
@@ -773,8 +775,8 @@ sis_5571_init(UNUSED(const device_t *info))
sis_5571_t *dev = (sis_5571_t *) malloc(sizeof(sis_5571_t));
memset(dev, 0x00, sizeof(sis_5571_t));
dev->nb_pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, memory_pci_bridge_read, memory_pci_bridge_write, dev);
dev->sb_pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, pci_isa_bridge_read, pci_isa_bridge_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, memory_pci_bridge_read, memory_pci_bridge_write, dev, &dev->nb_slot);
pci_add_card(PCI_ADD_SOUTHBRIDGE, pci_isa_bridge_read, pci_isa_bridge_write, dev, &dev->sb_slot);
/* MIRQ */
pci_enable_mirq(0);

6
src/chipset/sis_85c496.c
View File

@@ -45,9 +45,13 @@
typedef struct sis_85c496_t {
uint8_t cur_reg;
uint8_t rmsmiblk_count;
uint8_t pci_slot;
uint8_t pad;
#ifndef USE_DRB_HACK
uint8_t drb_default;
uint8_t drb_bits;
uint8_t pad0;
uint8_t pad1;
#endif
uint8_t regs[127];
uint8_t pci_conf[256];
@@ -648,7 +652,7 @@ static void
dev->pci_conf[0xd0] = 0x78; /* ROM at E0000-FFFFF, Flash enable. */
dev->pci_conf[0xd1] = 0xff;
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev, &dev->pci_slot);
#if 0
sis_85c497_isa_reset(dev);

8
src/chipset/sis_85c50x.c
View File

@@ -59,6 +59,10 @@ sis_85c50x_log(const char *fmt, ...)
typedef struct sis_85c50x_t {
uint8_t index;
uint8_t nb_slot;
uint8_t sb_slot;
uint8_t pad;
uint8_t pci_conf[256];
uint8_t pci_conf_sb[256];
uint8_t regs[256];
@@ -426,10 +430,10 @@ sis_85c50x_init(UNUSED(const device_t *info))
memset(dev, 0x00, sizeof(sis_85c50x_t));
/* 501/502 (Northbridge) */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c50x_read, sis_85c50x_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c50x_read, sis_85c50x_write, dev, &dev->nb_slot);
/* 503 (Southbridge) */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_85c50x_sb_read, sis_85c50x_sb_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_85c50x_sb_read, sis_85c50x_sb_write, dev, &dev->sb_slot);
io_sethandler(0x0022, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
dev->smram[0] = smram_add();

23
src/chipset/stpc.c
View File

@@ -45,6 +45,11 @@
#define STPC_CLIENT 0x100e55cc
typedef struct stpc_t {
uint8_t nb_slot;
uint8_t sb_slot;
uint8_t ide_slot;
uint8_t usb_slot;
uint32_t local;
/* Main registers (port 22h/23h) */
@@ -54,19 +59,19 @@ typedef struct stpc_t {
/* Host bus interface */
uint16_t host_base;
uint8_t host_offset;
uint8_t usb_irq_state;
uint8_t host_regs[256];
/* Local bus */
uint16_t localbus_base;
uint8_t localbus_offset;
uint8_t pad0;
uint8_t localbus_regs[256];
/* PCI devices */
uint8_t pci_conf[4][256];
smram_t *smram;
usb_t *usb;
int ide_slot;
int usb_slot;
sff8038i_t *bm[2];
/* Miscellaneous */
@@ -896,12 +901,12 @@ stpc_setup(stpc_t *dev)
static void
stpc_usb_update_interrupt(usb_t* usb, void* priv)
{
const stpc_t *dev = (stpc_t *) priv;
stpc_t *dev = (stpc_t *) priv;
if (usb->irq_level)
pci_set_irq(dev->usb_slot, PCI_INTA);
pci_set_irq(dev->usb_slot, PCI_INTA, &dev->usb_irq_state);
else
pci_clear_irq(dev->usb_slot, PCI_INTA);
pci_clear_irq(dev->usb_slot, PCI_INTA, &dev->usb_irq_state);
}
static void
@@ -926,16 +931,16 @@ stpc_init(const device_t *info)
dev->local = info->local;
pci_add_card(PCI_ADD_NORTHBRIDGE, stpc_nb_read, stpc_nb_write, dev);
dev->ide_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_isab_read, stpc_isab_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, stpc_nb_read, stpc_nb_write, dev, &dev->nb_slot);
pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_isab_read, stpc_isab_write, dev, &dev->sb_slot);
if (dev->local == STPC_ATLAS) {
dev->usb_params.smi_handle = NULL;
dev->usb_params.update_interrupt = stpc_usb_update_interrupt;
dev->usb_params.parent_priv = dev;
dev->ide_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_ide_read, stpc_ide_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE_IDE, stpc_ide_read, stpc_ide_write, dev, &dev->ide_slot);
dev->usb = device_add_parameters(&usb_device, &dev->usb_params);
dev->usb_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_usb_read, stpc_usb_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE_USB, stpc_usb_read, stpc_usb_write, dev, &dev->usb_slot);
}
dev->bm[0] = device_add_inst(&sff8038i_device, 1);

13
src/chipset/umc_8886.c
View File

@@ -121,8 +121,13 @@ umc_8886_log(const char *fmt, ...)
#define SB_ID dev->sb_id
typedef struct umc_8886_t {
uint8_t max_func; /* Last function number */
uint8_t pci_conf_sb[2][256]; /* PCI Registers */
uint8_t max_func; /* Last function number */
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pci_conf_sb[2][256]; /* PCI Registers */
uint16_t sb_id; /* Southbridge Revision */
int has_ide; /* Check if Southbridge Revision is AF or F */
} umc_8886_t;
@@ -202,7 +207,7 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
case 0x56:
dev->pci_conf_sb[func][addr] = val;
switch (val & 2) {
switch (val & 3) {
case 0:
cpu_set_isa_pci_div(3);
break;
@@ -371,7 +376,7 @@ umc_8886_init(const device_t *info)
memset(dev, 0, sizeof(umc_8886_t));
dev->has_ide = !!(info->local == 0x886a);
pci_add_card(PCI_ADD_SOUTHBRIDGE, umc_8886_read, umc_8886_write, dev); /* Device 12: UMC 8886xx */
pci_add_card(PCI_ADD_SOUTHBRIDGE, umc_8886_read, umc_8886_write, dev, &dev->pci_slot); /* Device 12: UMC 8886xx */
/* Add IDE if UM8886AF variant */
if (HAS_IDE)

4
src/chipset/umc_hb4.c
View File

@@ -146,6 +146,8 @@ typedef struct hb4_t {
uint8_t shadow;
uint8_t shadow_read;
uint8_t shadow_write;
uint8_t pci_slot;
uint8_t pci_conf[256]; /* PCI Registers */
int mem_state[9];
smram_t *smram[3]; /* SMRAM Handlers */
@@ -393,7 +395,7 @@ hb4_init(UNUSED(const device_t *info))
hb4_t *dev = (hb4_t *) malloc(sizeof(hb4_t));
memset(dev, 0, sizeof(hb4_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, hb4_read, hb4_write, dev); /* Device 10: UMC 8881x */
pci_add_card(PCI_ADD_NORTHBRIDGE, hb4_read, hb4_write, dev, &dev->pci_slot); /* Device 10: UMC 8881x */
/* Port 92 */
device_add(&port_92_pci_device);

9
src/chipset/via_apollo.c
View File

@@ -45,10 +45,15 @@
#define VIA_8601 0x86010500
typedef struct via_apollo_t {
uint32_t id;
uint8_t drb_unit;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pci_conf[256];
uint32_t id;
smram_t *smram;
agpgart_t *agpgart;
} via_apollo_t;
@@ -715,7 +720,7 @@ via_apollo_init(const device_t *info)
if (dev->id != VIA_8601)
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
pci_add_card(PCI_ADD_NORTHBRIDGE, via_apollo_read, via_apollo_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, via_apollo_read, via_apollo_write, dev, &dev->pci_slot);
dev->id = info->local;

22
src/chipset/via_pipc.c
View File

@@ -117,9 +117,10 @@ typedef struct {
} pipc_io_trap_t;
typedef struct _pipc_ {
uint32_t local;
uint8_t max_func;
uint8_t max_pcs;
uint8_t pci_slot;
uint8_t pad;
uint8_t pci_isa_regs[256];
uint8_t ide_regs[256];
@@ -129,10 +130,11 @@ typedef struct _pipc_ {
uint8_t fmnmi_regs[4];
uint8_t fmnmi_status;
uint32_t local;
sff8038i_t *bm[2];
nvr_t *nvr;
int nvr_enabled;
int slot;
ddma_t *ddma;
smbus_piix4_t *smbus;
usb_t *usb[2];
@@ -1094,7 +1096,7 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
case 0x47:
if (val & 0x01)
trc_write(0x0047, (val & 0x80) ? 0x06 : 0x04, NULL);
pci_write(0x0cf9, (val & 0x80) ? 0x06 : 0x04, NULL);
pic_set_shadow(!!(val & 0x10));
pic_elcr_io_handler(!!(val & 0x20));
dev->pci_isa_regs[0x47] = val & 0xfe;
@@ -1620,6 +1622,14 @@ pipc_reset(void *priv)
pipc_write(0, 0x44, 0x00, priv);
pipc_write(0, 0x77, 0x00, priv);
sff_set_slot(dev->bm[0], dev->pci_slot);
sff_set_slot(dev->bm[1], dev->pci_slot);
if (dev->local >= VIA_PIPC_686A)
ac97_via_set_slot(dev->ac97, dev->pci_slot, PCI_INTC);
if (dev->acpi)
acpi_set_slot(dev->acpi, dev->pci_slot);
}
static void *
@@ -1631,16 +1641,14 @@ pipc_init(const device_t *info)
pipc_log("PIPC: init()\n");
dev->local = info->local;
dev->slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, pipc_read, pipc_write, dev);
pci_add_card(PCI_ADD_SOUTHBRIDGE, pipc_read, pipc_write, dev, &dev->pci_slot);
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
sff_set_slot(dev->bm[0], dev->slot);
sff_set_irq_mode(dev->bm[0], 0, 0);
sff_set_irq_mode(dev->bm[0], 1, 0);
sff_set_irq_pin(dev->bm[0], PCI_INTA);
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
sff_set_slot(dev->bm[1], dev->slot);
sff_set_irq_mode(dev->bm[1], 0, 0);
sff_set_irq_mode(dev->bm[1], 1, 0);
sff_set_irq_pin(dev->bm[1], PCI_INTA);
@@ -1665,7 +1673,6 @@ pipc_init(const device_t *info)
dev->usb[1] = device_add_inst(&usb_device, 2);
dev->ac97 = device_add(&ac97_via_device);
ac97_via_set_slot(dev->ac97, dev->slot, PCI_INTC);
dev->sb = device_add_inst(&sb_pro_compat_device, 2);
sound_add_handler(pipc_sb_get_buffer, dev);
@@ -1695,7 +1702,6 @@ pipc_init(const device_t *info)
dev->ddma = device_add(&ddma_device);
if (dev->acpi) {
acpi_set_slot(dev->acpi, dev->slot);
acpi_set_nvr(dev->acpi, dev->nvr);
acpi_init_gporeg(dev->acpi, 0xff, 0xbf, 0xff, 0x7f);

6
src/chipset/via_vt82c505.c
View File

@@ -32,6 +32,10 @@
typedef struct vt82c505_t {
uint8_t index;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pci_conf[256];
} vt82c505_t;
@@ -203,7 +207,7 @@ vt82c505_init(UNUSED(const device_t *info))
vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
memset(dev, 0, sizeof(vt82c505_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, vt82c505_read, vt82c505_write, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, vt82c505_read, vt82c505_write, dev, &dev->pci_slot);
dev->pci_conf[0x00] = 0x06;
dev->pci_conf[0x01] = 0x11;

35
src/device/kbc_at.c
View File

@@ -128,6 +128,10 @@ typedef struct atkbc_t {
uint8_t channel;
uint8_t stat_hi;
uint8_t pending;
uint8_t irq_state;
uint8_t pad;
uint8_t pad0;
uint8_t pad1;
uint8_t mem[0x100];
@@ -347,15 +351,15 @@ kbc_send_to_ob(atkbc_t *dev, uint8_t val, uint8_t channel, uint8_t stat_hi)
dev->status |= STAT_MFULL;
if (dev->mem[0x20] & 0x02)
picint_common(1 << 12, 0, 1);
picint_common(1 << 1, 0, 0);
picint_common(1 << 12, 0, 1, NULL);
picint_common(1 << 1, 0, 0, NULL);
} else {
if (dev->mem[0x20] & 0x01)
picint_common(1 << 1, 0, 1);
picint_common(1 << 12, 0, 0);
picint_common(1 << 1, 0, 1, NULL);
picint_common(1 << 12, 0, 0, NULL);
}
} else if (dev->mem[0x20] & 0x01)
picintlevel(1 << 1); /* AT KBC: IRQ 1 is level-triggered because it is tied to OBF. */
picintlevel(1 << 1, &dev->irq_state); /* AT KBC: IRQ 1 is level-triggered because it is tied to OBF. */
dev->ob = temp;
}
@@ -720,10 +724,10 @@ write_p2(atkbc_t *dev, uint8_t val)
/* PS/2: Handle IRQ's. */
if (dev->misc_flags & FLAG_PS2) {
/* IRQ 12 */
picint_common(1 << 12, 0, val & 0x20);
picint_common(1 << 12, 0, val & 0x20, NULL);
/* IRQ 1 */
picint_common(1 << 1, 0, val & 0x10);
picint_common(1 << 1, 0, val & 0x10, NULL);
}
#endif
@@ -1550,7 +1554,8 @@ kbc_at_process_cmd(void *priv)
/* TODO: Proper P1 implementation, with OR and AND flags in the machine table. */
dev->p1 = dev->p1 & 0xff;
write_p2(dev, 0x4b);
picintc(0x1002);
picintc(0x1000);
picintc(0x0002);
}
dev->status = (dev->status & 0x0f) | 0x60;
@@ -1569,7 +1574,8 @@ kbc_at_process_cmd(void *priv)
/* TODO: Proper P1 implementation, with OR and AND flags in the machine table. */
dev->p1 = dev->p1 & 0xff;
write_p2(dev, 0xcf);
picintc(0x0002);
picintclevel(0x0002, &dev->irq_state);
dev->irq_state = 0;
}
dev->status = (dev->status & 0x0f) | 0x60;
@@ -1852,7 +1858,7 @@ kbc_at_read(uint16_t port, void *priv)
/* TODO: IRQ is only tied to OBF on the AT KBC, on the PS/2 KBC, it is controlled by a P2 bit.
This also means that in AT mode, the IRQ is level-triggered. */
if (!(dev->misc_flags & FLAG_PS2))
picintc(1 << 1);
picintclevel(1 << 1, &dev->irq_state);
break;
case 0x64:
@@ -1901,8 +1907,13 @@ kbc_at_reset(void *priv)
if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) {
dev->misc_flags |= FLAG_PS2;
kbc_at_do_poll = kbc_at_poll_ps2;
} else
picintc(0x1000);
picintc(0x0002);
} else {
kbc_at_do_poll = kbc_at_poll_at;
picintclevel(0x0002, &dev->irq_state);
dev->irq_state = 0;
}
dev->misc_flags |= FLAG_CACHE;
@@ -1924,8 +1935,6 @@ kbc_at_close(void *priv)
atkbc_t *dev = (atkbc_t *) priv;
int max_ports = ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) ? 2 : 1;
kbc_at_reset(dev);
/* Stop timers. */
timer_disable(&dev->send_delay_timer);

7
src/device/pci_bridge.c
View File

@@ -54,7 +54,7 @@ typedef struct pci_bridge_t {
uint8_t regs[256];
uint8_t bus_index;
int slot;
uint8_t slot;
} pci_bridge_t;
#ifdef ENABLE_PCI_BRIDGE_LOG
@@ -493,7 +493,10 @@ pci_bridge_init(const device_t *info)
pci_bridge_reset(dev);
dev->slot = pci_add_card(AGP_BRIDGE(dev->local) ? PCI_ADD_AGPBRIDGE : PCI_ADD_BRIDGE, pci_bridge_read, pci_bridge_write, dev);
if (AGP_BRIDGE(dev->local))
pci_add_card(PCI_ADD_AGPBRIDGE, pci_bridge_read, pci_bridge_write, dev, &dev->slot);
else
dev->slot = pci_add_bridge(pci_bridge_read, pci_bridge_write, dev);
interrupt_count = sizeof(interrupts);
interrupt_mask = interrupt_count - 1;

16
src/device/serial.c
View File

@@ -48,6 +48,8 @@ enum {
SERIAL_INT_TIMEOUT = 16
};
void serial_update_ints(serial_t *dev);
static int next_inst = 0;
static serial_device_t serial_devices[SERIAL_MAX];
@@ -84,6 +86,8 @@ serial_reset_port(serial_t *dev)
dev->out_new = 0xffff;
memset(dev->xmit_fifo, 0, 16);
memset(dev->rcvr_fifo, 0, 16);
serial_update_ints(dev);
dev->irq_state = 0;
}
void
@@ -133,11 +137,15 @@ serial_update_ints(serial_t *dev)
if (stat && (dev->irq != 0xff) && ((dev->mctrl & 8) || (dev->type == SERIAL_8250_PCJR))) {
if (dev->type >= SERIAL_16450)
picintlevel(1 << dev->irq);
else
picintlevel(1 << dev->irq, &dev->irq_state);
else
picint(1 << dev->irq);
} else
picintc(1 << dev->irq);
} else {
if (dev->type >= SERIAL_16450)
picintclevel(1 << dev->irq, &dev->irq_state);
else
picintc(1 << dev->irq);
}
}
static void

16
src/disk/hdc_ide_cmd640.c
View File

@@ -42,9 +42,12 @@ typedef struct cmd640_t {
uint8_t id;
uint8_t in_cfg;
uint8_t channels;
uint8_t pci, regs[256];
uint8_t pci;
uint8_t irq_state;
uint8_t pci_slot;
uint8_t pad0;
uint8_t regs[256];
uint32_t local;
int slot;
int irq_mode[2];
int irq_pin;
int irq_line;
@@ -95,12 +98,12 @@ cmd640_set_irq(int channel, void *priv)
if (irq) {
if (dev->irq_mode[channel] == 1)
pci_set_irq(dev->slot, dev->irq_pin);
pci_set_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
else
picint(1 << (14 + channel));
} else {
if (dev->irq_mode[channel] == 1)
pci_clear_irq(dev->slot, dev->irq_pin);
pci_clear_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
else
picintc(1 << (14 + channel));
}
@@ -500,7 +503,10 @@ cmd640_init(const device_t *info)
if (info->flags & DEVICE_PCI) {
device_add(&ide_pci_2ch_device);
dev->slot = pci_add_card(PCI_ADD_IDE, cmd640_pci_read, cmd640_pci_write, dev);
if (info->local & 0x80000)
pci_add_card(PCI_ADD_NORMAL, cmd640_pci_read, cmd640_pci_write, dev, &dev->pci_slot);
else
pci_add_card(PCI_ADD_IDE, cmd640_pci_read, cmd640_pci_write, dev, &dev->pci_slot);
if (dev->channels & 0x01)
ide_set_bus_master(0, NULL, cmd640_set_irq, dev);

17
src/disk/hdc_ide_cmd646.c
View File

@@ -41,11 +41,16 @@ typedef struct cmd646_t {
uint8_t vlb_idx;
uint8_t single_channel;
uint8_t in_cfg;
uint8_t pci_slot;
uint8_t regs[256];
uint32_t local;
int slot;
int irq_mode[2];
int irq_pin;
int irq_mode[2];
sff8038i_t *bm[2];
} cmd646_t;
@@ -102,6 +107,9 @@ cmd646_ide_handlers(cmd646_t *dev)
uint16_t side;
int irq_mode[2] = { 0, 0 };
sff_set_slot(dev->bm[0], dev->pci_slot);
sff_set_slot(dev->bm[1], dev->pci_slot);
ide_pri_disable();
if ((dev->regs[0x09] & 0x01) && (dev->regs[0x50] & 0x40)) {
@@ -382,7 +390,10 @@ cmd646_init(const device_t *info)
device_add(&ide_pci_2ch_device);
dev->slot = pci_add_card(PCI_ADD_IDE, cmd646_pci_read, cmd646_pci_write, dev);
if (info->local & 0x80000)
pci_add_card(PCI_ADD_NORMAL, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);
else
pci_add_card(PCI_ADD_IDE, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);
dev->single_channel = !!(info->local & 0x20000);

18
src/disk/hdc_ide_sff8038i.c
View File

@@ -409,31 +409,31 @@ sff_bus_master_set_irq(int channel, void *priv)
case 1:
/* Native PCI IRQ mode with interrupt pin. */
if (irq)
pci_set_irq(dev->slot, dev->irq_pin);
pci_set_irq(dev->slot, dev->irq_pin, &dev->irq_state);
else
pci_clear_irq(dev->slot, dev->irq_pin);
pci_clear_irq(dev->slot, dev->irq_pin, &dev->irq_state);
break;
case 2:
case 5:
/* MIRQ 0 or 1. */
if (irq)
pci_set_mirq(dev->irq_mode[channel] & 1, 0);
pci_set_mirq(dev->irq_mode[channel] & 1, 0, &dev->irq_state);
else
pci_clear_mirq(dev->irq_mode[channel] & 1, 0);
pci_clear_mirq(dev->irq_mode[channel] & 1, 0, &dev->irq_state);
break;
case 3:
/* Native PCI IRQ mode with specified interrupt line. */
if (irq)
picintlevel(1 << dev->irq_line);
picintlevel(1 << dev->irq_line, &dev->irq_state);
else
picintc(1 << dev->irq_line);
picintclevel(1 << dev->irq_line, &dev->irq_state);
break;
case 4:
/* ALi Aladdin Native PCI INTAJ mode. */
if (irq)
pci_set_mirq(channel + 2, dev->irq_level[channel]);
pci_set_mirq(channel + 2, dev->irq_level[channel], &dev->irq_state);
else
pci_clear_mirq(channel + 2, dev->irq_level[channel]);
pci_clear_mirq(channel + 2, dev->irq_level[channel], &dev->irq_state);
break;
}
}
@@ -456,6 +456,7 @@ sff_bus_master_reset(sff8038i_t *dev, uint16_t old_base)
dev->addr = 0x00000000;
dev->ptr0 = 0x00;
dev->count = dev->eot = 0x00000000;
dev->irq_state = 0;
ide_pri_disable();
ide_sec_disable();
@@ -570,6 +571,7 @@ sff_init(UNUSED(const device_t *info))
dev->irq_pin = PCI_INTA;
dev->irq_line = 14;
dev->irq_level[0] = dev->irq_level[1] = 0;
dev->irq_state = 0;
next_id++;

2
src/disk/hdd_image.c
View File

@@ -450,7 +450,7 @@ retry_vhd:
else
fatal("hdd_image_load(): VHD: Error opening VHD file '%s': %s\n", fn, mvhd_strerr(vhd_error));
} else if (vhd_error == MVHD_ERR_TIMESTAMP) {
fatal("hdd_image_load(): VHD: Parent/child timestamp mismatch for VHD file '%s'\n", fn);
pclog("hdd_image_load(): VHD: Parent/child timestamp mismatch for VHD file '%s'\n", fn);
}
hdd[id].tracks = hdd_images[id].vhd->footer.geom.cyl;

3
src/include/86box/acpi.h
View File

@@ -113,7 +113,8 @@ typedef struct acpi_regs_t {
typedef struct acpi_t {
acpi_regs_t regs;
uint8_t gpireg2_default;
uint8_t pad[3];
uint8_t irq_state;
uint8_t pad[2];
uint8_t gporeg_default[4];
uint8_t suspend_types[8];
uint16_t io_base;

4
src/include/86box/hdc_ide_sff8038i.h
View File

@@ -26,11 +26,11 @@ typedef struct sff8038i_t {
uint8_t ptr0;
uint8_t enabled;
uint8_t dma_mode;
uint8_t irq_state;
uint8_t pad;
uint8_t pad0;
uint8_t pad1;
uint16_t base;
uint16_t pad2;
uint16_t pad1;
uint32_t ptr;
uint32_t ptr_cur;
uint32_t addr;

300
src/include/86box/pci.h
View File

@@ -11,146 +11,260 @@
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2016-2020 Miran Grca.
* Copyright 2017-2020 Fred N. van Kempen.
* Copyright 2008-2020 Sarah Walker.
* Copyright 2023 Miran Grca.
*/
#ifndef EMU_PCI_H
#define EMU_PCI_H
#define PCI_REG_COMMAND 0x04
#define PCI_REG_VENDOR_ID_L 0x00
#define PCI_REG_VENDOR_ID_H 0x01
#define PCI_REG_DEVICE_ID_L 0x02
#define PCI_REG_DEVICE_ID_H 0x03
#define PCI_REG_COMMAND_L 0x04
#define PCI_REG_COMMAND_H 0x05
#define PCI_REG_STATUS_L 0x06
#define PCI_REG_STATUS_H 0x07
#define PCI_REG_REVISION 0x08
#define PCI_REG_PROG_IF 0x09
#define PCI_REG_SUBCLASS 0x0a
#define PCI_REG_CLASS 0x0b
#define PCI_REG_CACHELINE_SIZE 0x0c
#define PCI_REG_LATENCY_TIMER 0x0d
#define PCI_REG_HEADER_TYPE 0x0e
#define PCI_REG_BIST 0x0f
#define PCI_COMMAND_IO 0x01
#define PCI_COMMAND_MEM 0x02
#define PCI_COMMAND_L_IO 0x01
#define PCI_COMMAND_L_MEM 0x02
#define PCI_COMMAND_L_BM 0x04
#define PCI_COMMAND_L_SPECIAL 0x08
#define PCI_COMMAND_L_MEM_WIEN 0x10
#define PCI_COMMAND_L_VGASNOOP 0x20
#define PCI_COMMAND_L_PARITY 0x40
#define PCI_NO_IRQ_STEERING 0x8000
#define PCI_CAN_SWITCH_TYPE 0x10000
#define PCI_NO_BRIDGES 0x20000
#define PCI_ALWAYS_EXPOSE_DEV0 0x40000
#define PCI_COMMAND_H_SERR 0x01
#define PCI_COMMAND_H_FAST_B2B 0x02
#define PCI_COMMAND_H_INT_DIS 0x04
#define PCI_CONFIG_TYPE_1 1
#define PCI_CONFIG_TYPE_2 2
#define PCI_STATUS_L_INT 0x08
#define PCI_STATUS_L_CAPAB 0x10
#define PCI_STATUS_L_66MHZ 0x20
#define PCI_STATUS_L_FAST_B2B 0x80
#define PCI_CONFIG_TYPE_MASK 0x7fff
#define PCI_STATUS_H_MDPERR 0x01 /* Master Data Parity Error */
#define PCI_STATUS_H_DEVSEL 0x06
#define PCI_STATUS_H_STA 0x08 /* Signaled Target Abort */
#define PCI_STATUS_H_RTA 0x10 /* Received Target Abort */
#define PCI_STATUS_H_RMA 0x20 /* Received Master Abort */
#define PCI_STATUS_H_SSE 0x40 /* Signaled System Error */
#define PCI_STATUS_H_DPERR 0x80 /* Detected Parity Error */
#define PCI_INTA 1
#define PCI_INTB 2
#define PCI_INTC 3
#define PCI_INTD 4
#define PCI_DEVSEL_FAST 0x00
#define PCI_DEVSEL_MEDIUM 0x02
#define PCI_DEVSEL_SLOW 0x04
#define PCI_MIRQ0 0
#define PCI_MIRQ1 1
#define PCI_MIRQ2 2
#define PCI_MIRQ3 3
#define PCI_MIRQ4 4
#define PCI_MIRQ5 5
#define PCI_MIRQ6 6
#define PCI_MIRQ7 7
#define FLAG_MECHANISM_1 0x00000001
#define FLAG_MECHANISM_2 0x00000002
#define FLAG_MECHANISM_SWITCH 0x00000004
#define FLAG_CONFIG_IO_ON 0x00000008
#define FLAG_CONFIG_DEV0_IO_ON 0x00000010
#define FLAG_CONFIG_M1_IO_ON 0x00000020
#define FLAG_NO_IRQ_STEERING 0x00000040
#define FLAG_NO_BRIDGES 0x00000080
#define PCI_IRQ_DISABLED -1
#define FLAG_MECHANISM_MASK FLAG_MECHANISM_1 | FLAG_MECHANISM_2
#define FLAG_MASK 0x0000007f
#define PCI_ADD_STRICT 0x80
#define PCI_INTA 1
#define PCI_INTB 2
#define PCI_INTC 3
#define PCI_INTD 4
#define PCI_MIRQ0 0
#define PCI_MIRQ1 1
#define PCI_MIRQ2 2
#define PCI_MIRQ3 3
#define PCI_MIRQ4 4
#define PCI_MIRQ5 5
#define PCI_MIRQ6 6
#define PCI_MIRQ7 7
#define PCI_IRQ_DISABLED -1
#define PCI_ADD_STRICT 0x40
#define PCI_ADD_MASK (PCI_ADD_STRICT - 1)
#define PCI_ADD_VFIO 0x80
#define PCI_ADD_VFIO_MASK (PCI_ADD_VFIO - 1)
#define PCI_CARD_VFIO PCI_ADD_VFIO
#define PCI_BUS_INVALID 0xff
#define PCI_IGNORE_NO_SLOT 0xff
/* The number of an invalid PCI card. */
#define PCI_CARD_INVALID 0xef
/* PCI cards (currently 32). */
#define PCI_CARDS_NUM 0x20
#define PCI_CARD_MAX (PCI_CARDS_NUM - 1)
/* The number of PCI card INT pins - always at 4 per the PCI specification. */
#define PCI_INT_PINS_NUM 4
/* The base for MIRQ lines accepted by pci_irq(). */
#define PCI_MIRQ_BASE PCI_CARDS_NUM
/* PCI MIRQ lines (currently 8, this many are needed by the ALi M1543(C). */
#define PCI_MIRQS_NUM 8
#define PCI_MIRQ_MAX (PCI_MIRQS_NUM - 1)
/* The base for direct IRQ lines accepted by pci_irq(). */
#define PCI_DIRQ_BASE 0xf0
/* PCI direct IRQ lines (currently 16 because we only emulate the legacy PIC). */
#define PCI_DIRQS_NUM 16
#define PCI_DIRQ_MAX (PCI_DIRQS_NUM - 1)
/* PCI IRQ routings (currently 16, this many are needed by the OPTi 822). */
#define PCI_IRQS_NUM 16
#define PCI_IRQ_MAX (PCI_IRQS_NUM - 1)
/* Legacy flags. */
#define PCI_REG_COMMAND PCI_REG_COMMAND_L
#define PCI_COMMAND_IO PCI_COMMAND_L_IO
#define PCI_COMMAND_MEM PCI_COMMAND_L_MEM
#define PCI_CONFIG_TYPE_1 FLAG_MECHANISM_1
#define PCI_CONFIG_TYPE_2 FLAG_MECHANISM_2
#define PCI_CAN_SWITCH_TYPE FLAG_MECHANISM_SWITCH
#define PCI_ALWAYS_EXPOSE_DEV0 FLAG_CONFIG_DEV0_IO_ON
#define PCI_NO_IRQ_STEERING FLAG_NO_IRQ_STEERING
#define PCI_NO_BRIDGES FLAG_NO_BRIDGES
#define PCI_CONFIG_TYPE_MASK FLAG_MECHANISM_MASK
#define bar_t pci_bar_t
#define trc_init pci_trc_init
#define pci_register_slot(card, type, inta, intb, intc, intd) \
pci_register_bus_slot(0, card, type, inta, intb, intc, intd)
#define pci_set_mirq(mirq, level, irq_state) \
pci_irq(PCI_MIRQ_BASE | mirq, 0, level, 1, irq_state)
#define pci_set_irq(slot, pci_int, irq_state) \
pci_irq(slot, pci_int, 0, 1, irq_state)
#define pci_clear_mirq(mirq, level, irq_state) \
pci_irq(PCI_MIRQ_BASE | mirq, 0, level, 0, irq_state)
#define pci_clear_irq(slot, pci_int, irq_state) \
pci_irq(slot, pci_int, 0, 0, irq_state)
enum {
PCI_CARD_NORTHBRIDGE = 0,
PCI_CARD_AGPBRIDGE = 1,
PCI_CARD_SOUTHBRIDGE = 2,
PCI_CARD_SOUTHBRIDGE_IDE = 3,
PCI_CARD_SOUTHBRIDGE_PMU = 4,
PCI_CARD_SOUTHBRIDGE_USB = 5,
PCI_CARD_NORTHBRIDGE_SEC = 1,
PCI_CARD_AGPBRIDGE = 2,
PCI_CARD_SOUTHBRIDGE = 3,
PCI_CARD_SOUTHBRIDGE_IDE = 4,
PCI_CARD_SOUTHBRIDGE_PMU = 5,
PCI_CARD_SOUTHBRIDGE_USB = 6,
PCI_CARD_AGP = 0x0f,
PCI_CARD_NORMAL = 0x10,
PCI_CARD_VIDEO = 0x11,
PCI_CARD_SCSI = 0x12,
PCI_CARD_SOUND = 0x13,
PCI_CARD_IDE = 0x14,
PCI_CARD_NETWORK = 0x15,
PCI_CARD_BRIDGE = 0x16
PCI_CARD_HANGUL = 0x12,
PCI_CARD_IDE = 0x13,
PCI_CARD_SCSI = 0x14,
PCI_CARD_SOUND = 0x15,
PCI_CARD_MODEM = 0x16,
PCI_CARD_NETWORK = 0x17,
PCI_CARD_UART = 0x18,
PCI_CARD_USB = 0x19,
PCI_CARD_BRIDGE = 0x1a
};
enum {
PCI_ADD_NORTHBRIDGE = 0,
PCI_ADD_AGPBRIDGE = 1,
PCI_ADD_SOUTHBRIDGE = 2,
PCI_ADD_SOUTHBRIDGE_IDE = 3,
PCI_ADD_SOUTHBRIDGE_PMU = 4,
PCI_ADD_SOUTHBRIDGE_USB = 5,
PCI_ADD_NORTHBRIDGE_SEC = 1,
PCI_ADD_AGPBRIDGE = 2,
PCI_ADD_SOUTHBRIDGE = 3,
PCI_ADD_SOUTHBRIDGE_IDE = 4,
PCI_ADD_SOUTHBRIDGE_PMU = 5,
PCI_ADD_SOUTHBRIDGE_USB = 6,
PCI_ADD_AGP = 0x0f,
PCI_ADD_NORMAL = 0x10,
PCI_ADD_VIDEO = 0x11,
PCI_ADD_SCSI = 0x12,
PCI_ADD_SOUND = 0x13,
PCI_ADD_IDE = 0x14,
PCI_ADD_NETWORK = 0x15,
PCI_ADD_BRIDGE = 0x16
PCI_ADD_HANGUL = 0x12,
PCI_ADD_IDE = 0x13,
PCI_ADD_SCSI = 0x14,
PCI_ADD_SOUND = 0x15,
PCI_ADD_MODEM = 0x16,
PCI_ADD_NETWORK = 0x17,
PCI_ADD_UART = 0x18,
PCI_ADD_USB = 0x19,
PCI_ADD_BRIDGE = 0x1a
};
typedef union {
uint32_t addr;
uint8_t addr_regs[4];
} bar_t;
} pci_bar_t;
extern int pci_burst_time;
extern int agp_burst_time;
extern int pci_nonburst_time;
extern int agp_nonburst_time;
#define PCI_IO_ON 0x01
#define PCI_IO_DEV0 0x02
extern int pci_flags;
extern uint32_t pci_base;
extern uint32_t pci_size;
extern int pci_burst_time;
extern int agp_burst_time;
extern int pci_nonburst_time;
extern int agp_nonburst_time;
extern int pci_take_over_io;
extern void pci_set_irq_routing(int pci_int, int irq);
extern void pci_set_irq_level(int pci_int, int level);
extern void pci_enable_mirq(int mirq);
extern void pci_set_mirq_routing(int mirq, int irq);
extern uint32_t pci_base;
extern uint32_t pci_size;
/* PCI raise IRQ: the first parameter is slot if < PCI_MIRQ_BASE, MIRQ if >= PCI_MIRQ_BASE
and < PCI_DIRQ_BASE, and direct IRQ line if >= PCI_DIRQ_BASE (RichardG's
hack that may no longer be needed). */
extern void pci_irq(uint8_t slot, uint8_t pci_int, int level, int set, uint8_t *irq_state);
extern uint8_t pci_get_int(uint8_t slot, uint8_t pci_int);
extern void pci_type2_write(uint16_t port, uint8_t val, void *priv);
extern void pci_type2_writew(uint16_t port, uint16_t val, void *priv);
extern void pci_type2_writel(uint16_t port, uint32_t val, void *priv);
extern uint8_t pci_type2_read(uint16_t port, void *priv);
extern uint16_t pci_type2_readw(uint16_t port, void *priv);
extern uint32_t pci_type2_readl(uint16_t port, void *priv);
/* Relocate a PCI device to a new slot, required for the configurable
IDSEL's of ALi M1543(c). */
extern void pci_relocate_slot(int type, int new_slot);
extern void pci_set_irq_routing(int pci_int, int irq);
extern void pci_set_irq_level(int pci_int, int level);
/* Write PCI enable/disable key, split for the ALi M1435. */
extern void pci_key_write(uint8_t val);
extern void pci_enable_mirq(int mirq);
extern void pci_set_mirq_routing(int mirq, int irq);
/* Set PMC (ie. change PCI configuration mechanism), 0 = #2, 1 = #1. */
extern void pci_set_pmc(uint8_t pmc);
extern int pci_irq_is_level(int irq);
extern void pci_pic_reset(void);
extern void pci_reset(void);
extern void pci_set_mirq(uint8_t mirq, int level);
extern void pci_set_irq(uint8_t card, uint8_t pci_int);
extern void pci_clear_mirq(uint8_t mirq, int level);
extern void pci_clear_irq(uint8_t card, uint8_t pci_int);
extern uint8_t pci_get_int(uint8_t card, uint8_t pci_int);
/* Needed for the io.c handling of configuration mechanism #2 ports C000-CFFF. */
extern void pci_write(uint16_t port, uint8_t val, void *priv);
extern void pci_writew(uint16_t port, uint16_t val, void *priv);
extern void pci_writel(uint16_t port, uint32_t val, void *priv);
extern uint8_t pci_read(uint16_t port, void *priv);
extern uint16_t pci_readw(uint16_t port, void *priv);
extern uint32_t pci_readl(uint16_t port, void *priv);
extern void pci_reset(void);
extern void pci_init(int type);
extern uint8_t pci_register_bus(void);
extern void pci_set_pmc(uint8_t pmc);
extern void pci_remap_bus(uint8_t bus_index, uint8_t bus_number);
extern void pci_relocate_slot(int type, int new_slot);
extern void pci_register_slot(int card, int type,
int inta, int intb, int intc, int intd);
extern void pci_register_bus_slot(int bus, int card, int type,
int inta, int intb, int intc, int intd);
extern void pci_close(void);
extern uint8_t pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv);
extern uint8_t pci_register_bus(void);
extern void pci_remap_bus(uint8_t bus_index, uint8_t bus_number);
extern void pci_register_bus_slot(int bus, int card, int type, int inta, int intb, int intc, int intd);
extern void trc_init(void);
/* Add a PCI card. */
extern void pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot);
extern uint8_t trc_read(uint16_t port, void *priv);
extern void trc_write(uint16_t port, uint8_t val, void *priv);
/* Add an instance of the PCI bridge. */
extern uint8_t pci_add_bridge(uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv);
extern void pci_bridge_set_ctl(void *priv, uint8_t ctl);
/* Register the cards that have been added into slots. */
extern void pci_register_cards(void);
extern void pci_pic_reset(void);
extern void pci_init(int flags);
/* PCI bridge stuff. */
extern void pci_bridge_set_ctl(void *priv, uint8_t ctl);
#ifdef EMU_DEVICE_H
extern const device_t dec21150_device;

32
src/include/86box/pic.h
View File

@@ -19,6 +19,13 @@
#ifndef EMU_PIC_H
#define EMU_PIC_H
typedef struct pic_latch {
uint8_t d;
uint8_t e;
uint8_t q;
uint8_t nq;
} pic_latch_t;
typedef struct pic {
uint8_t icw1;
uint8_t icw2;
@@ -38,8 +45,13 @@ typedef struct pic {
uint8_t special_mask_mode;
uint8_t auto_eoi_rotate;
uint8_t interrupt;
uint8_t lines;
uint8_t data_bus;
uint8_t irq_latch;
uint8_t has_slaves;
uint8_t flags;
uint8_t edge_lines;
uint8_t pad;
uint32_t lines[8];
uint32_t at;
struct pic *slaves[8];
} pic_t;
@@ -70,12 +82,22 @@ extern void pic2_init(void);
extern void pic_reset(void);
extern int picint_is_level(int irq);
extern void picint_common(uint16_t num, int level, int set);
extern void picint(uint16_t num);
extern void picintlevel(uint16_t num);
extern void picintc(uint16_t num);
extern void picint_common(uint16_t num, int level, int set, uint8_t *irq_state);
extern int picinterrupt(void);
#define PIC_IRQ_EDGE 0
#define PIC_IRQ_LEVEL 1
#define PIC_SLAVE_PENDING 0x01
#define PIC_FREEZE 0x02
#define PIC_MASTER_CLEAR 0x04
/* Legacy defines. */
#define picint(num) picint_common(num, PIC_IRQ_EDGE, 1, NULL)
#define picintlevel(num, irq_state) picint_common(num, PIC_IRQ_LEVEL, 1, irq_state)
#define picintc(num) picint_common(num, PIC_IRQ_EDGE, 0, NULL)
#define picintclevel(num, irq_state) picint_common(num, PIC_IRQ_LEVEL, 0, irq_state)
extern uint8_t pic_irq_ack(void);
#endif /*EMU_PIC_H*/

6
src/include/86box/scsi_x54x.h
View File

@@ -396,6 +396,10 @@ typedef struct x54x_t {
uint8_t setup_info_len;
uint8_t max_id;
uint8_t pci_slot;
uint8_t irq_state;
uint8_t pad;
uint8_t pad0;
uint8_t pad1;
uint8_t temp_cdb[12];
/* for multi-threading, keep these volatile */
@@ -437,7 +441,7 @@ typedef struct x54x_t {
volatile int PendingInterrupt;
volatile int Lock;
volatile int target_data_len;
volatile int pad0;
volatile int pad2;
uint32_t Base;
uint32_t fdc_address;

4
src/include/86box/serial.h
View File

@@ -74,13 +74,13 @@ typedef struct serial_s {
uint8_t out;
uint8_t msr_set;
uint8_t pad;
uint8_t irq_state;
uint8_t pad0;
uint8_t pad1;
uint16_t dlab;
uint16_t base_address;
uint16_t out_new;
uint16_t pad2;
uint16_t pad1;
uint8_t rcvr_fifo_pos;
uint8_t xmit_fifo_pos;

16
src/include/86box/vid_8514a.h
View File

@@ -31,9 +31,13 @@ typedef struct ibm8514_t {
uint32_t vram_mask;
PALETTE vgapal;
uint8_t dac_mask, dac_status;
uint8_t dac_mask;
uint8_t dac_status;
uint32_t *map8;
int dac_addr, dac_pos, dac_r, dac_g;
int dac_addr;
int dac_pos;
int dac_r;
int dac_g;
int internal_pitch;
struct {
@@ -83,11 +87,11 @@ typedef struct ibm8514_t {
int16_t dy;
int16_t err;
uint32_t src;
uint16_t dest;
uint32_t dest;
uint32_t newsrc_blt;
uint16_t newdest_blt;
uint32_t newdest_blt;
uint32_t newdest_in;
uint16_t newdest_out;
uint32_t newdest_out;
uint8_t *writemono;
uint8_t *nibbleset;
int x_count;
@@ -143,7 +147,7 @@ typedef struct ibm8514_t {
uint8_t *vram;
uint8_t *changedvram;
uint8_t linedbl;
uint8_t linedbl;
uint8_t data_available;
uint8_t data_available2;

10
src/include/86box/vid_cga.h
View File

@@ -69,12 +69,12 @@ typedef struct cga_t {
} cga_t;
void cga_init(cga_t *cga);
void cga_out(uint16_t addr, uint8_t val, void *p);
uint8_t cga_in(uint16_t addr, void *p);
void cga_write(uint32_t addr, uint8_t val, void *p);
uint8_t cga_read(uint32_t addr, void *p);
void cga_out(uint16_t addr, uint8_t val, void *priv);
uint8_t cga_in(uint16_t addr, void *priv);
void cga_write(uint32_t addr, uint8_t val, void *priv);
uint8_t cga_read(uint32_t addr, void *priv);
void cga_recalctimings(cga_t *cga);
void cga_poll(void *p);
void cga_poll(void *priv);
#ifdef EMU_DEVICE_H
extern const device_config_t cga_config[];

8
src/include/86box/vid_cga_comp.h
View File

@@ -21,13 +21,11 @@
#ifndef VIDEO_CGA_COMP_H
#define VIDEO_CGA_COMP_H
#define Bit8u uint8_t
#define Bit32u uint32_t
#define Bitu unsigned int
#define bool uint8_t
#define Bitu unsigned int
#define bool uint8_t
void update_cga16_color(uint8_t cgamode);
void cga_comp_init(int revision);
Bit32u *Composite_Process(uint8_t cgamode, Bit8u border, Bit32u blocks /*, bool doublewidth*/, Bit32u *TempLine);
Bit32u *Composite_Process(uint8_t cgamode, uint8_t border, uint32_t blocks /*, bool doublewidth*/, uint32_t *TempLine);
#endif /*VIDEO_CGA_COMP_H*/

2
src/include/86box/vid_ega_render_remap.h
View File

@@ -85,7 +85,7 @@ ega_recalc_remap_func(ega_t *ega)
func_nr = VAR_DWORD_MODE;
else if (ega->crtc[0x17] & 0x40)
func_nr = VAR_BYTE_MODE;
else if ((ega->crtc[0x17] & 0x20) && ega->vram_limit > 64*1024)
else if ((ega->crtc[0x17] & 0x20) && ega->vram_limit > 64 * 1024)
func_nr = VAR_WORD_MODE_MA15;
else
func_nr = VAR_WORD_MODE_MA13;

10
src/include/86box/vid_mda.h
View File

@@ -52,12 +52,12 @@ typedef struct mda_t {
void mda_init(mda_t *mda);
void mda_setcol(int chr, int blink, int fg, uint8_t cga_ink);
void mda_out(uint16_t addr, uint8_t val, void *p);
uint8_t mda_in(uint16_t addr, void *p);
void mda_write(uint32_t addr, uint8_t val, void *p);
uint8_t mda_read(uint32_t addr, void *p);
void mda_out(uint16_t addr, uint8_t val, void *priv);
uint8_t mda_in(uint16_t addr, void *priv);
void mda_write(uint32_t addr, uint8_t val, void *priv);
uint8_t mda_read(uint32_t addr, void *priv);
void mda_recalctimings(mda_t *mda);
void mda_poll(void *p);
void mda_poll(void *priv);
#ifdef EMU_DEVICE_H
extern const device_t mda_device;

190
src/include/86box/vid_svga.h
View File

@@ -31,7 +31,7 @@
# define FLAG_NOSKEW 16
# define FLAG_ADDR_BY16 32
# define FLAG_RAMDAC_SHIFT 64
# define FLAG_ATI 128
# define FLAG_ATI 128
# define FLAG_S3_911_16BIT 256
# define FLAG_512K_MASK 512
struct monitor_t;
@@ -144,24 +144,24 @@ typedef struct svga_t {
For the example memory map, decode_mask would be 4MB-1 (4MB address space), vram_max would be 2MB
(present video memory only responds to first 2MB), vram_mask would be 1MB-1 (video memory wraps at 1MB)
*/
uint32_t decode_mask;
uint32_t vram_max;
uint32_t vram_mask;
uint32_t charseta;
uint32_t charsetb;
uint32_t adv_flags;
uint32_t ma_latch;
uint32_t ca_adj;
uint32_t ma;
uint32_t maback;
uint32_t write_bank;
uint32_t read_bank;
uint32_t extra_banks[2];
uint32_t banked_mask;
uint32_t ca;
uint32_t overscan_color;
uint32_t decode_mask;
uint32_t vram_max;
uint32_t vram_mask;
uint32_t charseta;
uint32_t charsetb;
uint32_t adv_flags;
uint32_t ma_latch;
uint32_t ca_adj;
uint32_t ma;
uint32_t maback;
uint32_t write_bank;
uint32_t read_bank;
uint32_t extra_banks[2];
uint32_t banked_mask;
uint32_t ca;
uint32_t overscan_color;
uint32_t *map8;
uint32_t pallook[512];
uint32_t pallook[512];
PALETTE vgapal;
@@ -183,8 +183,8 @@ typedef struct svga_t {
void (*render)(struct svga_t *svga);
void (*recalctimings_ex)(struct svga_t *svga);
void (*video_out)(uint16_t addr, uint8_t val, void *p);
uint8_t (*video_in)(uint16_t addr, void *p);
void (*video_out)(uint16_t addr, uint8_t val, void *priv);
uint8_t (*video_in)(uint16_t addr, void *priv);
void (*hwcursor_draw)(struct svga_t *svga, int displine);
@@ -195,7 +195,7 @@ typedef struct svga_t {
void (*vblank_start)(struct svga_t *svga);
void (*ven_write)(struct svga_t *svga, uint8_t val, uint32_t addr);
float (*getclock)(int clock, void *p);
float (*getclock)(int clock, void *priv);
/* Called when VC=R18 and friends. If this returns zero then MA resetting
is skipped. Matrox Mystique in Power mode reuses this counter for
@@ -205,17 +205,17 @@ typedef struct svga_t {
/*Called at the start of vertical sync*/
void (*vsync_callback)(struct svga_t *svga);
uint32_t (*translate_address)(uint32_t addr, void *p);
uint32_t (*translate_address)(uint32_t addr, void *priv);
/*If set then another device is driving the monitor output and the SVGA
card should not attempt to display anything */
int override;
void *priv;
uint8_t crtc[256];
uint8_t gdcreg[256];
uint8_t attrregs[32];
uint8_t seqregs[256];
uint8_t egapal[16];
uint8_t crtc[256];
uint8_t gdcreg[256];
uint8_t attrregs[32];
uint8_t seqregs[256];
uint8_t egapal[16];
uint8_t *vram;
uint8_t *changedvram;
@@ -266,55 +266,55 @@ typedef struct svga_t {
uint8_t monitor_index;
/* Pointer to monitor */
monitor_t* monitor;
monitor_t *monitor;
} svga_t;
extern int vga_on;
extern int ibm8514_on;
extern void ibm8514_poll(ibm8514_t *dev, svga_t *svga);
extern void ibm8514_recalctimings(svga_t *svga);
extern uint8_t ibm8514_ramdac_in(uint16_t port, void *p);
extern void ibm8514_ramdac_out(uint16_t port, uint8_t val, void *p);
extern int ibm8514_cpu_src(svga_t *svga);
extern int ibm8514_cpu_dest(svga_t *svga);
extern void ibm8514_accel_out_pixtrans(svga_t *svga, uint16_t port, uint16_t val, int len);
extern void ibm8514_short_stroke_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, svga_t *svga, uint8_t ssv, int len);
extern void ibm8514_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, svga_t *svga, int len);
extern void ibm8514_poll(ibm8514_t *dev, svga_t *svga);
extern void ibm8514_recalctimings(svga_t *svga);
extern uint8_t ibm8514_ramdac_in(uint16_t port, void *priv);
extern void ibm8514_ramdac_out(uint16_t port, uint8_t val, void *priv);
extern int ibm8514_cpu_src(svga_t *svga);
extern int ibm8514_cpu_dest(svga_t *svga);
extern void ibm8514_accel_out_pixtrans(svga_t *svga, uint16_t port, uint16_t val, int len);
extern void ibm8514_short_stroke_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, svga_t *svga, uint8_t ssv, int len);
extern void ibm8514_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, svga_t *svga, int len);
extern void xga_poll(xga_t *xga, svga_t *svga);
extern void xga_recalctimings(svga_t *svga);
extern int svga_init(const device_t *info, svga_t *svga, void *p, int memsize,
extern int svga_init(const device_t *info, svga_t *svga, void *priv, int memsize,
void (*recalctimings_ex)(struct svga_t *svga),
uint8_t (*video_in)(uint16_t addr, void *p),
void (*video_out)(uint16_t addr, uint8_t val, void *p),
uint8_t (*video_in)(uint16_t addr, void *priv),
void (*video_out)(uint16_t addr, uint8_t val, void *priv),
void (*hwcursor_draw)(struct svga_t *svga, int displine),
void (*overlay_draw)(struct svga_t *svga, int displine));
extern void svga_recalctimings(svga_t *svga);
extern void svga_close(svga_t *svga);
uint8_t svga_read(uint32_t addr, void *p);
uint16_t svga_readw(uint32_t addr, void *p);
uint32_t svga_readl(uint32_t addr, void *p);
void svga_write(uint32_t addr, uint8_t val, void *p);
void svga_writew(uint32_t addr, uint16_t val, void *p);
void svga_writel(uint32_t addr, uint32_t val, void *p);
uint8_t svga_read_linear(uint32_t addr, void *p);
uint8_t svga_readb_linear(uint32_t addr, void *p);
uint16_t svga_readw_linear(uint32_t addr, void *p);
uint32_t svga_readl_linear(uint32_t addr, void *p);
void svga_write_linear(uint32_t addr, uint8_t val, void *p);
void svga_writeb_linear(uint32_t addr, uint8_t val, void *p);
void svga_writew_linear(uint32_t addr, uint16_t val, void *p);
void svga_writel_linear(uint32_t addr, uint32_t val, void *p);
uint8_t svga_read(uint32_t addr, void *priv);
uint16_t svga_readw(uint32_t addr, void *priv);
uint32_t svga_readl(uint32_t addr, void *priv);
void svga_write(uint32_t addr, uint8_t val, void *priv);
void svga_writew(uint32_t addr, uint16_t val, void *priv);
void svga_writel(uint32_t addr, uint32_t val, void *priv);
uint8_t svga_read_linear(uint32_t addr, void *priv);
uint8_t svga_readb_linear(uint32_t addr, void *priv);
uint16_t svga_readw_linear(uint32_t addr, void *priv);
uint32_t svga_readl_linear(uint32_t addr, void *priv);
void svga_write_linear(uint32_t addr, uint8_t val, void *priv);
void svga_writeb_linear(uint32_t addr, uint8_t val, void *priv);
void svga_writew_linear(uint32_t addr, uint16_t val, void *priv);
void svga_writel_linear(uint32_t addr, uint32_t val, void *priv);
void svga_add_status_info(char *s, int max_len, void *p);
void svga_add_status_info(char *s, int max_len, void *priv);
extern uint8_t svga_rotate[8][256];
void svga_out(uint16_t addr, uint8_t val, void *p);
uint8_t svga_in(uint16_t addr, void *p);
void svga_out(uint16_t addr, uint8_t val, void *priv);
uint8_t svga_in(uint16_t addr, void *priv);
svga_t *svga_get_pri(void);
void svga_set_override(svga_t *svga, int val);
@@ -334,65 +334,65 @@ enum {
/* We need a way to add a device with a pointer to a parent device so it can attach itself to it, and
possibly also a second ATi 68860 RAM DAC type that auto-sets SVGA render on RAM DAC render change. */
extern void ati68860_ramdac_out(uint16_t addr, uint8_t val, void *p, svga_t *svga);
extern uint8_t ati68860_ramdac_in(uint16_t addr, void *p, svga_t *svga);
extern void ati68860_set_ramdac_type(void *p, int type);
extern void ati68860_ramdac_set_render(void *p, svga_t *svga);
extern void ati68860_ramdac_set_pallook(void *p, int i, uint32_t col);
extern void ati68860_ramdac_out(uint16_t addr, uint8_t val, void *priv, svga_t *svga);
extern uint8_t ati68860_ramdac_in(uint16_t addr, void *priv, svga_t *svga);
extern void ati68860_set_ramdac_type(void *priv, int type);
extern void ati68860_ramdac_set_render(void *priv, svga_t *svga);
extern void ati68860_ramdac_set_pallook(void *priv, int i, uint32_t col);
extern void ati68860_hwcursor_draw(svga_t *svga, int displine);
extern void att49x_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *p, svga_t *svga);
extern uint8_t att49x_ramdac_in(uint16_t addr, int rs2, void *p, svga_t *svga);
extern void att49x_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga);
extern uint8_t att49x_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga);
extern void att498_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *p, svga_t *svga);
extern uint8_t att498_ramdac_in(uint16_t addr, int rs2, void *p, svga_t *svga);
extern float av9194_getclock(int clock, void *p);
extern void att498_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga);
extern uint8_t att498_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga);
extern float av9194_getclock(int clock, void *priv);
extern void bt48x_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *p, svga_t *svga);
extern uint8_t bt48x_ramdac_in(uint16_t addr, int rs2, int rs3, void *p, svga_t *svga);
extern void bt48x_recalctimings(void *p, svga_t *svga);
extern void bt48x_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *priv, svga_t *svga);
extern uint8_t bt48x_ramdac_in(uint16_t addr, int rs2, int rs3, void *priv, svga_t *svga);
extern void bt48x_recalctimings(void *priv, svga_t *svga);
extern void bt48x_hwcursor_draw(svga_t *svga, int displine);
extern void ibm_rgb528_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *p, svga_t *svga);
extern uint8_t ibm_rgb528_ramdac_in(uint16_t addr, int rs2, void *p, svga_t *svga);
extern void ibm_rgb528_recalctimings(void *p, svga_t *svga);
extern void ibm_rgb528_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga);
extern uint8_t ibm_rgb528_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga);
extern void ibm_rgb528_recalctimings(void *priv, svga_t *svga);
extern void ibm_rgb528_hwcursor_draw(svga_t *svga, int displine);
extern void icd2061_write(void *p, int val);
extern float icd2061_getclock(int clock, void *p);
extern void icd2061_write(void *priv, int val);
extern float icd2061_getclock(int clock, void *priv);
/* The code is the same, the #define's are so that the correct name can be used. */
# define ics9161_write icd2061_write
# define ics9161_getclock icd2061_getclock
extern float ics2494_getclock(int clock, void *p);
extern float ics2494_getclock(int clock, void *priv);
extern void ics2595_write(void *p, int strobe, int dat);
extern double ics2595_getclock(void *p);
extern void ics2595_setclock(void *p, double clock);
extern void ics2595_write(void *priv, int strobe, int dat);
extern double ics2595_getclock(void *priv);
extern void ics2595_setclock(void *priv, double clock);
extern void sc1148x_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *p, svga_t *svga);
extern uint8_t sc1148x_ramdac_in(uint16_t addr, int rs2, void *p, svga_t *svga);
extern void sc1148x_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga);
extern uint8_t sc1148x_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga);
extern void sc1502x_ramdac_out(uint16_t addr, uint8_t val, void *p, svga_t *svga);
extern uint8_t sc1502x_ramdac_in(uint16_t addr, void *p, svga_t *svga);
extern void sc1502x_ramdac_out(uint16_t addr, uint8_t val, void *priv, svga_t *svga);
extern uint8_t sc1502x_ramdac_in(uint16_t addr, void *priv, svga_t *svga);
extern void sdac_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *p, svga_t *svga);
extern uint8_t sdac_ramdac_in(uint16_t addr, int rs2, void *p, svga_t *svga);
extern float sdac_getclock(int clock, void *p);
extern void sdac_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga);
extern uint8_t sdac_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga);
extern float sdac_getclock(int clock, void *priv);
extern void stg_ramdac_out(uint16_t addr, uint8_t val, void *p, svga_t *svga);
extern uint8_t stg_ramdac_in(uint16_t addr, void *p, svga_t *svga);
extern float stg_getclock(int clock, void *p);
extern void stg_ramdac_out(uint16_t addr, uint8_t val, void *priv, svga_t *svga);
extern uint8_t stg_ramdac_in(uint16_t addr, void *priv, svga_t *svga);
extern float stg_getclock(int clock, void *priv);
extern void tkd8001_ramdac_out(uint16_t addr, uint8_t val, void *p, svga_t *svga);
extern uint8_t tkd8001_ramdac_in(uint16_t addr, void *p, svga_t *svga);
extern void tkd8001_ramdac_out(uint16_t addr, uint8_t val, void *priv, svga_t *svga);
extern uint8_t tkd8001_ramdac_in(uint16_t addr, void *priv, svga_t *svga);
extern void tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *p, svga_t *svga);
extern uint8_t tvp3026_ramdac_in(uint16_t addr, int rs2, int rs3, void *p, svga_t *svga);
extern void tvp3026_recalctimings(void *p, svga_t *svga);
extern void tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *priv, svga_t *svga);
extern uint8_t tvp3026_ramdac_in(uint16_t addr, int rs2, int rs3, void *priv, svga_t *svga);
extern void tvp3026_recalctimings(void *priv, svga_t *svga);
extern void tvp3026_hwcursor_draw(svga_t *svga, int displine);
extern float tvp3026_getclock(int clock, void *p);
extern float tvp3026_getclock(int clock, void *priv);
# ifdef EMU_DEVICE_H
extern const device_t ati68860_ramdac_device;

4
src/include/86box/vid_vga.h
View File

@@ -30,7 +30,7 @@ typedef struct vga_t {
static video_timings_t timing_vga = { VIDEO_ISA, 8, 16, 32, 8, 16, 32 };
void vga_out(uint16_t addr, uint8_t val, void *p);
uint8_t vga_in(uint16_t addr, void *p);
void vga_out(uint16_t addr, uint8_t val, void *priv);
uint8_t vga_in(uint16_t addr, void *priv);
#endif /*VIDEO_VGA_H*/

2
src/include/86box/vid_voodoo_common.h
View File

@@ -271,6 +271,8 @@ typedef struct voodoo_t {
int pci_enable;
uint8_t pci_slot;
uint8_t dac_data[8];
int dac_reg;
int dac_reg_ff;

136
src/include/86box/vid_xga.h
View File

@@ -20,7 +20,7 @@
#include <86box/rom.h>
typedef struct {
typedef struct xga_hwcursor_t {
int ena;
int x;
int y;
@@ -36,12 +36,15 @@ typedef struct xga_t {
mem_mapping_t linear_mapping;
mem_mapping_t video_mapping;
rom_t bios_rom;
rom_t vga_bios_rom;
xga_hwcursor_t hwcursor, hwcursor_latch;
rom_t vga_bios_rom;
xga_hwcursor_t hwcursor;
xga_hwcursor_t hwcursor_latch;
PALETTE extpal;
uint8_t test, atest[2], testpixel;
;
uint8_t test;
uint8_t atest[2];
uint8_t testpixel;
uint8_t pos_regs[8];
uint8_t disp_addr;
uint8_t cfg_reg;
@@ -54,34 +57,44 @@ typedef struct xga_t {
uint8_t regs_idx;
uint8_t hwc_hotspot_x;
uint8_t hwc_hotspot_y;
uint8_t disp_cntl_1, disp_cntl_2;
uint8_t clk_sel_1, clk_sel_2;
uint8_t disp_cntl_1;
uint8_t disp_cntl_2;
uint8_t clk_sel_1;
uint8_t clk_sel_2;
uint8_t hwc_control;
uint8_t bus_arb;
uint8_t isa_pos_enable;
uint8_t hwcursor_oddeven;
uint8_t cfg_reg_instance;
uint8_t rowcount;
uint8_t pal_idx, pal_idx_prefetch;
uint8_t pal_idx;
uint8_t pal_idx_prefetch;
uint8_t pal_seq;
uint8_t pal_mask;
uint8_t pal_r, pal_r_prefetch;
uint8_t pal_g, pal_g_prefetch;
uint8_t pal_b, pal_b_prefetch;
uint8_t pal_r;
uint8_t pal_r_prefetch;
uint8_t pal_g;
uint8_t pal_g_prefetch;
uint8_t pal_b;
uint8_t pal_b_prefetch;
uint8_t sprite_data[1024];
uint8_t scrollcache;
uint8_t border_color;
uint8_t direct_color;
uint8_t dma_channel;
uint8_t instance_isa, instance_num, ext_mem_addr;
uint8_t *vram, *changedvram;
uint8_t instance_isa;
uint8_t instance_num;
uint8_t ext_mem_addr;
uint8_t *vram;
uint8_t *changedvram;
int16_t hwc_pos_x;
int16_t hwc_pos_y;
uint16_t pos_idx;
uint16_t htotal;
uint16_t sprite_idx, sprite_idx_prefetch;
uint16_t sprite_idx;
uint16_t sprite_idx_prefetch;
uint16_t hdisp;
uint16_t vtotal;
uint16_t vdispend;
@@ -89,41 +102,74 @@ typedef struct xga_t {
uint16_t vsyncstart;
uint16_t linecmp;
uint16_t pix_map_width;
uint16_t sprite_pal_addr_idx, old_pal_addr_idx;
uint16_t sprite_pal_addr_idx;
uint16_t old_pal_addr_idx;
uint16_t sprite_pal_addr_idx_prefetch;
int v_total, dispend, v_syncstart, split, v_blankstart,
h_disp, h_disp_old, h_total, h_disp_time, rowoffset,
dispon, h_disp_on, vc, sc, linepos, oddeven, firstline, lastline,
firstline_draw, lastline_draw, displine, fullchange, interlace,
char_width, hwcursor_on;
int pal_pos, pal_pos_prefetch;
int v_total;
int dispend;
int v_syncstart;
int split;
int v_blankstart;
int h_disp;
int h_disp_old;
int h_total;
int h_disp_time;
int rowoffset;
int dispon;
int h_disp_on;
int vc;
int sc;
int linepos;
int oddeven;
int firstline;
int lastline;
int firstline_draw;
int lastline_draw;
int displine;
int fullchange;
int interlace;
int char_width;
int hwcursor_on;
int pal_pos;
int pal_pos_prefetch;
int on;
int op_mode_reset, linear_endian_reverse;
int sprite_pos, sprite_pos_prefetch, cursor_data_on;
int pal_test, a5_test;
int type, bus;
int op_mode_reset;
int linear_endian_reverse;
int sprite_pos;
int sprite_pos_prefetch;
int cursor_data_on;
int pal_test;
int a5_test;
int type;
int bus;
uint32_t linear_base, linear_size, banked_mask;
uint32_t linear_base;
uint32_t linear_size;
uint32_t banked_mask;
uint32_t base_addr_1mb;
uint32_t hwc_color0, hwc_color1;
uint32_t hwc_color0;
uint32_t hwc_color1;
uint32_t disp_start_addr;
uint32_t ma_latch;
uint32_t vram_size;
uint32_t vram_mask;
uint32_t rom_addr;
uint32_t ma, maback;
uint32_t ma;
uint32_t maback;
uint32_t extpallook[256];
uint32_t read_bank, write_bank;
uint32_t read_bank;
uint32_t write_bank;
uint32_t px_map_base;
uint64_t dispontime, dispofftime;
uint64_t dispontime;
uint64_t dispofftime;
struct
{
struct {
uint8_t control;
uint8_t px_map_idx;
uint8_t frgd_mix, bkgd_mix;
uint8_t frgd_mix;
uint8_t bkgd_mix;
uint8_t cc_cond;
uint8_t octant;
uint8_t draw_mode;
@@ -134,15 +180,19 @@ typedef struct xga_t {
uint8_t short_stroke_vector4;
int16_t bres_err_term;
int16_t bres_k1, bres_k2;
int16_t bres_k1;
int16_t bres_k2;
uint16_t blt_width;
uint16_t blt_height;
uint16_t mask_map_origin_x_off;
uint16_t mask_map_origin_y_off;
uint16_t src_map_x, src_map_y;
uint16_t dst_map_x, dst_map_y;
uint16_t pat_map_x, pat_map_y;
uint16_t src_map_x;
uint16_t src_map_y;
uint16_t dst_map_x;
uint16_t dst_map_y;
uint16_t pat_map_x;
uint16_t pat_map_y;
int ssv_state;
int pat_src;
@@ -150,7 +200,14 @@ typedef struct xga_t {
int dst_map;
int bkgd_src;
int fore_src;
int x, y, sx, sy, dx, dy, px, py;
int x;
int y;
int sx;
int sy;
int dx;
int dy;
int px;
int py;
int pattern;
int command_len;
@@ -158,7 +215,8 @@ typedef struct xga_t {
uint32_t color_cmp;
uint32_t carry_chain;
uint32_t plane_mask;
uint32_t frgd_color, bkgd_color;
uint32_t frgd_color;
uint32_t bkgd_color;
uint32_t command;
uint32_t dir_cmd;

48
src/io.c
View File

@@ -288,12 +288,12 @@ inb(uint16_t port)
int found = 0;
int qfound = 0;
if ((pci_take_over_io & PCI_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
ret = pci_type2_read(port, NULL);
if ((pci_flags & FLAG_CONFIG_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
ret = pci_read(port, NULL);
found = 1;
qfound = 1;
} else if ((pci_take_over_io & PCI_IO_DEV0) && (port >= 0xc000) && (port < 0xc100)) {
ret = pci_type2_read(port, NULL);
} else if ((pci_flags & FLAG_CONFIG_DEV0_IO_ON) && (port >= 0xc000) && (port < 0xc100)) {
ret = pci_read(port, NULL);
found = 1;
qfound = 1;
} else {
@@ -340,12 +340,12 @@ outb(uint16_t port, uint8_t val)
int found = 0;
int qfound = 0;
if ((pci_take_over_io & PCI_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
pci_type2_write(port, val, NULL);
if ((pci_flags & FLAG_CONFIG_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
pci_write(port, val, NULL);
found = 1;
qfound = 1;
} else if ((pci_take_over_io & PCI_IO_DEV0) && (port >= 0xc000) && (port < 0xc100)) {
pci_type2_write(port, val, NULL);
} else if ((pci_flags & FLAG_CONFIG_DEV0_IO_ON) && (port >= 0xc000) && (port < 0xc100)) {
pci_write(port, val, NULL);
found = 1;
qfound = 1;
} else {
@@ -384,12 +384,12 @@ inw(uint16_t port)
int qfound = 0;
uint8_t ret8[2];
if ((pci_take_over_io & PCI_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
ret = pci_type2_readw(port, NULL);
if ((pci_flags & FLAG_CONFIG_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
ret = pci_readw(port, NULL);
found = 2;
qfound = 1;
} else if ((pci_take_over_io & PCI_IO_DEV0) && (port >= 0xc000) && (port < 0xc100)) {
ret = pci_type2_readw(port, NULL);
} else if ((pci_flags & FLAG_CONFIG_DEV0_IO_ON) && (port >= 0xc000) && (port < 0xc100)) {
ret = pci_readw(port, NULL);
found = 2;
qfound = 1;
} else {
@@ -446,12 +446,12 @@ outw(uint16_t port, uint16_t val)
int found = 0;
int qfound = 0;
if ((pci_take_over_io & PCI_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
pci_type2_writew(port, val, NULL);
if ((pci_flags & FLAG_CONFIG_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
pci_writew(port, val, NULL);
found = 2;
qfound = 1;
} else if ((pci_take_over_io & PCI_IO_DEV0) && (port >= 0xc000) && (port < 0xc100)) {
pci_type2_writew(port, val, NULL);
} else if ((pci_flags & FLAG_CONFIG_DEV0_IO_ON) && (port >= 0xc000) && (port < 0xc100)) {
pci_writew(port, val, NULL);
found = 2;
qfound = 1;
} else {
@@ -504,12 +504,12 @@ inl(uint16_t port)
int found = 0;
int qfound = 0;
if ((pci_take_over_io & PCI_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
ret = pci_type2_readl(port, NULL);
if ((pci_flags & FLAG_CONFIG_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
ret = pci_readl(port, NULL);
found = 4;
qfound = 1;
} else if ((pci_take_over_io & PCI_IO_DEV0) && (port >= 0xc000) && (port < 0xc100)) {
ret = pci_type2_readl(port, NULL);
} else if ((pci_flags & FLAG_CONFIG_DEV0_IO_ON) && (port >= 0xc000) && (port < 0xc100)) {
ret = pci_readl(port, NULL);
found = 4;
qfound = 1;
} else {
@@ -594,12 +594,12 @@ outl(uint16_t port, uint32_t val)
int qfound = 0;
int i = 0;
if ((pci_take_over_io & PCI_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
pci_type2_writel(port, val, NULL);
if ((pci_flags & FLAG_CONFIG_IO_ON) && (port >= pci_base) && (port < (pci_base + pci_size))) {
pci_writel(port, val, NULL);
found = 4;
qfound = 1;
} else if ((pci_take_over_io & PCI_IO_DEV0) && (port >= 0xc000) && (port < 0xc100)) {
pci_type2_writel(port, val, NULL);
} else if ((pci_flags & FLAG_CONFIG_DEV0_IO_ON) && (port >= 0xc000) && (port < 0xc100)) {
pci_writel(port, val, NULL);
found = 4;
qfound = 1;
} else {

14
src/machine/m_at_386dx_486.c
View File

@@ -1527,11 +1527,11 @@ machine_at_pcm5330_init(const machine_t *model)
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_SOUTHBRIDGE_IDE, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&stpc_serial_device);
device_add(&w83977f_370_device);
device_add(&keyboard_ps2_ami_pci_device);
@@ -1738,7 +1738,7 @@ machine_at_ms4134_init(const machine_t *model)
device_add(&fdc37c665_ide_pri_device);
pci_init(PCI_CAN_SWITCH_TYPE | PCI_ALWAYS_EXPOSE_DEV0);
pci_init(FLAG_MECHANISM_1 | FLAG_MECHANISM_2 | PCI_ALWAYS_EXPOSE_DEV0);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_SCSI, 4, 1, 2, 3);
@@ -1772,7 +1772,7 @@ machine_at_tg486gp_init(const machine_t *model)
device_add(&fdc37c665_ide_pri_device);
pci_init(PCI_CAN_SWITCH_TYPE | PCI_ALWAYS_EXPOSE_DEV0);
pci_init(FLAG_MECHANISM_1 | FLAG_MECHANISM_2 | PCI_ALWAYS_EXPOSE_DEV0);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);

2
src/machine/machine.c
View File

@@ -108,7 +108,7 @@ machine_init_ex(int m)
/* Reset the fast off stuff. */
cpu_fast_off_reset();
pci_take_over_io = 0x00000000;
pci_flags = 0x00000000;
}
/* All good, boot the machine! */

2
src/mem/row.c
View File

@@ -214,7 +214,7 @@ row_reset(UNUSED(void *priv))
uint32_t boundary;
uint32_t shift;
for (uint8_t i = (rows_num - 1); i >= 0; i--)
for (int8_t i = (rows_num - 1); i >= 0; i--)
row_disable(i);
for (uint8_t i = 0; i < rows_num; i++) {

54
src/network/net_ne2000.c
View File

@@ -97,36 +97,45 @@ static uint8_t rtl8019as_pnp_rom[] = {
typedef struct nic_t {
dp8390_t *dp8390;
const char *name;
uint8_t pnp_csnsav;
uint8_t pci_slot;
uint8_t irq_state;
uint8_t pad;
/* RTL8019AS/RTL8029AS registers */
uint8_t config0;
uint8_t config2;
uint8_t config3;
uint8_t _9346cr;
uint8_t pci_regs[PCI_REGSIZE];
uint8_t eeprom[128]; /* for RTL8029AS */
uint8_t maclocal[6]; /* configured MAC (local) address */
/* POS registers, MCA boards only */
uint8_t pos_regs[8];
int board;
int is_pci;
int is_mca;
int is_8bit;
uint32_t base_address;
int base_irq;
int has_bios;
uint32_t base_address;
uint32_t bios_addr;
uint32_t bios_size;
uint32_t bios_mask;
int card; /* PCI card slot */
int has_bios;
int pad;
bar_t pci_bar[2];
uint8_t pci_regs[PCI_REGSIZE];
uint8_t eeprom[128]; /* for RTL8029AS */
rom_t bios_rom;
void *pnp_card;
uint8_t pnp_csnsav;
uint8_t maclocal[6]; /* configured MAC (local) address */
/* RTL8019AS/RTL8029AS registers */
uint8_t config0;
uint8_t config2;
uint8_t config3;
uint8_t _9346cr;
uint32_t pad0;
/* POS registers, MCA boards only */
uint8_t pos_regs[8];
} nic_t;
#ifdef ENABLE_NE2K_LOG
@@ -150,13 +159,13 @@ nelog(int lvl, const char *fmt, ...)
static void
nic_interrupt(void *priv, int set)
{
const nic_t *dev = (nic_t *) priv;
nic_t *dev = (nic_t *) priv;
if (dev->is_pci) {
if (set)
pci_set_irq(dev->card, PCI_INTA);
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
else
pci_clear_irq(dev->card, PCI_INTA);
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
} else {
if (set)
picint(1 << dev->base_irq);
@@ -1087,8 +1096,7 @@ nic_init(const device_t *info)
mem_mapping_disable(&dev->bios_rom.mapping);
/* Add device to the PCI bus, keep its slot number. */
dev->card = pci_add_card(PCI_ADD_NORMAL,
nic_pci_read, nic_pci_write, dev);
pci_add_card(PCI_ADD_NORMAL, nic_pci_read, nic_pci_write, dev, &dev->pci_slot);
}
/* Initialize the RTL8029 EEPROM. */

10
src/network/net_pcnet.c
View File

@@ -216,7 +216,8 @@ typedef struct {
uint32_t base_address;
int base_irq;
int dma_channel;
int card; /* PCI card slot */
uint8_t pci_slot; /* PCI card slot */
uint8_t irq_state;
int xmit_pos;
/** Register Address Pointer */
uint32_t u32RAP;
@@ -413,9 +414,9 @@ pcnet_do_irq(nic_t *dev, int issue)
{
if (dev->is_pci) {
if (issue)
pci_set_irq(dev->card, PCI_INTA);
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
else
pci_clear_irq(dev->card, PCI_INTA);
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
} else {
if (issue)
picint(1 << dev->base_irq);
@@ -2995,8 +2996,7 @@ pcnet_init(const device_t *info)
pcnet_pci_regs[0x04] = 3;
/* Add device to the PCI bus, keep its slot number. */
dev->card = pci_add_card(PCI_ADD_NORMAL,
pcnet_pci_read, pcnet_pci_write, dev);
pci_add_card(PCI_ADD_NORMAL, pcnet_pci_read, pcnet_pci_write, dev, &dev->pci_slot);
} else if (dev->board == DEV_AM79C961) {
dev->dma_channel = -1;

108
src/nvr_at.c
View File

@@ -306,7 +306,7 @@ typedef struct local_t {
uint8_t read_addr;
uint8_t wp_0d;
uint8_t wp_32;
uint8_t pad;
uint8_t irq_state;
uint8_t pad0;
uint8_t addr[8];
@@ -434,6 +434,21 @@ check_alarm_via(nvr_t *nvr, int8_t addr, int8_t addr_2)
return 1;
}
static void
timer_update_irq(nvr_t *nvr)
{
local_t *local = (local_t *) nvr->data;
uint8_t irq = (nvr->regs[RTC_REGB] & nvr->regs[RTC_REGC]) & (REGB_UIE | REGB_AIE | REGB_PIE);
if (irq) {
nvr->regs[RTC_REGC] |= REGC_IRQF;
picintlevel(1 << nvr->irq, &local->irq_state);
} else {
nvr->regs[RTC_REGC] &= ~REGC_IRQF;
picintclevel(1 << nvr->irq, &local->irq_state);
}
}
/* Update the NVR registers from the internal clock. */
static void
timer_update(void *priv)
@@ -442,45 +457,38 @@ timer_update(void *priv)
local_t *local = (local_t *) nvr->data;
struct tm tm;
local->ecount = 0LL;
if (local->ecount == (244ULL * TIMER_USEC)) {
rtc_tick();
if (!(nvr->regs[RTC_REGB] & REGB_SET)) {
/* Get the current time from the internal clock. */
nvr_time_get(&tm);
/* Update registers with current time. */
time_set(nvr, &tm);
/* Clear update status. */
local->stat = 0x00;
/* Check for any alarms we need to handle. */
if (check_alarm(nvr, RTC_SECONDS) && check_alarm(nvr, RTC_MINUTES) && check_alarm(nvr, RTC_HOURS) && check_alarm_via(nvr, RTC_DOM, RTC_ALDAY) && check_alarm_via(nvr, RTC_MONTH, RTC_ALMONTH) /* &&
check_alarm_via(nvr, RTC_DOM, RTC_ALDAY_SIS) &&
check_alarm_via(nvr, RTC_MONTH, RTC_ALMONT_SIS)*/
) {
if (check_alarm(nvr, RTC_SECONDS) && check_alarm(nvr, RTC_MINUTES) && check_alarm(nvr, RTC_HOURS) &&
check_alarm_via(nvr, RTC_DOM, RTC_ALDAY) && check_alarm_via(nvr, RTC_MONTH, RTC_ALMONTH) /* &&
check_alarm_via(nvr, RTC_DOM, RTC_ALDAY_SIS) && check_alarm_via(nvr, RTC_MONTH, RTC_ALMONT_SIS) */) {
nvr->regs[RTC_REGC] |= REGC_AF;
if (nvr->regs[RTC_REGB] & REGB_AIE) {
/* Generate an interrupt. */
if ((nvr->irq != -1) && (!(nvr->regs[RTC_REGC] & REGC_IRQF))) {
picintlevel(1 << nvr->irq);
nvr->regs[RTC_REGC] |= REGC_IRQF;
}
}
timer_update_irq(nvr);
}
/* Schedule the end of the update. */
local->ecount = 1984ULL * TIMER_USEC;
timer_set_delay_u64(&local->update_timer, local->ecount);
} else {
/*
* The flag and interrupt should be issued
* on update ended, not started.
*/
nvr->regs[RTC_REGC] |= REGC_UF;
if (nvr->regs[RTC_REGB] & REGB_UIE) {
/* Generate an interrupt. */
if ((nvr->irq != -1) && (!(nvr->regs[RTC_REGC] & REGC_IRQF))) {
picintlevel(1 << nvr->irq);
nvr->regs[RTC_REGC] |= REGC_IRQF;
}
}
timer_update_irq(nvr);
/* Clear update status. */
local->stat = 0x00;
local->ecount = 0LL;
}
}
@@ -525,13 +533,7 @@ timer_intr(void *priv)
timer_load_count(nvr);
nvr->regs[RTC_REGC] |= REGC_PF;
if (nvr->regs[RTC_REGB] & REGB_PIE) {
/* Generate an interrupt. */
if ((nvr->irq != -1) && (!(nvr->regs[RTC_REGC] & REGC_IRQF))) {
picintlevel(1 << nvr->irq);
nvr->regs[RTC_REGC] |= REGC_IRQF;
}
}
timer_update_irq(nvr);
}
}
@@ -541,15 +543,14 @@ timer_tick(nvr_t *nvr)
{
local_t *local = (local_t *) nvr->data;
/* Only update it there is no SET in progress. */
if (!(nvr->regs[RTC_REGB] & REGB_SET)) {
/* Only update it there is no SET in progress.
Also avoid updating it is DV2-DV0 are not set to 0, 1, 0. */
if (((nvr->regs[RTC_REGA] & 0x70) == 0x20) && !(nvr->regs[RTC_REGB] & REGB_SET)) {
/* Set the UIP bit, announcing the update. */
local->stat = REGA_UIP;
rtc_tick();
/* Schedule the actual update. */
local->ecount = (244ULL + 1984ULL) * TIMER_USEC;
local->ecount = 244ULL * TIMER_USEC;
timer_set_delay_u64(&local->update_timer, local->ecount);
}
}
@@ -583,32 +584,29 @@ nvr_reg_write(uint16_t reg, uint8_t val, void *priv)
local_t *local = (local_t *) nvr->data;
struct tm tm;
uint8_t old;
uint8_t irq = 0;
uint8_t old_irq = 0;
old = nvr->regs[reg];
switch (reg) {
case RTC_SECONDS: /* bit 7 of seconds is read-only */
nvr_reg_common_write(reg, val & 0x7f, nvr, local);
break;
case RTC_REGA:
nvr->regs[RTC_REGA] = val;
timer_load_count(nvr);
if ((val & nvr->regs[RTC_REGA]) & ~REGA_UIP) {
nvr->regs[RTC_REGA] = (nvr->regs[RTC_REGA] & REGA_UIP) | (val & ~REGA_UIP);
timer_load_count(nvr);
}
break;
case RTC_REGB:
old_irq = (nvr->regs[RTC_REGB] & nvr->regs[RTC_REGC]) & 0x70;
nvr->regs[RTC_REGB] = val;
if (((old ^ val) & REGB_SET) && (val & REGB_SET)) {
/* According to the datasheet... */
nvr->regs[RTC_REGA] &= ~REGA_UIP;
nvr->regs[RTC_REGB] &= ~REGB_UIE;
}
irq = (nvr->regs[RTC_REGB] & nvr->regs[RTC_REGC]) & 0x70;
if (old_irq && !irq) {
picintc(1 << nvr->irq);
nvr->regs[RTC_REGC] &= ~REGC_IRQF;
} else if (!old_irq && irq) {
picintlevel(1 << nvr->irq);
nvr->regs[RTC_REGC] |= REGC_IRQF;
val &= ~REGB_UIE;
local->stat &= ~REGA_UIP;
}
nvr->regs[RTC_REGB] = val;
timer_update_irq(nvr);
break;
case RTC_REGC: /* R/O */
@@ -698,9 +696,9 @@ nvr_read(uint16_t addr, void *priv)
break;
case RTC_REGC:
ret = nvr->regs[RTC_REGC];
picintc(1 << nvr->irq);
nvr->regs[RTC_REGC] = 0x00;
ret = nvr->regs[RTC_REGC] & (REGC_IRQF | REGC_PF | REGC_AF | REGC_UF);
nvr->regs[RTC_REGC] &= ~(REGC_IRQF | REGC_PF | REGC_AF | REGC_UF);
timer_update_irq(nvr);
break;
case RTC_REGD:

1674
src/pci.c
View File

File diff suppressed because it is too large Load Diff

14
src/pci_dummy.c
View File

@@ -19,15 +19,21 @@ typedef struct pci_dummy_t {
uint8_t card;
uint8_t interrupt_on;
uint8_t irq_level;
} pci_dummy_t;
static void
pci_dummy_interrupt(int set, pci_dummy_t *dev)
{
if (set)
pci_set_irq(dev->card, PCI_INTA);
else
pci_clear_irq(dev->card, PCI_INTA);
if (set != dev->irq_level) {
if (set)
pci_set_irq(dev->card, PCI_INTA);
else
pci_clear_irq(dev->card, PCI_INTA);
}
dev->irq_level = set;
}
static uint8_t

345
src/pic.c
View File

@@ -51,20 +51,22 @@ pic_t pic2;
static pc_timer_t pic_timer;
static uint16_t smi_irq_mask = 0x0000;
static uint16_t smi_irq_status = 0x0000;
static uint16_t enabled_latches = 0x0000;
static uint16_t latched_irqs = 0x0000;
static int shadow = 0;
static int elcr_enabled = 0;
static int tmr_inited = 0;
static int latched = 0;
static int pic_pci = 0;
static int kbd_latch = 0;
static int mouse_latch = 0;
static uint16_t smi_irq_mask = 0x0000;
static uint16_t smi_irq_status = 0x0000;
static void (*update_pending)(void);
static uint16_t latched_irqs = 0x0000;
static void (*update_pending)(void);
static void pic_update_request(pic_t *dev, int irq);
static void pic_cascade(int set);
#ifdef ENABLE_PIC_LOG
int pic_do_log = ENABLE_PIC_LOG;
@@ -236,10 +238,7 @@ pic_update_pending_at(void)
{
pic2.int_pending = (find_best_interrupt(&pic2) != -1);
if (pic2.int_pending)
pic.irr |= (1 << pic2.icw3);
else
pic.irr &= ~(1 << pic2.icw3);
pic_cascade(pic2.int_pending);
pic.int_pending = (find_best_interrupt(&pic) != -1);
}
@@ -268,8 +267,13 @@ pic_reset(void)
pic.is_master = 1;
pic.interrupt = pic2.interrupt = 0x17;
if (is_at)
pic.has_slaves = 0;
pic2.has_slaves = 0;
if (is_at) {
pic.slaves[2] = &pic2;
pic.has_slaves = 1;
}
if (tmr_inited)
timer_on_auto(&pic_timer, 0.0);
@@ -326,8 +330,16 @@ pic_acknowledge(pic_t *dev)
int pic_int_num = 1 << pic_int;
dev->isr |= pic_int_num;
if (!pic_level_triggered(dev, pic_int) || !(dev->lines & pic_int_num))
dev->irr &= ~pic_int_num;
/* Simulate the clearing of the edge pulse. */
dev->edge_lines &= ~pic_int_num;
/* Clear the edge sense latch. */
dev->irq_latch &= ~pic_int_num;
dev->flags |= PIC_FREEZE; /* Freeze it so it still takes interrupts but they do not
override the one currently being processed. */
/* Clear the reset latch. */
pic_update_request(dev, pic_int);
}
/* Find IRQ for non-specific EOI (either by command or automatic) by finding the highest IRQ
@@ -403,12 +415,12 @@ pic_latch_read(UNUSED(uint16_t addr), UNUSED(void *priv))
{
uint8_t ret = 0xff;
pic_log("pic_latch_read(%i, %i): %02X%02X\n", kbd_latch, mouse_latch, pic2.lines & 0x10, pic.lines & 0x02);
pic_log("pic_latch_read(%04X): %02X%02X\n", enabled_latches, latched_irqs & 0x10, latched_irqs & 0x02);
if (kbd_latch && (latched_irqs & 0x0002))
if ((latched_irqs & enabled_latches) & 0x0002)
picintc(0x0002);
if (mouse_latch && (latched_irqs & 0x1000))
if ((latched_irqs & enabled_latches) & 0x1000)
picintc(0x1000);
/* Return FF - we just lower IRQ 1 and IRQ 12. */
@@ -433,12 +445,8 @@ pic_read(uint16_t addr, void *priv)
}
} else {
/* Standard 8259 PIC read */
#ifndef UNDEFINED_READ
/* Put the IRR on to the data bus by default until the real PIC is probed. */
dev->data_bus = dev->irr;
#endif
if (dev->ocw3 & 0x04) {
dev->interrupt &= ~0x20; /* Freeze the interrupt until the poll is over. */
dev->flags &= ~PIC_FREEZE; /* Freeze the interrupt until the poll is over. */
if (dev->int_pending) {
dev->data_bus = 0x80 | (dev->interrupt & 7);
pic_acknowledge(dev);
@@ -452,10 +460,8 @@ pic_read(uint16_t addr, void *priv)
else if (dev->ocw3 & 0x02) {
if (dev->ocw3 & 0x01)
dev->data_bus = dev->isr;
#ifdef UNDEFINED_READ
else
dev->data_bus = 0x00;
#endif
dev->data_bus = dev->irr;
}
/* If A0 = 0, VIA shadow is disabled, and poll mode is disabled,
simply read whatever is currently on the data bus. */
@@ -470,6 +476,7 @@ static void
pic_write(uint16_t addr, uint8_t val, void *priv)
{
pic_t *dev = (pic_t *) priv;
uint8_t i;
pic_log("pic_write(%04X, %02X, %08X)\n", addr, val, priv);
@@ -511,7 +518,13 @@ pic_write(uint16_t addr, uint8_t val, void *priv)
if (!(dev->icw1 & 1))
dev->icw4 = 0x00;
dev->ocw2 = dev->ocw3 = 0x00;
dev->irr = dev->lines;
dev->irr = 0x00;
dev->edge_lines = 0x00;
dev->irq_latch = 0x00;
dev->flags |= PIC_MASTER_CLEAR;
for (i = 0; i <= 7; i++)
pic_update_request(dev, i);
dev->flags &= ~PIC_MASTER_CLEAR;
dev->imr = dev->isr = 0x00;
dev->ack_bytes = dev->priority = 0x00;
dev->auto_eoi_rotate = dev->special_mask_mode = 0x00;
@@ -522,7 +535,7 @@ pic_write(uint16_t addr, uint8_t val, void *priv)
} else if (val & 0x08) {
dev->ocw3 = val;
if (dev->ocw3 & 0x04)
dev->interrupt |= 0x20; /* Freeze the interrupt until the poll is over. */
dev->flags |= PIC_FREEZE; /* Freeze the interrupt until the poll is over. */
if (dev->ocw3 & 0x40)
dev->special_mask_mode = !!(dev->ocw3 & 0x20);
} else {
@@ -549,12 +562,15 @@ pic_set_pci(void)
void
pic_kbd_latch(int enable)
{
uint16_t old_latches = enabled_latches;
pic_log("PIC keyboard latch now %sabled\n", enable ? "en" : "dis");
if (!!(enable | mouse_latch) != !!(kbd_latch | mouse_latch))
io_handler(!!(enable | mouse_latch), 0x0060, 0x0001, pic_latch_read, NULL, NULL, NULL, NULL, NULL, NULL);
enable = (!!enable) << 1;
enabled_latches = (enabled_latches & 0x1000) | enable;
kbd_latch = !!enable;
if (!!(enabled_latches & 0x1002) != !!(old_latches & 0x1002))
io_handler(!!(enabled_latches & 0x1002), 0x0060, 0x0001, pic_latch_read, NULL, NULL, NULL, NULL, NULL, NULL);
if (!enable)
picintc(0x0002);
@@ -563,12 +579,15 @@ pic_kbd_latch(int enable)
void
pic_mouse_latch(int enable)
{
uint16_t old_latches = enabled_latches;
pic_log("PIC mouse latch now %sabled\n", enable ? "en" : "dis");
if (!!(kbd_latch | enable) != !!(kbd_latch | mouse_latch))
io_handler(!!(kbd_latch | enable), 0x0060, 0x0001, pic_latch_read, NULL, NULL, NULL, NULL, NULL, NULL);
enable = (!!enable) << 12;
enabled_latches = (enabled_latches & 0x0002) | enable;
mouse_latch = !!enable;
if (!!(enabled_latches & 0x1002) != !!(old_latches & 0x1002))
io_handler(!!(enabled_latches & 0x1002), 0x0060, 0x0001, pic_latch_read, NULL, NULL, NULL, NULL, NULL, NULL);
if (!enable)
picintc(0x1000);
@@ -580,11 +599,11 @@ pic_reset_hard(void)
pic_reset();
/* Explicitly reset the latches. */
kbd_latch = mouse_latch = 0;
enabled_latches = 0x0000;
latched_irqs = 0x0000;
/* The situation is as follows: There is a giant mess when it comes to these latches on real hardware,
to the point that there's even boards with board-level latched that get used in place of the latches
to the point that there's even boards with board-level latches that get used in place of the latches
on the chipset, therefore, I'm just doing this here for the sake of simplicity. */
if (machine_has_bus(machine, MACHINE_BUS_PS2_LATCH)) {
pic_kbd_latch(0x01);
@@ -621,30 +640,131 @@ pic2_init(void)
}
void
picint_common(uint16_t num, int level, int set)
pic_update_lines(pic_t *dev, uint16_t num, int level, int set, uint8_t *irq_state)
{
int raise;
uint8_t b;
uint8_t slaves = 0;
uint8_t old_edge_lines, bit;
switch (level) {
case PIC_IRQ_EDGE:
old_edge_lines = dev->edge_lines;
dev->edge_lines &= ~num;
if (set)
dev->edge_lines |= num;
if ((dev->isr & num) || (dev->flags & PIC_MASTER_CLEAR))
dev->irq_latch = (dev->irq_latch & ~num) | (dev->edge_lines & num);
else if ((dev->edge_lines & num) && !(old_edge_lines & num))
dev->irq_latch |= num;
break;
case PIC_IRQ_LEVEL:
for (uint8_t i = 0; i < 8; i++) {
bit = (1 << i);
if ((num & bit) && ((!!*irq_state) != !!set))
dev->lines[i] += (set ? 1 : -1);
}
if ((!!*irq_state) != !!set)
*irq_state = set;
break;
}
}
static uint8_t
pic_irq_get_request(pic_t *dev, int irq)
{
uint8_t ret;
ret = ((dev->edge_lines & (1 << irq)) || (dev->lines[irq] > 0));
pic_log("pic_irq_get_request(%08X, %i) = %02X\n", (uint32_t) (uintptr_t) dev, irq, ret);
return ret;
}
static uint8_t
pic_es_latch_clear(pic_t *dev, int irq)
{
uint8_t ret;
ret = (dev->isr & (1 << irq)) || (dev->flags & PIC_MASTER_CLEAR);
pic_log("pic_es_latch_clear(%08X, %i) = %02X\n", (uint32_t) (uintptr_t) dev, irq, ret);
return ret;
}
static uint8_t
pic_es_latch_out(pic_t *dev, int irq)
{
uint8_t ret;
ret = !((pic_es_latch_clear(dev, irq) && (dev->irq_latch & (1 << irq))) || !pic_irq_get_request(dev, irq));
pic_log("pic_es_latch_out(%08X, %i) = %02X\n", (uint32_t) (uintptr_t) dev, irq, ret);
return ret;
}
static uint8_t
pic_es_latch_nor(pic_t *dev, int irq)
{
uint8_t ret;
ret = !(pic_es_latch_out(dev, irq) || picint_is_level(irq));
pic_log("pic_es_latch_nor(%08X, %i) = %02X\n", (uint32_t) (uintptr_t) dev, irq, ret);
return ret;
}
static uint8_t
pic_irq_request_nor(pic_t *dev, int irq)
{
uint8_t ret;
ret = !(pic_es_latch_nor(dev, irq) || !pic_irq_get_request(dev, irq));
pic_log("pic_irq_request_nor(%08X, %i) = %02X\n", (uint32_t) (uintptr_t) dev, irq, ret);
return ret;
}
static void
pic_update_request(pic_t *dev, int irq)
{
dev->irr &= ~(1 << irq);
if (dev->flags & PIC_FREEZE) {
pic_log("pic_update_request(%08X, %i): FREEZE#\n", (uint32_t) (uintptr_t) dev, irq);
} else {
dev->irr |= (pic_irq_request_nor(dev, irq) << irq);
pic_log("pic_update_request(%08X, %i): IRR = %02X\n", (uint32_t) (uintptr_t) dev, irq, dev->irr);
}
}
static void
pic_update_irr(pic_t *dev, uint16_t num)
{
for (uint8_t i = 0; i < 8; i++) {
if (num & (1 << i))
pic_update_request(dev, i);
}
pic_log("IRQ %04x: IRR now: %02X\n", num, dev->irr);
}
void
picint_common(uint16_t num, int level, int set, uint8_t *irq_state)
{
pic_log("picint_common(%04X, %i, %i, %08X)\n", num, level, set, (uint32_t) (uintptr_t) irq_state);
set = !!set;
/* Make sure to ignore all slave IRQ's, and in case of AT+,
translate IRQ 2 to IRQ 9. */
for (uint8_t i = 0; i < 8; i++) {
b = (uint8_t) (1 << i);
raise = num & b;
if (pic.icw3 & b) {
slaves++;
if (raise) {
num &= ~b;
if (pic.at && (i == 2))
num |= (1 << 9);
}
}
if (num & pic.icw3) {
num &= ~pic.icw3;
if (pic.at)
num |= (1 << 9);
}
if (!slaves)
if (!pic.has_slaves)
num &= 0x00ff;
if (!num) {
@@ -655,77 +775,41 @@ picint_common(uint16_t num, int level, int set)
if (num & 0x0100)
acpi_rtc_status = !!set;
if (set) {
if (smi_irq_mask & num) {
smi_raise();
smi_irq_status |= num;
}
if (num & 0xff00) {
if (level)
pic2.lines |= (num >> 8);
/* Latch IRQ 12 if the mouse latch is enabled. */
if ((num & 0x1000) && mouse_latch)
latched_irqs |= 0x1000;
pic2.irr |= (num >> 8);
}
if (num & 0x00ff) {
if (level)
pic.lines |= (num & 0x00ff);
/* Latch IRQ 1 if the keyboard latch is enabled. */
if (kbd_latch && (num & 0x0002))
latched_irqs |= 0x0002;
pic.irr |= (num & 0x00ff);
}
} else {
smi_irq_status &= ~num;
if (num & 0xff00) {
pic2.lines &= ~(num >> 8);
/* Unlatch IRQ 12 if the mouse latch is enabled. */
if ((num & 0x1000) && mouse_latch)
latched_irqs &= 0xefff;
pic2.irr &= ~(num >> 8);
}
if (num & 0x00ff) {
pic.lines &= ~(num & 0x00ff);
/* Unlatch IRQ 1 if the keyboard latch is enabled. */
if (kbd_latch && (num & 0x0002))
latched_irqs &= 0xfffd;
pic.irr &= ~(num & 0x00ff);
}
smi_irq_status &= ~num;
if (set && (smi_irq_mask & num)) {
smi_raise();
smi_irq_status |= num;
}
if (!(pic.interrupt & 0x20) && !(pic2.interrupt & 0x20))
if (num & 0xff00) {
pic_update_lines(&pic2, num >> 8, level, set, irq_state);
/* Latch IRQ 12 if the mouse latch is enabled. */
if ((num & enabled_latches) & 0x1000)
latched_irqs = (latched_irqs & 0xefff) | (set << 12);
pic_update_irr(&pic2, num >> 8);
}
if (num & 0x00ff) {
pic_update_lines(&pic, num & 0x00ff, level, set, irq_state);
/* Latch IRQ 1 if the keyboard latch is enabled. */
if ((num & enabled_latches) & 0x0002)
latched_irqs = (latched_irqs & 0xfffd) | (set << 1);
pic_update_irr(&pic, num & 0x00ff);
}
if (!(pic.flags & PIC_FREEZE) && !(pic2.flags & PIC_FREEZE))
update_pending();
}
void
picint(uint16_t num)
static void
pic_cascade(int set)
{
picint_common(num, 0, 1);
}
void
picintlevel(uint16_t num)
{
picint_common(num, 1, 1);
}
void
picintc(uint16_t num)
{
picint_common(num, 0, 0);
pic_update_lines(&pic, (1 << pic2.icw3), PIC_IRQ_EDGE, set, NULL);
pic_update_irr(&pic, (1 << pic2.icw3));
}
static uint8_t
@@ -737,15 +821,12 @@ pic_i86_mode(pic_t *dev)
static uint8_t
pic_irq_ack_read(pic_t *dev, int phase)
{
uint8_t intr = dev->interrupt & 0x47;
uint8_t slave = intr & 0x40;
intr &= 0x07;
uint8_t intr = dev->interrupt & 0x07;
uint8_t slave = dev->flags & PIC_SLAVE_PENDING;
pic_log(" pic_irq_ack_read(%08X, %i)\n", dev, phase);
if (dev != NULL) {
if (phase == 0) {
dev->interrupt |= 0x20; /* Freeze it so it still takes interrupts but they do not
override the one currently being processed. */
pic_acknowledge(dev);
if (slave)
dev->data_bus = pic_irq_ack_read(dev->slaves[intr], phase);
@@ -791,7 +872,7 @@ pic_irq_ack(void)
exit(-1);
}
pic.interrupt |= 0x40; /* Mark slave pending. */
pic.flags |= PIC_SLAVE_PENDING;
}
ret = pic_irq_ack_read(&pic, pic.ack_bytes);
@@ -799,8 +880,13 @@ pic_irq_ack(void)
if (pic.ack_bytes == 0) {
/* Needed for Xi8088. */
if (pic.interrupt & 0x40)
if (pic.flags & PIC_SLAVE_PENDING) {
pic2.flags &= ~PIC_FREEZE;
pic_update_request(&pic2, pic2.interrupt & 0x07);
pic2.interrupt = 0x17;
}
pic.flags &= ~(PIC_SLAVE_PENDING | PIC_FREEZE);
pic_update_request(&pic, pic.interrupt & 0x07);
pic.interrupt = 0x17;
update_pending();
}
@@ -821,7 +907,7 @@ picinterrupt(void)
exit(-1);
}
pic.interrupt |= 0x40; /* Mark slave pending. */
pic.flags |= PIC_SLAVE_PENDING;
}
if ((pic.interrupt == 0) && (pit_devs[1].data != NULL))
@@ -833,8 +919,13 @@ picinterrupt(void)
pic.ack_bytes = (pic.ack_bytes + 1) % (pic_i86_mode(&pic) ? 2 : 3);
if (pic.ack_bytes == 0) {
if (pic.interrupt & 0x40)
if (pic.flags & PIC_SLAVE_PENDING) {
pic2.flags &= ~PIC_FREEZE;
pic_update_request(&pic2, pic2.interrupt & 0x07);
pic2.interrupt = 0x17;
}
pic.flags &= ~(PIC_SLAVE_PENDING | PIC_FREEZE);
pic_update_request(&pic, pic.interrupt & 0x07);
pic.interrupt = 0x17;
update_pending();
}

14
src/qt/languages/zh-TW.po
View File

@@ -182,7 +182,7 @@ msgid "Take s&creenshot\tCtrl+F11"
msgstr "擷圖(&C)\tCtrl+F11"
msgid "&Preferences..."
msgstr "首選項(&P)..."
msgstr "偏好設定(&P)..."
msgid "Enable &Discord integration"
msgstr "啟用 Discord 整合(&D)"
@@ -278,7 +278,7 @@ msgid "&Remove shader"
msgstr "移除著色器(&R)"
msgid "Preferences"
msgstr "首選項"
msgstr "偏好設定"
msgid "Sound Gain"
msgstr "音量增益"
@@ -407,16 +407,16 @@ msgid "Joystick 4..."
msgstr "搖桿 4..."
msgid "Sound card 1:"
msgstr "音訊卡 1:"
msgstr "音效卡 1:"
msgid "Sound card 2:"
msgstr "音訊卡 2:"
msgstr "音效卡 2:"
msgid "Sound card 3:"
msgstr "音訊卡 3:"
msgstr "音效卡 3:"
msgid "Sound card 4:"
msgstr "音訊卡 4:"
msgstr "音效卡 4:"
msgid "MIDI Out Device:"
msgstr "MIDI 輸出裝置:"
@@ -557,7 +557,7 @@ msgid "Heads:"
msgstr "磁頭(H):"
msgid "Cylinders:"
msgstr "柱面(C):"
msgstr "磁柱(C):"
msgid "Size (MB):"
msgstr "大小 (MB):"

2
src/scsi/scsi_buslogic.c
View File

@@ -1748,7 +1748,7 @@ buslogic_init(const device_t *info)
}
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
dev->pci_slot = pci_add_card(PCI_ADD_NORMAL, BuslogicPCIRead, BuslogicPCIWrite, dev);
pci_add_card(PCI_ADD_NORMAL, BuslogicPCIRead, BuslogicPCIWrite, dev, &dev->pci_slot);
buslogic_pci_bar[0].addr_regs[0] = 1;
buslogic_pci_bar[1].addr_regs[0] = 0;

13
src/scsi/scsi_ncr53c8xx.c
View File

@@ -234,6 +234,7 @@ typedef struct ncr53c8xx_t {
int waiting;
uint8_t current_lun;
uint8_t irq_state;
uint8_t istat;
uint8_t dcmd;
@@ -498,10 +499,10 @@ static void
do_irq(ncr53c8xx_t *dev, int level)
{
if (level) {
pci_set_irq(dev->pci_slot, PCI_INTA);
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
ncr53c8xx_log("Raising IRQ...\n");
} else {
pci_clear_irq(dev->pci_slot, PCI_INTA);
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
ncr53c8xx_log("Lowering IRQ...\n");
}
}
@@ -534,12 +535,16 @@ ncr53c8xx_update_irq(ncr53c8xx_t *dev)
level = 1;
}
#ifdef STATE_KEEPING
if (level != dev->last_level) {
#endif
ncr53c8xx_log("Update IRQ level %d dstat %02x sist %02x%02x\n",
level, dev->dstat, dev->sist1, dev->sist0);
dev->last_level = level;
do_irq(dev, level); /* Only do something with the IRQ if the new level differs from the previous one. */
#ifdef STATE_KEEPING
}
#endif
}
/* Stop SCRIPTS execution and raise a SCSI interrupt. */
@@ -2552,9 +2557,9 @@ ncr53c8xx_init(const device_t *info)
dev->has_bios = 0;
if (info->local & 0x8000)
dev->pci_slot = pci_add_card(PCI_ADD_SCSI, ncr53c8xx_pci_read, ncr53c8xx_pci_write, dev);
pci_add_card(PCI_ADD_SCSI, ncr53c8xx_pci_read, ncr53c8xx_pci_write, dev, &dev->pci_slot);
else
dev->pci_slot = pci_add_card(PCI_ADD_NORMAL, ncr53c8xx_pci_read, ncr53c8xx_pci_write, dev);
pci_add_card(PCI_ADD_NORMAL, ncr53c8xx_pci_read, ncr53c8xx_pci_write, dev, &dev->pci_slot);
if (dev->chip == CHIP_875) {
dev->chip_rev = 0x04;

7
src/scsi/scsi_pcscsi.c
View File

@@ -197,6 +197,7 @@ typedef struct esp_t {
int pos;
} dma_86c01;
uint8_t irq_state;
uint8_t pos_regs[8];
} esp_t;
@@ -247,10 +248,10 @@ esp_irq(esp_t *dev, int level)
}
} else {
if (level) {
pci_set_irq(dev->pci_slot, PCI_INTA);
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
esp_log("Raising IRQ...\n");
} else {
pci_clear_irq(dev->pci_slot, PCI_INTA);
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
esp_log("Lowering IRQ...\n");
}
}
@@ -1842,7 +1843,7 @@ dc390_init(UNUSED(const device_t *info))
dev->PCIBase = 0;
dev->MMIOBase = 0;
dev->pci_slot = pci_add_card(PCI_ADD_NORMAL, esp_pci_read, esp_pci_write, dev);
pci_add_card(PCI_ADD_NORMAL, esp_pci_read, esp_pci_write, dev, &dev->pci_slot);
esp_pci_bar[0].addr_regs[0] = 1;
esp_pci_regs[0x04] = 3;

23
src/scsi/scsi_x54x.c
View File

@@ -83,23 +83,27 @@ x54x_irq(x54x_t *dev, int set)
if (dev->card_bus & DEVICE_PCI) {
x54x_log("PCI IRQ: %02X, PCI_INTA\n", dev->pci_slot);
if (set)
pci_set_irq(dev->pci_slot, PCI_INTA);
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
else
pci_clear_irq(dev->pci_slot, PCI_INTA);
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
} else {
x54x_log("%sing IRQ %i\n", set ? "Rais" : "Lower", irq);
if (set) {
if (dev->interrupt_type)
int_type = dev->interrupt_type(dev);
if (dev->interrupt_type)
int_type = dev->interrupt_type(dev);
if (set) {
if (int_type)
picintlevel(1 << irq);
picintlevel(1 << irq, &dev->irq_state);
else
picint(1 << irq);
} else
picintc(1 << irq);
}
} else {
if (int_type)
picintclevel(1 << irq, &dev->irq_state);
else
picintc(1 << irq);
}
}
}
static void
@@ -1415,6 +1419,7 @@ static void
x54x_reset(x54x_t *dev)
{
clear_irq(dev);
dev->irq_state = 0;
if (dev->flags & X54X_INT_GEOM_WRITABLE)
dev->Geometry = 0x90;
else

11
src/sound/snd_ac97_via.c
View File

@@ -73,7 +73,8 @@ typedef struct _ac97_via_ {
uint8_t regs_linear[256];
};
} codec_shadow[2];
int slot;
uint8_t pci_slot;
uint8_t irq_state;
int irq_pin;
ac97_codec_t *codec[2][2];
@@ -115,8 +116,8 @@ ac97_via_set_slot(void *priv, int slot, int irq_pin)
ac97_via_log("AC97 VIA: set_slot(%d, %d)\n", slot, irq_pin);
dev->slot = slot;
dev->irq_pin = irq_pin;
dev->pci_slot = slot;
dev->irq_pin = irq_pin;
}
uint8_t
@@ -182,12 +183,12 @@ ac97_via_update_irqs(ac97_via_t *dev)
/* Stop immediately if any flag is set. Doing it this way optimizes
rising edges for the playback SGD (0 - first to be checked). */
if (dev->sgd_regs[i] & (dev->sgd_regs[i | 0x2] & 0x03)) {
pci_set_irq(dev->slot, dev->irq_pin);
pci_set_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
return;
}
}
pci_clear_irq(dev->slot, dev->irq_pin);
pci_clear_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
}
static void

37
src/sound/snd_audiopci.c
View File

@@ -53,6 +53,7 @@ typedef struct es1371_t {
uint32_t base_addr;
uint8_t int_line;
uint8_t irq_state;
uint16_t pmcsr;
@@ -120,7 +121,7 @@ typedef struct es1371_t {
int cd_vol_l;
int cd_vol_r;
int card;
uint8_t pci_slot;
int pos;
int16_t buffer[SOUNDBUFLEN * 2];
@@ -235,9 +236,9 @@ es1371_update_irqs(es1371_t *dev)
irq = 1;
if (irq)
pci_set_irq(dev->card, PCI_INTA);
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
else
pci_clear_irq(dev->card, PCI_INTA);
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
}
static void
@@ -325,21 +326,15 @@ es1371_reset(void *priv)
/* Interrupt/Chip Select Control Register, Address 00H
Addressable as byte, word, longword */
dev->int_ctrl = 0xfc0f0000;
dev->int_ctrl = 0xfcff0000;
/* Interrupt/Chip Select Control Register, Address 00H
Addressable as longword only */
/* Bit 13 is supposed to be always 1 on ES1371, and one of the GPIO interrupt
flags on ES1373. The 5.12.01 WDM driver only initializes its GPIO interrupt
handler on chip revisions which support this feature (1371 >= 0x04 and 5880
all), but calls it anyway during interrupt servicing regardless of revision,
crashing on ES1371 as soon as an interrupt arrives while that bit is set.
Pending hardware research because actual early ES1371 cards are rare. */
dev->int_status = 0x7fffdec0;
dev->int_status = 0x7ffffec0;
/* UART Status Register, Address 09H
Addressable as byte only */
dev->uart_status = 0x00;
dev->uart_status = 0xff;
/* UART Control Register, Address 09H
Addressable as byte only */
@@ -347,15 +342,15 @@ es1371_reset(void *priv)
/* UART Reserved Register, Address 0AH
Addressable as byte only */
dev->uart_res = 0x00;
dev->uart_res = 0xff;
/* Memory Page Register, Address 0CH
Addressable as byte, word, longword */
dev->mem_page = 0x00;
dev->mem_page = 0xf0; /* FIXME: hardware reads 0xfffffff0 */
/* Sample Rate Converter Interface Register, Address 10H
Addressable as longword only */
dev->sr_cir = 0x00000000;
dev->sr_cir = 0x00470000;
/* CODEC Write Register, Address 14H
Addressable as longword only */
@@ -363,7 +358,7 @@ es1371_reset(void *priv)
/* Legacy Control/Status Register, Address 18H
Addressable as byte, word, longword */
dev->legacy_ctrl = 0x0000f800;
dev->legacy_ctrl = 0x0000f801;
/* Serial Interface Control Register, Address 20H
Addressable as byte, word, longword */
@@ -371,17 +366,17 @@ es1371_reset(void *priv)
/* DAC1 Channel Sample Count Register, Address 24H
Addressable as word, longword */
dev->dac[0].samp_ct = 0x00000000;
dev->dac[0].samp_ct = 0x00000000; /* FIXME: hardware reads 0x00010000 */
dev->dac[0].curr_samp_ct = 0x00000000;
/* DAC2 Channel Sample Count Register, Address 28H
Addressable as word, longword */
dev->dac[1].samp_ct = 0x00000000;
dev->dac[1].samp_ct = 0x00000000; /* FIXME: hardware reads 0x00010000 */
dev->dac[1].curr_samp_ct = 0x00000000;
/* ADC Channel Sample Count Register, Address 2CH
Addressable as word, longword */
dev->adc.samp_ct = 0x00000000;
dev->adc.samp_ct = 0x00000000; /* FIXME: hardware reads 0x00010000 */
dev->adc.curr_samp_ct = 0x00000000;
/* DAC1 Frame Register 1, Address 30H, Memory Page 1100b
@@ -1632,7 +1627,7 @@ es1371_pci_read(int func, int addr, void *priv)
return 0x00;
case 0x08:
return 0x02; /* Revision ID - 0x02 is supposed to be early Ensoniq-branded ES1371 but unconfirmed */
return 0x02; /* Revision ID - 0x02 is actual Ensoniq-branded ES1371 */
case 0x09:
return 0x00; /* Multimedia audio device */
case 0x0a:
@@ -2106,7 +2101,7 @@ es1371_init(const device_t *info)
dev->gameport = gameport_add(&gameport_pnp_device);
gameport_remap(dev->gameport, 0x200);
dev->card = pci_add_card(info->local ? PCI_ADD_SOUND : PCI_ADD_NORMAL, es1371_pci_read, es1371_pci_write, dev);
pci_add_card(info->local ? PCI_ADD_SOUND : PCI_ADD_NORMAL, es1371_pci_read, es1371_pci_write, dev, &dev->pci_slot);
timer_add(&dev->dac[1].timer, es1371_poll, dev, 1);

13
src/sound/snd_cmi8x38.c
View File

@@ -97,7 +97,8 @@ typedef struct _cmi8x38_ {
uint16_t mpu_base;
uint8_t pci_regs[256];
uint8_t io_regs[256];
int slot;
uint8_t pci_slot;
uint8_t irq_state;
sb_t *sb;
void *gameport;
@@ -148,11 +149,11 @@ cmi8x38_update_irqs(cmi8x38_t *dev)
/* Calculate and use the INTR flag. */
if (*((uint32_t *) &dev->io_regs[0x10]) & 0x0401c003) {
dev->io_regs[0x13] |= 0x80;
pci_set_irq(dev->slot, PCI_INTA);
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
cmi8x38_log("CMI8x38: Raising IRQ\n");
} else {
dev->io_regs[0x13] &= ~0x80;
pci_clear_irq(dev->slot, PCI_INTA);
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
}
}
@@ -823,9 +824,9 @@ cmi8x38_write(uint16_t addr, uint8_t val, void *priv)
/* Force IRQ if requested. Clearing this bit is undefined. */
if (val & 0x10)
pci_set_irq(dev->slot, PCI_INTA);
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
else if ((dev->io_regs[0x17] & 0x10) && !(val & 0x10))
pci_clear_irq(dev->slot, PCI_INTA);
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
/* Enable or disable I/O traps. */
dev->io_regs[addr] = val;
@@ -1473,7 +1474,7 @@ cmi8x38_init(const device_t *info)
}
/* Add PCI card. */
dev->slot = pci_add_card((info->local & (1 << 13)) ? PCI_ADD_SOUND : PCI_ADD_NORMAL, cmi8x38_pci_read, cmi8x38_pci_write, dev);
pci_add_card((info->local & (1 << 13)) ? PCI_ADD_SOUND : PCI_ADD_NORMAL, cmi8x38_pci_read, cmi8x38_pci_write, dev, &dev->pci_slot);
/* Perform initial reset. */
cmi8x38_reset(dev);

151
src/sound/snd_gus.c
View File

@@ -98,6 +98,9 @@ typedef struct gus_t {
int irqnext;
uint8_t irq_state;
uint8_t midi_irq_state;
pc_timer_t timer_1;
pc_timer_t timer_2;
@@ -157,8 +160,10 @@ double vol16bit[4096];
void
gus_update_int_status(gus_t *gus)
{
int irq_pending = 0;
int midi_irq_pending = 0;
int irq_pending = 0;
int midi_irq_pending = 0;
int intr_pending = 0;
int midi_intr_pending = 0;
gus->irqstatus &= ~0x60;
gus->irqstatus2 = 0xE0;
@@ -187,24 +192,35 @@ gus_update_int_status(gus_t *gus)
midi_irq_pending = gus->midi_status & MIDI_INT_MASTER;
if (gus->irq == gus->irq_midi && gus->irq != -1) {
if (gus->irq == gus->irq_midi) {
if (irq_pending || midi_irq_pending)
picintlevel(1 << gus->irq);
intr_pending = 1;
else
picintc(1 << gus->irq);
intr_pending = 0;
} else {
if (gus->irq != -1) {
if (irq_pending)
picintlevel(1 << gus->irq);
else
picintc(1 << gus->irq);
}
if (gus->irq_midi != -1) {
if (midi_irq_pending)
picintlevel(1 << gus->irq_midi);
else
picintc(1 << gus->irq_midi);
}
if (irq_pending)
intr_pending = 1;
else
intr_pending = 0;
if (midi_irq_pending)
midi_intr_pending = 1;
else
midi_intr_pending = 0;
}
if (gus->irq != -1) {
if (intr_pending)
picintlevel(1 << gus->irq, &gus->irq_state);
else
picintclevel(1 << gus->irq, &gus->irq_state);
}
if (gus->irq_midi != -1) {
if (midi_intr_pending)
picintlevel(1 << gus->irq_midi, &gus->midi_irq_state);
else
picintclevel(1 << gus->irq_midi, &gus->midi_irq_state);
}
}
@@ -1174,6 +1190,103 @@ gus_input_sysex(void *p, uint8_t *buffer, uint32_t len, int abort)
return 0;
}
static void
gus_reset(void *p)
{
gus_t *gus = (gus_t *) p;
int c;
double out = 1.0;
if (gus == NULL)
return;
memset(gus->ram, 0x00, (gus->gus_end_ram));
for (c = 0; c < 32; c++) {
gus->ctrl[c] = 1;
gus->rctrl[c] = 1;
gus->rfreq[c] = 63 * 512;
}
for (c = 4095; c >= 0; c--) {
vol16bit[c] = out;
out /= 1.002709201; /* 0.0235 dB Steps */
}
gus->voices = 14;
gus->samp_latch = (uint64_t) (TIMER_USEC * (1000000.0 / 44100.0));
gus->t1l = gus->t2l = 0xff;
gus->global = 0;
gus->addr = 0;
gus->dmaaddr = 0;
gus->voice = 0;
memset(gus->start, 0x00, 32 * sizeof(uint32_t));
memset(gus->end, 0x00, 32 * sizeof(uint32_t));
memset(gus->cur, 0x00, 32 * sizeof(uint32_t));
memset(gus->startx, 0x00, 32 * sizeof(uint32_t));
memset(gus->endx, 0x00, 32 * sizeof(uint32_t));
memset(gus->curx, 0x00, 32 * sizeof(uint32_t));
memset(gus->rstart, 0x00, 32 * sizeof(int));
memset(gus->rend, 0x00, 32 * sizeof(int));
memset(gus->rcur, 0x00, 32 * sizeof(int));
memset(gus->freq, 0x00, 32 * sizeof(uint16_t));
memset(gus->curvol, 0x00, 32 * sizeof(int));
memset(gus->pan_l, 0x00, 32 * sizeof(int));
memset(gus->pan_r, 0x00, 32 * sizeof(int));
gus->t1on = 0;
gus->t2on = 0;
gus->tctrl = 0;
gus->t1 = 0;
gus->t2 = 0;
gus->irqstatus = 0;
gus->irqstatus2 = 0;
gus->adcommand = 0;
memset(gus->waveirqs, 0x00, 32 * sizeof(int));
memset(gus->rampirqs, 0x00, 32 * sizeof(int));
gus->dmactrl = 0;
gus->uart_out = 1;
gus->sb_2xa = 0;
gus->sb_2xc = 0;
gus->sb_2xe = 0;
gus->sb_ctrl = 0;
gus->sb_nmi = 0;
gus->reg_ctrl = 0;
gus->ad_status = 0;
gus->ad_data = 0;
gus->ad_timer_ctrl = 0;
gus->midi_ctrl = 0;
gus->midi_status = 0;
memset(gus->midi_queue, 0x00, 64 * sizeof(uint8_t));
gus->midi_data = 0;
gus->midi_r = 0;
gus->midi_w = 0;
gus->uart_in = 0;
gus->uart_out = 0;
gus->sysex = 0;
gus->gp1 = 0;
gus->gp2 = 0;
gus->gp1_addr = 0;
gus->gp2_addr = 0;
gus->usrr = 0;
gus->max_ctrl = 0;
gus->irq_state = 0;
gus->midi_irq_state = 0;
gus_update_int_status(gus);
}
void *
gus_init(UNUSED(const device_t *info))
{
@@ -1181,7 +1294,7 @@ gus_init(UNUSED(const device_t *info))
double out = 1.0;
uint8_t gus_ram = device_get_config_int("gus_ram");
gus_t *gus = malloc(sizeof(gus_t));
memset(gus, 0, sizeof(gus_t));
memset(gus, 0x00, sizeof(gus_t));
gus->gus_end_ram = 1 << (18 + gus_ram);
gus->ram = (uint8_t *) malloc(gus->gus_end_ram);
@@ -1359,7 +1472,7 @@ const device_t gus_device = {
.local = 0,
.init = gus_init,
.close = gus_close,
.reset = NULL,
.reset = gus_reset,
{ .available = NULL },
.speed_changed = gus_speed_changed,
.force_redraw = NULL,

4
src/usb.c
View File

@@ -317,10 +317,14 @@ ohci_update_irq(usb_t *dev)
{
uint32_t level = !!(dev->ohci_mmio[OHCI_HcInterruptStatus].l & dev->ohci_mmio[OHCI_HcInterruptEnable].l);
#ifdef STATE_KEEPING
if (level != dev->irq_level) {
#endif
dev->irq_level = level;
usb_interrupt_ohci(dev, level);
#ifdef STATE_KEEPING
}
#endif
}
void

132
src/video/vid_8514a.c
View File

@@ -212,7 +212,7 @@ int ibm8514_has_vga = 0;
int
ibm8514_cpu_src(svga_t *svga)
{
ibm8514_t *dev = &svga->dev8514;
const ibm8514_t *dev = &svga->dev8514;
if (!(dev->accel.cmd & 0x100))
return 0;
@@ -226,7 +226,7 @@ ibm8514_cpu_src(svga_t *svga)
int
ibm8514_cpu_dest(svga_t *svga)
{
ibm8514_t *dev = &svga->dev8514;
const ibm8514_t *dev = &svga->dev8514;
if (!(dev->accel.cmd & 0x100))
return 0;
@@ -240,16 +240,16 @@ ibm8514_cpu_dest(svga_t *svga)
void
ibm8514_accel_out_pixtrans(svga_t *svga, UNUSED(uint16_t port), uint16_t val, int len)
{
ibm8514_t *dev = &svga->dev8514;
uint8_t nibble = 0;
uint32_t pixelxfer = 0;
uint32_t monoxfer = 0xffffffff;
int pixcnt = 0;
int pixcntl = (dev->accel.multifunc[0x0a] >> 6) & 3;
int frgd_mix = (dev->accel.frgd_mix >> 5) & 3;
int bkgd_mix = (dev->accel.bkgd_mix >> 5) & 3;
int cmd = dev->accel.cmd >> 13;
int and3 = dev->accel.cur_x & 3;
ibm8514_t *dev = &svga->dev8514;
uint8_t nibble = 0;
uint32_t pixelxfer = 0;
uint32_t monoxfer = 0xffffffff;
int pixcnt = 0;
int pixcntl = (dev->accel.multifunc[0x0a] >> 6) & 3;
int frgd_mix = (dev->accel.frgd_mix >> 5) & 3;
int bkgd_mix = (dev->accel.bkgd_mix >> 5) & 3;
int cmd = dev->accel.cmd >> 13;
int and3 = dev->accel.cur_x & 3;
if (dev->accel.cmd & 0x100) {
if (len != 1) {
@@ -537,7 +537,7 @@ ibm8514_accel_out_fifo(svga_t *svga, uint16_t port, uint32_t val, int len)
if (len != 1)
dev->test = val;
#ifdef FALLTHROUGH_ANNOTATION
[[fallthrough]];
[[fallthrough]];
#endif
case 0xd2e8:
if (len == 1)
@@ -981,8 +981,8 @@ ibm8514_accel_out(uint16_t port, uint32_t val, svga_t *svga, int len)
if (!val)
break;
dev->accel.advfunc_cntl = val & 7;
ibm8514_on = (dev->accel.advfunc_cntl & 1);
vga_on = !ibm8514_on;
ibm8514_on = (dev->accel.advfunc_cntl & 1);
vga_on = !ibm8514_on;
ibm8514_log("IBM 8514/A: VGA ON = %i, val = %02x\n", vga_on, val);
svga_recalctimings(svga);
break;
@@ -1013,8 +1013,8 @@ ibm8514_accel_in(uint16_t port, svga_t *svga, int len)
ibm8514_t *dev = &svga->dev8514;
uint32_t temp = 0;
int cmd;
int vpos = dev->displine + svga->y_add;
int vblankend = svga->vblankstart + svga->crtc[0x16];
int vpos = dev->displine + svga->y_add;
int vblankend = svga->vblankstart + svga->crtc[0x16];
switch (port) {
case 0x2e8:
@@ -1024,7 +1024,7 @@ ibm8514_accel_in(uint16_t port, svga_t *svga, int len)
if (vpos >= svga->vblankstart || vpos <= vblankend)
temp |= 2;
} else {
if (vpos >= svga->vblankstart && vpos <= vblankend)
if (vpos >= svga->vblankstart && vpos <= vblankend)
temp |= 2;
}
break;
@@ -1059,7 +1059,7 @@ ibm8514_accel_in(uint16_t port, svga_t *svga, int len)
if (vpos >= svga->vblankstart || vpos <= vblankend)
dev->subsys_stat |= 1;
} else {
if (vpos >= svga->vblankstart && vpos <= vblankend)
if (vpos >= svga->vblankstart && vpos <= vblankend)
dev->subsys_stat |= 1;
}
if (len != 1) {
@@ -1140,6 +1140,7 @@ static uint8_t
ibm8514_accel_inb(uint16_t port, void *priv)
{
svga_t *svga = (svga_t *) priv;
return ibm8514_accel_in(port, svga, 1);
}
@@ -1147,6 +1148,7 @@ static uint16_t
ibm8514_accel_inw(uint16_t port, void *priv)
{
svga_t *svga = (svga_t *) priv;
return ibm8514_accel_in(port, svga, 2);
}
@@ -1171,8 +1173,8 @@ ibm8514_short_stroke_start(int count, int cpu_input, uint32_t mix_dat, uint32_t
void
ibm8514_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, svga_t *svga, UNUSED(int len))
{
ibm8514_t *dev = &svga->dev8514;
uint16_t *vram_w = (uint16_t *)svga->vram;
ibm8514_t *dev = &svga->dev8514;
uint16_t *vram_w = (uint16_t *) svga->vram;
uint16_t src_dat = 0;
uint16_t dest_dat;
uint16_t old_dest_dat;
@@ -1181,7 +1183,7 @@ ibm8514_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat
uint16_t clip_b = dev->accel.multifunc[3];
uint16_t clip_r = dev->accel.multifunc[4];
int pixcntl = (dev->accel.multifunc[0x0a] >> 6) & 3;
uint16_t mix_mask = ((svga->bpp == 8) || (svga->bpp == 24)) ? 0x80 : 0x8000;
uint16_t mix_mask = ((svga->bpp == 8) || (svga->bpp == 24)) ? 0x80 : 0x8000;
uint16_t compare = dev->accel.color_cmp;
int compare_mode = dev->accel.multifunc[0x0a] & 0x38;
int cmd = dev->accel.cmd >> 13;
@@ -1340,9 +1342,9 @@ ibm8514_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if (dev->accel.ssv_draw) {
if ((dev->accel.cmd & 4) && dev->accel.ssv_len) {
@@ -1402,7 +1404,8 @@ ibm8514_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat
}
} else {
while (count-- && (dev->accel.ssv_len >= 0)) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
if ((dev->accel.cx >= dev->accel.clip_left) && (dev->accel.cx <= clip_r) &&
(dev->accel.cy >= dev->accel.clip_top) && (dev->accel.cy <= clip_b)) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
@@ -2020,10 +2023,10 @@ ibm8514_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat
dev->accel.cy |= ~0x5ff;
if (dev->local && dev->accel.ge_offset && (svga->bpp == 24))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.fill_state = 0;
if (cmd == 4)
@@ -2070,7 +2073,7 @@ ibm8514_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat
} else {
if (!(dev->accel.cmd & 0x40) && (frgd_mix == 2) && (bkgd_mix == 2) && (pixcntl == 0) && (cmd == 2)) {
if (!(dev->accel.sx & 1)) {
dev->accel.output = 1;
dev->accel.output = 1;
if (dev->local && dev->accel.ge_offset && (svga->bpp == 24))
dev->accel.newdest_out = (dev->accel.ge_offset << 2) + ((dev->accel.cy + 1) * dev->pitch);
else
@@ -2348,9 +2351,9 @@ rect_fill_pix:
dev->accel.cy--;
if (dev->local && dev->accel.ge_offset && (svga->bpp == 24))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
return;
@@ -2440,9 +2443,9 @@ rect_fill_pix:
dev->accel.cy--;
if (dev->local && dev->accel.ge_offset && (svga->bpp == 24))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
return;
@@ -2974,15 +2977,15 @@ rect_fill:
case 5: /*Draw Polygon Boundary Line*/
if (!cpu_input) {
dev->accel.cx = dev->accel.cur_x;
dev->accel.cy = dev->accel.cur_y;
dev->accel.cx = dev->accel.cur_x;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
if (dev->accel.cur_y >= 0x600)
dev->accel.cy |= ~0x5ff;
dev->accel.oldcy = dev->accel.cy;
dev->accel.sy = 0;
dev->accel.sy = 0;
if (ibm8514_cpu_src(svga)) {
dev->data_available = 0;
@@ -3258,7 +3261,7 @@ bitblt_pix:
dev->accel.cy--;
}
dev->accel.src = dev->accel.cy * dev->pitch;
dev->accel.src = dev->accel.cy * dev->pitch;
dev->accel.dest = dev->accel.dy * dev->pitch;
dev->accel.sy--;
return;
@@ -3625,11 +3628,12 @@ bitblt:
int64_t cx;
int64_t dx;
cx = (int64_t)dev->accel.cx;
dx = (int64_t)dev->accel.dx;
cx = (int64_t) dev->accel.cx;
dx = (int64_t) dev->accel.dx;
while (1) {
if (dx >= (((int64_t)dev->accel.clip_left) * 3) && dx <= (((uint64_t)clip_r) * 3) && dev->accel.dy >= (dev->accel.clip_top << 1) && dev->accel.dy <= (clip_b << 1)) {
if ((dx >= (((int64_t)dev->accel.clip_left) * 3)) && (dx <= (((uint64_t)clip_r) * 3)) &&
(dev->accel.dy >= (dev->accel.clip_top << 1)) && (dev->accel.dy <= (clip_b << 1))) {
READ(dev->accel.src + (dev->accel.ge_offset << 2) + cx, src_dat);
READ(dev->accel.dest + (dev->accel.ge_offset << 2) + dx, dest_dat);
@@ -3649,7 +3653,8 @@ bitblt:
}
while (count-- && dev->accel.sy >= 0) {
if (dev->accel.dx >= dev->accel.clip_left && dev->accel.dx <= clip_r && dev->accel.dy >= dev->accel.clip_top && dev->accel.dy <= clip_b) {
if ((dev->accel.dx >= dev->accel.clip_left) && (dev->accel.dx <= clip_r) &&
(dev->accel.dy >= dev->accel.clip_top) && (dev->accel.dy <= clip_b)) {
if (pixcntl == 3) {
if (!(dev->accel.cmd & 0x10) && ((frgd_mix != 3) || (bkgd_mix != 3))) {
READ(dev->accel.src + dev->accel.cx, mix_dat);
@@ -3861,7 +3866,7 @@ ibm8514_poll(ibm8514_t *dev, svga_t *svga)
dev->linepos = 0;
if (dev->dispon) {
if (dev->sc == dev->rowcount) {
dev->sc = 0;
dev->sc = 0;
dev->maback += (dev->rowoffset << 3);
if (dev->interlace)
dev->maback += (dev->rowoffset << 3);
@@ -3937,13 +3942,13 @@ ibm8514_recalctimings(svga_t *svga)
ibm8514_t *dev = &svga->dev8514;
if (ibm8514_on) {
dev->h_disp = (dev->hdisp + 1) << 3;
dev->pitch = (dev->accel.advfunc_cntl & 4) ? 1024 : 640;
dev->h_total = (dev->htotal + 1);
dev->v_total = (dev->vtotal + 1);
dev->v_syncstart = (dev->vsyncstart + 1);
dev->rowcount = !!(dev->disp_cntl & 0x08);
dev->dispend = ((dev->vdisp >> 1) + 1);
dev->h_disp = (dev->hdisp + 1) << 3;
dev->pitch = (dev->accel.advfunc_cntl & 4) ? 1024 : 640;
dev->h_total = (dev->htotal + 1);
dev->v_total = (dev->vtotal + 1);
dev->v_syncstart = (dev->vsyncstart + 1);
dev->rowcount = !!(dev->disp_cntl & 0x08);
dev->dispend = ((dev->vdisp >> 1) + 1);
if (dev->dispend == 766)
dev->dispend = 768;
@@ -3953,9 +3958,9 @@ ibm8514_recalctimings(svga_t *svga)
if (dev->accel.advfunc_cntl & 4) {
if (!vga_on && dev->ibm_mode) {
if (dev->h_disp == 8) {
dev->h_disp = 1024;
dev->dispend = 768;
dev->v_total = 1536;
dev->h_disp = 1024;
dev->dispend = 768;
dev->v_total = 1536;
dev->v_syncstart = 1536;
}
}
@@ -3973,7 +3978,7 @@ ibm8514_recalctimings(svga_t *svga)
}
if (ibm8514_has_vga) {
dev->pitch = dev->ext_pitch;
dev->pitch = dev->ext_pitch;
dev->rowoffset = dev->ext_crt_pitch;
} else
dev->rowoffset = 128;
@@ -3983,7 +3988,7 @@ ibm8514_recalctimings(svga_t *svga)
} else {
if (!vga_on && dev->ibm_mode) {
if (dev->h_disp == 1024) {
dev->h_disp = 640;
dev->h_disp = 640;
dev->dispend = 480;
}
}
@@ -3998,7 +4003,7 @@ ibm8514_recalctimings(svga_t *svga)
}
if (ibm8514_has_vga) {
dev->pitch = dev->ext_pitch;
dev->pitch = dev->ext_pitch;
dev->rowoffset = dev->ext_crt_pitch;
} else
dev->rowoffset = 128;
@@ -4014,8 +4019,8 @@ ibm8514_recalctimings(svga_t *svga)
static uint8_t
ibm8514_mca_read(int port, void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = &svga->dev8514;
const svga_t *svga = (svga_t *) priv;
const ibm8514_t *dev = &svga->dev8514;
return (dev->pos_regs[port & 7]);
}
@@ -4037,15 +4042,14 @@ ibm8514_mca_write(int port, uint8_t val, void *priv)
static uint8_t
ibm8514_mca_feedb(void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = &svga->dev8514;
const svga_t *svga = (svga_t *) priv;
const ibm8514_t *dev = &svga->dev8514;
return dev->pos_regs[2] & 1;
}
static void
*
ibm8514_init(const device_t *info)
static void *
ibm8514_init(const device_t *info)
{
if (svga_get_pri() == NULL)
return NULL;
@@ -4059,9 +4063,9 @@ static void
dev->vram_mask = dev->vram_size - 1;
dev->map8 = svga->pallook;
dev->type = info->flags;
dev->type = info->flags;
dev->ibm_mode = 1;
dev->bpp = 8;
dev->bpp = 8;
ibm8514_io_set(svga);

2
src/video/vid_ati18800.c
View File

@@ -171,7 +171,7 @@ ati18800_in(uint16_t addr, void *priv)
static void
ati18800_recalctimings(svga_t *svga)
{
ati18800_t *ati18800 = (ati18800_t *) svga->priv;
const ati18800_t *ati18800 = (ati18800_t *) svga->priv;
if (svga->crtc[0x17] & 4) {
svga->vtotal <<= 1;

12
src/video/vid_ati28800.c
View File

@@ -357,10 +357,10 @@ ati28800_in(uint16_t addr, void *priv)
static uint8_t
ati28800k_in(uint16_t addr, void *priv)
{
ati28800_t *ati28800 = (ati28800_t *) priv;
svga_t *svga = &ati28800->svga;
uint16_t oldaddr = addr;
uint8_t temp = 0xFF;
ati28800_t *ati28800 = (ati28800_t *) priv;
const svga_t *svga = &ati28800->svga;
uint16_t oldaddr = addr;
uint8_t temp = 0xFF;
if (addr != 0x3da)
ati28800_log("ati28800k_in : %04X ", addr);
@@ -400,7 +400,7 @@ ati28800k_in(uint16_t addr, void *priv)
static void
ati28800_recalctimings(svga_t *svga)
{
ati28800_t *ati28800 = (ati28800_t *) svga->priv;
const ati28800_t *ati28800 = (ati28800_t *) svga->priv;
if (ati28800->regs[0xa3] & 0x10)
svga->ma_latch |= 0x10000;
@@ -532,7 +532,7 @@ ati28800_recalctimings(svga_t *svga)
static void
ati28800k_recalctimings(svga_t *svga)
{
ati28800_t *ati28800 = (ati28800_t *) svga->priv;
const ati28800_t *ati28800 = (ati28800_t *) svga->priv;
ati28800_recalctimings(svga);

6
src/video/vid_ati_eeprom.c
View File

@@ -35,7 +35,7 @@ ati_eeprom_load(ati_eeprom_t *eeprom, char *fn, int type)
int size;
eeprom->type = type;
strncpy(eeprom->fn, fn, sizeof(eeprom->fn) - 1);
fp = nvr_fopen(eeprom->fn, "rb");
fp = nvr_fopen(eeprom->fn, "rb");
size = eeprom->type ? 512 : 128;
if (!fp) {
memset(eeprom->data, 0xff, size);
@@ -53,7 +53,7 @@ ati_eeprom_load_mach8(ati_eeprom_t *eeprom, char *fn)
int size;
eeprom->type = 0;
strncpy(eeprom->fn, fn, sizeof(eeprom->fn) - 1);
fp = nvr_fopen(eeprom->fn, "rb");
fp = nvr_fopen(eeprom->fn, "rb");
size = 128;
if (!fp) { /*The ATI Graphics Ultra bios expects an immediate write to nvram if none is present at boot time otherwise
it would hang the machine.*/
@@ -95,7 +95,7 @@ ati_eeprom_write(ati_eeprom_t *eeprom, int ena, int clk, int dat)
break;
eeprom->state = EEPROM_OPCODE;
#ifdef FALLTHROUGH_ANNOTATION
[[fallthrough]];
[[fallthrough]];
#endif
case EEPROM_OPCODE:
eeprom->opcode = (eeprom->opcode << 1) | (dat ? 1 : 0);

92
src/video/vid_ati_mach64.c
View File

@@ -91,11 +91,14 @@ typedef struct mach64_t {
uint8_t regs[256];
int index;
int type, pci;
int type;
int pci;
uint8_t pci_slot;
uint8_t irq_state;
uint8_t pci_regs[256];
uint8_t int_line;
int card;
int bank_r[2];
int bank_w[2];
@@ -503,7 +506,7 @@ mach64_in(uint16_t addr, void *priv)
void
mach64_recalctimings(svga_t *svga)
{
mach64_t *mach64 = (mach64_t *) svga->priv;
const mach64_t *mach64 = (mach64_t *) svga->priv;
if (((mach64->crtc_gen_cntl >> 24) & 3) == 3) {
svga->vtotal = (mach64->crtc_v_total_disp & 2047) + 1;
@@ -620,27 +623,16 @@ mach64_updatemapping(mach64_t *mach64)
/*8 MB aperture*/
mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 0x4000), 0x4000);
} else if ((mach64->config_cntl & 3) == 1) {
} else {
/*4 MB aperture*/
mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (4 << 20) - 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((4 << 20) - 0x4000), 0x4000);
} else {
/*Disable aperture on reserved values*/
mem_mapping_disable(&mach64->linear_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping);
}
} else {
if ((mach64->config_cntl & 3) == 2) {
/*2*8 MB aperture*/
mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 0x4000), 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping_2, mach64->linear_base + ((16 << 20) - 0x4000), 0x4000);
} else {
/*Disable aperture on reserved values*/
mem_mapping_disable(&mach64->linear_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping_2);
}
/*2*8 MB aperture*/
mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 0x4000), 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping_2, mach64->linear_base + ((16 << 20) - 0x4000), 0x4000);
}
} else {
mem_mapping_disable(&mach64->linear_mapping);
@@ -657,9 +649,9 @@ mach64_update_irqs(mach64_t *mach64)
}
if ((mach64->crtc_int_cntl & 0xaa0024) & ((mach64->crtc_int_cntl << 1) & 0xaa0024))
pci_set_irq(mach64->card, PCI_INTA);
pci_set_irq(mach64->pci_slot, PCI_INTA, &mach64->irq_state);
else
pci_clear_irq(mach64->card, PCI_INTA);
pci_clear_irq(mach64->pci_slot, PCI_INTA, &mach64->irq_state);
}
static __inline void
@@ -678,7 +670,7 @@ mach64_wait_fifo_idle(mach64_t *mach64)
}
#define READ8(addr, var) \
switch ((addr) & 3) { \
switch ((addr) &3) { \
case 0: \
ret = (var) &0xff; \
break; \
@@ -694,7 +686,7 @@ mach64_wait_fifo_idle(mach64_t *mach64)
}
#define WRITE8(addr, var, val) \
switch ((addr) & 3) { \
switch ((addr) &3) { \
case 0: \
var = (var & 0xffffff00) | (val); \
break; \
@@ -749,7 +741,7 @@ mach64_accel_write_fifo(mach64_t *mach64, uint32_t addr, uint8_t val)
case 0x11f:
WRITE8(addr, mach64->dst_height_width, val);
#ifdef FALLTHROUGH_ANNOTATION
[[fallthrough]];
[[fallthrough]];
#endif
case 0x113:
if (((addr & 0x3ff) == 0x11b || (addr & 0x3ff) == 0x11f || (addr & 0x3ff) == 0x113) && !(val & 0x80)) {
@@ -974,7 +966,7 @@ mach64_accel_write_fifo(mach64_t *mach64, uint32_t addr, uint8_t val)
case 0x2a5:
addr += 2;
#ifdef FALLTHROUGH_ANNOTATION
[[fallthrough]];
[[fallthrough]];
#endif
case 0x2aa:
case 0x2ab:
@@ -991,7 +983,7 @@ mach64_accel_write_fifo(mach64_t *mach64, uint32_t addr, uint8_t val)
case 0x2b1:
addr += 2;
#ifdef FALLTHROUGH_ANNOTATION
[[fallthrough]];
[[fallthrough]];
#endif
case 0x2b6:
case 0x2b7:
@@ -1245,8 +1237,8 @@ mach64_queue(mach64_t *mach64, uint32_t addr, uint32_t val, uint32_t type)
void
mach64_start_fill(mach64_t *mach64)
{
mach64->accel.dst_x = 0;
mach64->accel.dst_y = 0;
mach64->accel.dst_x = 0;
mach64->accel.dst_y = 0;
mach64->accel.dst_x_start = (mach64->dst_y_x >> 16) & 0xfff;
if ((mach64->dst_y_x >> 16) & 0x1000)
@@ -1263,11 +1255,11 @@ mach64_start_fill(mach64_t *mach64)
mach64->accel.dst_width = (mach64->accel.dst_width & ~7) + 8;
}
mach64->accel.x_count = mach64->accel.dst_width;
mach64->accel.x_count = mach64->accel.dst_width;
mach64->accel.xx_count = 0;
mach64->accel.src_x = 0;
mach64->accel.src_y = 0;
mach64->accel.src_x = 0;
mach64->accel.src_y = 0;
mach64->accel.src_x_start = (mach64->src_y_x >> 16) & 0xfff;
if ((mach64->src_y_x >> 16) & 0x1000)
@@ -1571,12 +1563,12 @@ mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
switch (mach64->accel.op) {
case OP_RECT:
while (count) {
uint8_t write_mask = 0;
uint32_t src_dat = 0;
uint8_t write_mask = 0;
uint32_t src_dat = 0;
uint32_t dest_dat;
uint32_t host_dat = 0;
uint32_t old_dest_dat;
int mix = 0;
int mix = 0;
int dst_x;
int dst_y;
int src_x;
@@ -1710,7 +1702,7 @@ mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
}
if (!(mach64->dst_cntl & DST_POLYGON_EN) || mach64->accel.poly_draw) {
READ(mach64->accel.dst_offset + ((dst_y) * mach64->accel.dst_pitch) + (dst_x), dest_dat, mach64->accel.dst_size);
READ(mach64->accel.dst_offset + ((dst_y) *mach64->accel.dst_pitch) + (dst_x), dest_dat, mach64->accel.dst_size);
switch (mach64->accel.clr_cmp_fn) {
case 1: /*TRUE*/
@@ -1777,8 +1769,8 @@ mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
mach64->accel.x_count--;
if (mach64->accel.x_count <= 0) {
mach64->accel.xx_count = 0;
mach64->accel.x_count = mach64->accel.dst_width;
mach64->accel.dst_x = 0;
mach64->accel.x_count = mach64->accel.dst_width;
mach64->accel.dst_x = 0;
mach64->accel.dst_y += mach64->accel.yinc;
mach64->accel.src_x_start = (mach64->src_y_x >> 16) & 0xfff;
mach64->accel.src_x_count = mach64->accel.src_width1;
@@ -1830,7 +1822,7 @@ mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
if (((mach64->crtc_gen_cntl >> 8) & 7) == BPP_24) {
int x = 0;
while (count) {
uint32_t src_dat = 0;
uint32_t src_dat = 0;
uint32_t dest_dat;
uint32_t host_dat = 0;
int mix = 0;
@@ -1965,7 +1957,7 @@ mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
}
} else {
while (count) {
uint32_t src_dat = 0;
uint32_t src_dat = 0;
uint32_t dest_dat;
uint32_t host_dat = 0;
int mix = 0;
@@ -2879,8 +2871,9 @@ mach64_ext_readb(uint32_t addr, void *priv)
uint16_t
mach64_ext_readw(uint32_t addr, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
const mach64_t *mach64 = (mach64_t *) priv;
uint16_t ret;
if (!(addr & 0x400)) {
mach64_log("nmach64_ext_readw: addr=%04x\n", addr);
ret = 0xffff;
@@ -2907,8 +2900,9 @@ mach64_ext_readw(uint32_t addr, void *priv)
uint32_t
mach64_ext_readl(uint32_t addr, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
uint32_t ret;
const mach64_t *mach64 = (mach64_t *) priv;
uint32_t ret;
if (!(addr & 0x400)) {
mach64_log("nmach64_ext_readl: addr=%04x\n", addr);
ret = 0xffffffff;
@@ -3317,7 +3311,7 @@ uint8_t
mach64_ext_inb(uint16_t port, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
uint8_t ret = 0xff;
uint8_t ret = 0xff;
switch (port) {
case 0x02ec:
@@ -4036,9 +4030,9 @@ mach64_overlay_draw(svga_t *svga, int displine)
}
} else {
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x++) {
int h = h_acc >> 12;
int gr_cmp = 0;
int vid_cmp = 0;
int h = h_acc >> 12;
int gr_cmp = 0;
int vid_cmp = 0;
int use_video = 0;
switch (video_key_fn) {
@@ -4216,7 +4210,7 @@ mach64_io_set(mach64_t *mach64)
uint8_t
mach64_pci_read(UNUSED(int func), int addr, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
const mach64_t *mach64 = (mach64_t *) priv;
switch (addr) {
case 0x00:
@@ -4409,7 +4403,7 @@ mach64_common_init(const device_t *info)
mach64_io_set(mach64);
if (info->flags & DEVICE_PCI)
mach64->card = pci_add_card(PCI_ADD_VIDEO, mach64_pci_read, mach64_pci_write, mach64);
pci_add_card(PCI_ADD_NORMAL, mach64_pci_read, mach64_pci_write, mach64, &mach64->pci_slot);
mach64->pci_regs[PCI_REG_COMMAND] = 3;
mach64->pci_regs[0x30] = 0x00;
@@ -4448,7 +4442,7 @@ mach64gx_init(const device_t *info)
mach64->type = MACH64_GX;
mach64->pci = !!(info->flags & DEVICE_PCI);
mach64->pci_id = (int) 'X' | ((int) 'G' << 8);
mach64->pci_id = 'X' | ('G' << 8);
mach64->config_chip_id = 0x000000d7;
mach64->dac_cntl = 5 << 16; /*ATI 68860 RAMDAC*/
mach64->config_stat0 = (5 << 9) | (3 << 3); /*ATI-68860, 256Kx16 DRAM*/

528
src/video/vid_ati_mach8.c
View File

File diff suppressed because it is too large Load Diff

4
src/video/vid_cga.c
View File

@@ -99,7 +99,7 @@ cga_out(uint16_t addr, uint8_t val, void *priv)
uint8_t
cga_in(uint16_t addr, void *priv)
{
cga_t *cga = (cga_t *) priv;
const cga_t *cga = (cga_t *) priv;
uint8_t ret = 0xff;
@@ -135,7 +135,7 @@ cga_pravetz_out(UNUSED(uint16_t addr), uint8_t val, void *priv)
uint8_t
cga_pravetz_in(UNUSED(uint16_t addr), void *priv)
{
cga_t *cga = (cga_t *) priv;
const cga_t *cga = (cga_t *) priv;
return (cga->fontbase >> 8);
}

31
src/video/vid_cga_comp.c
View File

@@ -172,7 +172,7 @@ update_cga16_color(uint8_t cgamode)
video_sharpness = (int) (sharpness * 256 / 100);
}
static Bit8u
static uint8_t
byte_clamp(int v)
{
v >>= 13;
@@ -186,21 +186,20 @@ static int temp[SCALER_MAXWIDTH + 10] = { 0 };
static int atemp[SCALER_MAXWIDTH + 2] = { 0 };
static int btemp[SCALER_MAXWIDTH + 2] = { 0 };
Bit32u *
Composite_Process(uint8_t cgamode, Bit8u border, Bit32u blocks /*, bool doublewidth*/, Bit32u *TempLine)
uint32_t *
Composite_Process(uint8_t cgamode, uint8_t border, uint32_t blocks /*, bool doublewidth*/, uint32_t *TempLine)
{
int x;
Bit32u x2;
uint32_t x2;
int w = blocks * 4;
int *o;
Bit32u *rgbi;
int *b;
int *i;
Bit32u *srgb;
int *ap;
int *bp;
int *o;
const uint32_t *rgbi;
const int *b;
int *i;
uint32_t *srgb;
int *ap;
int *bp;
#define COMPOSITE_CONVERT(I, Q) \
do { \
@@ -230,15 +229,15 @@ Composite_Process(uint8_t cgamode, Bit8u border, Bit32u blocks /*, bool doublewi
o = temp;
rgbi = TempLine;
b = &CGA_Composite_Table[border * 68];
for (x = 0; x < 4; ++x)
for (uint8_t x = 0; x < 4; ++x)
OUT(b[(x + 3) & 3]);
OUT(CGA_Composite_Table[(border << 6) | ((*rgbi & 0x0f) << 2) | 3]);
for (x = 0; x < w - 1; ++x) {
for (int x = 0; x < w - 1; ++x) {
OUT(CGA_Composite_Table[((rgbi[0] & 0x0f) << 6) | ((rgbi[1] & 0x0f) << 2) | (x & 3)]);
++rgbi;
}
OUT(CGA_Composite_Table[((*rgbi & 0x0f) << 6) | (border << 2) | 3]);
for (x = 0; x < 5; ++x)
for (uint8_t x = 0; x < 5; ++x)
OUT(b[x & 3]);
if ((cgamode & 4) != 0) {
@@ -258,7 +257,7 @@ Composite_Process(uint8_t cgamode, Bit8u border, Bit32u blocks /*, bool doublewi
i = temp + 4;
ap = atemp + 1;
bp = btemp + 1;
for (x = -1; x < w + 1; ++x) {
for (int x = -1; x < w + 1; ++x) {
ap[x] = i[-4] - ((i[-2] - i[0] + i[2]) << 1) + i[4];
bp[x] = (i[-3] - i[-1] + i[1] - i[3]) << 1;
++i;

14
src/video/vid_cl54xx.c
View File

@@ -217,7 +217,10 @@ typedef struct gd54xx_t {
uint8_t fc; /* Feature Connector */
int card, id;
int id;
uint8_t pci_slot;
uint8_t irq_state;
uint8_t pos_regs[8];
@@ -484,9 +487,9 @@ gd54xx_update_irqs(gd54xx_t *gd54xx)
return;
if ((gd54xx->vblank_irq > 0) && gd54xx_vga_vsync_enabled(gd54xx))
pci_set_irq(gd54xx->card, PCI_INTA);
pci_set_irq(gd54xx->pci_slot, PCI_INTA, &gd54xx->irq_state);
else
pci_clear_irq(gd54xx->card, PCI_INTA);
pci_clear_irq(gd54xx->pci_slot, PCI_INTA, &gd54xx->irq_state);
}
static void
@@ -4056,7 +4059,10 @@ static void
io_sethandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx);
if (gd54xx->pci && id >= CIRRUS_ID_CLGD5430) {
pci_add_card(PCI_ADD_VIDEO, cl_pci_read, cl_pci_write, gd54xx);
if (romfn == NULL)
pci_add_card(PCI_ADD_VIDEO, cl_pci_read, cl_pci_write, gd54xx, &gd54xx->pci_slot);
else
pci_add_card(PCI_ADD_NORMAL, cl_pci_read, cl_pci_write, gd54xx, &gd54xx->pci_slot);
mem_mapping_disable(&gd54xx->bios_rom.mapping);
}

63
src/video/vid_ega.c
View File

@@ -56,7 +56,7 @@ static video_timings_t timing_ega = { .type = VIDEO_ISA, .write_b = 8, .write_w
static uint8_t ega_rotate[8][256];
static uint32_t pallook16[256];
static uint32_t pallook64[256];
static int ega_type = 0;
static int ega_type = 0;
static int old_overscan_color = 0;
uint8_t egaremap2bpp[256];
@@ -64,7 +64,7 @@ uint8_t egaremap2bpp[256];
/* 3C2 controls default mode on EGA. On VGA, it determines monitor type (mono or colour):
7=CGA mode (200 lines), 9=EGA mode (350 lines), 8=EGA mode (200 lines). */
int egaswitchread;
int egaswitches = 9;
int egaswitches = 9;
int update_overscan = 0;
uint8_t ega_in(uint16_t addr, void *priv);
@@ -102,6 +102,9 @@ ega_out(uint16_t addr, uint8_t val, void *priv)
case 0xb3:
ati_eeprom_write((ati_eeprom_t *) ega->eeprom, val & 8, val & 2, val & 1);
break;
default:
break;
}
break;
@@ -180,6 +183,9 @@ ega_out(uint16_t addr, uint8_t val, void *priv)
case 4:
ega->chain2_write = !(val & 4);
break;
default:
break;
}
break;
case 0x3ce:
@@ -213,11 +219,17 @@ ega_out(uint16_t addr, uint8_t val, void *priv)
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&ega->mapping, 0xb8000, 0x08000);
break;
default:
break;
}
break;
case 7:
ega->colournocare = val;
break;
default:
break;
}
break;
case 0x3d0:
@@ -244,6 +256,9 @@ ega_out(uint16_t addr, uint8_t val, void *priv)
}
}
break;
default:
break;
}
}
@@ -267,6 +282,7 @@ ega_in(uint16_t addr, void *priv)
if (ati_eeprom_read((ati_eeprom_t *) ega->eeprom))
ret |= 8;
break;
default:
ret = ega->regs[ega->index];
break;
@@ -315,7 +331,7 @@ ega_in(uint16_t addr, void *priv)
break;
case 0x3d1:
case 0x3d5:
switch(ega->crtcreg) {
switch (ega->crtcreg) {
case 0xc:
case 0xd:
case 0xe:
@@ -340,6 +356,9 @@ ega_in(uint16_t addr, void *priv)
ega->stat ^= 0x30; /*Fools IBM EGA video BIOS self-test*/
ret = ega->stat;
break;
default:
break;
}
return ret;
@@ -435,11 +454,11 @@ ega_recalctimings(ega_t *ega)
ega->hdisp *= (ega->seqregs[1] & 1) ? 16 : 18;
else
ega->hdisp *= (ega->seqregs[1] & 1) ? 8 : 9;
ega->render = ega_render_text;
ega->render = ega_render_text;
ega->hdisp_old = ega->hdisp;
} else {
ega->hdisp *= (ega->seqregs[1] & 8) ? 16 : 8;
ega->render = ega_render_graphics;
ega->render = ega_render_graphics;
ega->hdisp_old = ega->hdisp;
}
}
@@ -779,7 +798,7 @@ ega_remap_cpu_addr(uint32_t inaddr, ega_t *ega)
if (ega->gdcreg[6] & 2) {
a0mux |= 2;
}
if (ega->vram_limit <= 64*1024) {
if (ega->vram_limit <= 64 * 1024) {
a0mux |= 1;
}
@@ -798,6 +817,9 @@ ega_remap_cpu_addr(uint32_t inaddr, ega_t *ega)
case 0xC: // 32K B800
addr &= 0x7FFF;
break;
default:
break;
}
switch (a0mux) {
@@ -811,15 +833,18 @@ ega_remap_cpu_addr(uint32_t inaddr, ega_t *ega)
// A0 becomes the inversion of PGSEL (reg 0x3C2, miscout, bit 5)
// That is, 1 selects the "low" 64k, and 0 selects the "high" 64k.
addr &= ~1;
addr |= (~ega->miscout>>5)&1;
addr |= (~ega->miscout >> 5) & 1;
break;
case 3: // A0 becomes A14
addr &= ~1;
addr |= (inaddr>>14)&1;
addr |= (inaddr >> 14) & 1;
break;
case 6: // A0 becomes A16
addr &= ~1;
addr |= (inaddr>>16)&1;
addr |= (inaddr >> 16) & 1;
break;
default:
break;
}
@@ -940,6 +965,9 @@ ega_write(uint32_t addr, uint8_t val, void *priv)
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald & ega->gdcreg[8]) ^ ega->ld;
break;
default:
break;
}
}
break;
@@ -999,9 +1027,15 @@ ega_write(uint32_t addr, uint8_t val, void *priv)
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald & ega->gdcreg[8]) ^ ega->ld;
break;
default:
break;
}
}
break;
default:
break;
}
}
@@ -1111,6 +1145,9 @@ ega_init(ega_t *ega, int monitor_type, int is_mono)
case 3:
pallook64[c] = pallook16[c] = makecol32(0x34, 0xff, 0x5d);
break;
default:
break;
}
break;
case DISPLAY_AMBER:
@@ -1124,6 +1161,9 @@ ega_init(ega_t *ega, int monitor_type, int is_mono)
case 3:
pallook64[c] = pallook16[c] = makecol32(0xff, 0xe3, 0x34);
break;
default:
break;
}
break;
case DISPLAY_WHITE:
@@ -1138,6 +1178,9 @@ ega_init(ega_t *ega, int monitor_type, int is_mono)
case 3:
pallook64[c] = pallook16[c] = makecol32(0xff, 0xfd, 0xed);
break;
default:
break;
}
break;
}
@@ -1201,8 +1244,8 @@ ega_standalone_init(const device_t *info)
ega_type = 1;
switch (info->local) {
case EGA_IBM:
default:
case EGA_IBM:
rom_init(&ega->bios_rom, BIOS_IBM_PATH,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
break;

74
src/video/vid_ega_render.c
View File

@@ -115,16 +115,16 @@ ega_render_text(ega_t *ega)
ega->lastline_draw = ega->displine;
if (ega->fullchange) {
const bool doublewidth = ((ega->seqregs[1] & 8) != 0);
const bool attrblink = ((ega->attrregs[0x10] & 8) != 0);
const bool doublewidth = ((ega->seqregs[1] & 8) != 0);
const bool attrblink = ((ega->attrregs[0x10] & 8) != 0);
const bool attrlinechars = (ega->attrregs[0x10] & 4);
const bool crtcreset = ((ega->crtc[0x17] & 0x80) == 0);
const bool seq9dot = ((ega->seqregs[1] & 1) == 0);
const int dwshift = doublewidth ? 1 : 0;
const int dotwidth = 1 << dwshift;
const int charwidth = dotwidth*(seq9dot ? 9 : 8);
const bool blinked = ega->blink & 0x10;
uint32_t *p = &buffer32->line[ega->displine + ega->y_add][ega->x_add];
const bool crtcreset = ((ega->crtc[0x17] & 0x80) == 0);
const bool seq9dot = ((ega->seqregs[1] & 1) == 0);
const int dwshift = doublewidth ? 1 : 0;
const int dotwidth = 1 << dwshift;
const int charwidth = dotwidth * (seq9dot ? 9 : 8);
const bool blinked = ega->blink & 0x10;
uint32_t *p = &buffer32->line[ega->displine + ega->y_add][ega->x_add];
for (int x = 0; x < (ega->hdisp + ega->scrollcache); x += charwidth) {
uint32_t addr = ega->remap_func(ega, ega->ma) & ega->vrammask;
@@ -167,7 +167,7 @@ ega_render_text(ega_t *ega)
dat |= (dat >> 1) & 1;
for (int xx = 0; xx < charwidth; xx++)
p[xx] = (dat & (0x100 >> (xx>>dwshift))) ? fg : bg;
p[xx] = (dat & (0x100 >> (xx >> dwshift))) ? fg : bg;
ega->ma += 4;
p += charwidth;
@@ -186,28 +186,28 @@ ega_render_graphics(ega_t *ega)
ega->firstline_draw = ega->displine;
ega->lastline_draw = ega->displine;
const bool doublewidth = ((ega->seqregs[1] & 8) != 0);
const bool cga2bpp = ((ega->gdcreg[5] & 0x20) != 0);
const bool attrblink = ((ega->attrregs[0x10] & 8) != 0);
const bool blinked = ega->blink & 0x10;
const bool crtcreset = ((ega->crtc[0x17] & 0x80) == 0);
const bool seqoddeven = ((ega->seqregs[1] & 4) != 0);
const uint8_t blinkmask = (attrblink && blinked ? 0x8 : 0x0);
uint32_t *p = &buffer32->line[ega->displine + ega->y_add][ega->x_add];
const int dwshift = doublewidth ? 1 : 0;
const int dotwidth = 1 << dwshift;
const int charwidth = dotwidth*8;
int secondcclk = 0;
const bool doublewidth = ((ega->seqregs[1] & 8) != 0);
const bool cga2bpp = ((ega->gdcreg[5] & 0x20) != 0);
const bool attrblink = ((ega->attrregs[0x10] & 8) != 0);
const bool blinked = ega->blink & 0x10;
const bool crtcreset = ((ega->crtc[0x17] & 0x80) == 0);
const bool seqoddeven = ((ega->seqregs[1] & 4) != 0);
const uint8_t blinkmask = (attrblink && blinked ? 0x8 : 0x0);
uint32_t *p = &buffer32->line[ega->displine + ega->y_add][ega->x_add];
const int dwshift = doublewidth ? 1 : 0;
const int dotwidth = 1 << dwshift;
const int charwidth = dotwidth * 8;
int secondcclk = 0;
for (int x = 0; x <= (ega->hdisp + ega->scrollcache); x += charwidth) {
uint32_t addr = ega->remap_func(ega, ega->ma) & ega->vrammask;
uint8_t edat[4];
if (seqoddeven) {
// FIXME: Verify the behaviour of planes 1,3 on actual hardware
edat[0] = ega->vram[(addr | 0) ^ secondcclk];
edat[1] = ega->vram[(addr | 1) ^ secondcclk];
edat[2] = ega->vram[(addr | 2) ^ secondcclk];
edat[3] = ega->vram[(addr | 3) ^ secondcclk];
edat[0] = ega->vram[(addr | 0) ^ secondcclk];
edat[1] = ega->vram[(addr | 1) ^ secondcclk];
edat[2] = ega->vram[(addr | 2) ^ secondcclk];
edat[3] = ega->vram[(addr | 3) ^ secondcclk];
secondcclk = (secondcclk + 1) & 1;
if (secondcclk == 0)
ega->ma += 4;
@@ -219,25 +219,25 @@ ega_render_graphics(ega_t *ega)
if (cga2bpp) {
// Remap CGA 2bpp-chunky data into fully planar data
uint8_t dat0 = egaremap2bpp[edat[1] ] | (egaremap2bpp[edat[0] ] << 4);
uint8_t dat1 = egaremap2bpp[edat[1]>>1] | (egaremap2bpp[edat[0]>>1] << 4);
uint8_t dat2 = egaremap2bpp[edat[3] ] | (egaremap2bpp[edat[2] ] << 4);
uint8_t dat3 = egaremap2bpp[edat[3]>>1] | (egaremap2bpp[edat[2]>>1] << 4);
edat[0] = dat0;
edat[1] = dat1;
edat[2] = dat2;
edat[3] = dat3;
uint8_t dat0 = egaremap2bpp[edat[1]] | (egaremap2bpp[edat[0]] << 4);
uint8_t dat1 = egaremap2bpp[edat[1] >> 1] | (egaremap2bpp[edat[0] >> 1] << 4);
uint8_t dat2 = egaremap2bpp[edat[3]] | (egaremap2bpp[edat[2]] << 4);
uint8_t dat3 = egaremap2bpp[edat[3] >> 1] | (egaremap2bpp[edat[2] >> 1] << 4);
edat[0] = dat0;
edat[1] = dat1;
edat[2] = dat2;
edat[3] = dat3;
}
if (!crtcreset) {
for (int i = 0; i < 8; i += 2) {
const int outoffs = i << dwshift;
const int inshift = 6 - i;
uint8_t dat = (edatlookup[(edat[0] >> inshift) & 3][(edat[1] >> inshift) & 3] )
| (edatlookup[(edat[2] >> inshift) & 3][(edat[3] >> inshift) & 3] << 2);
uint8_t dat = (edatlookup[(edat[0] >> inshift) & 3][(edat[1] >> inshift) & 3])
| (edatlookup[(edat[2] >> inshift) & 3][(edat[3] >> inshift) & 3] << 2);
// FIXME: Confirm blink behaviour is actually XOR on real hardware
uint32_t p0 = ega->pallook[ega->egapal[((dat >> 4) & ega->plane_mask) ^ blinkmask]];
uint32_t p1 = ega->pallook[ega->egapal[(dat & ega->plane_mask) ^ blinkmask]];
uint32_t p1 = ega->pallook[ega->egapal[(dat & ega->plane_mask) ^ blinkmask]];
for (int subx = 0; subx < dotwidth; subx++)
p[outoffs + subx] = p0;
for (int subx = 0; subx < dotwidth; subx++)

4
src/video/vid_et4000w32.c
View File

@@ -69,7 +69,7 @@ typedef struct et4000w32p_t {
svga_t svga;
uint8_t banking, banking2, adjust_cursor, rev;
uint8_t banking, banking2, adjust_cursor, rev, pci_slot;
uint8_t regs[256], pci_regs[256];
@@ -2800,7 +2800,7 @@ et4000w32p_init(const device_t *info)
et4000w32p_io_set(et4000);
if (info->flags & DEVICE_PCI)
pci_add_card(PCI_ADD_VIDEO, et4000w32p_pci_read, et4000w32p_pci_write, et4000);
pci_add_card(PCI_ADD_NORMAL, et4000w32p_pci_read, et4000w32p_pci_write, et4000, &et4000->pci_slot);
/* Hardwired bits: 00000000 1xx0x0xx */
/* R/W bits: xx xxxx */

4
src/video/vid_mda.c
View File

@@ -75,7 +75,7 @@ mda_out(uint16_t addr, uint8_t val, void *priv)
uint8_t
mda_in(uint16_t addr, void *priv)
{
mda_t *mda = (mda_t *) priv;
const mda_t *mda = (mda_t *) priv;
switch (addr) {
case 0x3b0:
@@ -107,7 +107,7 @@ mda_write(uint32_t addr, uint8_t val, void *priv)
uint8_t
mda_read(uint32_t addr, void *priv)
{
mda_t *mda = (mda_t *) priv;
const mda_t *mda = (mda_t *) priv;
return mda->vram[addr & 0xfff];
}

16
src/video/vid_mga.c
View File

@@ -424,11 +424,12 @@ typedef struct mystique_t {
xcolkeyl, xcolkeyh,
xcrcbitsel;
uint8_t pci_slot, irq_state, pad, pad0;
uint8_t pci_regs[256], crtcext_regs[6],
xreg_regs[256], dmamap[16];
int card, vram_size, crtcext_idx, xreg_idx,
xzoomctrl,
int vram_size, crtcext_idx, xreg_idx, xzoomctrl,
pixel_count, trap_count;
atomic_int busy, blitter_submit_refcount,
@@ -1031,9 +1032,9 @@ mystique_update_irqs(mystique_t *mystique)
irq = 1;
if (irq)
pci_set_irq(mystique->card, PCI_INTA);
pci_set_irq(mystique->pci_slot, PCI_INTA, &mystique->irq_state);
else
pci_clear_irq(mystique->card, PCI_INTA);
pci_clear_irq(mystique->pci_slot, PCI_INTA, &mystique->irq_state);
}
#define READ8(addr, var) \
@@ -5460,7 +5461,7 @@ static void *
mystique_init(const device_t *info)
{
mystique_t *mystique = malloc(sizeof(mystique_t));
char *romfn;
char *romfn = NULL;
memset(mystique, 0, sizeof(mystique_t));
@@ -5524,7 +5525,10 @@ mystique_init(const device_t *info)
NULL, 0, mystique);
mem_mapping_disable(&mystique->iload_mapping);
mystique->card = pci_add_card(PCI_ADD_VIDEO, mystique_pci_read, mystique_pci_write, mystique);
if (romfn = NULL)
pci_add_card(PCI_ADD_NORMAL, mystique_pci_read, mystique_pci_write, mystique, &mystique->pci_slot);
else
pci_add_card(PCI_ADD_VIDEO, mystique_pci_read, mystique_pci_write, mystique, &mystique->pci_slot);
mystique->pci_regs[0x06] = 0x80;
mystique->pci_regs[0x07] = 0 << 1;
mystique->pci_regs[0x2c] = mystique->bios_rom.rom[0x7ff8];

16
src/video/vid_s3.c
View File

@@ -209,7 +209,9 @@ typedef struct s3_t {
uint32_t linear_base, linear_size;
uint8_t pci_regs[256];
int card;
uint8_t pci_slot;
uint8_t irq_state;
uint32_t vram_mask;
uint8_t data_available;
@@ -465,9 +467,9 @@ s3_update_irqs(s3_t *s3)
return;
if (s3->subsys_cntl & s3->subsys_stat & INT_MASK) {
pci_set_irq(s3->card, PCI_INTA);
pci_set_irq(s3->pci_slot, PCI_INTA, &s3->irq_state);
} else {
pci_clear_irq(s3->card, PCI_INTA);
pci_clear_irq(s3->pci_slot, PCI_INTA, &s3->irq_state);
}
}
@@ -8349,8 +8351,12 @@ s3_init(const device_t *info)
return NULL;
}
if (s3->pci)
s3->card = pci_add_card(PCI_ADD_VIDEO, s3_pci_read, s3_pci_write, s3);
if (s3->pci) {
if (bios_fn == NULL)
pci_add_card(PCI_ADD_VIDEO, s3_pci_read, s3_pci_write, s3, &s3->pci_slot);
else
pci_add_card(PCI_ADD_NORMAL, s3_pci_read, s3_pci_write, s3, &s3->pci_slot);
}
s3->i2c = i2c_gpio_init("ddc_s3");
s3->ddc = ddc_init(i2c_gpio_get_bus(s3->i2c));

131
src/video/vid_s3_virge.c
View File

@@ -172,7 +172,9 @@ typedef struct virge_t {
uint32_t linear_base, linear_size;
uint8_t pci_regs[256];
int card;
uint8_t pci_slot;
uint8_t irq_state;
int pci;
int chip;
@@ -278,7 +280,7 @@ typedef struct virge_t {
uint32_t cmd_dma_base;
uint32_t dma_ptr;
uint64_t blitter_time;
volatile int fifo_slot;
int fifo_slots_num;
pc_timer_t tri_timer;
@@ -418,9 +420,9 @@ static void
s3_virge_update_irqs(virge_t *virge)
{
if ((virge->svga.crtc[0x32] & 0x10) && (virge->subsys_stat & (virge->subsys_cntl & INT_MASK)))
pci_set_irq(virge->card, PCI_INTA);
pci_set_irq(virge->pci_slot, PCI_INTA, &virge->irq_state);
else
pci_clear_irq(virge->card, PCI_INTA);
pci_clear_irq(virge->pci_slot, PCI_INTA, &virge->irq_state);
}
static void
@@ -997,9 +999,9 @@ s3_virge_vblank_start(svga_t *svga)
static void
s3_virge_mmio_fifo_write(uint32_t addr, uint8_t val, virge_t *virge)
{
if ((addr & 0xffff) < 0x8000) {
if ((addr & 0xffff) < 0x8000)
s3_virge_bitblt(virge, 8, val);
} else {
else {
switch (addr & 0xffff) {
case 0x859c:
virge->cmd_dma = val;
@@ -1031,7 +1033,6 @@ s3_virge_mmio_fifo_write_l(uint32_t addr, uint32_t val, virge_t *virge)
else
s3_virge_bitblt(virge, 32, val);
} else {
virge->fifo_slot++;
switch (addr & 0xfffc) {
case 0x8590:
virge->cmd_dma_base = val;
@@ -1479,16 +1480,25 @@ s3_virge_mmio_read(uint32_t addr, void *priv)
s3_virge_log("[%04X:%08X]: MMIO ReadB addr = %04x\n", CS, cpu_state.pc, addr & 0xffff);
switch (addr & 0xffff) {
case 0x8505:
ret = 0;
if (virge->s3d_busy || virge->fifo_slot) {
ret = 0x10;
} else {
ret = 0x30;
}
if (virge->fifo_slot)
virge->fifo_slot--;
case 0x8504:
virge->subsys_stat |= (INT_3DF_EMP | INT_FIFO_EMP);
ret = virge->subsys_stat;
s3_virge_update_irqs(virge);
return ret;
case 0x8505:
ret = 0xd0;
if (!virge->s3d_busy)
ret |= 0x20;
return ret;
case 0x850c:
ret = virge->advfunc_cntl & 0x3f;
ret |= virge->fifo_slots_num << 6;
ret &= 0xff;
break;
case 0x850d:
ret = virge->fifo_slots_num >> 2;
break;
case 0x83b0:
case 0x83b1:
@@ -1564,15 +1574,19 @@ s3_virge_mmio_read_w(uint32_t addr, void *priv)
switch (addr & 0xfffe) {
case 0x8504:
if (!virge->fifo_slot)
virge->subsys_stat |= INT_FIFO_EMP;
ret = 0xd000;
if (!virge->s3d_busy)
ret |= 0x2000;
virge->subsys_stat |= (INT_3DF_EMP | INT_FIFO_EMP);
ret |= virge->subsys_stat;
if (virge->fifo_slot)
virge->fifo_slot--;
ret |= 0x30; /*A bit of a workaround at the moment.*/
s3_virge_update_irqs(virge);
return ret;
case 0x850c:
ret = virge->advfunc_cntl & 0x3f;
ret |= virge->fifo_slots_num << 6;
break;
case 0x859c:
return virge->cmd_dma;
@@ -1660,21 +1674,19 @@ s3_virge_mmio_read_l(uint32_t addr, void *priv)
break;
case 0x8504:
if (virge->s3d_busy || virge->fifo_slot) {
ret = (0x10 << 8);
} else {
ret = (0x10 << 8) | (1 << 13);
if (!virge->s3d_busy)
virge->subsys_stat |= INT_3DF_EMP;
if (!virge->fifo_slot)
virge->subsys_stat |= INT_FIFO_EMP;
}
ret = 0x0000d000;
if (!virge->s3d_busy)
ret |= 0x00002000;
virge->subsys_stat |= (INT_3DF_EMP | INT_FIFO_EMP);
ret |= virge->subsys_stat;
if (virge->fifo_slot)
virge->fifo_slot--;
s3_virge_update_irqs(virge);
break;
case 0x850c:
ret = virge->advfunc_cntl & 0x3f;
ret |= virge->fifo_slots_num << 6;
break;
case 0x8590:
ret = virge->cmd_dma_base;
break;
@@ -3498,26 +3510,41 @@ s3_virge_hwcursor_draw(svga_t *svga, int displine)
svga->hwcursor_latch.addr += 16;
switch (svga->bpp) {
default:
if (virge->chip != S3_VIRGEGX2) {
fg = svga->pallook[virge->hwc_fg_col & 0xff];
bg = svga->pallook[virge->hwc_bg_col & 0xff];
break;
}
#ifdef FALLTHROUGH_ANNOTATION
[[fallthrough]];
#endif
case 15:
fg = video_15to32[virge->hwc_fg_col & 0xffff];
bg = video_15to32[virge->hwc_bg_col & 0xffff];
break;
if (virge->chip != S3_VIRGEGX2) {
fg = video_15to32[virge->hwc_fg_col & 0xffff];
bg = video_15to32[virge->hwc_bg_col & 0xffff];
break;
}
#ifdef FALLTHROUGH_ANNOTATION
[[fallthrough]];
#endif
case 16:
fg = video_16to32[virge->hwc_fg_col & 0xffff];
bg = video_16to32[virge->hwc_bg_col & 0xffff];
break;
if (virge->chip != S3_VIRGEGX2) {
fg = video_16to32[virge->hwc_fg_col & 0xffff];
bg = video_16to32[virge->hwc_bg_col & 0xffff];
break;
}
#ifdef FALLTHROUGH_ANNOTATION
[[fallthrough]];
#endif
case 24:
case 32:
fg = virge->hwc_fg_col;
bg = virge->hwc_bg_col;
break;
default:
fg = svga->pallook[virge->hwc_fg_col & 0xff];
bg = svga->pallook[virge->hwc_bg_col & 0xff];
break;
}
for (uint8_t x = 0; x < 64; x += 16) {
@@ -3527,6 +3554,9 @@ s3_virge_hwcursor_draw(svga_t *svga, int displine)
/*X11*/
for (xx = 0; xx < 16; xx++) {
if (offset >= 0) {
if (virge->chip == S3_VIRGEGX2)
dat[0] ^= 0x8000;
if (dat[0] & 0x8000)
buffer32->line[displine][offset + svga->x_add] = (dat[1] & 0x8000) ? fg : bg;
}
@@ -4086,24 +4116,29 @@ s3_virge_reset(void *priv)
switch (virge->local) {
case S3_VIRGE_325:
case S3_DIAMOND_STEALTH3D_2000:
virge->fifo_slots_num = 8;
virge->svga.crtc[0x59] = 0x70;
break;
case S3_DIAMOND_STEALTH3D_3000:
case S3_STB_VELOCITY_3D:
virge->fifo_slots_num = 8;
virge->svga.crtc[0x59] = 0x70;
break;
case S3_VIRGE_GX2:
case S3_DIAMOND_STEALTH3D_4000:
virge->fifo_slots_num = 16;
virge->svga.crtc[0x6c] = 1;
virge->svga.crtc[0x59] = 0x70;
break;
case S3_TRIO_3D2X:
virge->fifo_slots_num = 16;
virge->svga.crtc[0x6c] = 1;
virge->svga.crtc[0x59] = 0x70;
break;
default:
virge->fifo_slots_num = 8;
virge->svga.crtc[0x6c] = 1;
virge->svga.crtc[0x59] = 0x70;
break;
@@ -4262,6 +4297,7 @@ s3_virge_init(const device_t *info)
switch (info->local) {
case S3_VIRGE_325:
case S3_DIAMOND_STEALTH3D_2000:
virge->fifo_slots_num = 8;
virge->svga.decode_mask = (4 << 20) - 1;
virge->virge_id_high = 0x56;
virge->virge_id_low = 0x31;
@@ -4271,6 +4307,7 @@ s3_virge_init(const device_t *info)
break;
case S3_DIAMOND_STEALTH3D_3000:
case S3_STB_VELOCITY_3D:
virge->fifo_slots_num = 8;
virge->svga.decode_mask = (8 << 20) - 1;
virge->virge_id_high = 0x88;
virge->virge_id_low = 0x3d;
@@ -4280,6 +4317,7 @@ s3_virge_init(const device_t *info)
break;
case S3_VIRGE_GX2:
case S3_DIAMOND_STEALTH3D_4000:
virge->fifo_slots_num = 16;
virge->svga.decode_mask = (4 << 20) - 1;
virge->virge_id_high = 0x8a;
virge->virge_id_low = 0x10;
@@ -4291,6 +4329,7 @@ s3_virge_init(const device_t *info)
break;
case S3_TRIO_3D2X:
virge->fifo_slots_num = 16;
virge->svga.decode_mask = (8 << 20) - 1;
virge->virge_id_high = 0x8a;
virge->virge_id_low = 0x13;
@@ -4309,6 +4348,7 @@ s3_virge_init(const device_t *info)
#endif
default:
virge->fifo_slots_num = 8;
virge->svga.decode_mask = (4 << 20) - 1;
virge->virge_id_high = 0x8a;
virge->virge_id_low = 0x01;
@@ -4364,7 +4404,10 @@ s3_virge_init(const device_t *info)
virge->svga.crtc[0x37] = 1 | (7 << 5);
virge->svga.crtc[0x53] = 8;
virge->card = pci_add_card(virge->is_agp ? PCI_ADD_AGP : PCI_ADD_VIDEO, s3_virge_pci_read, s3_virge_pci_write, virge);
if (bios_fn == NULL)
pci_add_card(virge->is_agp ? PCI_ADD_AGP : PCI_ADD_VIDEO, s3_virge_pci_read, s3_virge_pci_write, virge, &virge->pci_slot);
else
pci_add_card(virge->is_agp ? PCI_ADD_AGP : PCI_ADD_NORMAL, s3_virge_pci_read, s3_virge_pci_write, virge, &virge->pci_slot);
virge->i2c = i2c_gpio_init("ddc_s3_virge");
virge->ddc = ddc_init(i2c_gpio_get_bus(virge->i2c));

111
src/video/vid_svga.c
View File

@@ -169,7 +169,7 @@ svga_out(uint16_t addr, uint8_t val, void *priv)
case 0x3c3:
if (xga_enabled) {
svga->xga.on = (val & 0x01) ? 0 : 1;
vga_on = !svga->xga.on;
vga_on = !svga->xga.on;
}
break;
case 0x3c4:
@@ -205,6 +205,9 @@ svga_out(uint16_t addr, uint8_t val, void *priv)
svga->chain4 = val & 8;
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) && !(svga->adv_flags & FLAG_ADDR_BY8);
break;
default:
break;
}
break;
case 0x2ea:
@@ -245,6 +248,9 @@ svga_out(uint16_t addr, uint8_t val, void *priv)
svga->dac_pos = 0;
svga->dac_addr = (svga->dac_addr + 1) & 255;
break;
default:
break;
}
break;
case 0x3ce:
@@ -283,18 +289,27 @@ svga_out(uint16_t addr, uint8_t val, void *priv)
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
}
break;
case 7:
svga->colournocare = val;
break;
default:
break;
}
svga->gdcreg[svga->gdcaddr & 15] = val;
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only);
if (((svga->gdcaddr & 15) == 5 && (val ^ o) & 0x70) || ((svga->gdcaddr & 15) == 6 && (val ^ o) & 1))
svga_recalctimings(svga);
break;
default:
break;
}
}
@@ -362,6 +377,9 @@ svga_in(uint16_t addr, void *priv)
else
ret = svga->vgapal[index].b & 0x3f;
break;
default:
break;
}
if (svga->adv_flags & FLAG_RAMDAC_SHIFT)
ret >>= 2;
@@ -403,6 +421,9 @@ svga_in(uint16_t addr, void *priv)
ret = svga->cgastat;
break;
default:
break;
}
return ret;
@@ -561,8 +582,14 @@ svga_recalctimings(svga_t *svga)
else
svga->render = svga_render_32bpp_highres;
break;
default:
break;
}
break;
default:
break;
}
}
}
@@ -602,6 +629,9 @@ svga_recalctimings(svga_t *svga)
xga_recalctimings(svga);
}
if (svga->hdisp >= 2048)
svga->monitor->mon_overscan_x = 0;
svga->y_add = (svga->monitor->mon_overscan_y >> 1) - (svga->crtc[8] & 0x1f);
svga->x_add = (svga->monitor->mon_overscan_x >> 1);
@@ -695,15 +725,15 @@ svga_do_render(svga_t *svga)
void
svga_poll(void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = &svga->dev8514;
uint32_t x;
uint32_t blink_delay;
int wx;
int wy;
int ret;
int old_ma;
int linecountff = 0;
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = &svga->dev8514;
uint32_t x;
uint32_t blink_delay;
int wx;
int wy;
int ret;
int old_ma;
int linecountff = 0;
if (!vga_on && ibm8514_enabled && ibm8514_on) {
if (!dev->local) {
@@ -792,7 +822,7 @@ svga_poll(void *priv)
if ((svga->cgastat & 8) && ((svga->displine & 15) == (svga->crtc[0x11] & 15)) && svga->vslines)
svga->cgastat &= ~8;
svga->vslines++;
if (svga->displine > 1500)
if (svga->displine > 2000)
svga->displine = 0;
} else {
timer_advance_u64(&svga->timer, svga->dispontime);
@@ -805,14 +835,14 @@ svga_poll(void *priv)
if ((svga->sc == (svga->crtc[11] & 31)) || (svga->sc == svga->rowcount))
svga->con = 0;
if (svga->dispon) {
/*Real IBM 8514/A or compatibility mode doesn't have linedbl, so skip those.*/
/*Real IBM 8514/A or compatibility mode doesn't have linedbl, so skip those.*/
if (dev->local && ibm8514_on) {
svga->linedbl = 0;
svga->linedbl = 0;
svga->linecountff = 0;
linecountff = 1;
linecountff = 1;
}
if (svga->linedbl && !svga->linecountff && !linecountff) {
svga->linecountff = 1;
svga->linecountff = 1;
svga->ma = svga->maback;
} else if (svga->sc == svga->rowcount) {
svga->linecountff = 0;
@@ -917,7 +947,7 @@ svga_poll(void *priv)
svga->oddeven ^= 1;
svga->monitor->mon_changeframecount = svga->interlace ? 3 : 2;
svga->vslines = 0;
svga->vslines = 0;
if ((dev->local && vga_on) || !dev->local) {
if (svga->interlace && svga->oddeven)
@@ -930,7 +960,7 @@ svga_poll(void *priv)
else
svga->ma = svga->maback = svga->ma_latch;
}
svga->ca = ((svga->crtc[0xe] << 8) | svga->crtc[0xf]) + ((svga->crtc[0xb] & 0x60) >> 5) + svga->ca_adj;
svga->ca = ((svga->crtc[0xe] << 8) | svga->crtc[0xf]) + ((svga->crtc[0xb] & 0x60) >> 5) + svga->ca_adj;
svga->ma = (svga->ma << 2);
svga->maback = (svga->maback << 2);
svga->ca = (svga->ca << 2);
@@ -991,9 +1021,9 @@ svga_init(const device_t *info, svga_t *svga, void *priv, int memsize,
{
int e;
svga->priv = priv;
svga->priv = priv;
svga->monitor_index = monitor_index_global;
svga->monitor = &monitors[svga->monitor_index];
svga->monitor = &monitors[svga->monitor_index];
for (int c = 0; c < 256; c++) {
e = c;
@@ -1007,10 +1037,10 @@ svga_init(const device_t *info, svga_t *svga, void *priv, int memsize,
svga->attrregs[0x11] = 0;
svga->overscan_color = 0x000000;
svga->monitor->mon_overscan_x = 16;
svga->monitor->mon_overscan_y = 32;
svga->x_add = 8;
svga->y_add = 16;
svga->monitor->mon_overscan_x = 16;
svga->monitor->mon_overscan_y = 32;
svga->x_add = 8;
svga->y_add = 16;
svga->crtc[0] = 63;
svga->crtc[6] = 255;
@@ -1124,7 +1154,7 @@ svga_write_common(uint32_t addr, uint8_t val, uint8_t linear, void *priv)
svga_t *svga = (svga_t *) priv;
int writemask2 = svga->writemask;
int reset_wm = 0;
int reset_wm = 0;
latch_t vall;
uint8_t wm = svga->writemask;
uint8_t count;
@@ -1153,7 +1183,7 @@ svga_write_common(uint32_t addr, uint8_t val, uint8_t linear, void *priv)
}
} else {
svga->xga.on = 0;
vga_on = !svga->xga.on;
vga_on = !svga->xga.on;
}
}
addr = svga_decode_addr(svga, addr, 1);
@@ -1325,6 +1355,9 @@ svga_write_common(uint32_t addr, uint8_t val, uint8_t linear, void *priv)
}
}
break;
default:
break;
}
if (reset_wm)
@@ -1351,11 +1384,11 @@ svga_read_common(uint32_t addr, uint8_t linear, void *priv)
if (((svga->xga.op_mode & 7) >= 4) && (svga->xga.aperture_cntl >= 1)) {
if (svga->xga.test == 0xa5) { /*Memory size test of XGA*/
svga->xga.on = 1;
vga_on = !svga->xga.on;
vga_on = !svga->xga.on;
return svga->xga.test;
} else if (svga->xga.test == 0x5a) {
svga->xga.on = 1;
vga_on = !svga->xga.on;
vga_on = !svga->xga.on;
return svga->xga.test;
} else if ((addr == 0xa0000) || (addr == 0xa0010)) {
addr += svga->xga.read_bank;
@@ -1363,7 +1396,7 @@ svga_read_common(uint32_t addr, uint8_t linear, void *priv)
}
} else {
svga->xga.on = 0;
vga_on = !svga->xga.on;
vga_on = !svga->xga.on;
}
}
addr = svga_decode_addr(svga, addr, 0);
@@ -1401,7 +1434,7 @@ svga_read_common(uint32_t addr, uint8_t linear, void *priv)
addr &= ~1;
if (linear && ibm8514_on && (svga->adv_flags & FLAG_ATI))
addr &= svga->vram_mask;
else
else
addr <<= 2;
} else {
if (linear && ibm8514_on && (svga->adv_flags & FLAG_ATI)) {
@@ -1583,8 +1616,8 @@ svga_writeb_linear(uint32_t addr, uint8_t val, void *priv)
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*(uint8_t *) &svga->vram[addr] = val;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*&svga->vram[addr] = val;
}
void
@@ -1710,7 +1743,7 @@ svga_writel_linear(uint32_t addr, uint32_t val, void *priv)
uint8_t
svga_readb_linear(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
const svga_t *svga = (svga_t *) priv;
if (!svga->fast)
return svga_read_linear(addr, priv);
@@ -1719,7 +1752,7 @@ svga_readb_linear(uint32_t addr, void *priv)
if (addr >= svga->vram_max)
return 0xff;
return *(uint8_t *) &svga->vram[addr & svga->vram_mask];
return *&svga->vram[addr & svga->vram_mask];
}
uint16_t
@@ -1741,8 +1774,8 @@ svga_readw_common(uint32_t addr, uint8_t linear, void *priv)
addr &= svga->decode_mask;
if (svga->translate_address) {
uint8_t val1 = 0xff;
uint8_t val2 = 0xff;
uint8_t val1 = 0xff;
uint8_t val2 = 0xff;
uint32_t addr2 = svga->translate_address(addr, priv);
if (addr2 < svga->vram_max)
val1 = svga->vram[addr2 & svga->vram_mask];
@@ -1789,10 +1822,10 @@ svga_readl_common(uint32_t addr, uint8_t linear, void *priv)
addr &= svga->decode_mask;
if (svga->translate_address) {
uint8_t val1 = 0xff;
uint8_t val2 = 0xff;
uint8_t val3 = 0xff;
uint8_t val4 = 0xff;
uint8_t val1 = 0xff;
uint8_t val2 = 0xff;
uint8_t val3 = 0xff;
uint8_t val4 = 0xff;
uint32_t addr2 = svga->translate_address(addr, priv);
if (addr2 < svga->vram_max)
val1 = svga->vram[addr2 & svga->vram_mask];

7
src/video/vid_svga_render.c
View File

@@ -65,6 +65,9 @@ svga_render_blank(svga_t *svga)
case 9:
char_width = 16;
break;
default:
break;
}
uint32_t *line_ptr = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
@@ -1305,7 +1308,7 @@ svga_render_15bpp_mix_lowres(svga_t *svga)
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
p[x << 1] = p[(x << 1) + 1] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : video_15to32[dat & 0xffff];
dat >>= 16;
@@ -1386,7 +1389,7 @@ svga_render_16bpp_lowres(svga_t *svga)
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
p[x << 1] = p[(x << 1) + 1] = video_16to32[dat & 0xffff];
p[(x << 1) + 2] = p[(x << 1) + 3] = video_16to32[dat >> 16];

2
src/video/vid_table.c
View File

@@ -412,7 +412,7 @@ video_get_video_from_internal_name(char *s)
int c = 0;
while (video_cards[c].device != NULL) {
if (!strcmp((char *) video_cards[c].device->internal_name, s))
if (!strcmp(video_cards[c].device->internal_name, s))
return c;
c++;
}

13
src/video/vid_tgui9440.c
View File

@@ -103,7 +103,10 @@ typedef struct tgui_t {
svga_t svga;
int pci;
int type, card;
uint8_t pci_slot;
uint8_t irq_state;
int type;
uint8_t int_line;
uint8_t pci_regs[256];
@@ -220,9 +223,9 @@ tgui_update_irqs(tgui_t *tgui)
return;
if (!(tgui->oldctrl1 & 0x40)) {
pci_set_irq(tgui->card, PCI_INTA);
pci_set_irq(tgui->pci_slot, PCI_INTA, &tgui->irq_state);
} else {
pci_clear_irq(tgui->card, PCI_INTA);
pci_clear_irq(tgui->pci_slot, PCI_INTA, &tgui->irq_state);
}
}
@@ -3516,9 +3519,9 @@ tgui_init(const device_t *info)
if (tgui->pci && (tgui->type >= TGUI_9440)) {
if (tgui->has_bios)
tgui->card = pci_add_card(PCI_ADD_VIDEO, tgui_pci_read, tgui_pci_write, tgui);
pci_add_card(PCI_ADD_NORMAL, tgui_pci_read, tgui_pci_write, tgui, &tgui->pci_slot);
else
tgui->card = pci_add_card(PCI_ADD_VIDEO | PCI_ADD_STRICT, tgui_pci_read, tgui_pci_write, tgui);
pci_add_card(PCI_ADD_VIDEO | PCI_ADD_STRICT, tgui_pci_read, tgui_pci_write, tgui, &tgui->pci_slot);
}
tgui->pci_regs[PCI_REG_COMMAND] = 7;

3
src/video/vid_vga.c
View File

@@ -69,6 +69,9 @@ vga_out(uint16_t addr, uint8_t val, void *priv)
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}

2
src/video/vid_voodoo.c
View File

@@ -923,7 +923,7 @@ voodoo_card_init(void)
else
voodoo_generate_filter_v1(voodoo);
pci_add_card(PCI_ADD_NORMAL, voodoo_pci_read, voodoo_pci_write, voodoo);
pci_add_card(PCI_ADD_NORMAL, voodoo_pci_read, voodoo_pci_write, voodoo, &voodoo->pci_slot);
mem_mapping_add(&voodoo->mapping, 0, 0, NULL, voodoo_readw, voodoo_readl, NULL, voodoo_writew, voodoo_writel, NULL, MEM_MAPPING_EXTERNAL, voodoo);

16
src/video/vid_voodoo_banshee.c
View File

@@ -142,8 +142,11 @@ typedef struct banshee_t {
int desktop_y;
uint32_t desktop_stride_tiled;
int type, card, agp, has_bios;
int vblank_irq;
int type, agp;
int has_bios, vblank_irq;
uint8_t pci_slot;
uint8_t irq_state;
void *i2c, *i2c_ddc, *ddc;
} banshee_t;
@@ -306,9 +309,9 @@ static void
banshee_update_irqs(banshee_t *banshee)
{
if (banshee->vblank_irq > 0 && banshee_vga_vsync_enabled(banshee)) {
pci_set_irq(banshee->card, PCI_INTA);
pci_set_irq(banshee->pci_slot, PCI_INTA, &banshee->irq_state);
} else {
pci_clear_irq(banshee->card, PCI_INTA);
pci_clear_irq(banshee->pci_slot, PCI_INTA, &banshee->irq_state);
}
}
@@ -3146,7 +3149,10 @@ banshee_init_common(const device_t *info, char *fn, int has_sgram, int type, int
banshee->dramInit1 = 1 << 30; /*SDRAM*/
banshee->svga.decode_mask = 0x1ffffff;
banshee->card = pci_add_card(banshee->agp ? PCI_ADD_AGP : PCI_ADD_VIDEO, banshee_pci_read, banshee_pci_write, banshee);
if (banshee->has_bios)
pci_add_card(banshee->agp ? PCI_ADD_AGP : PCI_ADD_VIDEO, banshee_pci_read, banshee_pci_write, banshee, &banshee->pci_slot);
else
pci_add_card(banshee->agp ? PCI_ADD_AGP : PCI_ADD_NORMAL, banshee_pci_read, banshee_pci_write, banshee, &banshee->pci_slot);
banshee->voodoo = voodoo_2d3d_card_init(voodoo_type);
banshee->voodoo->p = banshee;

493
src/video/vid_xga.c
View File

File diff suppressed because it is too large Load Diff

14
src/win/languages/zh-TW.rc
View File

@@ -109,7 +109,7 @@ BEGIN
MENUITEM SEPARATOR
MENUITEM "擷圖(&C)\tCtrl+F11", IDM_ACTION_SCREENSHOT
MENUITEM SEPARATOR
MENUITEM "首選項(&P)...", IDM_PREFERENCES
MENUITEM "偏好設定(&P)...", IDM_PREFERENCES
#ifdef DISCORD
MENUITEM "啟用 Discord 整合(&D)", IDM_DISCORD
#endif
@@ -240,7 +240,7 @@ END
// Dialog
//
#define STR_PREFERENCES "首選項"
#define STR_PREFERENCES "偏好設定"
#define STR_SND_GAIN "音量增益"
#define STR_NEW_FLOPPY "新增映像"
#define STR_CONFIG "設定"
@@ -293,10 +293,10 @@ END
#define STR_JOY3 "搖桿 3..."
#define STR_JOY4 "搖桿 4..."
#define STR_SOUND1 "音訊卡 1:"
#define STR_SOUND2 "音訊卡 2:"
#define STR_SOUND3 "音訊卡 3:"
#define STR_SOUND4 "音訊卡 4:"
#define STR_SOUND1 "音效卡 1:"
#define STR_SOUND2 "音效卡 2:"
#define STR_SOUND3 "音效卡 3:"
#define STR_SOUND4 "音效卡 4:"
#define STR_MIDI_OUT "MIDI 輸出裝置:"
#define STR_MIDI_IN "MIDI 輸入裝置:"
#define STR_MPU401 "獨立 MPU-401"
@@ -357,7 +357,7 @@ END
#define STR_SPECIFY "指定(&S)..."
#define STR_SECTORS "磁區(S):"
#define STR_HEADS "磁頭(H):"
#define STR_CYLS "柱面(C):"
#define STR_CYLS "磁柱(C):"
#define STR_SIZE_MB "大小 (MB):"
#define STR_TYPE "類型:"
#define STR_IMG_FORMAT "映像格式:"