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[core] Move platform/ files to cores/

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This commit is contained in:
Kuba Szczodrzyński
2023-02-25 15:24:04 +01:00
parent 3407891e9c
commit f1ecb312c7
68 changed files with 0 additions and 20 deletions
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207
cores/realtek-ambz/base/config/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, training, latest versions, license
and contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool.
Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
the code with commercial support, indemnification, and middleware, under
the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
provide a safety engineered and independently SIL3 certified version under
the SafeRTOS brand: http://www.SafeRTOS.com.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
#include "platform_autoconf.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( ( uint32_t ) 1000 )
#define configSYSTICK_CLOCK_HZ 32768
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 512 )
#ifdef CONFIG_WIFI_EN
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 160 * 1024 ) )
#else
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 20 * 1024 ) )
#endif
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_CO_ROUTINES 1
#define configUSE_MUTEXES 1
#define configUSE_TIMERS 1
#define configMAX_PRIORITIES ( 11 )
#define PRIORITIE_OFFSET ( 4 )
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_ALTERNATIVE_API 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configGENERATE_RUN_TIME_STATS 0
#if configGENERATE_RUN_TIME_STATS
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() //( ulHighFrequencyTimerTicks = 0UL )
#define portGET_RUN_TIME_COUNTER_VALUE() xTickCount //ulHighFrequencyTimerTicks
#undef configUSE_TRACE_FACILITY
#define configUSE_TRACE_FACILITY 1
#define portCONFIGURE_STATS_PEROID_VALUE 1000 //unit Ticks
#endif
#define configTIMER_TASK_PRIORITY ( 1 )
#define configTIMER_QUEUE_LENGTH ( 10 )
#define configTIMER_TASK_STACK_DEPTH ( 512 ) //USE_MIN_STACK_SIZE modify from 512 to 256
#if (__IASMARM__ != 1)
extern void freertos_pre_sleep_processing(unsigned int *expected_idle_time);
extern void freertos_post_sleep_processing(unsigned int *expected_idle_time);
extern int freertos_ready_to_sleep();
/* Enable tickless power saving. */
#define configUSE_TICKLESS_IDLE 1
/* In wlan usage, this value is suggested to use value less than 80 milliseconds */
#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
/* It's magic trick that let us can use our own sleep function */
#define configPRE_SLEEP_PROCESSING( x ) ( freertos_pre_sleep_processing(&x) )
#define configPOST_SLEEP_PROCESSING( x ) ( freertos_post_sleep_processing(&x) )
/* It's magic trick that let us can enable/disable tickless dynamically */
#define traceLOW_POWER_IDLE_BEGIN(); do { \
if (!freertos_ready_to_sleep()) { \
mtCOVERAGE_TEST_MARKER(); \
break; \
}
// portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
#define traceLOW_POWER_IDLE_END(); } while (0);
/* It's FreeRTOS related feature but it's not included in FreeRTOS design. */
#define configUSE_WAKELOCK_PMU 1
#endif // #if (__IASMARM__ != 1)
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_pcTaskGetTaskName 1
#define INCLUDE_xTimerPendFunctionCall 1
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4 /* 15 priority levels */
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x0f
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
//#define RTK_MODE_TIMER
#endif /* FREERTOS_CONFIG_H */

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cores/realtek-ambz/base/config/autoconf.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-07-20. */
#pragma once
#include_next "autoconf.h"

333
cores/realtek-ambz/base/config/lwipopts.h Normal file
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// CHANGES:
// - 2022-05-08 undefine LWIP_PROVIDE_ERRNO
// - 2022-05-23 enable LWIP_MDNS_RESPONDER
// - 2022-05-23 set LWIP_NUM_NETIF_CLIENT_DATA to 1
// - 2022-05-23 set MEMP_NUM_UDP_PCB to 7
/**
******************************************************************************
* @file lwipopts.h
* @author MCD Application Team
* @version V1.1.0
* @date 07-October-2011
* @brief lwIP Options Configuration.
* This file is based on Utilities\lwip_v1.3.2\src\include\lwip\opt.h
* and contains the lwIP configuration for the STM32F2x7 demonstration.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
#ifndef __LWIPOPTS_H__
#define __LWIPOPTS_H__
#include_next "lwipopts.h"
#include <platform/platform_stdlib.h>
#include "platform_opts.h"
#define WIFI_LOGO_CERTIFICATION_CONFIG 0 //for ping 10k test buffer setting
/**
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
* critical regions during buffer allocation, deallocation and memory
* allocation and deallocation.
*/
#define SYS_LIGHTWEIGHT_PROT 1
/* Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores
should be used instead */
#define LWIP_COMPAT_MUTEX 1
#define LWIP_COMPAT_MUTEX_ALLOWED 1
#define LWIP_TCPIP_TIMEOUT 1
#define ETHARP_TRUST_IP_MAC 0
#define IP_REASSEMBLY 1
#define IP_FRAG 1
#define ARP_QUEUEING 0
/**
* NO_SYS==1: Provides VERY minimal functionality. Otherwise,
* use lwIP facilities.
*/
#define NO_SYS 0
#ifndef CONFIG_DYNAMIC_TICKLESS
#define CONFIG_DYNAMIC_TICKLESS 0
#endif
/* ---------- Memory options ---------- */
/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
byte alignment -> define MEM_ALIGNMENT to 2. */
#define MEM_ALIGNMENT 4
/* MEM_SIZE: the size of the heap memory. If the application will send
a lot of data that needs to be copied, this should be set high. */
#if WIFI_LOGO_CERTIFICATION_CONFIG
#define MEM_SIZE (10*1024) //for ping 10k test
#elif CONFIG_ETHERNET
#define MEM_SIZE (6*1024) //for iperf test
#else
#define MEM_SIZE (5*1024)
#endif
/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
sends a lot of data out of ROM (or other static memory), this
should be set high. */
#define MEMP_NUM_PBUF 100
/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
per active UDP "connection". */
#define MEMP_NUM_UDP_PCB 7
/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
connections. */
#define MEMP_NUM_TCP_PCB 10
/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
connections. */
#define MEMP_NUM_TCP_PCB_LISTEN 5
/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
segments. */
#define MEMP_NUM_TCP_SEG 20
/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
timeouts. */
#define MEMP_NUM_SYS_TIMEOUT 10
/* ---------- Pbuf options ---------- */
/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
#if WIFI_LOGO_CERTIFICATION_CONFIG
#define PBUF_POOL_SIZE 30 //for ping 10k test
#else
#define PBUF_POOL_SIZE 20
#endif
/* IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.*/
#if WIFI_LOGO_CERTIFICATION_CONFIG
#define IP_REASS_MAX_PBUFS 30 //for ping 10k test
#else
#define IP_REASS_MAX_PBUFS 10
#endif
/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
#define PBUF_POOL_BUFSIZE 500
/* ---------- TCP options ---------- */
#define LWIP_TCP 1
#define TCP_TTL 255
/* Controls if TCP should queue segments that arrive out of
order. Define to 0 if your device is low on memory. */
#define TCP_QUEUE_OOSEQ 1
/* TCP Maximum segment size. */
#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */
/* TCP sender buffer space (bytes). */
#define TCP_SND_BUF (5*TCP_MSS)
/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */
#define TCP_SND_QUEUELEN (4* TCP_SND_BUF/TCP_MSS)
/* TCP receive window. */
#define TCP_WND (2*TCP_MSS)
/* ---------- ICMP options ---------- */
#define LWIP_ICMP 1
/* ---------- ARP options ----------- */
#define LWIP_ARP 1
/* ---------- DHCP options ---------- */
/* Define LWIP_DHCP to 1 if you want DHCP configuration of
interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
turning this on does currently not work. */
#define LWIP_DHCP 1
/* ---------- UDP options ---------- */
#define LWIP_UDP 1
#define UDP_TTL 255
/* ---------- DNS options ---------- */
#define LWIP_DNS 1
/* ---------- UPNP options --------- */
#define LWIP_UPNP 0
/* Support Multicast */
#define LWIP_IGMP 1
#define LWIP_RAND() rand()
#define LWIP_SRAND() srand(sys_now())
/* Support TCP Keepalive */
#define LWIP_TCP_KEEPALIVE 1
/*LWIP_UART_ADAPTER==1: Enable LWIP_UART_ADAPTER when CONFIG_GAGENT is enabled,
because some GAGENT functions denpond on the following macro definitions.*/
#define LWIP_UART_ADAPTER 0
#if LWIP_UART_ADAPTER || CONFIG_ETHERNET
#undef LWIP_SO_SNDTIMEO
#define LWIP_SO_SNDTIMEO 1
#undef SO_REUSE
#define SO_REUSE 1
#undef MEMP_NUM_NETCONN
#define MEMP_NUM_NETCONN 10
#undef TCP_WND
#define TCP_WND (4*TCP_MSS)
#define TCP_KEEPIDLE_DEFAULT 10000UL
#define TCP_KEEPINTVL_DEFAULT 1000UL
#define TCP_KEEPCNT_DEFAULT 10U
#endif
#if CONFIG_EXAMPLE_UART_ATCMD || CONFIG_EXAMPLE_SPI_ATCMD
#undef LWIP_SO_SNDTIMEO
#define LWIP_SO_SNDTIMEO 1
#undef SO_REUSE
#define SO_REUSE 1
#undef SO_REUSE_RXTOALL
#define SO_REUSE_RXTOALL 1
#undef MEMP_NUM_NETCONN
#define MEMP_NUM_NETCONN 10
#undef MEMP_NUM_TCP_PCB
#define MEMP_NUM_TCP_PCB (MEMP_NUM_NETCONN)
#undef MEMP_NUM_UDP_PCB
#define MEMP_NUM_UDP_PCB (MEMP_NUM_NETCONN)
#undef TCP_WND
#define TCP_WND (4*TCP_MSS)
#define TCP_KEEPIDLE_DEFAULT 10000UL
#define TCP_KEEPINTVL_DEFAULT 1000UL
#define TCP_KEEPCNT_DEFAULT 10U
#define ERRNO 1
#endif
/* ---------- Statistics options ---------- */
#define LWIP_STATS 0
/*
--------------------------------------
---------- Checksum options ----------
--------------------------------------
*/
/*
The STM32F2x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware:
- To use this feature let the following define uncommented.
- To disable it and process by CPU comment the the checksum.
*/
//Do checksum by lwip - WLAN nic does not support Checksum offload
//#define CHECKSUM_BY_HARDWARE
#ifdef CHECKSUM_BY_HARDWARE
/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 0
/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 0
/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 0
/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 0
/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 0
/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 0
#else
/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 1
/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 1
/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 1
/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 1
/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 1
/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 1
#endif
/*
----------------------------------------------
---------- Sequential layer options ----------
----------------------------------------------
*/
/**
* LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
*/
#define LWIP_NETCONN 1
/*
------------------------------------
---------- Socket options ----------
------------------------------------
*/
/**
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
*/
#define LWIP_SOCKET 1
/*
-----------------------------------
---------- DEBUG options ----------
-----------------------------------
*/
#define LWIP_DEBUG 0
/*
---------------------------------
---------- OS options ----------
---------------------------------
*/
#define TCPIP_THREAD_STACKSIZE 1000
#define TCPIP_MBOX_SIZE 6
#define DEFAULT_UDP_RECVMBOX_SIZE 6
#define DEFAULT_TCP_RECVMBOX_SIZE 6
#define DEFAULT_RAW_RECVMBOX_SIZE 6
#define DEFAULT_ACCEPTMBOX_SIZE 6
#define DEFAULT_THREAD_STACKSIZE 500
#define TCPIP_THREAD_PRIO (configMAX_PRIORITIES - 2)
/* Added by Realtek */
#ifndef DNS_IGNORE_REPLY_ERR
#define DNS_IGNORE_REPLY_ERR 1
#endif /* DNS_IGNORE_REPLY_ERR */
// for mDNS support
#define LWIP_MDNS_RESPONDER 1
#define LWIP_NUM_NETIF_CLIENT_DATA 1
#endif /* __LWIPOPTS_H__ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

241
cores/realtek-ambz/base/config/platform_autoconf.h Normal file
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/*
* Automatically generated by make menuconfig: don't edit
*/
#define AUTOCONF_INCLUDED
/*
* < MENUCONFIG FOR CHIP CONFIG
*/
/*
* < CONFIG CHIP
*/
#define CONFIG_RTL8711B 1
#undef ARM_CORE_CM3
#define ARM_CORE_CM4 1
#define CONFIG_CHIP_A_CUT 1
#undef CONFIG_FPGA
/*
* < CONFIG CPU CLK
*/
#define CONFIG_CPU_CLK 1
#define CONFIG_CPU_125MHZ 1
#undef CONFIG_CPU_62_5MHZ
#undef CONFIG_CPU_31_25MHZ
#undef CONFIG_CPU_15_625MHZ
#undef CONFIG_CPU_7_8125MHZ
#undef CONFIG_CPU_4MHZ
#undef CONFIG_FPGA_CLK
#define PLATFORM_CLOCK (125000000)
#define CPU_CLOCK_SEL_VALUE (0)
/*
* < CONFIG OSC8M CLK
*/
#define CONFIG_OSC8M_CLK 1
#define CONFIG_OSC8M_8388608HZ 1
#undef CONFIG_OSC8M_8192000HZ
#undef CONFIG_OSC8M_8000000HZ
#undef CONFIG_OSC8M_16777216HZ
#define OSC8M_CLOCK (8388608)
/*
* < CONFIG TEST MODE
*/
#undef CONFIG_MP
#undef CONFIG_CP
#undef CONFIG_FT
#undef CONFIG_EQC
#undef CONFIG_RTL_SIM
#undef CONFIG_POST_SIM
/*
* < CONFIG OS
*/
#define CONFIG_KERNEL 1
#define PLATFORM_FREERTOS 1
#undef PLATFORM_UCOSII
#undef PLATFORM_ECOS
#undef CONFIG_TASK_SCHEDUL_DIS
#define TASK_SCHEDULER_DISABLED (0)
/*
* < CONFIG GTIMER
*/
#define CONFIG_TIMER_EN 1
#define CONFIG_TIMER_MODULE 1
/*
* < CONFIG WDG
*/
#define CONFIG_WDG 1
#define CONFIG_WDG_MODULE 1
/*
* < CONFIG GDMA
*/
#define CONFIG_GDMA_EN 1
#define CONFIG_GDMA_MODULE 1
/*
* < CONFIG GPIO
*/
#define CONFIG_GPIO_EN 1
#define CONFIG_GPIO_MODULE 1
/*
* < CONFIG SPI
*/
#define CONFIG_SPI_COM_EN 1
#define CONFIG_SPI_COM_MODULE 1
/*
* < CONFIG UART
*/
#define CONFIG_UART_EN 1
#define CONFIG_UART_MODULE 1
/*
* < CONFIG I2C
*/
#define CONFIG_I2C_EN 1
#define CONFIG_I2C_MODULE 1
/*
* < CONFIG I2S
*/
#define CONFIG_I2S_EN 1
#define CONFIG_I2S_MODULE 1
/*
* < CONFIG SOC PS
*/
#define CONFIG_SOC_PS_EN 1
#define CONFIG_SOC_PS_MODULE 1
/*
* < CONFIG CRYPTO
*/
#define CONFIG_CRYPTO_EN 1
#define CONFIG_CRYPTO_MODULE 1
/*
* < CONFIG PWM
*/
#define CONFIG_PWM_EN 1
/*
* < CONFIG EFUSE
*/
#define CONFIG_EFUSE_EN 1
#define CONFIG_EFUSE_MODULE 1
/*
* < CONFIG SPIC
*/
#define CONFIG_SPIC_EN 1
#define CONFIG_SPIC_MODULE 1
#define CONFIG_SPIC_PHASE_CALIBATION 1
#undef CONFIG_SPIC_4BYTES_ADDRESS
/*
* < CONFIG ADC
*/
#define CONFIG_ADC_EN 1
#define CONFIG_ADC_MODULE 1
/*
* < CONFIG SDIO Device
*/
#define CONFIG_SDIO_DEVICE_EN 1
#define CONFIG_SDIO_DEVICE_NORMAL 1
#define CONFIG_SDIO_DEVICE_MODULE 1
/*
* < CONFIG USB
*/
#define CONFIG_USB_EN 1
#define CONFIG_USB_MODULE 1
/*
* < CONFIG RDP
*/
#define CONFIG_RDP_ENABLE 1
/*
* < CONFIG PINMUX
*/
#undef CONFIG_PINMAP_ENABLE
/*
* < CONFIG PER TEST
*/
#undef CONFIG_PER_TEST
/*
* < CONFIG WIFI
*/
#define CONFIG_WIFI_EN 1
#define CONFIG_WIFI_NORMAL 1
#undef CONFIG_WIFI_TEST
#define CONFIG_WIFI_MODULE 1
/*
* < CONFIG NETWORK
*/
#define CONFIG_NETWORK 1
/*
* < CONFIG INIC
*/
#undef CONFIG_INIC_EN
/*
* < CONFIG USB_NIC
*/
#undef CONFIG_USB_DONGLE_NIC_EN
/*
* < RTK STD lib
*/
#define CONFIG_RTLIB_EN 1
#define CONFIG_RTLIB_MODULE 1
#undef CONFIG_RTLIB_VERIFY
/*
* < Add MBED SDK
*/
#undef CONFIG_MBED_ENABLED
/*
* < Build App Demo
*/
#undef CONFIG_APP_DEMO
/*
* < Dhrystone
*/
#undef CONFIG_DHRYSTONE_TEST
/*
* < SSL
*/
#undef CONFIG_SSL_ROM_TEST
/*
* < System Debug Message Config
*/
#define CONFIG_UART_LOG_HISTORY 1
#define CONFIG_DEBUG_LOG 1
#define CONFIG_DEBUG_ERR_MSG 1
#undef CONFIG_DEBUG_WARN_MSG
#undef CONFIG_DEBUG_INFO_MSG
/*
* < Build Option
*/
#define CONFIG_TOOLCHAIN_ASDK 1
#undef CONFIG_TOOLCHAIN_ARM_GCC
#define CONFIG_LINK_ROM_LIB 1
#undef CONFIG_LINK_ROM_SYMB

345
cores/realtek-ambz/base/config/platform_opts.h Normal file
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// CHANGES:
// - 2022-05-08 change CONFIG_USE_POLARSSL to CONFIG_USE_MBEDTLS
// - 2022-05-08 use static int errno
// - 2022-05-18 include lwip/init.h
// - 2022-06-13 extract errno to common/fixups/errno.h
/**
******************************************************************************
*This file contains general configurations for ameba platform
******************************************************************************
*/
#ifndef __PLATFORM_OPTS_H__
#define __PLATFORM_OPTS_H__
#include "platform_autoconf.h"
#include <lwip/init.h>
/*For MP mode setting*/
//#define SUPPORT_MP_MODE 1
/**
* For AT cmd Log service configurations
*/
#define SUPPORT_LOG_SERVICE 1
#if SUPPORT_LOG_SERVICE
#define LOG_SERVICE_BUFLEN 100 //can't larger than UART_LOG_CMD_BUFLEN(127)
#define CONFIG_LOG_HISTORY 0
#if CONFIG_LOG_HISTORY
#define LOG_HISTORY_LEN 5
#endif
#define SUPPORT_INTERACTIVE_MODE 0//on/off wifi_interactive_mode
#define CONFIG_LOG_SERVICE_LOCK 0
#endif
/* For DCT example*/
#define CONFIG_EXAMPLE_DCT 0
/**
* For interactive mode configurations, depents on log service
*/
#if SUPPORT_INTERACTIVE_MODE
#define CONFIG_INTERACTIVE_MODE 1
#define CONFIG_INTERACTIVE_EXT 0
#else
#define CONFIG_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_EXT 0
#endif
/**
* For FreeRTOS tickless configurations
*/
#define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 1 // In sleep mode, 1: suspend SDRAM, 0: no act
/******************************************************************************/
/**
* For common flash usage
*/
#define AP_SETTING_SECTOR 0x000FE000
#define UART_SETTING_SECTOR 0x000FC000
#define SPI_SETTING_SECTOR 0x000FC000
#define FAST_RECONNECT_DATA (0x80000 - 0x1000)
#define FLASH_SECTOR_SIZE 0x1000
#define CONFIG_ENABLE_RDP 0
/**
* For Wlan configurations
*/
#define CONFIG_WLAN 1
#if CONFIG_WLAN
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 //init lwip layer when start up
#define CONFIG_WIFI_IND_USE_THREAD 0 // wifi indicate worker thread
//on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_WEBSERVER 0
#define CONFIG_OTA_UPDATE 1
#define CONFIG_BSD_TCP 1//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#define CONFIG_AIRKISS 0//on or off tencent airkiss
#define CONFIG_UART_SOCKET 0
#define CONFIG_UART_XMODEM 0//support uart xmodem upgrade or not
#define CONFIG_TRANSPORT 0//on or off the at command for transport socket
/* For WPS and P2P */
#define CONFIG_ENABLE_WPS 0
#define CONFIG_ENABLE_WPS_DISCOVERY 0
#if CONFIG_ENABLE_P2P
#define CONFIG_ENABLE_WPS_AP 1
#undef CONFIG_WIFI_IND_USE_THREAD
#define CONFIG_WIFI_IND_USE_THREAD 1
#endif
#if (CONFIG_ENABLE_P2P && ((CONFIG_ENABLE_WPS_AP == 0) || (CONFIG_ENABLE_WPS == 0)))
#error "If CONFIG_ENABLE_P2P, need to define CONFIG_ENABLE_WPS_AP 1"
#endif
/* For SSL/TLS */
#define CONFIG_USE_POLARSSL 0
#define CONFIG_USE_MBEDTLS 1
#if ((CONFIG_USE_POLARSSL == 0) && (CONFIG_USE_MBEDTLS == 0)) || ((CONFIG_USE_POLARSSL == 1) && (CONFIG_USE_MBEDTLS == 1))
#undef CONFIG_USE_POLARSSL
#define CONFIG_USE_POLARSSL 1
#undef CONFIG_USE_MBEDTLS
#define CONFIG_USE_MBEDTLS 0
#endif
/* For Simple Link */
#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
/*For fast reconnection*/
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#define CONFIG_GAGENT 0
/*Disable CONFIG_EXAMPLE_WLAN_FAST_CONNECT when CONFIG_GAGENT is enabled,because
reconnect to previous AP is not suitable when re-configuration.
*/
#if CONFIG_GAGENT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#endif //end of #if CONFIG_WLAN
/*******************************************************************************/
/**
* For Ethernet configurations
*/
#define CONFIG_ETHERNET 0
#if CONFIG_ETHERNET
#define CONFIG_LWIP_LAYER 1
#define CONFIG_INIT_NET 1 //init lwip layer when start up
//on/off relative commands in log service
#define CONFIG_SSL_CLIENT 0
#define CONFIG_BSD_TCP 0//NOTE : Enable CONFIG_BSD_TCP will increase about 11KB code size
#endif
/**
* For user to adjust SLEEP_INTERVAL
*/
#define CONFIG_DYNAMIC_TICKLESS 1
/*******************************************************************************/
/**
* For iNIC configurations
*/
//#define CONFIG_INIC_EN 0//enable iNIC mode
#if CONFIG_INIC_EN
#ifndef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 0
#endif
#ifndef CONFIG_INIC_SDIO_HCI
#define CONFIG_INIC_SDIO_HCI 0 //for SDIO or USB iNIC
#endif
#ifndef CONFIG_INIC_CMD_RSP
#define CONFIG_INIC_CMD_RSP 0
#endif
#ifndef CONFIG_INIC_USB_HCI
#define CONFIG_INIC_USB_HCI 0
#endif
#endif
/******************End of iNIC configurations*******************/
/* For WIFI GET BEACON FRAME example */
#define CONFIG_EXAMPLE_GET_BEACON_FRAME 0
/* For WIFI MAC MONITOR example */
#define CONFIG_EXAMPLE_WIFI_MAC_MONITOR 0
/* For HTTP CLIENT example */
#define CONFIG_EXAMPLE_HTTP_CLIENT 0
/* For MQTT example */
#define CONFIG_EXAMPLE_MQTT 0
/* For mDNS example */
#define CONFIG_EXAMPLE_MDNS 0
/* For multicast example */
#define CONFIG_EXAMPLE_MCAST 0
/* For XML example */
#define CONFIG_EXAMPLE_XML 0
/* For socket select example */
#define CONFIG_EXAMPLE_SOCKET_SELECT 0
/* For socket nonblocking connect example */
#define CONFIG_EXAMPLE_NONBLOCK_CONNECT 0
/* For socket TCP bidirectional transmission example */
#define CONFIG_EXAMPLE_SOCKET_TCP_TRX 0
/* For ssl download example */
#define CONFIG_EXAMPLE_SSL_DOWNLOAD 0
/* For http download example */
#define CONFIG_EXAMPLE_HTTP_DOWNLOAD 0
/* For httpc example */
#define CONFIG_EXAMPLE_HTTPC 0
/* For httpd example */
#define CONFIG_EXAMPLE_HTTPD 0
/* For tcp keepalive example */
#define CONFIG_EXAMPLE_TCP_KEEPALIVE 0
/* For sntp show time example */
#define CONFIG_EXAMPLE_SNTP_SHOWTIME 0
/* For websocket client example */
#define CONFIG_EXAMPLE_WEBSOCKET 0
/* For UART Module AT command example */
#define CONFIG_EXAMPLE_UART_ATCMD 0
#if CONFIG_EXAMPLE_UART_ATCMD
#undef CONFIG_OTA_UPDATE
#define CONFIG_OTA_UPDATE 1
#undef CONFIG_TRANSPORT
#define CONFIG_TRANSPORT 1
#undef LOG_SERVICE_BUFLEN
#define LOG_SERVICE_BUFLEN 1600
#undef CONFIG_LOG_SERVICE_LOCK
#define CONFIG_LOG_SERVICE_LOCK 1
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
/****************** For EAP method example *******************/
#define CONFIG_EXAMPLE_EAP 0
// on/off specified eap method
#define CONFIG_ENABLE_PEAP 0
#define CONFIG_ENABLE_TLS 0
#define CONFIG_ENABLE_TTLS 0
// optional feature: whether to verify the cert of radius server
#define ENABLE_EAP_SSL_VERIFY_SERVER 0
#if CONFIG_ENABLE_PEAP || CONFIG_ENABLE_TLS || CONFIG_ENABLE_TTLS
#define CONFIG_ENABLE_EAP
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
#if CONFIG_ENABLE_TLS
#define ENABLE_EAP_SSL_VERIFY_CLIENT 1
#else
#define ENABLE_EAP_SSL_VERIFY_CLIENT 0
#endif
/******************End of EAP configurations*******************/
/* For iNIC host example*/
#ifdef CONFIG_INIC_GSPI_HOST //this flag is defined in IAR project
#define CONFIG_EXAMPLE_INIC_GSPI_HOST 1
#if CONFIG_EXAMPLE_INIC_GSPI_HOST
#define CONFIG_INIC_HOST 1
#undef CONFIG_WLAN
#define CONFIG_WLAN 0
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#undef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 1
#undef CONFIG_BSD_TCP
#define CONFIG_BSD_TCP 1
#endif
#endif
/*For uart update example*/
#define CONFIG_UART_UPDATE 0
#if CONFIG_UART_UPDATE
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 0
#endif
/* For uart adapter example */
/* Please also configure LWIP_UART_ADAPTER to 1
in lwip_opt.h for support uart adapter*/
#define CONFIG_EXAMPLE_UART_ADAPTER 0
#if CONFIG_EXAMPLE_UART_ADAPTER
#undef CONFIG_EXAMPLE_WLAN_FAST_CONNECT
#define CONFIG_EXAMPLE_WLAN_FAST_CONNECT 1
#undef CONFIG_EXAMPLE_MDNS
#define CONFIG_EXAMPLE_MDNS 1
#endif
/* For wifi scenarios example (Wi-Fi, WPS enrollee, P2P GO) */
// also need to enable WPS and P2P
#define CONFIG_EXAMPLE_WLAN_SCENARIO 0
/* For broadcast example */
#define CONFIG_EXAMPLE_BCAST 0
/* For high-load memory use case memory usage */
#define CONFIG_EXAMPLE_HIGH_LOAD_MEMORY_USE 0
/* For rarp example */
#define CONFIG_EXAMPLE_RARP 0
/* For ssl server example */
#define CONFIG_EXAMPLE_SSL_SERVER 0
#if CONFIG_QQ_LINK
#define FATFS_R_10C
#define FATFS_DISK_USB 0
#define FATFS_DISK_SD 1
#endif
#if CONFIG_ENABLE_WPS
#define WPS_CONNECT_RETRY_COUNT 4
#define WPS_CONNECT_RETRY_INTERVAL 5000 // in ms
#endif
#define AUTO_RECONNECT_COUNT 8
#define AUTO_RECONNECT_INTERVAL 5 // in sec
#if CONFIG_INIC_EN
#undef CONFIG_INCLUDE_SIMPLE_CONFIG
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
#define SUPPORT_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_MODE 0
#define CONFIG_INTERACTIVE_EXT 0
#define CONFIG_OTA_UPDATE 0
#endif
#endif

22
cores/realtek-ambz/base/inc/fixups/strproc.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-11-26. */
// make <strproc.h> not #define isprint, isdigit, isxdigit, islower and isspace
// this conflicts with stdlib <ctype.h>, if <strproc.h> is included before it
// include <ctype.h> before to get all its macros
#include <ctype.h>
// make 'static inline int _tolower' unused
#undef _tolower
#define _tolower _tolower_dummy
#include_next <strproc.h>
// restore _tolower to ctype's macro
#undef _tolower
#define _tolower(__c) ((unsigned char)(__c) - 'A' + 'a')
// dirty fix for compiling mbedTLS which uses _B as variable name
#ifdef CONFIG_SSL_RSA
#undef _B
#endif

5
cores/realtek-ambz/base/inc/proxy/lwip_timers.h Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-05-22. */
#pragma once
#include <lwip/timeouts.h>

118
cores/realtek-ambz/base/src/fixups/app_start_patch.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
// NOTE: this file has the default main() function removed.
#include "ameba_soc.h"
#include "build_info.h"
#if (defined(CONFIG_POST_SIM))
void Simulation_Init(void);
#endif
#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)
extern void init_rom_wlan_ram_map(void);
extern VOID wlan_network(VOID);
#endif
#ifdef CONFIG_MBED_ENABLED
extern void __libc_fini_array (void);
extern void __libc_init_array (void);
extern void SVC_Handler (void);
extern void PendSV_Handler (void);
extern void SysTick_Handler (void);
void APP_StartMbed(void)
{
InterruptForOSInit((VOID*)SVC_Handler,
(VOID*)PendSV_Handler,
(VOID*)SysTick_Handler);
__asm (
"ldr r0, =SystemInit\n"
"blx r0\n"
"ldr r0, =_start\n"
"bx r0\n"
);
for(;;);
}
#endif
void APP_InitTrace(void)
{
u32 debug[4];
#if (defined(CONFIG_POST_SIM) || defined(CONFIG_CP))
return;
#endif
debug[LEVEL_ERROR] = BIT(MODULE_BOOT);
debug[LEVEL_WARN] = 0x0;
debug[LEVEL_INFO] = BIT(MODULE_BOOT);
debug[LEVEL_TRACE] = 0x0;
#ifdef CONFIG_DEBUG_ERR_MSG
debug[LEVEL_ERROR] = 0xFFFFFFFF;
#endif
#ifdef CONFIG_DEBUG_WARN_MSG
debug[LEVEL_WARN] = 0xFFFFFFFF;
#endif
#ifdef CONFIG_DEBUG_INFO_MSG
debug[LEVEL_INFO] = 0xFFFFFFFF;
#endif
LOG_MASK(debug);
DBG_PRINTF(MODULE_BOOT, LEVEL_INFO, "APP_InitTrace: %x:%x:%x:%x\n",debug[0], debug[1], debug[2], debug[3]);
DBG_PRINTF(MODULE_BOOT, LEVEL_ERROR, "APP_InitTrace: %x:%x:%x:%x\n",debug[0], debug[1], debug[2], debug[3]);
}
extern void main(void);
// The Main App entry point
void APP_Start(void)
{
#if CONFIG_SOC_PS_MODULE
SOCPS_InitSYSIRQ();
#endif
#ifdef CONFIG_KERNEL
#ifdef PLATFORM_FREERTOS
InterruptForOSInit((VOID*)vPortSVCHandler,
(VOID*)xPortPendSVHandler,
(VOID*)xPortSysTickHandler);
#endif
#endif
#ifdef CONFIG_MBED_ENABLED
APP_StartMbed();
#else
#if 0//def CONFIG_APP_DEMO
#ifdef PLATFORM_FREERTOS
xTaskCreate( (TaskFunction_t)main, "MAIN_APP__TASK", (2048 /4), (void *)NULL, (tskIDLE_PRIORITY + 1), NULL);
vTaskStartScheduler();
#endif
#else
#if defined ( __ICCARM__ )
__iar_cstart_call_ctors(NULL);
#endif
// force SP align to 8 byte not 4 byte (initial SP is 4 byte align)
__asm(
"mov r0, sp\n"
"bic r0, r0, #7\n"
"mov sp, r0\n"
);
main();
#endif // end of #if CONFIG_APP_DEMO
#endif // end of else of "#ifdef CONFIG_MBED_ENABLED"
}

11
cores/realtek-ambz/base/src/fixups/cmsis_ipsr.c Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-04-22. */
#include <stdint.h>
// for some reason, cmsis_os.c does not link properly when this method is inlined in core_cmFunc.h
// (or I am too stupid to understand this)
__attribute__((weak)) uint32_t __get_IPSR()
{
uint32_t result;
asm volatile ("MRS %0, ipsr" : "=r" (result) );
}

BIN
cores/realtek-ambz/base/src/fixups/lib_rtlstd_patch.a Normal file
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Binary file not shown.

10
cores/realtek-ambz/base/src/fixups/lib_rtlstd_patch.md Normal file
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# lib_rtlstd_patch.a
```
arm-none-eabi-gcc-ar xo lib_rtlstd.a
rm rtl_eabi_cast_ram.o
arm-none-eabi-objcopy --strip-debug --strip-unneeded ram_libc.o
arm-none-eabi-objcopy --strip-debug --strip-unneeded ram_libgloss_retarget.o
arm-none-eabi-objcopy --strip-debug --strip-unneeded rtl_math_ram.o
arm-none-eabi-gcc-ar qs lib_rtlstd_patch.a *.o
```

30
cores/realtek-ambz/base/src/fixups/log_uart.c Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-04-22. */
#include <ameba_soc.h>
#include <osdep_service.h>
// usage:
// extern int LOGUART_SetBaud(uint32_t BaudRate);
int LOGUART_SetBaud(uint32_t BaudRate)
{
UART_INTConfig(UART2_DEV, RUART_IER_ERBI | RUART_IER_ELSI, DISABLE);
UART_RxCmd(UART2_DEV, DISABLE);
UART_SetBaud(UART2_DEV, BaudRate);
UART_INTConfig(UART2_DEV, RUART_IER_ERBI | RUART_IER_ELSI, ENABLE);
UART_RxCmd(UART2_DEV, ENABLE);
return 1;
}
void LOGUART_SetBaud_FromFlash(void)
{
// useless, nop
}
void ReRegisterPlatformLogUart(void)
{
// useless, nop
}

739
cores/realtek-ambz/base/src/fixups/net_sockets.c Normal file
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/*
* TCP/IP or UDP/IP networking functions
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* This file is part of mbed TLS (https://tls.mbed.org)
*/
#if !defined(MBEDTLS_CONFIG_FILE)
#include "mbedtls/config.h"
#else
#include MBEDTLS_CONFIG_FILE
#endif
#if defined(MBEDTLS_NET_C)
/*
#if !defined(unix) && !defined(__unix__) && !defined(__unix) && \
!defined(__APPLE__) && !defined(_WIN32)
#error "This module only works on Unix and Windows, see MBEDTLS_NET_C in config.h"
#endif
*/
#if defined(MBEDTLS_PLATFORM_C)
#include "mbedtls/platform.h"
#else
#include <stdlib.h>
#endif
#include "mbedtls/net_sockets.h"
#include <string.h>
#if (defined(_WIN32) || defined(_WIN32_WCE)) && !defined(EFIX64) && \
!defined(EFI32)
#ifdef _WIN32_WINNT
#undef _WIN32_WINNT
#endif
/* Enables getaddrinfo() & Co */
#define _WIN32_WINNT 0x0501
#include <ws2tcpip.h>
#include <winsock2.h>
#include <windows.h>
#if defined(_MSC_VER)
#if defined(_WIN32_WCE)
#pragma comment( lib, "ws2.lib" )
#else
#pragma comment( lib, "ws2_32.lib" )
#endif
#endif /* _MSC_VER */
#define read(fd,buf,len) recv(fd,(char*)buf,(int) len,0)
#define write(fd,buf,len) send(fd,(char*)buf,(int) len,0)
#define close(fd) closesocket(fd)
static int wsa_init_done = 0;
#elif defined(__ICCARM__) || defined(__CC_ARM) || defined ( __GNUC__ )
#include "lwip/sockets.h"
#include "lwip/inet.h"
#if LWIP_DNS
#include "lwip/netdb.h"
#endif
#include <errno.h>
#define net_htons(n) htons(n)
#define net_htonl(n) htonl(n)
#else /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <arpa/inet.h>
#include <sys/time.h>
#include <unistd.h>
#include <signal.h>
#include <fcntl.h>
#include <netdb.h>
#include <errno.h>
#endif /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */
/* Some MS functions want int and MSVC warns if we pass size_t,
* but the standard fucntions use socklen_t, so cast only for MSVC */
#if defined(_MSC_VER)
#define MSVC_INT_CAST (int)
#else
#define MSVC_INT_CAST
#endif
#include <stdio.h>
#include <time.h>
#include <stdint.h>
/*
* Prepare for using the sockets interface
*/
static int net_prepare( void )
{
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
WSADATA wsaData;
if( wsa_init_done == 0 )
{
if( WSAStartup( MAKEWORD(2,0), &wsaData ) != 0 )
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
wsa_init_done = 1;
}
#else
#if !defined(EFIX64) && !defined(EFI32) && !defined(__ICCARM__) && !defined(__CC_ARM) && !defined ( __GNUC__ )
signal( SIGPIPE, SIG_IGN );
#endif
#endif
return( 0 );
}
/*
* Initialize a context
*/
void mbedtls_net_init( mbedtls_net_context *ctx )
{
ctx->fd = -1;
}
/*
* Initiate a TCP connection with host:port and the given protocol
*/
int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char *port, int proto )
{
#if defined(MBEDTLS_HAVE_IPV6)
int ret;
struct addrinfo hints, *addr_list, *cur;
if( ( ret = net_prepare() ) != 0 )
return( ret );
/* Do name resolution with both IPv6 and IPv4 */
memset( &hints, 0, sizeof( hints ) );
hints.ai_family = AF_UNSPEC;
hints.ai_socktype = proto == MBEDTLS_NET_PROTO_UDP ? SOCK_DGRAM : SOCK_STREAM;
hints.ai_protocol = proto == MBEDTLS_NET_PROTO_UDP ? IPPROTO_UDP : IPPROTO_TCP;
if( getaddrinfo( host, port, &hints, &addr_list ) != 0 )
return( MBEDTLS_ERR_NET_UNKNOWN_HOST );
/* Try the sockaddrs until a connection succeeds */
ret = MBEDTLS_ERR_NET_UNKNOWN_HOST;
for( cur = addr_list; cur != NULL; cur = cur->ai_next )
{
ctx->fd = (int) socket( cur->ai_family, cur->ai_socktype,
cur->ai_protocol );
if( ctx->fd < 0 )
{
ret = MBEDTLS_ERR_NET_SOCKET_FAILED;
continue;
}
if( connect( ctx->fd, cur->ai_addr, MSVC_INT_CAST cur->ai_addrlen ) == 0 )
{
ret = 0;
break;
}
close( ctx->fd );
ret = MBEDTLS_ERR_NET_CONNECT_FAILED;
}
freeaddrinfo( addr_list );
return( ret );
#else
/* Legacy IPv4-only version */
int ret;
int type, protocol;
struct sockaddr_in server_addr;
#if LWIP_DNS
struct hostent *server_host;
#endif
if( ( ret = net_prepare() ) != 0 )
return( ret );
type = ( proto == MBEDTLS_NET_PROTO_UDP ) ? SOCK_DGRAM : SOCK_STREAM;
protocol = ( proto == MBEDTLS_NET_PROTO_UDP ) ? IPPROTO_UDP : IPPROTO_TCP;
#if LWIP_DNS
if( ( server_host = gethostbyname( host ) ) == NULL )
return( MBEDTLS_ERR_NET_UNKNOWN_HOST );
if( ( ctx->fd = (int) socket( AF_INET, type, protocol ) ) < 0 )
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
memcpy( (void *) &server_addr.sin_addr,
(void *) server_host->h_addr,
server_host->h_length );
#else
if( ( ctx->fd = (int) socket( AF_INET, type, protocol ) ) < 0 )
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
server_addr.sin_len = sizeof(server_addr);
server_addr.sin_addr.s_addr = inet_addr(host);
#endif
server_addr.sin_family = AF_INET;
server_addr.sin_port = net_htons( atoi(port) );
if( connect( ctx->fd, (struct sockaddr *) &server_addr,
sizeof( server_addr ) ) < 0 )
{
close( ctx->fd );
return( MBEDTLS_ERR_NET_CONNECT_FAILED );
}
return( 0 );
#endif /* MBEDTLS_HAVE_IPV6 */
}
/*
* Create a listening socket on bind_ip:port
*/
int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char *port, int proto )
{
#if defined(MBEDTLS_HAVE_IPV6)
int n, ret;
struct addrinfo hints, *addr_list, *cur;
if( ( ret = net_prepare() ) != 0 )
return( ret );
/* Bind to IPv6 and/or IPv4, but only in the desired protocol */
memset( &hints, 0, sizeof( hints ) );
hints.ai_family = AF_UNSPEC;
hints.ai_socktype = proto == MBEDTLS_NET_PROTO_UDP ? SOCK_DGRAM : SOCK_STREAM;
hints.ai_protocol = proto == MBEDTLS_NET_PROTO_UDP ? IPPROTO_UDP : IPPROTO_TCP;
if( bind_ip == NULL )
hints.ai_flags = AI_PASSIVE;
if( getaddrinfo( bind_ip, port, &hints, &addr_list ) != 0 )
return( MBEDTLS_ERR_NET_UNKNOWN_HOST );
/* Try the sockaddrs until a binding succeeds */
ret = MBEDTLS_ERR_NET_UNKNOWN_HOST;
for( cur = addr_list; cur != NULL; cur = cur->ai_next )
{
ctx->fd = (int) socket( cur->ai_family, cur->ai_socktype,
cur->ai_protocol );
if( ctx->fd < 0 )
{
ret = MBEDTLS_ERR_NET_SOCKET_FAILED;
continue;
}
n = 1;
if( setsockopt( ctx->fd, SOL_SOCKET, SO_REUSEADDR,
(const char *) &n, sizeof( n ) ) != 0 )
{
close( ctx->fd );
ret = MBEDTLS_ERR_NET_SOCKET_FAILED;
continue;
}
if( bind( ctx->fd, cur->ai_addr, MSVC_INT_CAST cur->ai_addrlen ) != 0 )
{
close( ctx->fd );
ret = MBEDTLS_ERR_NET_BIND_FAILED;
continue;
}
/* Listen only makes sense for TCP */
if( proto == MBEDTLS_NET_PROTO_TCP )
{
if( listen( ctx->fd, MBEDTLS_NET_LISTEN_BACKLOG ) != 0 )
{
close( ctx->fd );
ret = MBEDTLS_ERR_NET_LISTEN_FAILED;
continue;
}
}
/* I we ever get there, it's a success */
ret = 0;
break;
}
freeaddrinfo( addr_list );
return( ret );
#else
/* Legacy IPv4-only version */
int ret, n, c[4];
int type, protocol;
struct sockaddr_in server_addr;
if( ( ret = net_prepare() ) != 0 )
return( ret );
type = ( proto == MBEDTLS_NET_PROTO_UDP ) ? SOCK_DGRAM : SOCK_STREAM;
protocol = ( proto == MBEDTLS_NET_PROTO_UDP ) ? IPPROTO_UDP : IPPROTO_TCP;
if( ( ctx->fd = (int) socket( AF_INET, type, protocol ) ) < 0 )
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
n = 1;
setsockopt( ctx->fd, SOL_SOCKET, SO_REUSEADDR,
(const char *) &n, sizeof( n ) );
server_addr.sin_addr.s_addr = net_htonl( INADDR_ANY );
server_addr.sin_family = AF_INET;
server_addr.sin_port = net_htons( atoi(port) );
if( bind_ip != NULL )
{
memset( c, 0, sizeof( c ) );
sscanf( bind_ip, "%d.%d.%d.%d", &c[0], &c[1], &c[2], &c[3] );
for( n = 0; n < 4; n++ )
if( c[n] < 0 || c[n] > 255 )
break;
if( n == 4 )
server_addr.sin_addr.s_addr = net_htonl(
( (uint32_t) c[0] << 24 ) |
( (uint32_t) c[1] << 16 ) |
( (uint32_t) c[2] << 8 ) |
( (uint32_t) c[3] ) );
}
if( bind( ctx->fd, (struct sockaddr *) &server_addr,
sizeof( server_addr ) ) < 0 )
{
close( ctx->fd );
return( MBEDTLS_ERR_NET_BIND_FAILED );
}
/* Listen only makes sense for TCP */
if( proto == MBEDTLS_NET_PROTO_TCP )
{
if( listen( ctx->fd, MBEDTLS_NET_LISTEN_BACKLOG ) != 0 )
{
close( ctx->fd );
return( MBEDTLS_ERR_NET_LISTEN_FAILED );
}
}
return( 0 );
#endif /* MBEDTLS_HAVE_IPV6 */
}
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
/*
* Check if the requested operation would be blocking on a non-blocking socket
* and thus 'failed' with a negative return value.
*/
static int net_would_block( const mbedtls_net_context *ctx )
{
((void) ctx);
return( WSAGetLastError() == WSAEWOULDBLOCK );
}
#else
/*
* Check if the requested operation would be blocking on a non-blocking socket
* and thus 'failed' with a negative return value.
*
* Note: on a blocking socket this function always returns 0!
*/
static int net_would_block( const mbedtls_net_context *ctx )
{
/*
* Never return 'WOULD BLOCK' on a non-blocking socket
*/
if( ( fcntl( ctx->fd, F_GETFL , 0 ) & O_NONBLOCK ) != O_NONBLOCK )
return( 0 );
switch( errno )
{
#if defined EAGAIN
case EAGAIN:
#endif
#if defined EWOULDBLOCK && EWOULDBLOCK != EAGAIN
case EWOULDBLOCK:
#endif
return( 1 );
}
return( 0 );
}
#endif /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */
/*
* Accept a connection from a remote client
*/
int mbedtls_net_accept( mbedtls_net_context *bind_ctx,
mbedtls_net_context *client_ctx,
void *client_ip, size_t buf_size, size_t *ip_len )
{
int ret;
int type;
#if defined(MBEDTLS_HAVE_IPV6)
struct sockaddr_storage client_addr;
#else
struct sockaddr_in client_addr;
#endif
#if defined(__socklen_t_defined) || defined(_SOCKLEN_T) || \
defined(_SOCKLEN_T_DECLARED) || defined(__DEFINED_socklen_t)
socklen_t n = (socklen_t) sizeof( client_addr );
socklen_t type_len = (socklen_t) sizeof( type );
#else
int n = (int) sizeof( client_addr );
int type_len = (int) sizeof( type );
#endif
/* Is this a TCP or UDP socket? */
if( getsockopt( bind_ctx->fd, SOL_SOCKET, SO_TYPE,
(void *) &type, &type_len ) != 0 ||
( type != SOCK_STREAM && type != SOCK_DGRAM ) )
{
return( MBEDTLS_ERR_NET_ACCEPT_FAILED );
}
if( type == SOCK_STREAM )
{
/* TCP: actual accept() */
ret = client_ctx->fd = (int) accept( bind_ctx->fd,
(struct sockaddr *) &client_addr, &n );
}
else
{
/* UDP: wait for a message, but keep it in the queue */
char buf[1] = { 0 };
ret = (int) recvfrom( bind_ctx->fd, buf, sizeof( buf ), MSG_PEEK,
(struct sockaddr *) &client_addr, &n );
#if defined(_WIN32)
if( ret == SOCKET_ERROR &&
WSAGetLastError() == WSAEMSGSIZE )
{
/* We know buf is too small, thanks, just peeking here */
ret = 0;
}
#endif
}
if( ret < 0 )
{
if( net_would_block( bind_ctx ) != 0 )
return( MBEDTLS_ERR_SSL_WANT_READ );
return( MBEDTLS_ERR_NET_ACCEPT_FAILED );
}
/* UDP: hijack the listening socket to communicate with the client,
* then bind a new socket to accept new connections */
if( type != SOCK_STREAM )
{
#if defined(MBEDTLS_HAVE_IPV6)
struct sockaddr_storage local_addr;
#else
struct sockaddr_in local_addr;
#endif
int one = 1;
if( connect( bind_ctx->fd, (struct sockaddr *) &client_addr, n ) != 0 )
return( MBEDTLS_ERR_NET_ACCEPT_FAILED );
client_ctx->fd = bind_ctx->fd;
bind_ctx->fd = -1; /* In case we exit early */
#if defined(MBEDTLS_HAVE_IPV6)
n = sizeof( struct sockaddr_storage );
if( getsockname( client_ctx->fd,
(struct sockaddr *) &local_addr, &n ) != 0 ||
( bind_ctx->fd = (int) socket( local_addr.ss_family,
SOCK_DGRAM, IPPROTO_UDP ) ) < 0 ||
setsockopt( bind_ctx->fd, SOL_SOCKET, SO_REUSEADDR,
(const char *) &one, sizeof( one ) ) != 0 )
{
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
}
#else
n = sizeof( struct sockaddr_in );
if( getsockname( client_ctx->fd,
(struct sockaddr *) &local_addr, &n ) != 0 ||
( bind_ctx->fd = (int) socket( local_addr.sin_family,
SOCK_DGRAM, IPPROTO_UDP ) ) < 0 ||
setsockopt( bind_ctx->fd, SOL_SOCKET, SO_REUSEADDR,
(const char *) &one, sizeof( one ) ) != 0 )
{
return( MBEDTLS_ERR_NET_SOCKET_FAILED );
}
#endif
if( bind( bind_ctx->fd, (struct sockaddr *) &local_addr, n ) != 0 )
{
return( MBEDTLS_ERR_NET_BIND_FAILED );
}
}
if( client_ip != NULL )
{
#if defined(MBEDTLS_HAVE_IPV6)
if( client_addr.ss_family == AF_INET )
{
struct sockaddr_in *addr4 = (struct sockaddr_in *) &client_addr;
*ip_len = sizeof( addr4->sin_addr.s_addr );
if( buf_size < *ip_len )
return( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL );
memcpy( client_ip, &addr4->sin_addr.s_addr, *ip_len );
}
else
{
struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *) &client_addr;
*ip_len = sizeof( addr6->sin6_addr.s6_addr );
if( buf_size < *ip_len )
return( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL );
memcpy( client_ip, &addr6->sin6_addr.s6_addr, *ip_len );
}
#else
*ip_len = sizeof( client_addr.sin_addr.s_addr );
if( buf_size < *ip_len )
return( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL );
memcpy( client_ip, &client_addr.sin_addr.s_addr, *ip_len );
#endif /* MBEDTLS_HAVE_IPV6 */
}
return( 0 );
}
/*
* Set the socket blocking or non-blocking
*/
int mbedtls_net_set_block( mbedtls_net_context *ctx )
{
#if ( defined(_WIN32) || defined(_WIN32_WCE) || defined(__ICCARM__) || defined(__CC_ARM) || defined ( __GNUC__ ) ) && !defined(EFIX64) && \
!defined(EFI32)
unsigned long n = 0;
return( ioctlsocket( ctx->fd, FIONBIO, &n ) );
#else
return( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL ) & ~O_NONBLOCK ) );
#endif
}
int mbedtls_net_set_nonblock( mbedtls_net_context *ctx )
{
#if ( defined(_WIN32) || defined(_WIN32_WCE) || defined(__ICCARM__) || defined(__CC_ARM) || defined ( __GNUC__ ) ) && !defined(EFIX64) && \
!defined(EFI32)
unsigned long n = 1;
return( ioctlsocket( ctx->fd, FIONBIO, &n ) );
#else
return( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL ) | O_NONBLOCK ) );
#endif
}
/*
* Portable usleep helper
*/
void mbedtls_net_usleep( unsigned long usec )
{
#if defined(_WIN32)
Sleep( ( usec + 999 ) / 1000 );
#else
struct timeval tv;
tv.tv_sec = usec / 1000000;
#if defined(__unix__) || defined(__unix) || \
( defined(__APPLE__) && defined(__MACH__) )
tv.tv_usec = (suseconds_t) usec % 1000000;
#else
tv.tv_usec = usec % 1000000;
#endif
select( 0, NULL, NULL, NULL, &tv );
#endif
}
/*
* Read at most 'len' characters
*/
int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len )
{
int ret;
int fd = ((mbedtls_net_context *) ctx)->fd;
if( fd < 0 )
return( MBEDTLS_ERR_NET_INVALID_CONTEXT );
ret = (int) read( fd, buf, len );
if( ret < 0 )
{
if( net_would_block( ctx ) != 0 )
return( MBEDTLS_ERR_SSL_WANT_READ );
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
if( WSAGetLastError() == WSAECONNRESET )
return( MBEDTLS_ERR_NET_CONN_RESET );
#else
#ifdef ERRNO
if( errno == EPIPE || errno == ECONNRESET )
return( MBEDTLS_ERR_NET_CONN_RESET );
if( errno == EINTR )
return( MBEDTLS_ERR_SSL_WANT_READ );
#endif
#endif
return( MBEDTLS_ERR_NET_RECV_FAILED );
}
return( ret );
}
/*
* Read at most 'len' characters, blocking for at most 'timeout' ms
*/
int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len,
uint32_t timeout )
{
int ret;
struct timeval tv;
fd_set read_fds;
int fd = ((mbedtls_net_context *) ctx)->fd;
if( fd < 0 )
return( MBEDTLS_ERR_NET_INVALID_CONTEXT );
FD_ZERO( &read_fds );
FD_SET( fd, &read_fds );
tv.tv_sec = timeout / 1000;
tv.tv_usec = ( timeout % 1000 ) * 1000;
ret = select( fd + 1, &read_fds, NULL, NULL, timeout == 0 ? NULL : &tv );
/* Zero fds ready means we timed out */
if( ret == 0 )
return( MBEDTLS_ERR_SSL_TIMEOUT );
if( ret < 0 )
{
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
if( WSAGetLastError() == WSAEINTR )
return( MBEDTLS_ERR_SSL_WANT_READ );
#else
#ifdef ERRNO
if( errno == EINTR )
return( MBEDTLS_ERR_SSL_WANT_READ );
#endif
#endif
return( MBEDTLS_ERR_NET_RECV_FAILED );
}
/* This call will not block */
return( mbedtls_net_recv( ctx, buf, len ) );
}
/*
* Write at most 'len' characters
*/
int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len )
{
int ret;
int fd = ((mbedtls_net_context *) ctx)->fd;
if( fd < 0 )
return( MBEDTLS_ERR_NET_INVALID_CONTEXT );
ret = (int) write( fd, buf, len );
if( ret < 0 )
{
if( net_would_block( ctx ) != 0 )
return( MBEDTLS_ERR_SSL_WANT_WRITE );
#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \
!defined(EFI32)
if( WSAGetLastError() == WSAECONNRESET )
return( MBEDTLS_ERR_NET_CONN_RESET );
#else
#ifdef ERRNO
if( errno == EPIPE || errno == ECONNRESET )
return( MBEDTLS_ERR_NET_CONN_RESET );
if( errno == EINTR )
return( MBEDTLS_ERR_SSL_WANT_WRITE );
#endif
#endif
return( MBEDTLS_ERR_NET_SEND_FAILED );
}
return( ret );
}
/*
* Gracefully close the connection
*/
void mbedtls_net_free( mbedtls_net_context *ctx )
{
if( ctx->fd == -1 )
return;
shutdown( ctx->fd, 2 );
close( ctx->fd );
ctx->fd = -1;
}
#endif /* MBEDTLS_NET_C */

7688
cores/realtek-ambz/base/src/fixups/ssl_tls.c Normal file
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cores/realtek-ambz/base/src/fixups/wifi_mode.c Normal file
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/* Copyright (c) Kuba Szczodrzyński 2022-04-22. */
#include <wifi_conf.h>
// wifi_mode is declared in atcmd_wifi.c, which is a part of the built-in trash console
rtw_mode_t wifi_mode = RTW_MODE_NONE;

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cores/realtek-ambz/misc/amebaz.cfg Normal file
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# Main file for AmebaZ series Cortex-M3 parts
#
# !!!!!!
#
set CHIPNAME rtl8711b
set CHIPSERIES amebaz
transport select swd
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
error "CHIPNAME not set. Please do not include amebaz.cfg directly."
}
if { [info exists CHIPSERIES] } {
# Validate chip series is supported
if { $CHIPSERIES != "amebaz" } {
error "Unsupported chip series specified."
}
set _CHIPSERIES $CHIPSERIES
} else {
error "CHIPSERIES not set. Please do not include amebaz.cfg directly."
}
if { [info exists CPUTAPID] } {
# Allow user override
set _CPUTAPID $CPUTAPID
} else {
# Amebaz use a Cortex M4 core.
if { $_CHIPSERIES == "amebaz" } {
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _ENDIAN little
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
adapter speed 1000
adapter srst delay 200
# AmebaZ (Cortex M4 core) support SYSRESETREQ
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
$_TARGETNAME configure -event reset-init {amebaz_init}

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cores/realtek-ambz/misc/boot_all_10C7.bin Normal file
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cores/realtek-ambz/misc/boot_all_77F7.bin Normal file
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BIN
cores/realtek-ambz/misc/boot_all_C556.bin Normal file
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cores/realtek-ambz/misc/export-rom_symbol_v01.txt Normal file
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222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip1_2M_468k_cpp.ld Normal file
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ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP1
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld Normal file
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@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP1
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip1_4M_980k_cpp.ld Normal file
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@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xF5000-0x20 /* XIP1: 980k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08100000+0x20, LENGTH = 0xF5000-0x20 /* XIP2: 980k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP1
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip2_2M_468k_cpp.ld Normal file
View File

@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP2
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip2_2M_cpp.ld Normal file
View File

@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP2
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}

222
cores/realtek-ambz/misc/rlx8711B-symbol-v02-img2_xip2_4M_980k_cpp.ld Normal file
View File

@@ -0,0 +1,222 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
GROUP (
libgcc.a
libc.a
libg.a
libm.a
libnosys.a
)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xF5000-0x20 /* XIP1: 980k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08100000+0x20, LENGTH = 0xF5000-0x20 /* XIP2: 980k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidx.*)
__exidx_end = .;
} > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
} > BD_RAM
. = ALIGN(8);
PROVIDE(heap_start = .);
PROVIDE(heap_end = 0x1003CFFF);
PROVIDE(heap_len = heap_end - heap_start);
.rom.bss :
{
*(.heap.stdlib*)
} > ROM_BSS_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text)
*(.text*)
*(.rodata)
*(.rodata*)
*(.debug_trace*)
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
KEEP(*crtbegin.o(.ctors))
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
KEEP(*(SORT(.ctors.*)))
KEEP(*crtend.o(.ctors))
KEEP(*crtbegin.o(.dtors))
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP(*(SORT(.dtors.*)))
KEEP(*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
/* Add This for C++ support */
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
__init_array_end = .;
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
__fini_array_end = .;
/*-----------------*/
. = ALIGN (4);
__cmd_table_start__ = .;
KEEP(*(.cmd.table.data*))
__cmd_table_end__ = .;
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
KEEP(*(.init))
KEEP(*(.fini))
*(.init)
*(.fini)
__flash_text_end__ = .;
. = ALIGN (16);
} > XIP2
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}