[core] Split lt_api.c into separate units
This commit is contained in:
Kuba Szczodrzyński
34
cores/realtek-ambz/base/api/lt_cpu.c
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34
cores/realtek-ambz/base/api/lt_cpu.c
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@@ -0,0 +1,34 @@
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/* Copyright (c) Kuba Szczodrzyński 2023-02-27. */
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#include <libretiny.h>
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#include <sdk_private.h>
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lt_cpu_model_t lt_cpu_get_model() {
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uint8_t chipId;
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EFUSE_OneByteReadROM(9902, 0xF8, &chipId, L25EOUTVOLTAGE);
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return CPU_MODEL_ENUM(FAMILY, chipId);
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}
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uint32_t lt_cpu_get_mac_id() {
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uint32_t chipId = 0;
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uint8_t *id = (uint8_t *)&chipId;
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// 9902 was extracted from ROM disassembly, probably not needed
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/* EFUSE_OneByteReadROM(9902, 0x3B, id + 0, L25EOUTVOLTAGE);
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EFUSE_OneByteReadROM(9902, 0x3C, id + 1, L25EOUTVOLTAGE);
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EFUSE_OneByteReadROM(9902, 0x3D, id + 2, L25EOUTVOLTAGE); */
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// new method, based on EFUSE logical map
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uint8_t *efuse = (uint8_t *)malloc(512);
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// TODO do what EFUSE_LogicalMapRead() does, and read only the used data
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EFUSE_LogicalMap_Read(efuse);
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memcpy(id, efuse + 0x11A + 3, 3);
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free(efuse);
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return chipId;
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}
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const char *lt_cpu_get_core_type() {
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return "ARM Cortex-M4F (ARMv7E-M)";
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}
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uint32_t lt_cpu_get_freq() {
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return CPU_ClkGet(false);
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}
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39
cores/realtek-ambz/base/api/lt_device.c
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39
cores/realtek-ambz/base/api/lt_device.c
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@@ -0,0 +1,39 @@
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/* Copyright (c) Kuba Szczodrzyński 2023-02-27. */
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#include <libretiny.h>
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#include <sdk_private.h>
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void lt_get_device_mac(uint8_t *mac) {
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uint8_t *efuse = (uint8_t *)malloc(512);
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EFUSE_LogicalMap_Read(efuse);
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memcpy(mac, efuse + 0x11A, 6);
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free(efuse);
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}
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bool lt_reboot_download_mode() {
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// mww 0x40000138 0x8
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_NORESET_FF, 0x08);
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// reboot it the ugly way
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sys_reset();
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while (1) {}
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return true;
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}
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bool lt_set_debug_mode(lt_debug_mode_t mode) {
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uint32_t *swd;
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switch (mode) {
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case DEBUG_MODE_OFF:
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sys_jtag_off();
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Pinmux_Config(PA_14, PINMUX_FUNCTION_GPIO);
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Pinmux_Config(PA_15, PINMUX_FUNCTION_GPIO);
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return true;
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case DEBUG_MODE_SWD:
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Pinmux_Config(PA_14, PINMUX_FUNCTION_SWD);
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Pinmux_Config(PA_15, PINMUX_FUNCTION_SWD);
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uint32_t *swd = (uint32_t *)0x400000A4;
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*swd |= 0x1000;
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return true;
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default:
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return false;
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}
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}
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14
cores/realtek-ambz/base/api/lt_flash.c
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14
cores/realtek-ambz/base/api/lt_flash.c
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@@ -0,0 +1,14 @@
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/* Copyright (c) Kuba Szczodrzyński 2023-02-27. */
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#include <libretiny.h>
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#include <sdk_private.h>
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lt_flash_id_t lt_flash_get_id() {
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lt_flash_id_t id;
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uint8_t idBytes[3];
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flash_read_id(NULL, idBytes, 3);
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id.manufacturer_id = idBytes[0];
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id.chip_id = idBytes[1];
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id.chip_size_id = idBytes[2];
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return id;
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}
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16
cores/realtek-ambz/base/api/lt_init.c
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16
cores/realtek-ambz/base/api/lt_init.c
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@@ -0,0 +1,16 @@
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/* Copyright (c) Kuba Szczodrzyński 2023-02-27. */
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#include <libretiny.h>
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#include <sdk_private.h>
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extern uint32_t GlobalDebugEnable;
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extern uint16_t GlobalDebugLevel;
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extern uint8_t GlobalPrivateLog;
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extern uint8_t lt_uart_port;
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void lt_init_family() {
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// make the SDK less verbose by default
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GlobalDebugEnable = 0;
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GlobalPrivateLog = 0;
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lt_uart_port = LT_UART_DEFAULT_PORT;
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}
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8
cores/realtek-ambz/base/api/lt_mem.c
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8
cores/realtek-ambz/base/api/lt_mem.c
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@@ -0,0 +1,8 @@
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/* Copyright (c) Kuba Szczodrzyński 2023-02-27. */
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#include <libretiny.h>
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#include <sdk_private.h>
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uint32_t lt_ram_get_size() {
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return 256 * 1024;
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}
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78
cores/realtek-ambz/base/api/lt_ota.c
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78
cores/realtek-ambz/base/api/lt_ota.c
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@@ -0,0 +1,78 @@
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/* Copyright (c) Kuba Szczodrzyński 2023-02-27. */
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#include <libretiny.h>
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#include <sdk_private.h>
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lt_ota_type_t lt_ota_get_type() {
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return OTA_TYPE_DUAL;
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}
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bool lt_ota_is_valid(uint8_t index) {
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uint32_t offset;
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switch (index) {
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case 1:
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offset = FLASH_OTA1_OFFSET;
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break;
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case 2:
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offset = FLASH_OTA2_OFFSET;
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break;
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default:
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return false;
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}
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uint8_t *address = (uint8_t *)(SPI_FLASH_BASE + offset);
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return memcmp(address, "81958711", 8) == 0;
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}
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uint8_t lt_ota_dual_get_current() {
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// RTL8710B is XIP, so check the code offset in flash
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uint32_t addr = (uint32_t)lt_log;
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uint32_t offs = addr - SPI_FLASH_BASE;
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return offs > FLASH_OTA2_OFFSET ? 2 : 1;
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}
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uint8_t lt_ota_dual_get_stored() {
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uint32_t *ota_address = (uint32_t *)0x8009000;
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if (*ota_address == 0xFFFFFFFF)
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return 1;
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uint32_t ota_counter = *((uint32_t *)0x8009004);
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// even count of zero-bits means OTA1, odd count means OTA2
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// this allows to switch OTA images by simply clearing next bits,
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// without needing to erase the flash
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uint8_t count = 0;
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for (uint8_t i = 0; i < 32; i++) {
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if ((ota_counter & (1 << i)) == 0)
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count++;
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}
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return 1 + (count % 2);
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}
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bool lt_ota_switch(bool revert) {
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uint8_t current = lt_ota_dual_get_current();
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uint8_t stored = lt_ota_dual_get_stored();
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if ((current == stored) == revert)
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return true;
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if (!lt_ota_is_valid(stored ^ 0b11))
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return false;
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// - read current OTA switch value from 0x9004
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// - reset OTA switch to 0xFFFFFFFE if it's 0x0
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// - else check first non-zero bit of OTA switch
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// - write OTA switch with first non-zero bit cleared
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uint32_t value = HAL_READ32(SPI_FLASH_BASE, FLASH_SYSTEM_OFFSET + 4);
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if (value == 0) {
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uint8_t *system = (uint8_t *)malloc(64);
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lt_flash_read(FLASH_SYSTEM_OFFSET, system, 64);
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// reset OTA switch
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((uint32_t *)system)[1] = -2;
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lt_flash_erase_block(FLASH_SYSTEM_OFFSET);
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return lt_flash_write(FLASH_SYSTEM_OFFSET, system, 64);
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}
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// clear first non-zero bit
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value <<= 1;
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// write OTA switch to flash
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flash_write_word(NULL, FLASH_SYSTEM_OFFSET + 4, value);
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return true;
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}
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@@ -1,201 +0,0 @@
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/* Copyright (c) Kuba Szczodrzyński 2023-02-27. */
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#include <libretiny.h>
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#include <sdk_private.h>
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extern uint32_t GlobalDebugEnable;
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extern uint16_t GlobalDebugLevel;
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extern uint8_t GlobalPrivateLog;
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extern uint8_t lt_uart_port;
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void lt_init_family() {
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// make the SDK less verbose by default
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GlobalDebugEnable = 0;
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GlobalPrivateLog = 0;
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lt_uart_port = LT_UART_DEFAULT_PORT;
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}
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/* _____ _____ _ _
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/ ____| __ \| | | |
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| | | |__) | | | |
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| | | ___/| | | |
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| |____| | | |__| |
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\_____|_| \____*/
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lt_cpu_model_t lt_cpu_get_model() {
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uint8_t chipId;
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EFUSE_OneByteReadROM(9902, 0xF8, &chipId, L25EOUTVOLTAGE);
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return CPU_MODEL_ENUM(FAMILY, chipId);
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}
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uint32_t lt_cpu_get_mac_id() {
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uint32_t chipId = 0;
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uint8_t *id = (uint8_t *)&chipId;
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// 9902 was extracted from ROM disassembly, probably not needed
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/* EFUSE_OneByteReadROM(9902, 0x3B, id + 0, L25EOUTVOLTAGE);
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EFUSE_OneByteReadROM(9902, 0x3C, id + 1, L25EOUTVOLTAGE);
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EFUSE_OneByteReadROM(9902, 0x3D, id + 2, L25EOUTVOLTAGE); */
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// new method, based on EFUSE logical map
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uint8_t *efuse = (uint8_t *)malloc(512);
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// TODO do what EFUSE_LogicalMapRead() does, and read only the used data
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EFUSE_LogicalMap_Read(efuse);
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memcpy(id, efuse + 0x11A + 3, 3);
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free(efuse);
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return chipId;
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}
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const char *lt_cpu_get_core_type() {
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return "ARM Cortex-M4F (ARMv7E-M)";
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}
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uint32_t lt_cpu_get_freq() {
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return CPU_ClkGet(false);
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}
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/*_____ _
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| __ \ (_)
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| | | | _____ ___ ___ ___
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| | | |/ _ \ \ / / |/ __/ _ \
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| |__| | __/\ V /| | (_| __/
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|_____/ \___| \_/ |_|\___\__*/
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void lt_get_device_mac(uint8_t *mac) {
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uint8_t *efuse = (uint8_t *)malloc(512);
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EFUSE_LogicalMap_Read(efuse);
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memcpy(mac, efuse + 0x11A, 6);
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free(efuse);
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}
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bool lt_reboot_download_mode() {
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// mww 0x40000138 0x8
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_NORESET_FF, 0x08);
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// reboot it the ugly way
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sys_reset();
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while (1) {}
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return true;
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}
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bool lt_set_debug_mode(lt_debug_mode_t mode) {
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uint32_t *swd;
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switch (mode) {
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case DEBUG_MODE_OFF:
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sys_jtag_off();
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Pinmux_Config(PA_14, PINMUX_FUNCTION_GPIO);
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Pinmux_Config(PA_15, PINMUX_FUNCTION_GPIO);
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return true;
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case DEBUG_MODE_SWD:
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Pinmux_Config(PA_14, PINMUX_FUNCTION_SWD);
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Pinmux_Config(PA_15, PINMUX_FUNCTION_SWD);
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uint32_t *swd = (uint32_t *)0x400000A4;
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*swd |= 0x1000;
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return true;
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default:
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return false;
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}
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}
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/*______ _ _
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| ____| | | |
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| |__ | | __ _ ___| |__
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| __| | |/ _` / __| '_ \
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| | | | (_| \__ \ | | |
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|_| |_|\__,_|___/_| |*/
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lt_flash_id_t lt_flash_get_id() {
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lt_flash_id_t id;
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uint8_t idBytes[3];
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flash_read_id(NULL, idBytes, 3);
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id.manufacturer_id = idBytes[0];
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id.chip_id = idBytes[1];
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id.chip_size_id = idBytes[2];
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return id;
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}
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/*__ __
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| \/ |
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| \ / | ___ _ __ ___ ___ _ __ _ _
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| |\/| |/ _ \ '_ ` _ \ / _ \| '__| | | |
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| | | | __/ | | | | | (_) | | | |_| |
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|_| |_|\___|_| |_| |_|\___/|_| \__, |
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__/ |
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|__*/
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uint32_t lt_ram_get_size() {
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return 256 * 1024;
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}
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/* ____ _______
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/ __ \__ __|/\
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| | | | | | / \
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| | | | | | / /\ \
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| |__| | | |/ ____ \
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\____/ |_/_/ \*/
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lt_ota_type_t lt_ota_get_type() {
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return OTA_TYPE_DUAL;
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}
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bool lt_ota_is_valid(uint8_t index) {
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uint32_t offset;
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switch (index) {
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case 1:
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offset = FLASH_OTA1_OFFSET;
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break;
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case 2:
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offset = FLASH_OTA2_OFFSET;
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break;
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default:
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return false;
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}
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uint8_t *address = (uint8_t *)(SPI_FLASH_BASE + offset);
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return memcmp(address, "81958711", 8) == 0;
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}
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uint8_t lt_ota_dual_get_current() {
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// RTL8710B is XIP, so check the code offset in flash
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uint32_t addr = (uint32_t)lt_log;
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uint32_t offs = addr - SPI_FLASH_BASE;
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return offs > FLASH_OTA2_OFFSET ? 2 : 1;
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}
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uint8_t lt_ota_dual_get_stored() {
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uint32_t *ota_address = (uint32_t *)0x8009000;
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if (*ota_address == 0xFFFFFFFF)
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return 1;
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uint32_t ota_counter = *((uint32_t *)0x8009004);
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// even count of zero-bits means OTA1, odd count means OTA2
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// this allows to switch OTA images by simply clearing next bits,
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// without needing to erase the flash
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uint8_t count = 0;
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for (uint8_t i = 0; i < 32; i++) {
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if ((ota_counter & (1 << i)) == 0)
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count++;
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}
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return 1 + (count % 2);
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}
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bool lt_ota_switch(bool revert) {
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uint8_t current = lt_ota_dual_get_current();
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uint8_t stored = lt_ota_dual_get_stored();
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if ((current == stored) == revert)
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return true;
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if (!lt_ota_is_valid(stored ^ 0b11))
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return false;
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// - read current OTA switch value from 0x9004
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// - reset OTA switch to 0xFFFFFFFE if it's 0x0
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// - else check first non-zero bit of OTA switch
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// - write OTA switch with first non-zero bit cleared
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uint32_t value = HAL_READ32(SPI_FLASH_BASE, FLASH_SYSTEM_OFFSET + 4);
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if (value == 0) {
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uint8_t *system = (uint8_t *)malloc(64);
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lt_flash_read(FLASH_SYSTEM_OFFSET, system, 64);
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// reset OTA switch
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((uint32_t *)system)[1] = -2;
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lt_flash_erase_block(FLASH_SYSTEM_OFFSET);
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return lt_flash_write(FLASH_SYSTEM_OFFSET, system, 64);
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}
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// clear first non-zero bit
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value <<= 1;
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// write OTA switch to flash
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flash_write_word(NULL, FLASH_SYSTEM_OFFSET + 4, value);
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return true;
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}
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