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Figured out what the zeta buffer is and update the date again (waiting...)

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starfrost013
2025-01-22 21:18:37 +00:00
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_posts/2025-01-19-riva128-part-1.md → _posts/2025-01-22-riva128-part-1.md
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@@ -147,7 +147,7 @@ This is the primary area of memory mapping, and is set up as Base Address Regist
| `0x540000-0x541FFF` | UTOMEM | 2D/3D graphics engine: Transfer to memory object |
| `0x550000-0x551FFF` | USTRTCH | 2D/3D graphics engine: Stretched image from CPU object |
| `0x570000-0x571FFF` | UD3D0Z | 2D/3D graphics engine: Direct3D 5.0 triangle w/zeta buffer object |
| `0x580000-0x581FFF` | UPOINTZ | 2D/3D graphics engine: Point w/zeta buffer |
| `0x580000-0x581FFF` | UPOINTZ | 2D/3D graphics engine: Point w/zeta buffer* |
| `0x5C0000-0x5C1FFF` | UINMEM | 2D/3D graphics engine: Image in memory object |
| `0x601000-0x601FFF` | PRMCIO | VGA CRTC registers |
| `0x601000-0x601FFF` | PRMCIO | VGA CRTC registers |
@@ -158,6 +158,8 @@ This is the primary area of memory mapping, and is set up as Base Address Regist
_Note_: There is a wrinkle to this setup here. The VBIOS has to be able to communicate with the main GPU in real mode when PCI is not available. This is achieved by mapping I/O ports `0x3d0`-`0x3d3` in the Weitek core to the registers for a mechanism called RMA - Real Mode Access - that effectively serve as a mechanism for forming a 32-bit address; when a 32-bit address is formed by writing to all four RMA registers, (internally implemented using a mode register) the next SVGA x86 I/O port read/write will become a read/write from the main GPU PCI BAR0 MMIO space. This allows the VBIOS to POST the GPU during its initialisation process.
*A zeta buffer is Nvidia parlance for a combined Z-buffer (sorting polygons based on their distance from the camera) and stencil buffer (a buffer allowing for part of an image to be discarded).
#### DFB
DFB means "Dumb Framebuffer" (that's what Nvidia chose to call it) and is simply a linear framebuffer. It is mapped into PCI BAR1 and has a size of 0x400000 by default (depending on the VRAM size?). In the NV3, it is mapped into BAR1 (on later GPUs it was moved to BAR0 starting at `0x1000000`). It is presumably meant for manipulating the GPU without using its DMA facilities.