From c3a28d1e7714f179cf7c5d5d6ce218b6031bfd82 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Sat, 18 Jan 2025 12:44:34 +0000 Subject: [PATCH] Fixed a remaining double space. --- _posts/2025-01-17-riva128-part-1.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/_posts/2025-01-17-riva128-part-1.md b/_posts/2025-01-17-riva128-part-1.md index d06afa8..063a73c 100644 --- a/_posts/2025-01-17-riva128-part-1.md +++ b/_posts/2025-01-17-riva128-part-1.md @@ -112,7 +112,7 @@ This is the primary area of memory mapping, and is set up as Base Address Regist | ------------------- | ----------- | ------------------------------------------------------------------- | | `0x0-0xfff` | PMC | Controls the GPU functional units and interrupt state | | `0x1000-0x1fff` | PBUS | Controls the 128-bit internal bus | -| `0x1800-0x18ff` | PCI mirror | Mirror of PCI configuration registers | +| `0x1800-0x18ff` | PCI mirror | Mirror of PCI configuration registers | | `0x2000-0x3fff` | PFIFO | FIFO buffer for graphics command submission from DMA | | `0x4000-0x4fff` | PRM | Real-Mode Device Support (e.g. MPU-401) | | `0x6000-0x6FFF` | PRAM | Controls RAMIN area configuration | @@ -159,7 +159,7 @@ This is the primary area of memory mapping, and is set up as Base Address Regist _Note_: There is a wrinkle to this setup here. The VBIOS has to be able to communicate with the main GPU in real mode when PCI is not available. This is achieved by mapping I/O ports `0x3d0`-`0x3d3` in the Weitek core to the registers for a mechanism called RMA - Real Mode Access - that effectively serve as a mechanism for forming a 32-bit address; when a 32-bit address is formed by writing to all four RMA registers, (internally implemented using a mode register) the next SVGA x86 I/O port read/write will become a read/write from the main GPU PCI BAR0 MMIO space. This allows the VBIOS to POST the GPU during its initialisation process. #### DFB -DFB means "Dumb Framebuffer" (that's what Nvidia chose to call it) and is simply a linear framebuffer. It is mapped into PCI BAR1 and has a size of 0x400000 by default (depending on the VRAM size?). In the NV3, it is mapped into BAR1 (on later GPUs it was moved to BAR0 starting at `0x1000000`). It is presumably meant for manipulating the GPU without using its DMA facilities. +DFB means "Dumb Framebuffer" (that's what Nvidia chose to call it) and is simply a linear framebuffer. It is mapped into PCI BAR1 and has a size of 0x400000 by default (depending on the VRAM size?). In the NV3, it is mapped into BAR1 (on later GPUs it was moved to BAR0 starting at `0x1000000`). It is presumably meant for manipulating the GPU without using its DMA facilities. #### RAMIN Also in PCI BAR1 is the `RAMIN` region. While this area is somewhat complicated, it is the most important area to understand in order to understand how the GPU actually operates. RAMIN is the area of the GPU's VRAM where graphics objects and the structures containing references to them are stored. It is effectively addressed as the last megabyte of VRAM (regardless of the size of VRAM), but addressed in reverse, and aligned to a 16-byte boundary. If this is difficult to understand, you can convert an address in PRAMIN to a real VRAM address using the following formula (where reversal_unit_size is equal to 16): @@ -211,7 +211,7 @@ The exact methods of every graphics object are incredibly long and often shared An arbitrary point on the screen. Depending on the methods used to submit the object, this object can take the form of: * Up to 32 points, each with a single arbitrary 32-bit colour (probably BGRA format) and 16-bit size and position values. -* Up to 16 points, each with a single arbitrary 32-bit colour (probably BGRA format) and 32-bit size and position values. +* Up to 16 points, each with a single arbitrary 32-bit colour (probably BGRA format) and 32-bit size and position values. * Up to 16 points, making up a polygon, with an arbitrary 32-bit colour for each polygon line (probably BGRA format) and 16-bit size and position values. **`0x09` (Line)**: