mirror of
https://github.com/86Box/86Box.git
synced 2026-02-22 17:45:31 -07:00
0a11a6d3b4
Applied some more of greatpsycho's CPU patches; Reworked the PS/2 Model 80 split memory block handling and removed the top 256k remap from it (that's what the split memory block is for) - fixes OS/2 2.x on that machine.
780 lines
28 KiB
C
780 lines
28 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Intel DMA controllers.
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*
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* Version: @(#)dma.c 1.0.6 2017/11/04
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2017 Sarah Walker.
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* Copyright 2016,2017 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <wchar.h>
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#include "86box.h"
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#include "cpu/cpu.h"
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#include "cpu/x86.h"
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#include "machine/machine.h"
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#include "mem.h"
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#include "io.h"
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#include "dma.h"
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static uint8_t dmaregs[16];
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static uint8_t dma16regs[16];
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static uint8_t dmapages[16];
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DMA dma, dma16;
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void dma_reset(void)
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{
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#if 1
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int c;
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dma.wp = 0;
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for (c = 0; c < 16; c++)
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dmaregs[c] = 0;
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for (c = 0; c < 4; c++)
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{
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dma.mode[c] = 0;
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dma.ac[c] = 0;
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dma.cc[c] = 0;
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dma.ab[c] = 0;
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dma.cb[c] = 0;
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}
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dma.m = 0;
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dma16.wp = 0;
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for (c = 0; c < 16; c++)
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dma16regs[c] = 0;
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for (c = 0; c < 4; c++)
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{
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dma16.mode[c] = 0;
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dma16.ac[c] = 0;
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dma16.cc[c] = 0;
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dma16.ab[c] = 0;
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dma16.cb[c] = 0;
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}
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dma16.m = 0;
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#else
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memset(dmaregs, 0, 16);
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memset(dma16regs, 0, 16);
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memset(dmapages, 0, 16);
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memset(&dma, 0, sizeof(DMA));
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memset(&dma16, 0, sizeof(DMA));
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#endif
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}
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uint8_t dma_read(uint16_t addr, void *priv)
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{
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uint8_t temp;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma.wp ^= 1;
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if (dma.wp)
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return dma.ac[(addr >> 1) & 3] & 0xff;
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return (dma.ac[(addr >> 1) & 3] >> 8) & 0xff;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma.wp ^= 1;
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if (dma.wp) temp = dma.cc[(addr >> 1) & 3] & 0xff;
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else temp = dma.cc[(addr >> 1) & 3] >> 8;
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return temp;
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case 8: /*Status register*/
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temp = dma.stat;
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dma.stat = 0;
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return temp;
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case 0xd:
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return 0;
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}
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return dmaregs[addr & 0xf];
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}
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void dma_write(uint16_t addr, uint8_t val, void *priv)
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{
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dmaregs[addr & 0xf] = val;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma.wp ^= 1;
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if (dma.wp) dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0xffff00) | val;
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else dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0xff00ff) | (val << 8);
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dma.ac[(addr >> 1) & 3] = dma.ab[(addr >> 1) & 3];
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return;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma.wp ^= 1;
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if (dma.wp) dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0xff00) | val;
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else dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma.cc[(addr >> 1) & 3] = dma.cb[(addr >> 1) & 3];
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return;
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case 8: /*Control register*/
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dma.command = val;
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return;
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case 0xa: /*Mask*/
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if (val & 4) dma.m |= (1 << (val & 3));
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else dma.m &= ~(1 << (val & 3));
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return;
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case 0xb: /*Mode*/
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dma.mode[val & 3] = val;
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if (dma.is_ps2)
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{
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dma.ps2_mode[val & 3] &= ~0x1c;
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if (val & 0x20)
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dma.ps2_mode[val & 3] |= 0x10;
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if ((val & 0xc) == 8)
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dma.ps2_mode[val & 3] |= 4;
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else if ((val & 0xc) == 4)
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dma.ps2_mode[val & 3] |= 0xc;
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}
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return;
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case 0xc: /*Clear FF*/
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dma.wp = 0;
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return;
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case 0xd: /*Master clear*/
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dma.wp = 0;
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dma.m = 0xf;
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return;
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case 0xf: /*Mask write*/
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dma.m = val & 0xf;
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return;
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}
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}
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static uint8_t dma_ps2_read(uint16_t addr, void *priv)
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{
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uint8_t temp = 0xff;
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switch (addr)
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{
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case 0x1a:
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switch (dma.xfr_command)
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{
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case 2: /*Address*/
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case 3:
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switch (dma.byte_ptr)
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{
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case 0:
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temp = (dma.xfr_channel & 4) ? (dma16.ac[dma.xfr_channel & 3] & 0xff) : (dma.ac[dma.xfr_channel] & 0xff);
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dma.byte_ptr = 1;
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break;
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case 1:
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temp = (dma.xfr_channel & 4) ? (dma16.ac[dma.xfr_channel & 3] >> 8) : (dma.ac[dma.xfr_channel] >> 8);
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dma.byte_ptr = 2;
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break;
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case 2:
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temp = (dma.xfr_channel & 4) ? (dma16.ac[dma.xfr_channel & 3] >> 16) : (dma.ac[dma.xfr_channel] >> 16);
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dma.byte_ptr = 0;
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break;
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}
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break;
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case 4: /*Count*/
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case 5:
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if (dma.byte_ptr)
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temp = (dma.xfr_channel & 4) ? (dma16.cc[dma.xfr_channel & 3] >> 8) : (dma.cc[dma.xfr_channel] >> 8);
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else
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temp = (dma.xfr_channel & 4) ? (dma16.cc[dma.xfr_channel & 3] & 0xff) : (dma.cc[dma.xfr_channel] & 0xff);
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dma.byte_ptr = (dma.byte_ptr + 1) & 1;
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break;
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case 6: /*Read DMA status*/
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if (dma.byte_ptr)
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{
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temp = dma16.stat_rq | (dma16.stat << 4);
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dma16.stat = 0;
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dma16.stat_rq = 0;
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}
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else
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{
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temp = dma.stat_rq | (dma.stat << 4);
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dma.stat = 0;
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dma.stat_rq = 0;
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}
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dma.byte_ptr = (dma.byte_ptr + 1) & 1;
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break;
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case 7: /*Mode*/
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temp = (dma.xfr_channel & 4) ? dma16.ps2_mode[dma.xfr_channel & 3] : dma.ps2_mode[dma.xfr_channel];
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break;
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case 8: /*Arbitration Level*/
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temp = (dma.xfr_channel & 4) ? dma16.arb_level[dma.xfr_channel & 3] : dma.arb_level[dma.xfr_channel];
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break;
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default:
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fatal("Bad XFR Read command %i channel %i\n", dma.xfr_command, dma.xfr_channel);
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}
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break;
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}
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return temp;
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}
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static void dma_ps2_write(uint16_t addr, uint8_t val, void *priv)
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{
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uint8_t mode;
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switch (addr)
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{
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case 0x18:
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dma.xfr_channel = val & 0x7;
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dma.xfr_command = val >> 4;
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dma.byte_ptr = 0;
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switch (dma.xfr_command)
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{
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case 9: /*Set DMA mask*/
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if (dma.xfr_channel & 4)
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dma16.m |= (1 << (dma.xfr_channel & 3));
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else
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dma.m |= (1 << dma.xfr_channel);
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break;
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case 0xa: /*Reset DMA mask*/
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if (dma.xfr_channel & 4)
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dma16.m &= ~(1 << (dma.xfr_channel & 3));
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else
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dma.m &= ~(1 << dma.xfr_channel);
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break;
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}
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break;
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case 0x1a:
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switch (dma.xfr_command)
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{
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case 2: /*Address*/
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switch (dma.byte_ptr)
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{
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case 0:
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if (dma.xfr_channel & 4)
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dma16.ac[dma.xfr_channel & 3] = (dma16.ac[dma.xfr_channel & 3] & 0xffff00) | val;
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else
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dma.ac[dma.xfr_channel] = (dma.ac[dma.xfr_channel] & 0xffff00) | val;
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dma.byte_ptr = 1;
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break;
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case 1:
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if (dma.xfr_channel & 4)
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dma16.ac[dma.xfr_channel & 3] = (dma16.ac[dma.xfr_channel & 3] & 0xff00ff) | (val << 8);
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else
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dma.ac[dma.xfr_channel] = (dma.ac[dma.xfr_channel] & 0xff00ff) | (val << 8);
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dma.byte_ptr = 2;
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break;
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case 2:
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if (dma.xfr_channel & 4)
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dma16.ac[dma.xfr_channel & 3] = (dma16.ac[dma.xfr_channel & 3] & 0x00ffff) | (val << 16);
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else
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dma.ac[dma.xfr_channel] = (dma.ac[dma.xfr_channel] & 0x00ffff) | (val << 16);
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dma.byte_ptr = 0;
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break;
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}
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if (dma.xfr_channel & 4)
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dma16.ab[dma.xfr_channel & 3] = dma16.ac[dma.xfr_channel & 3];
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else
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dma.ab[dma.xfr_channel] = dma.ac[dma.xfr_channel];
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break;
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case 4: /*Count*/
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if (dma.byte_ptr)
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{
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if (dma.xfr_channel & 4)
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dma16.cc[dma.xfr_channel & 3] = (dma16.cc[dma.xfr_channel & 3] & 0xff) | (val << 8);
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else
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dma.cc[dma.xfr_channel] = (dma.cc[dma.xfr_channel] & 0xff) | (val << 8);
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}
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else
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{
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if (dma.xfr_channel & 4)
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dma16.cc[dma.xfr_channel & 3] = (dma16.cc[dma.xfr_channel & 3] & 0xff00) | val;
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else
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dma.cc[dma.xfr_channel] = (dma.cc[dma.xfr_channel] & 0xff00) | val;
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}
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dma.byte_ptr = (dma.byte_ptr + 1) & 1;
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if (dma.xfr_channel & 4)
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dma16.cb[dma.xfr_channel & 3] = dma16.cc[dma.xfr_channel & 3];
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else
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dma.cb[dma.xfr_channel] = dma.cc[dma.xfr_channel];
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break;
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case 7: /*Mode register*/
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mode = 0;
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if (val & 0x10)
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mode |= 0x20;
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if ((val & 0xc) == 4)
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mode |= 8;
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else if ((val & 0xc) == 0xc)
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mode |= 4;
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if ((val & 0x40) && !(dma.xfr_channel & 4))
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fatal("16-bit DMA on 8-bit channel\n");
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if (!(val & 0x40) && (dma.xfr_channel & 4))
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fatal("8-bit DMA on 16-bit channel\n");
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if (dma.xfr_channel & 4)
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{
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dma16.mode[dma.xfr_channel & 3] = (dma16.mode[dma.xfr_channel & 3] & ~0x2c) | mode;
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dma16.ps2_mode[dma.xfr_channel & 3] = val;
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}
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else
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{
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dma.mode[dma.xfr_channel] = (dma.mode[dma.xfr_channel] & ~0x2c) | mode;
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dma.ps2_mode[dma.xfr_channel] = val;
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}
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break;
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case 8: /*Arbitration Level*/
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if (dma.xfr_channel & 4)
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dma16.arb_level[dma.xfr_channel & 3] = val;
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else
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dma.arb_level[dma.xfr_channel] = val;
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break;
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default:
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fatal("Bad XFR command %i channel %i val %02x\n", dma.xfr_command, dma.xfr_channel, val);
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}
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break;
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}
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}
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uint8_t dma16_read(uint16_t addr, void *priv)
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{
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uint8_t temp;
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addr >>= 1;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma16.wp ^= 1;
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if (dma.is_ps2)
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{
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if (dma16.wp)
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return dma16.ac[(addr >> 1) & 3] & 0xff;
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return (dma16.ac[(addr >> 1) & 3] >> 8) & 0xff;
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}
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if (dma16.wp)
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return (dma16.ac[(addr >> 1) & 3] >> 1) & 0xff;
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return (dma16.ac[(addr >> 1) & 3] >> 9) & 0xff;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma16.wp ^= 1;
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if (dma16.wp) temp = dma16.cc[(addr >> 1) & 3] & 0xff;
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else temp = dma16.cc[(addr >> 1) & 3] >> 8;
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return temp;
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case 8: /*Status register*/
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temp = dma16.stat;
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dma16.stat = 0;
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return temp;
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}
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return dma16regs[addr & 0xf];
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}
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void dma16_write(uint16_t addr, uint8_t val, void *priv)
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{
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addr >>= 1;
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dma16regs[addr & 0xf] = val;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma16.wp ^= 1;
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if (dma.is_ps2)
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{
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if (dma16.wp) dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xffff00) | val;
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else dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xff00ff) | (val << 8);
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}
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else
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{
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if (dma16.wp) dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xfffe00) | (val << 1);
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else dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xfe01ff) | (val << 9);
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}
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dma16.ac[(addr >> 1) & 3] = dma16.ab[(addr >> 1) & 3];
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return;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma16.wp ^= 1;
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if (dma16.wp) dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0xff00) | val;
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else dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma16.cc[(addr >> 1) & 3] = dma16.cb[(addr >> 1) & 3];
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return;
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case 8: /*Control register*/
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return;
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case 0xa: /*Mask*/
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if (val & 4) dma16.m |= (1 << (val & 3));
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else dma16.m &= ~(1 << (val & 3));
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return;
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case 0xb: /*Mode*/
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dma16.mode[val & 3] = val;
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if (dma.is_ps2)
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{
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dma16.ps2_mode[val & 3] &= ~0x1c;
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if (val & 0x20)
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dma16.ps2_mode[val & 3] |= 0x10;
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if ((val & 0xc) == 8)
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dma16.ps2_mode[val & 3] |= 4;
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else if ((val & 0xc) == 4)
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dma16.ps2_mode[val & 3] |= 0xc;
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}
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return;
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case 0xc: /*Clear FF*/
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dma16.wp = 0;
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return;
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case 0xd: /*Master clear*/
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dma16.wp = 0;
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dma16.m = 0xf;
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return;
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case 0xf: /*Mask write*/
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dma16.m = val&0xf;
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return;
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}
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}
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void dma_page_write(uint16_t addr, uint8_t val, void *priv)
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{
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dmapages[addr & 0xf] = val;
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switch (addr & 0xf)
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{
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case 1:
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dma.page[2] = (AT) ? val : val & 0xf;
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dma.ab[2] = (dma.ab[2] & 0xffff) | (dma.page[2] << 16);
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dma.ac[2] = (dma.ac[2] & 0xffff) | (dma.page[2] << 16);
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break;
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case 2:
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dma.page[3] = (AT) ? val : val & 0xf;
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dma.ab[3] = (dma.ab[3] & 0xffff) | (dma.page[3] << 16);
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dma.ac[3] = (dma.ac[3] & 0xffff) | (dma.page[3] << 16);
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break;
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case 3:
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dma.page[1] = (AT) ? val : val & 0xf;
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dma.ab[1] = (dma.ab[1] & 0xffff) | (dma.page[1] << 16);
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dma.ac[1] = (dma.ac[1] & 0xffff) | (dma.page[1] << 16);
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break;
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case 7:
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dma.page[0] = (AT) ? val : val & 0xf;
|
|
dma.ab[0] = (dma.ab[0] & 0xffff) | (dma.page[0] << 16);
|
|
dma.ac[0] = (dma.ac[0] & 0xffff) | (dma.page[0] << 16);
|
|
break;
|
|
case 0x9:
|
|
dma16.page[2] = val & 0xfe;
|
|
dma16.ab[2] = (dma16.ab[2] & 0x1ffff) | (dma16.page[2] << 16);
|
|
dma16.ac[2] = (dma16.ac[2] & 0x1ffff) | (dma16.page[2] << 16);
|
|
break;
|
|
case 0xa:
|
|
dma16.page[3] = val & 0xfe;
|
|
dma16.ab[3] = (dma16.ab[3] & 0x1ffff) | (dma16.page[3] << 16);
|
|
dma16.ac[3] = (dma16.ac[3] & 0x1ffff) | (dma16.page[3] << 16);
|
|
break;
|
|
case 0xb:
|
|
dma16.page[1] = val & 0xfe;
|
|
dma16.ab[1] = (dma16.ab[1] & 0x1ffff) | (dma16.page[1] << 16);
|
|
dma16.ac[1] = (dma16.ac[1] & 0x1ffff) | (dma16.page[1] << 16);
|
|
break;
|
|
case 0xf:
|
|
dma16.page[0] = val & 0xfe;
|
|
dma16.ab[0] = (dma16.ab[0] & 0x1ffff) | (dma16.page[0] << 16);
|
|
dma16.ac[0] = (dma16.ac[0] & 0x1ffff) | (dma16.page[0] << 16);
|
|
break;
|
|
}
|
|
}
|
|
|
|
uint8_t dma_page_read(uint16_t addr, void *priv)
|
|
{
|
|
return dmapages[addr & 0xf];
|
|
}
|
|
|
|
void dma_init(void)
|
|
{
|
|
io_sethandler(0x0000, 0x0010, dma_read, NULL, NULL, dma_write, NULL, NULL, NULL);
|
|
io_sethandler(0x0080, 0x0008, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
|
|
dma.is_ps2 = 0;
|
|
}
|
|
|
|
void dma16_init(void)
|
|
{
|
|
io_sethandler(0x00C0, 0x0020, dma16_read, NULL, NULL, dma16_write, NULL, NULL, NULL);
|
|
io_sethandler(0x0088, 0x0008, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
|
|
}
|
|
|
|
void dma_alias_set(void)
|
|
{
|
|
io_sethandler(0x0090, 0x0010, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
|
|
}
|
|
|
|
void dma_alias_remove(void)
|
|
{
|
|
io_removehandler(0x0090, 0x0010, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
|
|
}
|
|
|
|
void dma_alias_remove_piix(void)
|
|
{
|
|
io_removehandler(0x0090, 0x0001, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
|
|
io_removehandler(0x0094, 0x0003, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
|
|
io_removehandler(0x0098, 0x0001, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
|
|
io_removehandler(0x009C, 0x0003, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
|
|
}
|
|
|
|
void ps2_dma_init(void)
|
|
{
|
|
io_sethandler(0x0018, 0x0001, dma_ps2_read, NULL, NULL, dma_ps2_write, NULL, NULL, NULL);
|
|
io_sethandler(0x001a, 0x0001, dma_ps2_read, NULL, NULL, dma_ps2_write, NULL, NULL, NULL);
|
|
dma.is_ps2 = 1;
|
|
}
|
|
|
|
|
|
uint8_t _dma_read(uint32_t addr)
|
|
{
|
|
uint8_t temp = mem_readb_phys_dma(addr);
|
|
return temp;
|
|
}
|
|
|
|
void _dma_write(uint32_t addr, uint8_t val)
|
|
{
|
|
mem_writeb_phys_dma(addr, val);
|
|
mem_invalidate_range(addr, addr);
|
|
}
|
|
|
|
int dma_channel_read(int channel)
|
|
{
|
|
uint16_t temp;
|
|
int tc = 0;
|
|
|
|
if (dma.command & 0x04)
|
|
return DMA_NODATA;
|
|
|
|
if (!AT)
|
|
refreshread();
|
|
|
|
if (channel < 4)
|
|
{
|
|
if (dma.m & (1 << channel))
|
|
return DMA_NODATA;
|
|
if ((dma.mode[channel] & 0xC) != 8)
|
|
return DMA_NODATA;
|
|
|
|
temp = _dma_read(dma.ac[channel]);
|
|
dma.stat_rq |= (1 << channel);
|
|
|
|
if (dma.mode[channel] & 0x20)
|
|
{
|
|
if (dma.is_ps2)
|
|
dma.ac[channel]--;
|
|
else
|
|
dma.ac[channel] = (dma.ac[channel] & 0xff0000) | ((dma.ac[channel] - 1) & 0xffff);
|
|
}
|
|
else
|
|
{
|
|
if (dma.is_ps2)
|
|
dma.ac[channel]++;
|
|
else
|
|
dma.ac[channel] = (dma.ac[channel] & 0xff0000) | ((dma.ac[channel] + 1) & 0xffff);
|
|
}
|
|
dma.cc[channel]--;
|
|
if (dma.cc[channel] < 0)
|
|
{
|
|
tc = 1;
|
|
if (dma.mode[channel] & 0x10) /*Auto-init*/
|
|
{
|
|
dma.cc[channel] = dma.cb[channel];
|
|
dma.ac[channel] = dma.ab[channel];
|
|
}
|
|
else
|
|
dma.m |= (1 << channel);
|
|
dma.stat |= (1 << channel);
|
|
}
|
|
|
|
if (tc)
|
|
return temp | DMA_OVER;
|
|
return temp;
|
|
}
|
|
else
|
|
{
|
|
channel &= 3;
|
|
if (dma16.m & (1 << channel))
|
|
return DMA_NODATA;
|
|
if ((dma16.mode[channel] & 0xC) != 8)
|
|
return DMA_NODATA;
|
|
|
|
temp = _dma_read(dma16.ac[channel]) |
|
|
(_dma_read(dma16.ac[channel] + 1) << 8);
|
|
dma16.stat_rq |= (1 << channel);
|
|
|
|
if (dma16.mode[channel] & 0x20)
|
|
{
|
|
if (dma.is_ps2)
|
|
dma16.ac[channel] -= 2;
|
|
else
|
|
dma16.ac[channel] = (dma16.ac[channel] & 0xfe0000) | ((dma16.ac[channel] - 2) & 0x1ffff);
|
|
}
|
|
else
|
|
{
|
|
if (dma.is_ps2)
|
|
dma16.ac[channel] += 2;
|
|
else
|
|
dma16.ac[channel] = (dma16.ac[channel] & 0xfe0000) | ((dma16.ac[channel] + 2) & 0x1ffff);
|
|
}
|
|
|
|
dma16.cc[channel]--;
|
|
if (dma16.cc[channel] < 0)
|
|
{
|
|
tc = 1;
|
|
if (dma16.mode[channel] & 0x10) /*Auto-init*/
|
|
{
|
|
dma16.cc[channel] = dma16.cb[channel];
|
|
dma16.ac[channel] = dma16.ab[channel];
|
|
}
|
|
else
|
|
dma16.m |= (1 << channel);
|
|
dma16.stat |= (1 << channel);
|
|
}
|
|
|
|
if (tc)
|
|
return temp | DMA_OVER;
|
|
return temp;
|
|
}
|
|
}
|
|
|
|
int dma_channel_write(int channel, uint16_t val)
|
|
{
|
|
if (dma.command & 0x04)
|
|
return DMA_NODATA;
|
|
|
|
if (!AT)
|
|
refreshread();
|
|
|
|
if (channel < 4)
|
|
{
|
|
if (dma.m & (1 << channel))
|
|
return DMA_NODATA;
|
|
if ((dma.mode[channel] & 0xC) != 4)
|
|
return DMA_NODATA;
|
|
|
|
_dma_write(dma.ac[channel], val);
|
|
dma.stat_rq |= (1 << channel);
|
|
|
|
if (dma.mode[channel] & 0x20)
|
|
{
|
|
if (dma.is_ps2)
|
|
dma.ac[channel]--;
|
|
else
|
|
dma.ac[channel] = (dma.ac[channel] & 0xff0000) | ((dma.ac[channel] - 1) & 0xffff);
|
|
}
|
|
else
|
|
{
|
|
if (dma.is_ps2)
|
|
dma.ac[channel]++;
|
|
else
|
|
dma.ac[channel] = (dma.ac[channel] & 0xff0000) | ((dma.ac[channel] + 1) & 0xffff);
|
|
}
|
|
|
|
dma.cc[channel]--;
|
|
if (dma.cc[channel] < 0)
|
|
{
|
|
if (dma.mode[channel] & 0x10) /*Auto-init*/
|
|
{
|
|
dma.cc[channel] = dma.cb[channel];
|
|
dma.ac[channel] = dma.ab[channel];
|
|
}
|
|
else
|
|
dma.m |= (1 << channel);
|
|
dma.stat |= (1 << channel);
|
|
}
|
|
|
|
if (dma.m & (1 << channel))
|
|
return DMA_OVER;
|
|
}
|
|
else
|
|
{
|
|
channel &= 3;
|
|
if (dma16.m & (1 << channel))
|
|
return DMA_NODATA;
|
|
if ((dma16.mode[channel] & 0xC) != 4)
|
|
return DMA_NODATA;
|
|
|
|
_dma_write(dma16.ac[channel], val);
|
|
_dma_write(dma16.ac[channel] + 1, val >> 8);
|
|
dma16.stat_rq |= (1 << channel);
|
|
|
|
if (dma16.mode[channel] & 0x20)
|
|
{
|
|
if (dma.is_ps2)
|
|
dma16.ac[channel] -= 2;
|
|
else
|
|
dma16.ac[channel] = (dma16.ac[channel] & 0xfe0000) | ((dma16.ac[channel] - 2) & 0x1ffff);
|
|
}
|
|
else
|
|
{
|
|
if (dma.is_ps2)
|
|
dma16.ac[channel] += 2;
|
|
else
|
|
dma16.ac[channel] = (dma16.ac[channel] & 0xfe0000) | ((dma16.ac[channel] + 2) & 0x1ffff);
|
|
}
|
|
|
|
dma16.cc[channel]--;
|
|
if (dma16.cc[channel] < 0)
|
|
{
|
|
if (dma16.mode[channel] & 0x10) /*Auto-init*/
|
|
{
|
|
dma16.cc[channel] = dma16.cb[channel];
|
|
dma16.ac[channel] = dma16.ab[channel];
|
|
}
|
|
else
|
|
dma16.m |= (1 << channel);
|
|
dma16.stat |= (1 << channel);
|
|
}
|
|
|
|
if (dma16.m & (1 << channel))
|
|
return DMA_OVER;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int dma_mode(int channel)
|
|
{
|
|
if (channel < 4)
|
|
{
|
|
return dma.mode[channel];
|
|
}
|
|
else
|
|
{
|
|
return dma16.mode[channel & 3];
|
|
}
|
|
}
|
|
|
|
/* DMA Bus Master Page Read/Write */
|
|
void DMAPageRead(uint32_t PhysAddress, char *DataRead, uint32_t TotalSize)
|
|
{
|
|
int i = 0;
|
|
|
|
// memcpy(DataRead, &ram[PhysAddress], TotalSize);
|
|
|
|
for (i = 0; i < TotalSize; i++)
|
|
DataRead[i] = mem_readb_phys_dma(PhysAddress + i);
|
|
}
|
|
|
|
void DMAPageWrite(uint32_t PhysAddress, const char *DataWrite, uint32_t TotalSize)
|
|
{
|
|
int i = 0;
|
|
|
|
// mem_invalidate_range(PhysAddress, PhysAddress + TotalSize - 1);
|
|
// memcpy(&ram[PhysAddress], DataWrite, TotalSize);
|
|
|
|
for (i = 0; i < TotalSize; i++)
|
|
mem_writeb_phys_dma(PhysAddress + i, DataWrite[i]);
|
|
|
|
mem_invalidate_range(PhysAddress, PhysAddress + TotalSize - 1);
|
|
}
|