830 Commits

Author	SHA1	Message	Date
Cacodemon345	41ecd0bc62	Mark stack-related functions in x86seg inline (#6281)	2025-10-05 18:22:12 +02:00
OBattler	4af766092f	Also add the 600 MHz overclocked version of the 570 MHz.	2025-10-01 19:14:50 +02:00
OBattler	5d194d8e80	Added AMD K6_2 570 MHz.	2025-10-01 18:36:00 +02:00
RichardG867	7c25ca22e3	Convert existing code to the integer casting macros	2025-09-19 20:09:29 -03:00
RichardG867	4b8b0efa48	Optimize a couple CPU block checks	2025-09-19 18:45:35 -03:00
starfrost013	a44ad7e776	Remove 32-bit core dynarec	2025-09-14 15:50:01 +01:00
starfrost013	02b0960148	A few minor further i386 removals	2025-09-14 11:01:34 +01:00
starfrost013	57ae731e22	Goodbye, 32-bit	2025-09-14 01:32:41 +01:00
OBattler	5a2f9eacbf	And another fix.	2025-09-02 16:46:12 +02:00
OBattler	c5be7e9261	More fixed and disabled the wait states selection on 386DX.	2025-09-02 16:45:01 +02:00
OBattler	b825aed242	386DX: Fix cache defaults to be the equivalent of 0 wait states.	2025-09-02 16:41:30 +02:00
OBattler	766734eb3a	386DX: Force external cache enabled to improve performance.	2025-09-02 16:36:41 +02:00
OBattler	95e98b1b20	Added the two Silicon Valley machiens and fixes 386 FPU flag on reset.	2025-08-14 16:29:09 +02:00
Jasmine Iwanek	a96146742e	Fix another warn in 808x.c	2025-07-28 01:52:40 -04:00
Jasmine Iwanek	6d6d5931bf	Fix several codeql warns	2025-07-27 20:59:55 -04:00
Cacodemon345	916533499a	Add 10ms interval option (not exposed yet to UI) ... Fix percentage counter	2025-07-09 12:59:16 +06:00
Cacodemon345	ddea070faa	Fix cycle period of dynarec	2025-07-08 16:51:53 +06:00
OBattler	773ebf6254	Fix V20/V30 CPU speeds.	2025-07-08 05:59:04 +02:00
OBattler	42c0077703	808x: Suspend trap for 1 instruction after POPF and do not do it after IRET.	2025-07-08 05:21:44 +02:00
OBattler	a2354599c6	Vx0: Always resume from interrupt on HLT, even if I_FLAG is not set.	2025-07-08 05:08:23 +02:00
OBattler	4a468246cc	808x: Rename wait() to wait_cycs() to avoid conflict with the Apple SDK.	2025-06-30 00:52:00 +02:00
OBattler	ad5aa6e52f	Attempt to undefine wait to avoid the conflicts on Mac.	2025-06-30 00:18:59 +02:00
OBattler	e601f25805	x87: Fix the rounding_modes warnings.	2025-06-30 00:17:33 +02:00
Cacodemon345	b44042ef1c	x86-specific FADD (SSE2 version)	2025-06-30 02:08:48 +06:00
Cacodemon345	96734590ca	x86-specific FADD implementation	2025-06-30 01:10:58 +06:00
Jasmine Iwanek	026f765495	Some codeql fixes	2025-06-29 00:12:06 -04:00
Jasmine Iwanek	3a26b9d46b	Many warning fixes	2025-06-28 23:54:07 -04:00
OBattler	25f0a26ea1	Vastly improve the ALi M1409 emulation (all of shadow RAM now work, as does bus speed and external cache setting), and fix the "Writing unimplemented Cyrix register FF" error as well.	2025-05-29 09:45:49 +02:00
OBattler	b3147ee473	LOCK instruction: ensure it is always illegal on opcodes 90h and ECh.	2025-05-18 02:20:18 +02:00
OBattler	ddd271f6ee	Honore the fixed bits of flags when pushing them to the stack, fixes #5093.	2025-05-17 21:02:06 +02:00
OBattler	a0b80e04cd	Remove the unused mmu_perm stuff.	2025-05-06 03:18:46 +02:00
OBattler	1e81473d34	Fix MMX_ENTER() exceptions.	2025-05-05 05:59:20 +02:00
OBattler	9b93e71b23	#included the missing plat_fallthrough.h.	2025-04-27 18:57:21 +02:00
OBattler	5b4db319bf	Opcode D6 is now an alias of opcode D7 (XLAT) on NEC Vx0, closes #5516.	2025-04-27 18:50:45 +02:00
Cacodemon345	e076c1051d	Fix x87_op being outside of structure, fixing crashes in ARM64 NDR	2025-04-26 23:23:34 +06:00
OBattler	b15f25ffa4	Fixed old recompiler compiling in a kludgy way because it appears there's no STORE_IMM_ADDR_W.	2025-04-22 09:46:58 +02:00
OBattler	8790395a05	Fix the FXSAVE/FXRSTOR instructions.	2025-04-22 09:13:38 +02:00
Miran Grča	a434a98495	Merge pull request #5455 from Torinde/patch-3 ... VIA Cyrix III (Samuel) - add codename	2025-04-21 02:28:23 +02:00
OBattler	8aa15fa21f	The update value handler should be at Pentium Pro, not Cyrix Cx6x86.	2025-04-11 20:27:41 +02:00
OBattler	95a6aa0bdf	Fix the LxS fix again.	2025-04-11 19:29:40 +02:00
Torinde	9032af002d	VIA Cyrix III (Samuel) - add codename ... To distinguish from Cyrix-heritage Joshua CPUs. #5451	2025-04-09 12:17:50 +02:00
OBattler	3b5966eb46	LDS/LES/LFS/LGS/LSS: Fix segment wraparounds in 16-bit address mode.	2025-04-07 06:03:19 +02:00
RichardG867	4bd374a7df	Don't apply the Deschutes cacheability fix to Covington	2025-04-02 16:55:57 -03:00
RichardG867	f56f636248	Report 4 GB cacheable memory on Deschutes CPUs, fixes modern Linux limiting itself to 512 MB on some machines	2025-04-02 16:27:10 -03:00
Cacodemon345	abbae5efd2	Cleanups	2025-03-26 23:18:36 +06:00
Cacodemon345	ad4e90e345	Finally fix RETEM	2025-03-26 23:01:09 +06:00
Cacodemon345	2b107725bd	Custom NMI handling for i8080 emulation	2025-03-26 20:17:13 +06:00
Cacodemon345	99e8d13afa	Implement NEC V20/V30's i8080 emulation mode	2025-03-26 20:04:43 +06:00
OBattler	609f34cc49	Only flush write MMU cache on WP flag toggle as read and execute MMU cache is not affected by the flag.	2025-03-23 15:36:05 +01:00
Cacodemon345	a9c97abfb6	Pre-calculate pow table for FXTRACT instruction	2025-03-20 21:52:48 +06:00