diff --git a/src/include/86box/nv/vid_nv4_defines.h b/src/include/86box/nv/vid_nv4_defines.h
index 3bda4dc1c..2a959670c 100644
--- a/src/include/86box/nv/vid_nv4_defines.h
+++ b/src/include/86box/nv/vid_nv4_defines.h
@@ -49,15 +49,15 @@
 #define NV4_PRAMDAC_NVPLL_COEFF                             0x680500 
 #define NV4_PRAMDAC_NVPLL_COEFF_MDIV                               0 
 #define NV4_PRAMDAC_NVPLL_COEFF_NDIV                               8 
-#define NV4_PRAMDAC_NVPLL_COEFF_PDIV                              16 
+#define NV4_PRAMDAC_NVPLL_COEFF_PDIV                              16 // 18:16
 #define NV4_PRAMDAC_MPLL_COEFF                              0x680504 
 #define NV4_PRAMDAC_MPLL_COEFF_MDIV                                0 
 #define NV4_PRAMDAC_MPLL_COEFF_NDIV                                8 
-#define NV4_PRAMDAC_MPLL_COEFF_PDIV                               16 
+#define NV4_PRAMDAC_MPLL_COEFF_PDIV                               16 // 18:16
 #define NV4_PRAMDAC_VPLL_COEFF                              0x680508 
 #define NV4_PRAMDAC_VPLL_COEFF_MDIV                                0 
 #define NV4_PRAMDAC_VPLL_COEFF_NDIV                                8 
-#define NV4_PRAMDAC_VPLL_COEFF_PDIV                               16 
+#define NV4_PRAMDAC_VPLL_COEFF_PDIV                               16 // 18:16
 #define NV4_PRAMDAC_PLL_COEFF_SELECT                        0x68050C 
 #define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE                   0 
 #define NV4_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_XTAL     		 0x0 
diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c
index f179c8136..9ce5a189a 100644
--- a/src/video/nv/nv3/subsystems/nv3_pramdac.c
+++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c
@@ -156,8 +156,6 @@ void nv3_pramdac_set_pixel_clock(void)
     // frequency divider algorithm from old varcem/86box/pcbox riva driver,
     // verified by reversing NT drivers v1.50e CalcMNP [symbols] function
 
-    // todo: actually implement it
-
     // missing section
     // not really needed.
     // if (nv3->pfb.boot.clock_crystal == CLOCK_CRYSTAL_13500)
diff --git a/src/video/nv/nv4/nv4_core_io.c b/src/video/nv/nv4/nv4_core_io.c
index 51a702bd3..d9fa6f58a 100644
--- a/src/video/nv/nv4/nv4_core_io.c
+++ b/src/video/nv/nv4/nv4_core_io.c
@@ -44,12 +44,12 @@ void nv4_svga_write(uint16_t addr, uint8_t val, void* priv);
 
 uint32_t nv4_mmio_arbitrate_read(uint32_t addr)
 {
-    nv_log_verbose_only("MMIO read from address=0x%08x", addr);
+    nv_log_verbose_only("MMIO read from address=0x%08x\n", addr);
 }
 
 void nv4_mmio_arbitrate_write(uint32_t addr, uint32_t val)
 {
-    nv_log_verbose_only("MMIO write to address=0x%08x value %08x", addr, val);
+    nv_log_verbose_only("MMIO write to address=0x%08x value %08x\n", addr, val);
 }
 
 // Determine if this address needs to be redirected to the SVGA subsystem.
@@ -95,7 +95,7 @@ uint8_t nv4_rma_read(uint16_t addr)
             }
 
             // log current location for vbios RE
-            nv_log_verbose_only("MMIO Real Mode Access read, initial address=0x%04x final RMA MMIO address=0x%08x data=0x%08x\n",
+            nv_log_verbose_only("MMIO Real Mode Access read, initial address=0x%08x final RMA MMIO address=0x%08x data=0x%08x\n",
                 addr, real_final_address, ret);
 
             break;