From 946d8b5bb24f8e962aded83160191192332abe0d Mon Sep 17 00:00:00 2001
From: TC1995 <mariogplayer90@gmail.com>
Date: Wed, 11 Feb 2026 23:38:13 +0100
Subject: [PATCH] Make Cirrus specific 4bpp mode work again.

Alongside the ETEN24 chinese system as well.
Basically, reset the banking/reset to VGA mode only if the bank mode is not 64k at 0xA000.
---
 src/video/vid_cl54xx.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/src/video/vid_cl54xx.c b/src/video/vid_cl54xx.c
index 7979758ef..0a3060467 100644
--- a/src/video/vid_cl54xx.c
+++ b/src/video/vid_cl54xx.c
@@ -1870,10 +1870,12 @@ gd54xx_recalctimings(svga_t *svga)
 
     svga->interlace = (svga->crtc[0x1a] & 0x01);
 
-    if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
-        svga->interlace = 0;
+    if (!svga->scrblank && svga->attr_palette_enable) {
+        if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) /*Text mode*/
+            svga->interlace = 0;
     }
 
+    pclog("CRTC1a=%x, interlace=%x.\n", svga->crtc[0x1a] & 0x01, svga->interlace);
     clocksel = (svga->miscout >> 2) & 3;
 
     if (!gd54xx->vclk_n[clocksel] || !gd54xx->vclk_d[clocksel])
@@ -2059,19 +2061,19 @@ gd54xx_recalctimings(svga_t *svga)
         }
     }
 
-    svga->vram_display_mask = (svga->crtc[0x1b] & 2) ? gd54xx->vram_mask : 0x3ffff;
+    svga->vram_display_mask = (svga->crtc[0x1b] & 0x02) ? gd54xx->vram_mask : 0x3ffff;
 
     if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5430)
         svga->htotal += ((svga->crtc[0x1c] >> 3) & 0x07);
 
-    if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
+    if (!(svga->gdcreg[6] & 0x01) && !(svga->attrregs[0x10] & 0x01)) { /*Text mode*/
         if (svga->seqregs[1] & 8)
             svga->render = svga_render_text_40;
         else
             svga->render = svga_render_text_80;
     }
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
+    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) && (((svga->gdcreg[6] >> 2) & 0x03) != 0x01)) {
         svga->extra_banks[0] = 0;
         svga->extra_banks[1] = 0x8000;
     }
@@ -2288,7 +2290,7 @@ gd54xx_write(uint32_t addr, uint8_t val, void *priv)
 
     xga_write_test(addr, val, svga);
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
+    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) && (((svga->gdcreg[6] >> 2) & 0x03) != 0x01)) {
         svga_write(addr, val, svga);
         return;
     }
@@ -2318,7 +2320,7 @@ gd54xx_writew(uint32_t addr, uint16_t val, void *priv)
     xga_write_test(addr, val, svga);
     xga_write_test(addr + 1, val >> 8, svga);
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
+    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) && (((svga->gdcreg[6] >> 2) & 0x03) != 0x01)) {
         svga_writew(addr, val, svga);
         return;
     }
@@ -2357,7 +2359,7 @@ gd54xx_writel(uint32_t addr, uint32_t val, void *priv)
     xga_write_test(addr + 2, val >> 16, svga);
     xga_write_test(addr + 3, val >> 24, svga);
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
+    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) && (((svga->gdcreg[6] >> 2) & 0x03) != 0x01)) {
         svga_writel(addr, val, svga);
         return;
     }
@@ -2914,7 +2916,7 @@ gd54xx_read(uint32_t addr, void *priv)
     svga_t   *svga   = (svga_t *) priv;
     gd54xx_t *gd54xx = (gd54xx_t *) svga->local;
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA))
+    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) && (((svga->gdcreg[6] >> 2) & 0x03) != 0x01))
         return svga_read(addr, svga);
 
     if (gd54xx->countminusone && gd54xx->blt.ms_is_dest &&
@@ -2935,7 +2937,7 @@ gd54xx_readw(uint32_t addr, void *priv)
     gd54xx_t *gd54xx = (gd54xx_t *) svga->local;
     uint16_t  ret;
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA))
+    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) && (((svga->gdcreg[6] >> 2) & 0x03) != 0x01))
         return svga_readw(addr, svga);
 
     if (gd54xx->countminusone && gd54xx->blt.ms_is_dest &&
@@ -2960,7 +2962,7 @@ gd54xx_readl(uint32_t addr, void *priv)
     gd54xx_t *gd54xx = (gd54xx_t *) svga->local;
     uint32_t  ret;
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA))
+    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) && (((svga->gdcreg[6] >> 2) & 0x03) != 0x01))
         return svga_readl(addr, svga);
 
     if (gd54xx->countminusone && gd54xx->blt.ms_is_dest &&
@@ -4421,6 +4423,7 @@ gd54xx_init(const device_t *info)
             vram              = 1024;
         else
             vram = device_get_config_int("memory");
+
         gd54xx->vram_size = vram << 10;
     } else {
         if (id <= CIRRUS_ID_CLGD5428) {
@@ -4432,6 +4435,7 @@ gd54xx_init(const device_t *info)
                 vram = 512;
             else
                 vram = device_get_config_int("memory");
+
             gd54xx->vram_size = vram << 10;
         } else {
             vram              = device_get_config_int("memory");