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Reapply "Merge pull request #6172 from Cacodemon345/armfixes-2"

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This reverts commit 5577efe301.
This commit is contained in:
Cacodemon345
2025-11-04 17:03:27 +06:00
parent 2369b1c529
commit c00a82c58c
9 changed files with 64 additions and 45 deletions
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28
src/codegen_new/codegen_backend_arm64_ops.c
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@@ -102,6 +102,10 @@
# define OPCODE_SUB_LSR (0x25a << 21)
# define OPCODE_SUBX_LSL (0x658 << 21)
# define OPCODE_INS_B (0x6e010400)
# define OPCODE_INS_H (0x6e020400)
# define OPCODE_INS_S (0x6e040400)
# define OPCODE_INS_D (0x6e080400)
# define OPCODE_ADD_V8B (0x0e208400)
# define OPCODE_ADD_V4H (0x0e608400)
# define OPCODE_ADD_V2S (0x0ea08400)
@@ -180,6 +184,7 @@
# define OPCODE_SQSUB_V8B (0x0e202c00)
# define OPCODE_SQSUB_V4H (0x0e602c00)
# define OPCODE_SQXTN_V8B_8H (0x0e214800)
# define OPCODE_SQXTUN_V8B_8H (0x2e212800)
# define OPCODE_SQXTN_V4H_4S (0x0e614800)
# define OPCODE_SHL_VD (0x0f005400)
# define OPCODE_SHL_VQ (0x4f005400)
@@ -207,6 +212,7 @@
# define OPCODE_ZIP1_V8B (0x0e003800)
# define OPCODE_ZIP1_V4H (0x0e403800)
# define OPCODE_ZIP1_V2S (0x0e803800)
# define OPCODE_ZIP1_V2D (0x4ec03800)
# define OPCODE_ZIP2_V8B (0x0e007800)
# define OPCODE_ZIP2_V4H (0x0e407800)
# define OPCODE_ZIP2_V2S (0x0e807800)
@@ -225,11 +231,11 @@
# define IMM_LOGICAL(imm) ((imm) << 10)
# define BIT_TBxZ(bit) ((((bit) &0x1f) << 19) | (((bit) &0x20) ? (1 << 31) : 0))
# define BIT_TBxZ(bit) ((((bit) & 0x1f) << 19) | (((bit) & 0x20) ? (1 << 31) : 0))
# define OFFSET14(offset) (((offset >> 2) << 5) & 0x0007ffe0)
# define OFFSET19(offset) (((offset >> 2) << 5) & 0x00ffffe0)
# define OFFSET20(offset) (((offset & 3) << 29) | ((((offset) &0x1fffff) >> 2) << 5))
# define OFFSET20(offset) (((offset & 3) << 29) | ((((offset) & 0x1fffff) >> 2) << 5))
# define OFFSET26(offset) ((offset >> 2) & 0x03ffffff)
# define OFFSET12_B(offset) (offset << 10)
@@ -716,6 +722,12 @@ host_arm64_DUP_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int element)
codegen_addlong(block, OPCODE_DUP_V2S | Rd(dst_reg) | Rn(src_n_reg) | DUP_ELEMENT(element));
}
void
host_arm64_INS_D(codeblock_t *block, int dst_reg, int src_reg, int dst_index, int src_index)
{
codegen_addlong(block, OPCODE_INS_D | Rd(dst_reg) | Rn(src_reg) | ((dst_index & 1) << 20) | ((src_index & 1) << 14));
}
void
host_arm64_EOR_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data)
{
@@ -1225,6 +1237,13 @@ host_arm64_SQXTN_V8B_8H(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_SQXTN_V8B_8H | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_SQXTUN_V8B_8H(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_SQXTUN_V8B_8H | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_SQXTN_V4H_4S(codeblock_t *block, int dst_reg, int src_reg)
{
@@ -1475,6 +1494,11 @@ host_arm64_ZIP1_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_re
codegen_addlong(block, OPCODE_ZIP1_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ZIP1_V2D(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ZIP1_V2D | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ZIP2_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ZIP2_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));