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start working on the actual graphics objects. Since we figured out the pfifo/ramht/object class crap.

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starfrost013
2024-12-31 00:38:06 +00:00
parent 56a5522aa6
commit bdc47bf3ee
15 changed files with 591 additions and 20 deletions
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66
src/include/86box/nv/classes/vid_nv3_classes.h Normal file
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@@ -0,0 +1,66 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Defines graphics objects for Nvidia NV3 architecture-based GPU (RIVA 128/RIVA 128 ZX),
* as well as for later GPUs if they use the same objects.
*
*
*
* Authors: Connor Hyde <mario64crashed@gmail.com>
*
* Copyright 2024-2025 Connor Hyde
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
/*
Note: These uint32_ts are basically object methods that are being submitted
They have different names so the user can use them more easily but different versions of the same class can be distinguished
ALL of these structures HAVE to be a size of exactly 0x2000 bytes because that's what the hashtable expects.
Also, these class IDs don't relate to the internal architecture of the GPU.
Effectively, the NVIDIA drivers are faking shit. There are only 16 classes but the drivers recognise many more. See nv3_object_classes_driver.txt for the list of
classes recognised by the driver.
The 3-bit DMA SUBCHANNEL is combined with a 4-bit CLASS ID to get the REAL CLASS ID. There are 32 CLASSES per subchannel and 8 SUBCHANNELS.
This is why the Class IDs you see here are not the same as you may see in other places.
*/
extern const char* nv3_class_names[];
/*
Object Class 0x07 (real hardware)
0x1E (drivers)
Also 0x47 in context IDs
A rectangle. Wahey!
*/
typedef struct nv_object_class_007
{
uint8_t reserved[0xFF]; // Required for NV_CLASS Core Functionality
uint32_t set_notify_ctx_dma; // Set notifier context for DMA
uint32_t set_notify; // Set notifier
uint32_t set_image_output; // Set the image output type
uint8_t reserved2[0xF5]; // up to 0x200
uint32_t set_zeta_output; // Zeta buffer input
uint32_t set_zeta_input; // Zeta buffer input
uint32_t set_color_format; // Color format: 0x100000=15bpp.
uint8_t reserved3[0xF5]; // up to 0x300
/* THESE ARE ALL THE SAME METHOD */
uint32_t color_zeta32; // 32-bit zeta buffer color (?)
uint32_t point; // Draw a point i guess
uint8_t reserved4[0x4F3]; // up to 0x7fc
uint32_t control_out; // 7fd-7ff
uint8_t reserved5[0x1800]; // up to 0x2000
} nv3_rectangle_t;

21
src/include/86box/nv/vid_nv.h
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@@ -6,20 +6,23 @@
*
* This file is part of the 86Box distribution.
*
* JENSEN HUANG APPROVED !!!!
* Shared implementation file for all NVIDIA GPUs (hopefully to be) emulated by 86box.
*
* Credit to:
*
* - fuel (PCBox developer)
* - Marcelina Kościelnicka (envytools)
* - nouveau developers
* - Utah GLX developers
* - XFree86 developers
* - xemu developers
*
* - Marcelina Kościelnicka (envytools) https://envytools.readthedocs.io/en/latest/
* - fuel (PCBox developer) https://github.com/PCBox/PCBox
* - nouveau developers https://nouveau.freedesktop.org/
* - Utah GLX developers https://utah-glx.sourceforge.net/
* - XFree86 developers https://www.xfree86.org/
* - xemu developers https://github.com/xemu-project/xemu
* - RivaTV developers https://rivatv.sourceforge.net (esp. https://rivatv.sourceforge.net/stuff/riva128.txt)
* - Nvidia for leaking their driver symbols numerous times ;^) https://nvidia.com
* - People who prevented me from giving up (various)
*
* Authors: Connor Hyde / starfrost <mario64crashed@gmail.com>
*
* Copyright 2024 Connor Hyde
* Copyright 2024-2025 Connor Hyde
*/
#ifdef EMU_DEVICE_H // what

70
src/include/86box/nv/vid_nv3.h
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@@ -12,11 +12,11 @@
*
* Authors: Connor Hyde <mario64crashed@gmail.com>
*
* Copyright 2024 Connor Hyde
* Copyright 2024-2025 Connor Hyde
*/
// vid_nv3.h: NV3 Architecture Hardware Reference (open-source)
// Last updated 2 December 2024
// Last updated 30 December 2024
// The GPU base structure
extern const device_config_t nv3_config[];
@@ -28,13 +28,20 @@ extern const device_config_t nv3_config[];
#define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start
#define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN
// DMA channels are basically the number of contexts that the gpu can deal with at once.
// Channel 0 is always taken up by NV drivers.
// Subchannels deal with specific parts of the GPU and are manipulated by the driver to manipulate the gpu.
#define NV3_DMA_CHANNELS 8
#define NV3_DMA_SUBCHANNELS_PER_CHANNEL 8
#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 10 // The amount by which we have to ration out the memory clock because it's not fast enough...
// Multiply by this value to get the real clock speed.
// Default value for the boot information register.
// Depends on the chip
#define NV3_BOOT_REG_REV_A00 0x00030100
#define NV3_BOOT_REG_REV_B00 0x00030110
#define NV3_BOOT_REG_REV_C00 0x00030120
#define NV3_BOOT_REG_REV_A00 0x00030100
#define NV3_BOOT_REG_REV_B00 0x00030110
#define NV3_BOOT_REG_REV_C00 0x00030120
// various vbioses for testing
// Coming soon: MIROmagic Premium BIOS (when I get mine dumped)
@@ -297,9 +304,9 @@ extern const device_config_t nv3_config[];
#define NV3_PSTRAPS_OVERWRITE_ENABLED 0x1
#define NV3_PEXTDEV_END 0x101FFF
#define NV3_PROM_START 0x110000 // VBIOS?
#define NV3_PROM_END 0x110FFF
#define NV3_PROM_END 0x11FFFF
#define NV3_PALT_START 0x120000 // ??? but it exists
#define NV3_PALT_END 0x120FFF
#define NV3_PALT_END 0x12FFFF
#define NV3_PME_START 0x200000 // Mediaport
#define NV3_PME_INTR 0x200100 // Mediaport: Interrupt Pending?
#define NV3_PME_INTR_EN 0x200140 // Mediaport: Interrupt Enable
@@ -459,7 +466,7 @@ extern const device_config_t nv3_config[];
#define NV3_PDAC_END 0x680FFF // OPTIONAL external DAC
#define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO
#define NV3_USER_START 0x800000 // Mapping for the area where objects are submitted into the FIFO (up to 0x880000?)
#define NV3_USER_END 0xFFFFFF
// easier name
@@ -478,6 +485,8 @@ extern const device_config_t nv3_config[];
// these all have configurable sizes, define them here
#define NV3_PRAMIN_START 0x1C00000
#define NV3_PRAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects
#define NV3_PRAMIN_RAMHT_END 0x1C00FFF
#define NV3_PRAMIN_RAMHT_SIZE_0 0xFFF
@@ -651,8 +660,15 @@ typedef struct nv_pfifo_s
{
uint32_t interrupt_status; // Interrupt status
uint32_t interrupt_enable; // Interrupt enable
uint32_t ramht_config; // RAMHT config
uint32_t ramfc_config; // RAMFC config
uint32_t ramro_config; // RAMRO config
uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0?
} nv3_pfifo_t;
// create_object(uint32_t type) here
// RAMDAC
typedef struct nv3_pramdac_s
{
@@ -761,12 +777,48 @@ typedef struct nv3_ptimer_s
uint32_t alarm; // The value of time when there should be an alarm
} nv3_ptimer_t;
typedef struct nv3_pramin_name_s
{
union
{
uint32_t name;
uint8_t byte_high;
uint8_t byte_mid2;
uint8_t byte_mid1;
uint8_t byte_low;
};
} nv3_pramin_name_t;
typedef struct nv3_pramin_context_s
{
union
{
uint32_t context;
uint8_t dma_channel;
uint8_t render_object; //0=sw, 1=render
uint8_t class_id;
uint8_t ramin_offset; //find
};
} nv3_pramin_context_t;
// Graphics object hashtable for specific DMA [channel, subchannel] pair
typedef struct nv3_pramin_ramht_subchannel_s
{
nv3_pramin_name_t name; // must be >4096
// Contextual information.
// See the above union.
nv3_pramin_context_t context;
} nv3_pramin_ramht_subchannel_t;
// Graphics object hashtable
typedef struct nv3_pramin_ramht_s
{
nv3_pramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL];
} nv3_pramin_ramht_t;
uint32_t nv3_pramin_ramht_hash(nv3_pramin_name_t name, uint32_t channel);
// Anti-fuckup device
typedef struct nv3_pramin_ramro_s
{