From ba8c8f10d3954619e4d8a6b6d9caf9e752dc6202 Mon Sep 17 00:00:00 2001
From: WNT50 <173389620+WNT50@users.noreply.github.com>
Date: Fri, 27 Feb 2026 22:56:09 +0800
Subject: [PATCH] Fix IBM PS/1 XTA controller in OS/2 1.1

---
 src/disk/hdc_xta_ps1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/disk/hdc_xta_ps1.c b/src/disk/hdc_xta_ps1.c
index c37bf3186..60fb7b13f 100644
--- a/src/disk/hdc_xta_ps1.c
+++ b/src/disk/hdc_xta_ps1.c
@@ -1184,6 +1184,7 @@ hdc_read(uint16_t port, void *priv)
             break;
 
         case 4: /* ISR */
+            dev->status &= ~ASR_INT_REQ;
             ret          = dev->intstat;
             dev->intstat = 0x00;
             break;
@@ -1225,6 +1226,7 @@ hdc_write(uint16_t port, uint8_t val, void *priv)
                     /* We got all the data we need. */
                     dev->status &= ~ASR_DATA_REQ;
                     dev->state = STATE_IDLE;
+                    set_intr(dev, 1);
 
                     /* If we were receiving a CCB, execute it. */
                     if (dev->attn & ATT_CCB) {
@@ -1256,7 +1258,6 @@ hdc_write(uint16_t port, uint8_t val, void *priv)
                 /* Schedule command execution. */
                 timer_set_delay_u64(&dev->timer, HDC_TIME);
             }
-
             break;
 
         case 4: /* ATTN */
@@ -1295,7 +1296,6 @@ hdc_write(uint16_t port, uint8_t val, void *priv)
 
                 dev->state = STATE_RDATA;
                 dev->status |= ASR_DATA_REQ;
-                set_intr(dev, 1);
             }
             break;