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https://github.com/86Box/86Box.git
synced 2026-03-01 02:14:21 -07:00
Merge branch '86Box:master' into master
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@@ -333,6 +333,20 @@
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#define BUS_IDLE (1 << 31)
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#define STATE_IDLE 0
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#define STATE_COMMAND 1
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#define STATE_DATAIN 2
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#define STATE_DATAOUT 3
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#define STATE_STATUS 4
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#define STATE_MESSAGEIN 5
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#define STATE_SELECT 6
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#define STATE_MESSAGEOUT 7
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#define STATE_MESSAGE_ID 8
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#define PIO_TX_BUS 0
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#define DMA_IN_TX_BUS 1
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#define DMA_OUT_TX_BUS 2
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#define PHASE_IDLE 0x00
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#define PHASE_COMMAND 0x01
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#define PHASE_DATA_IN 0x02
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@@ -420,6 +434,36 @@ typedef struct scsi_device_t {
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void (*command_stop)(scsi_common_t *sc);
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} scsi_device_t;
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typedef struct scsi_bus_t {
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int tx_mode;
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int clear_req;
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int wait_data;
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int wait_complete;
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int bus_out;
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int bus_in;
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int command_pos;
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int command_issued;
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int data_pos;
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int msgout_pos;
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int is_msgout;
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int state;
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int dma_on_pio_enabled;
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uint8_t data;
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uint8_t msglun;
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uint8_t data_wait;
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uint8_t command[16];
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uint8_t msgout[4];
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uint8_t target_id;
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uint8_t bus_device;
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uint32_t bus_phase;
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double period;
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double speed;
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double divider;
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double multi;
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void *priv;
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void (*timer)(void *priv, double period);
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} scsi_bus_t;
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/* These are based on the INQUIRY values. */
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#define SCSI_NONE 0x0060
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#define SCSI_FIXED_DISK 0x0000
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@@ -454,6 +498,8 @@ extern void scsi_device_init(void);
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extern void scsi_reset(void);
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extern uint8_t scsi_get_bus(void);
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extern int scsi_bus_read(scsi_bus_t *scsi_bus);
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extern void scsi_bus_update(scsi_bus_t *scsi_bus, int bus);
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extern void scsi_bus_set_speed(uint8_t bus, double speed);
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extern double scsi_bus_get_speed(uint8_t bus);
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@@ -44,6 +44,9 @@
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#define ICR_ACK 0x10
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#define ICR_ARB_LOST 0x20
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#define ICR_ARB_IN_PROGRESS 0x40
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#define ICR_RST 0x80
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#define ICR_PHASE 0x9e
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#define ICR_WRITE 0x9f
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#define MODE_ARBITRATE 0x01
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#define MODE_DMA 0x02
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@@ -63,70 +66,33 @@
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#define TCR_REQ 0x08
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#define TCR_LAST_BYTE_SENT 0x80
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#define STATE_IDLE 0
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#define STATE_COMMAND 1
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#define STATE_DATAIN 2
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#define STATE_DATAOUT 3
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#define STATE_STATUS 4
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#define STATE_MESSAGEIN 5
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#define STATE_SELECT 6
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#define STATE_MESSAGEOUT 7
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#define STATE_MESSAGE_ID 8
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#define DMA_IDLE 0
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#define DMA_SEND 1
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#define DMA_INITIATOR_RECEIVE 2
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typedef struct ncr_t {
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uint8_t icr;
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uint8_t mode;
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uint8_t tcr;
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uint8_t data_wait;
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uint8_t isr;
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uint8_t output_data;
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uint8_t target_id;
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uint8_t tx_data;
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uint8_t msglun;
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uint8_t irq_state;
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uint8_t command[20];
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uint8_t msgout[4];
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uint8_t bus;
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int msgout_pos;
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int is_msgout;
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int dma_mode;
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int cur_bus;
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int bus_in;
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int new_phase;
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int state;
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int clear_req;
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int wait_data;
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int wait_data_back;
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int wait_complete;
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int command_pos;
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int data_pos;
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int irq;
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double period;
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void *priv;
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void (*dma_mode_ext)(void *priv, void *ext_priv);
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void (*dma_mode_ext)(void *priv, void *ext_priv, uint8_t val);
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int (*dma_send_ext)(void *priv, void *ext_priv);
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int (*dma_initiator_receive_ext)(void *priv, void *ext_priv);
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void (*timer)(void *ext_priv, double period);
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scsi_bus_t scsibus;
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} ncr_t;
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extern int ncr5380_cmd_len[8];
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extern void ncr5380_irq(ncr_t *ncr, int set_irq);
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extern void ncr5380_set_irq(ncr_t *ncr, int irq);
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extern void ncr5380_set_irq(ncr_t *ncr, int irq);
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extern uint32_t ncr5380_get_bus_host(ncr_t *ncr);
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extern void ncr5380_bus_read(ncr_t *ncr);
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extern void ncr5380_bus_update(ncr_t *ncr, int bus);
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extern void ncr5380_write(uint16_t port, uint8_t val, ncr_t *ncr);
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extern uint8_t ncr5380_read(uint16_t port, ncr_t *ncr);
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@@ -202,6 +202,14 @@ typedef struct svga_t {
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void (*vblank_start)(struct svga_t *svga);
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void (*write)(uint32_t addr, uint8_t val, void *priv);
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void (*writew)(uint32_t addr, uint16_t val, void *priv);
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void (*writel)(uint32_t addr, uint32_t val, void *priv);
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uint8_t (*read)(uint32_t addr, void *priv);
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uint16_t (*readw)(uint32_t addr, void *priv);
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uint32_t (*readl)(uint32_t addr, void *priv);
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void (*ven_write)(struct svga_t *svga, uint8_t val, uint32_t addr);
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float (*getclock)(int clock, void *priv);
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float (*getclock8514)(int clock, void *priv);
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