From 84f82351618f22bf06b89ddc41e28f7c7e4ab1ef Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 17 Mar 2025 01:15:02 +0000 Subject: [PATCH] Implement bpixel, bformat, bpitch. Actually apply these to class 0x1C mthd 0300,0308,030c. Temporary ROP code too. --- .../B = BUFFER. REMEMBER THESE!!!.txt | 1 + doc/nvidia_notes/NV128.xlsx | Bin 9325 -> 9550 bytes doc/nvidia_notes/NV3 DMA Engine.txt | 3 ++ .../86box/nv/classes/vid_nv3_classes.h | 8 +-- src/include/86box/nv/vid_nv3.h | 50 ++++++++++++++++-- src/include/86box/utils/video_stdlib.h | 2 +- .../classes/nv3_class_01c_image_in_memory.c | 39 ++++++++++++-- src/video/nv/nv3/render/nv3_render_core.c | 3 +- 8 files changed, 92 insertions(+), 14 deletions(-) create mode 100644 doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt diff --git a/doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt b/doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt new file mode 100644 index 000000000..e8f183240 --- /dev/null +++ b/doc/nvidia_notes/B = BUFFER. REMEMBER THESE!!!.txt @@ -0,0 +1 @@ +B = BUFFER. REMEMBER THESE!!! \ No newline at end of file diff --git a/doc/nvidia_notes/NV128.xlsx b/doc/nvidia_notes/NV128.xlsx index e293a97ebdeea621058b4c580a4a72be07c06e12..1cb14fdcc0d22153a3862cf106641e349aea72c8 100644 GIT binary patch delta 3677 zcmZ8kXHXN&77ZmpXrY8&B7`En3L?E1l^&1|Dm4T_dJQG?P5@~tO`6gL1VfF06e%i( zYCsS{Ac8cJ_CB3A^Sycdn>glp5$&ZJk{4SLjyp@wc*gsTl@<4q-}SozGL{aMdhr0z(jHnmTs$s)>zT5)p=Y4mi0}>9)^e{{PF^;VmcM9X zE(mJ(3Ms417i*=Q`ka4|aY-JI#)A6Y6e*zE)GC9-SMOHj#8@J8;0I|esP1USGgo=i z_ut!cGx6x6~(>2aNfyh;8y&PAu#lurAh>03Ve&&2b;WIQTy1bG%X z_T-2x)hDAEL?vDv^SYRHhZ{}KS4UvcOO;q5X zWFM!Pql!q|dV+OOP9)VwXhC1^g&wf%L(99zruu@LnCs$V9uCo8ka&|c(2;Nu#X`Z; z`2*FYbh|K;i6M6LIJSx@y1T`-&TFstuNyr_|N zPhsuwReIbsljg@tg`8R7|Ihw4{){e{t`S#U|C*AL*0lNlVbENQhn-c0cGAIb@Iui=%V zw#lje>&osbi6=N4`3dH$?_BM&rf8DLBrt*xj)5n8ky~zWrW4u)k@snUozX(z)J*8Q za4mfog)}{rtwYv)f#h-IJ1+*y@Rm4MchOq%YrkqxM?FNyRLiA-d=!MdR_f}55skMq zsU~eD4 zh};?I)08~$1R_+hN9a!BsX(iHVR@Vm+apm`y;rNzDZE_!@F!|y1UyANvs96Dvw}ou z=v=fLyM^U(*w!rts{ZG&SLaL8t_Lc!U!T>|FbO&;6bg7M=%y&JajDw3ks;d`erwNqY zUy=L`xsU982BaBuJD5UAqKC08{B3t(W}L}Vwv6OE#4YQ45j-2?`es03H9sb((xLD7 z)2-(2_S=ysSnEe|@9Q{w=J%a17ch0k_&9#KioCj>!c4inU9Z^ zx8L!&o5AOx6sJ4&HXrxxP!^NQr|!eNKvvC|C%j8WmwLgJJh`Flk#efPWucK@N<6tg zHb)Jtifs9rs@EQC%uZ%Y%kQ+wg_O+PY`o|HgB2UI9D*nP1L^-j#ed++jcRw8{YJF! z8@rg<<|{+W+zc5Z!VJo+Z#FwYa`aUCFW5+16E%^`lKKg#uL<1Ph=xFq=<{1NUh%}f zrbW{fJkd01yjw5W`HoL9=TX=v`UJ$2pAetm`*(Z{aR)kYnuM}lIt6+B=Y~S>nepQu z-n6Y6D`3F2(&{g?U=+SXPyIW+xAae{GuCMm)>mK+dHyIIt#L& zbd8k=`RO*{QxC(Inp;-3ohNffUOKMn@5{#%^Uw*SQGqNLi*0>u6qnVld2fbJhngm_E& z2ZVaN`b&l&y4JSdiiL_U3a>3s6|C!@0=d2LapL0-G3xw2;?eZj{%^(;Tx7SGE_ zyarQUJEAC$ZM-d#*m-R4gt1qMt&o_xW+6Lx5ueDI*C|?HU;XRUVLeTzjxHOxV)P#J z!y{b^kpHm{SWKC;6*fjfpD9a618W_e!`L?nFi6Q2;LlMr{nI`BfY1|kgg)1!aVR~j=7;l zg*~#;(2q(7NnHgtKhG_EOd5X*Z>_wDZ%4-s4im*kSgbiYvgl>;wgQYV?V7KY)XTSy z8S%3d0@wREZQD)*V>OBO(`_m@6dvsPKjT=L3=8G;J>%SCCb3q?z_jj(dfaSJ*yTWd zBa^v-6OXC8W;sUdW~Sb=0M7~pQN9@Cz17_nRzETUF8`qTF{O2&uGjIU?be~_AcqRC z3ai_UiL}jB0;@;{jx|za)+n61lPywWVt1ws9np|0S!%X3wqW(py-2VmpMrnNJMsZR z53a!LO3S@&V=modmE&tyc*=7QaP~)yp421V)JOGaZzr$m-5*%g5G|FMFZvATqdafI zZK;W0Fx2CC`-U`5cA9ELz`vw+j$#P=mGrL}Yejonk)`U(QZB$BN!P;kUudRj_!azO zySoibz+##9031|L;}*Zu8-YhR&185+N$1*&zBC?Ltxc7Ndro`dUb*}%)FMTVmn-GF zgoT70m#@!M0Ou`O}mq0bT9Xc(sw#-k^o+*ig)vNf44Bvm~w{7Btr?x+Jmp9(cb z&<8gY<90>}yhst=h=7BI2B7}S#6@AvZ3o?+Z}(x7!2<$!Rq@BK!@U003e@ z008n|FL}5;biHp8@X*u8{ja6axeka0X-L8k%2P0<19A#(jt#PDa?mo@mMTii+Hq_) zxhrGyQ=s$Z>0#b#6&FbF3VGP!#_Glfc5}(UVi{DA(Q`*T$&uFFv@nc(`*sq!=W5g! zS|(POHiSyUmcoKhhQYP|yaTp7vgYB0iK~IG>FK`sDqSA8qalTX#4=S=ye%Z}Ib&qS z2D;g9o~jmlua-Pt73)&B}B!qj>NhGh? zO^2dIDV)id#VOJ*K6NC1X(sgD8(D9@zdvpNgvfA{6&h-|V2x}+$2U_wO}ONJ*>g^{ zsHh=7U9zdhq6f+$I{`Qh#m(iyxeT5 zw#(S>{nMDsPMv{S76I@1VAm$bbnCLSxH!+%Ox%8*eZBSZr99`jBnpVhCWDaQCn)l^ z)^Q7ypv+9-q#^Ny+h^d)Ni7kYVud~?cUGwVU4Fe)yAPj{Iv$30u4myi-boXb|7ezo z_xC9h2g5fbV-@0aMEEt6RI==owTR{iC5`8ZHIA`L=Vv)t<*c-}ZjabNjUv{Zylr)w z3#4h^4BneMR(m`^-j-2_0JF%&_!|iO!b)aiG=rNEj3&(6=y7YNH;F}c&UT50h^a&zDaI^_DL3$3tBzume5#i@5O3= z>smd!Msb~L5?G;~j`=BTxAYZ}tLp+eT^ScPGhUasow^>i_2g290OXOZyO(syz!qw7 zHQ6IVj_(P;CU#Oy|LE_DVnhV!Tjik=WdHMd^WrxqA!0iDCAj{5xdH&}|2XR3#fKq* z>5{Zz^kG8W|3Ab2Wy!N+l3`Hp|2O8pgcL5!8<^1FYsC;@tfZkl7zzPZk`s)M0F2@l I{~zLi03YhQQ~&?~ delta 3466 zcmZ9Pc{J1y_s7SKZDg55WGvB)eJ!D^*^;g7*(YRQMidesTa;}wV~};iD6)o;ee7h7 z7-LN+Ym~Cf@B4Iq=X{^@+&}Ig_q_kQ@B2FU-XZ->y~+>t(8giS5*i2yM8%EKBY}W3 z1gtosm^AvmWbHT7bUDJT6zu9VR#*cW!iBx)f;_W?yBMwH1L?>s9|R@_y{puaX&tpUa;wHB*KEugXG0^h!Z|vl*DDM zjm9J0ts!an7gxte@O85ie*Mc;w~2Et08SyB~0a`%I{Vys=H8J`6|e3 zx{+`pwn8w1y zg`+Y5K9qB03)xE4BX@)dTqicvT(>5=XG%(QzHbF_22?$3H}pRLw3lm8RYs}VBgWP9 zhkj8YaQis=j)!kk5cx!^%jYOeG@{s$UM|bTIOPasz5hJeG5x(k(P2k3olwqw zB5Wv(9=K0OGS0 z!e!r;gW${URep>0T$AA(jgOW>%T<57eOKWgblZ`XJ&>bl{8VS{aMbXC?)3CkuLc}h#&YkLqD5Hs{GufAZc0%DJ#g?iTa&Eo-9Ss(|+Fn&A2#P;z?UEETu>Wt=Ck-;=6szhUIljEC00Dw0SzF;)^K*W7jq{m!aYM z$nRAfhQu>=abMt;K0(2!*LJlid8^^|&(=rG`Pf1i{W)0ZPGm=BZOttEZOx>V4`D}g zG&;X%U%VbG1OoZZA?Q*(Sng0 z#x{GMkZpnSJHD^XfUl1CEM1$sv0R$(6i!D7L?KJxfBY;iC!7WPt}wD!T{}TF}D97;ZZ+>;i0k2Y8ZhqjU70gNMVUWH1O-=hn5 z!Bu{-aR?5KuJUsaj^v+5l&;xd=!xl3nQ;8ST>*mtjPpg6;mhZWw2sJ>gct56VB@F2-?=noKtHCYw9>1>w3zltbT z2y#}xU=|r@eDiU{3d%exex#Z>g#6c#LspFe?{e4q$sb`U84)qU-Vq%`5dT7P%rYZ?W+6h>^GD#UhP!VE9;i*ZTsa{7$!za zW{;rswRO6bpDUA1B13rBn7qUXJm{Z1KNP{zKKy>=-ERp}RGv|{Y(Sus(R;S-MK{`u zW&Cn9%Nm8Pk*P%bRa?VaZFog+g*^4(hP={e63tj}aUcy#b1S{&kD=7=>@<4pxOXk- zRM%p=(Y%{XyuBEeg2%?#((Q>H(iP&&hPHgh0GT|LA`%Nvfd<$jxVz)V!&_st5AVlO zd?f$C$~ySTu^I=!N#z?cwtbnL-N<shtKv-+2f#iX^YX%{^uh}y6X{;p- zN&;@R&oW9Z@XsIoVgun)ARGXt(Uz1+0|I@e1%WvJ9|re(5AM5|1wQcbb^FUiOsdK4 zc3D`@ywNdhy4q@VAe|0knwchjpTHf}lD>&bvR9r?Cgjbrb~5yix>%1kI#!&_+slN{ zSg@1aOGm^7OS#T!;MXQwN_#JhbDq^Lz?D&@}+~$NCc{Z5YBU-a*B3-u9$U zHFd^M=a!p<4BKSIE4RwSJ-wovDv|kb5t}zZzOb|t1=stg8uUh-bx+;*L?8O;IZKRA z5)-~*pz9d2hv+Y*BIzWL^=rYev9@PSItiLqYwfw<1l`r{9GfdukVQX2E-4x6uihrqr*rBk@I0A)H2|?(<@)pE2ru^Rn~4&m>@>Z zgoiGpH5HF!ql*<7t>VJ>NV}mst(?F8_83TZhsq%x&m5O+JRw83+0;?H=W!m(ti7F# z(zc$15`wL4-Qiw@Beb;rklT)&l{eYM;Y6W2g^ zhRg1LWkTF=Qe12%`C81mI#b0@KtsXYJsqm@EKPC;Iuc%)YG&Zi_G?^Q`zFHeoN3s~ zV-Py_RV;nXRV5~&O{17C;L)XQ0TIU-Y4)a^UdQpdSH{XKn8%Pwf%# diff --git a/doc/nvidia_notes/NV3 DMA Engine.txt b/doc/nvidia_notes/NV3 DMA Engine.txt index fe2d61508..380e0281e 100644 --- a/doc/nvidia_notes/NV3 DMA Engine.txt +++ b/doc/nvidia_notes/NV3 DMA Engine.txt @@ -49,3 +49,6 @@ call of mthdCreate for ***DRIVER*** CLASS ID: a7b44, check ptr + + + diff --git a/src/include/86box/nv/classes/vid_nv3_classes.h b/src/include/86box/nv/classes/vid_nv3_classes.h index 39c03b295..e1458671e 100644 --- a/src/include/86box/nv/classes/vid_nv3_classes.h +++ b/src/include/86box/nv/classes/vid_nv3_classes.h @@ -1145,17 +1145,17 @@ typedef enum nv3_object_class_01C_pixel_format_e { // Y8P4 // 12-bits (Y8 - Planar YUV 8 bits (Y value only), 4 bits of indexed colour too? - nv3_m2mt_pixel_format_le_y8_p4 = 0x1010000, + nv3_image_in_memory_pixel_format_le_y8_p4 = 0x1010000, // Y16P2 // 16-bits (Y16) - Planar YUV 16 bits (Y value only), 2 bits of indexed colour too? - nv3_m2mt_pixel_format_le_y16_p2 = 0x1010101, + nv3_image_in_memory_pixel_format_le_y16_p2 = 0x1010101, /* 1 unused bit, 555 15-bit format, p2(?) */ - nv3_m2mt_pixel_format_x1r5g5b5_p2 = 0x1000000, + nv3_image_in_memory_pixel_format_x1r5g5b5_p2 = 0x1000000, // X8G8B8R8, 24-bit colour (or 24-bit colour with alpha) - nv3_m2mt_pixel_format_x8g8b8r8 = 0x1, + nv3_image_in_memory_pixel_format_x8g8b8r8 = 0x1, } nv3_object_class_01C_pixel_format; typedef struct nv3_object_class_01C diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index fb080f1cd..49bc8c64e 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -14,7 +14,7 @@ * Also check the doc folder for some more notres * * vid_nv3.h: NV3 Architecture Hardware Reference (open-source) - * Last updated: 13 March 2025 (STILL WORKING ON IT!!!) + * Last updated: 17 March 2025 (STILL WORKING ON IT!!!) * * Authors: Connor Hyde * @@ -454,6 +454,8 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_START 0x400000 // Scene graph for 2d/3d rendering...the most important part // PGRAPH Core +#define NV3_PGRAPH_MAX_BUFFERS 4 + // For these debug registers, 0=Disabled, 1=Enabled // Debug 0: General @@ -532,7 +534,25 @@ extern const device_config_t nv3_config[]; #define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1 //todo: add what this does #define NV3_PGRAPH_INTR_EN_1 0x400144 // Interrupt Control for PGRAPH #2 (it can receive two at onc) -#define NV3_PGRAPH_CONTEXT_SWITCH 0x400180 // DMA context switcher +#define NV3_PGRAPH_CONTEXT_SWITCH 0x400180 // Holds the current PGRAPH context, switched by context switching + +/* Contextual information for pgraph */ +#define NV3_PGRAPH_CONTEXT_SWITCH_COLOR_FORMAT 2 // Holds the current color format used for drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_ALPHA 3 // Holds a boolean if alpha transparency is currently enabled in drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_MONO_FORMAT 8 // Holds the current color format used for monochome drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_DAC_BYPASS 9 // Holds if PRAMDAC should be bypassed, and an external DAC drawn. +#define NV3_PGRAPH_CONTEXT_SWITCH_Z_WRITE 12 // Holds if we should write back to the zbuffer. +#define NV3_PGRAPH_CONTEXT_SWITCH_CHROMA_KEY 13 // Holds the current chroma mask used for drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_PLANE_MASK 14 // Holds the current plane mask used for drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_USER_CLIP 15 // Holds the user-specified clipping information used for drawing operations. +#define NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER 16 // Holds the buffer ID used for drawing operation (i.e. which bpixel/bpitch/boffset index to use) +#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED 20 // Holds a boolean indicating if buffer 0 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED 21 // Holds a boolean indicating if buffer 1 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED 22 // Holds a boolean indicating if buffer 2 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED 23 // Holds a boolean indicating if buffer 3 can be used as the destination for a drawing operation. +#define NV3_PGRAPH_CONTEXT_SWITCH_PATCH_CONFIG 24 // Something to do with an operation to do during a patchcord? +#define NV3_PGRAPH_CONTEXT_SWITCH_VOLATILE 31 // HUH + #define NV3_PGRAPH_CONTEXT_CONTROL 0x400190 // DMA context control #define NV3_PGRAPH_CONTEXT_USER 0x400194 // Current DMA context state, may rename #define NV3_PGRAPH_CONTEXT_CACHE(i) 0x4001A0+(i*4) // Context Cache @@ -1082,6 +1102,23 @@ typedef struct nv3_pgraph_status_s } nv3_pgraph_status_t; +/* All of this B* stuff is registers at 400630..40065c and 4006a8 in reality, easier to implement it like this + BPixel = Internal Binary Representation of the pixel within the architecture +*/ +#define NV3_BPIXEL_FORMAT 0 +#define NV3_BPIXEL_FORMAT_IS_VALID 2 + +typedef enum nv3_pgraph_bpixel_format_e +{ + // Y16 + bpixel_fmt_y16 = 0, + // 8-bit colour + bpixel_fmt_8bit = 1, + // 16-bit colour + bpixel_fmt_16bit = 2, + // 32-bit colour (BGRA/ARGB) + bpixel_fmt_32bit = 3, +} nv3_pgraph_bpixel_format; // Graphics Subsystem typedef struct nv3_pgraph_s @@ -1126,14 +1163,19 @@ typedef struct nv3_pgraph_s uint32_t beta_factor; nv3_pgraph_dma_settings_t dma_settings; uint8_t rop; // Current GDI Ternary Render Operation + // SURFACE STUFF - PGRAPH CAN OPERATE ON 4 SURFACES/BUFFERS AT A TIME + uint32_t boffset[NV3_PGRAPH_MAX_BUFFERS]; // 22-bit linear VRAM offset for the start of a surface. + uint16_t bpitch[NV3_PGRAPH_MAX_BUFFERS]; // 12-bit linear VRAM offset for the pitch of a surfac.e + uint32_t bpixel[NV3_PGRAPH_MAX_BUFFERS]; // Pixel format for each possible surfaces. + // CLIP nv3_pgraph_clip_misc_settings_t clip_misc_settings; nv3_notifier_t notifier; nv3_position_16_bigy_t clip0_min; nv3_position_16_bigy_t clip0_max; nv3_position_16_bigy_t clip1_min; nv3_position_16_bigy_t clip1_max; - uint32_t fifo_access; - nv3_pgraph_status_t status; + uint32_t fifo_access; // Determines if PGRAPH can access PFIFO. + nv3_pgraph_status_t status; // Current status of the 3D engine. uint32_t trapped_address; uint32_t trapped_data; uint32_t trapped_instance; diff --git a/src/include/86box/utils/video_stdlib.h b/src/include/86box/utils/video_stdlib.h index f8e2ed5af..3605631f1 100644 --- a/src/include/86box/utils/video_stdlib.h +++ b/src/include/86box/utils/video_stdlib.h @@ -17,4 +17,4 @@ /* ROP */ -int32_t video_rop_gdi_ternary(int32_t rop, int32_t dst, int32_t pattern, int32_t src, int32_t out); \ No newline at end of file +int32_t video_rop_gdi_ternary(int32_t rop, int32_t dst, int32_t pattern, int32_t src); \ No newline at end of file diff --git a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c index b42583f7a..547ffc441 100644 --- a/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c +++ b/src/video/nv/nv3/classes/nv3_class_01c_image_in_memory.c @@ -30,19 +30,52 @@ void nv3_class_01c_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t context, nv3_grobj_t grobj) { + /* We need this for a lot of methods, so may as well store it here. */ + uint32_t src_buffer_id = (nv3->pgraph.context_switch >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; + switch (method_id) { + /* Color format of the image */ case NV3_IMAGE_IN_MEMORY_COLOR_FORMAT: + // convert to how the bpixel registers represent surface + uint32_t real_format = 1; + + /* TODO: THIS CODE MIGHT BE NONSENSE + Convert between different internal representations of the pixel format, because Nvidia says: I WANT TO MAKE YOUR LIFE PAIN. + */ + switch (param) + { + case nv3_image_in_memory_pixel_format_x8g8b8r8: + real_format = 3; //32bit + // no change + break; + case nv3_image_in_memory_pixel_format_x1r5g5b5_p2: + real_format = 2; + break; + case nv3_image_in_memory_pixel_format_le_y16_p2: + real_format = 0; + break; + } + + /* Set the format */ + + nv3->pgraph.bpixel[src_buffer_id] = ((real_format & 0x03) | NV3_BPIXEL_FORMAT_IS_VALID); + nv_log("Image in Memory BUF%d COLOR_FORMAT=0x%04x", src_buffer_id, param); + break; /* Pitch - length between scanlines */ case NV3_IMAGE_IN_MEMORY_PITCH: + nv3->pgraph.image_in_memory.pitch = param & 0x1FF0; - nv_log("Image in Memory PITCH=0x%04x", nv3->pgraph.image_in_memory.pitch); + nv3->pgraph.bpitch[src_buffer_id] = param & 0x1FF0; // 12:0 + + nv_log("Image in Memory BUFL%d PITCH=0x%04x", src_buffer_id, nv3->pgraph.bpitch[src_buffer_id]); break; /* Byte offset in GPU VRAM of top left pixel (22:0) */ case NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET: - nv3->pgraph.image_in_memory.linear_address = param & ((1 << NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END) - 0x10); - nv_log("Image in Memory TOP_LEFT_OFFSET=0x%08x", nv3->pgraph.image_in_memory.linear_address); + nv3->pgraph.boffset[src_buffer_id] = param & ((1 << NV3_IMAGE_IN_MEMORY_TOP_LEFT_OFFSET_END) - 0x10); + + nv_log("Image in Memory BUF%d TOP_LEFT_OFFSET=0x%08x", src_buffer_id, nv3->pgraph.image_in_memory.linear_address); break; default: nv_log("%s: Invalid or Unimplemented method 0x%04x", nv3_class_names[context.class_id & 0x1F], method_id); diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c index 426cf2c9d..8b5771f36 100644 --- a/src/video/nv/nv3/render/nv3_render_core.c +++ b/src/video/nv/nv3/render/nv3_render_core.c @@ -27,11 +27,10 @@ #include <86box/video.h> #include <86box/nv/vid_nv.h> #include <86box/nv/vid_nv3.h> -#include <86box/nv/classes/vid_nv3_classes.h> #include <86box/utils/video_stdlib.h> /* Render Core: Performs a ROP */ -void nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, uint32_t pen, nv3_render_operation_type rop) +uint32_t nv3_perform_rop(uint32_t src, uint32_t dst, uint32_t pattern, nv3_render_operation_type rop) { return video_rop_gdi_ternary(rop, dst, pattern, src); } \ No newline at end of file