From 84cb84ed2fa4e6c8f1017f9850981118e86e9150 Mon Sep 17 00:00:00 2001 From: starfrost013 Date: Mon, 27 Jan 2025 01:35:21 +0000 Subject: [PATCH] add numerous reigsters for pfifo --- .../How to optimise riva 128 applications.txt | 4 +- src/include/86box/nv/vid_nv3.h | 62 ++++--- src/video/nv/nv3/subsystems/nv3_pfifo.c | 171 +++++++++++++++++- 3 files changed, 204 insertions(+), 33 deletions(-) diff --git a/doc/nvidia_notes/How to optimise riva 128 applications.txt b/doc/nvidia_notes/How to optimise riva 128 applications.txt index 1c20aef2a..004593a21 100644 --- a/doc/nvidia_notes/How to optimise riva 128 applications.txt +++ b/doc/nvidia_notes/How to optimise riva 128 applications.txt @@ -1,4 +1,6 @@ How to optimise riva 128 applications: * Ensure any set of polygons with one texture is close to a multiple of 128 polygons. * Try to sort areas of a model with one texture to as close to 128 polygons as possible for efficient submission due to the lack of texturing. -* Try to have around (32*128) for nv3 or (64*128) for nv3t polygons \ No newline at end of file +* Try to have around (32*128) for nv3 or (64*128) for nv3t polygons +* Get coding +* Alcohol \ No newline at end of file diff --git a/src/include/86box/nv/vid_nv3.h b/src/include/86box/nv/vid_nv3.h index f0286e2db..2842cd5da 100644 --- a/src/include/86box/nv/vid_nv3.h +++ b/src/include/86box/nv/vid_nv3.h @@ -243,24 +243,27 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_SIZE_REV_C 64 #define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C #define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500 -#define NV3_PFIFO_CACHE0_ACCESS 0x3000 -#define NV3_PFIFO_CACHE0_DMA_CHANNEL_ID 0x3004 +#define NV3_PFIFO_CACHE0_PUSH_ACCESS 0x3000 +#define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004 #define NV3_PFIFO_CACHE0_PUT 0x3010 #define NV3_PFIFO_CACHE0_STATUS 0x3014 #define NV3_PFIFO_CACHE0_STATUS_RANOUT 0 // 1 if we fucked up #define NV3_PFIFO_CACHE0_STATUS_LOW_MARK 4 // 1 if ramro is empty #define NV3_PFIFO_CACHE0_STATUS_HIGH_MARK 8 #define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit -#define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_SUCCESS 4 -#define NV3_PFIFO_CACHE0_PULLER_CONTROL_DEVICE 8 -#define NV3_PFIFO_CACHE0_PULLER_STATE1 0x3050 -#define NV3_PFIFO_CACHE0_PULLER_STATE1_CTX_IS_CLEAN 4 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_SUCCESS 4 +#define NV3_PFIFO_CACHE0_PULLER_CONTROL_DEVICE 8 +#define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY 0x3050 +#define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY_BOOL 4 // 1=dirty 0=clean #define NV3_PFIFO_CACHE0_GET 0x3070 #define NV3_PFIFO_CACHE0_GET_ADDRESS 2 // 1 bit -#define NV3_PFIFO_CACHE1_ACCESS 0x3200 -#define NV3_PFIFO_CACHE1_DMA_CHANNEL_ID 0x3204 +#define NV3_PFIFO_CACHE0_METHOD 0x3100 +#define NV3_PFIFO_CACHE0_METHOD_ADDRESS 2 // 12:2 +#define NV3_PFIFO_CACHE0_METHOD_SUBCHANNEL 13 // 15:13 +#define NV3_PFIFO_CACHE1_PUSH_ACCESS 0x3200 +#define NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID 0x3204 #define NV3_PFIFO_CACHE1_PUT 0x3210 #define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2 #define NV3_PFIFO_CACHE1_STATUS 0x3214 @@ -276,14 +279,17 @@ extern const device_config_t nv3_config[]; #define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230 #define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA #define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA -#define NV3_PFIFO_CACHE1_PULLER_CONTROL 0x3240 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_SUCCESS 4 -#define NV3_PFIFO_CACHE1_PULLER_CONTROL_DEVICE 8 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL 0x3240 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_SUCCESS 4 +#define NV3_PFIFO_CACHE1_PULLER_CONTROL_DEVICE 8 #define NV3_PFIFO_CACHE1_PULLER_STATE1 0x3250 -#define NV3_PFIFO_CACHE1_PULLER_STATE1_CTX_IS_CLEAN 4 +#define NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY 4 #define NV3_PFIFO_CACHE1_GET 0x3270 #define NV3_PFIFO_CACHE1_GET_ADDRESS 2 // 6:2 +#define NV3_PFIFO_CACHE1_METHOD 0x3300 +#define NV3_PFIFO_CACHE1_METHOD_ADDRESS 2 // 12:2 +#define NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 // 15:13 #define NV3_PFIFO_END 0x3FFF #define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem #define NV3_PRM_INTR 0x4100 @@ -588,7 +594,8 @@ extern const device_config_t nv3_config[]; #define NV3_PRAMIN_RAMHT_SIZE_2 0x3FFF #define NV3_PRAMIN_RAMHT_SIZE_3 0x7FFF -#define NV3_PRAMIN_RAMAU_START 0x1C01000 // Auxillary area +/* OBSOLETE AREA for AUDIO probably. DO NOT USE! */ +#define NV3_PRAMIN_RAMAU_START 0x1C01000 #define NV3_PRAMIN_RAMAU_END 0x1C01BFF #define NV3_PRAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels #define NV3_PRAMIN_RAMFC_END 0x1C01DFF @@ -767,9 +774,10 @@ typedef struct nv3_pbus_s typedef struct nv3_pfifo_cache_s { + bool access_enabled; // Can we even access this cache? uint8_t put_address; // Trigger a DMA into the value you put here. uint8_t get_address; // Trigger a DMA from the value you put here into where you were going. - uint8_t channel_id; + uint8_t channel_id; // The DMA channel ID of this cache. uint32_t status; uint32_t status_puller; uint32_t control; @@ -778,15 +786,19 @@ typedef struct nv3_pfifo_cache_s /* cache1 only do we even need to emulate this? */ + uint32_t dma_status; // 0x3218 bool dma_enabled; // 0x3220 bit0 bool dma_is_busy; // 0x3220 bit4 - uint32_t dma_length; - uint32_t dma_address; - uint8_t dma_target_node; // depends on card bus - uint8_t dma_tlb_tag; - uint8_t tlb_pte; // DMA Engine - Translation Lookaside Buffer - uint8_t tlb_pt_base; // DMA Engine - TLB Pagetable Base Addres + uint32_t dma_state; // Corresponds to PFIFO_CACHE1_DMA0 + uint32_t dma_length; // Corresponds to PFIFO_CACHE1_DMA1 + uint32_t dma_address; // Corresponds to PFIFO_CACHE1_DMA2 + uint8_t dma_target_node; // Corresponds to PFIFO_CACHE1_DMA3 depends on card bus + uint8_t dma_tlb_tag; + uint8_t dma_tlb_pte; // DMA Engine - Translation Lookaside Buffer + uint8_t dma_tlb_pt_base; // DMA Engine - TLB Pagetable Base Addres + uint16_t method_address; // address of the method (i.e. what method it is) + uint16_t method_subchannel; // subchannel bool context_is_dirty; /* TODO */ @@ -1293,6 +1305,10 @@ uint32_t nv3_pfifo_read(uint32_t address); void nv3_pfifo_write(uint32_t address, uint32_t value); // NV3 PFIFO - Caches +void nv3_pfifo_cache0_push(); +void nv3_pfifo_cache0_pull(); +void nv3_pfifo_cache1_push(); +void nv3_pfifo_cache1_pull(); uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val); uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val); diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c index aaf27ab25..7956632f4 100644 --- a/src/video/nv/nv3/subsystems/nv3_pfifo.c +++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c @@ -39,17 +39,33 @@ nv_register_t pfifo_registers[] = { { NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL }, { NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL }, - { NV3_PFIFO_CACHE0_PULLER_CONTROL, "PFIFO - Cache0 Puller State0", NULL, NULL}, - { NV3_PFIFO_CACHE0_PULLER_STATE1, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, + { NV3_PFIFO_CACHE0_PULLER_CONTROL, "PFIFO - Cache0 Puller Control", NULL, NULL}, + { NV3_PFIFO_CACHE1_PULLER_CONTROL, "PFIFO - Cache1 Puller Control"}, + { NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL}, { NV3_PFIFO_CACHE1_PULLER_CONTROL, "PFIFO - Cache1 Puller State0", NULL, NULL}, { NV3_PFIFO_CACHE1_PULLER_STATE1, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL}, - + { NV3_PFIFO_CACHE0_PUSH_ACCESS, "PFIFO - Cache0 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE1_PUSH_ACCESS, "PFIFO - Cache1 Access", NULL, NULL, }, + { NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID, "PFIFO - Cache0 DMA Channel ID", NULL, NULL, }, + { NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID, "PFIFO - Cache1 DMA Channel ID", NULL, NULL, }, + { NV3_PFIFO_CACHE0_ERROR_PENDING, "PFIFO - Cache0 DMA Error Pending?", NULL, NULL, }, { NV3_PFIFO_CACHE0_STATUS, "PFIFO - Cache0 Status", NULL, NULL}, { NV3_PFIFO_CACHE1_STATUS, "PFIFO - Cache1 Status", NULL, NULL}, { NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL }, { NV3_PFIFO_CACHE1_GET, "PFIFO - Cache1 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL }, { NV3_PFIFO_CACHE0_PUT, "PFIFO - Cache0 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL }, { NV3_PFIFO_CACHE1_PUT, "PFIFO - Cache1 Put MUST TRIGGER DMA NOW TO INSERT ENTRY", NULL, NULL }, + //Cache1 exclusive stuff + { NV3_PFIFO_CACHE1_DMA_CONFIG_0, "PFIFO - Cache1 DMA Config0"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_1, "PFIFO - Cache1 DMA Config1"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_2, "PFIFO - Cache1 DMA Config2"}, + { NV3_PFIFO_CACHE1_DMA_CONFIG_3, "PFIFO - Cache1 DMA Config3"}, + { NV3_PFIFO_CACHE1_DMA_STATUS, "PFIFO - Cache1 DMA Status"}, + { NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE, "PFIFO - Cache1 DMA Translation Lookaside Buffer - Pagetable Base"}, + { NV3_PFIFO_CACHE1_DMA_TLB_PTE, "PFIFO - Cache1 DMA Status"}, + { NV3_PFIFO_CACHE1_DMA_TLB_TAG, "PFIFO - Cache1 DMA Status"}, + + { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value }; @@ -107,7 +123,7 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_DEBUG_0: ret = nv3->pfifo.debug_0; break; - // These may need to become functions. + // Some of these may need to become functions. case NV3_PFIFO_CONFIG_RAMFC: ret = nv3->pfifo.ramfc_config; break; @@ -117,6 +133,45 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CONFIG_RAMRO: ret = nv3->pfifo.ramro_config; break; + case NV3_PFIFO_CACHE0_PULLER_CONTROL: + ret = nv3->pfifo.cache0_settings.control; + break; + case NV3_PFIFO_CACHE1_PULLER_CONTROL: + ret = nv3->pfifo.cache1_settings.control; + break; + case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY: + ret = nv3->pfifo.cache0_settings.context_is_dirty; + break; + case NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY: + ret = nv3->pfifo.cache1_settings.context_is_dirty; + break; + case NV3_PFIFO_CACHE0_PUSH_ACCESS: + ret = nv3->pfifo.cache0_settings.access_enabled; + break; + case NV3_PFIFO_CACHE1_PUSH_ACCESS: + ret = nv3->pfifo.cache1_settings.access_enabled; + break; + case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: + ret = nv3->pfifo.cache0_settings.channel_id; + break; + case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: + ret = nv3->pfifo.cache1_settings.channel_id; + break; + case NV3_PFIFO_CACHE0_STATUS: + /* Todo: Return values based on runout put/get*/ + ret = nv3->pfifo.cache0_settings.status; + break; + case NV3_PFIFO_CACHE1_STATUS: + ret = nv3->pfifo.cache1_settings.status; + break; + case NV3_PFIFO_CACHE0_METHOD: + ret = ((nv3->pfifo.cache0_settings.method_subchannel << 13) & 0x07) + | ((nv3->pfifo.cache0_settings.method_address << 2) & 0x7FF); + break; + case NV3_PFIFO_CACHE1_METHOD: + ret = ((nv3->pfifo.cache1_settings.method_subchannel << 13) & 0x07) + | ((nv3->pfifo.cache1_settings.method_address << 2) & 0x7FF); + break; case NV3_PFIFO_CACHE0_GET: //wa break; @@ -124,13 +179,34 @@ uint32_t nv3_pfifo_read(uint32_t address) case NV3_PFIFO_CACHE_REASSIGNMENT: ret = nv3->pfifo.cache_reassignment & 0x01; //1bit meaningful break; + // Cache1 exclusive stuff // Control - case NV3_PFIFO_CACHE0_PULLER_CONTROL: - ret = nv3->pfifo.cache0_settings.control; // 8bits meaningful + case NV3_PFIFO_CACHE1_DMA_CONFIG_0: + ret = nv3->pfifo.cache1_settings.dma_state; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_1: + ret = nv3->pfifo.cache1_settings.dma_length; break; - case NV3_PFIFO_CACHE1_PULLER_CONTROL: - ret = nv3->pfifo.cache1_settings.control; // only 8bits are meaningful + case NV3_PFIFO_CACHE1_DMA_CONFIG_2: + ret = nv3->pfifo.cache1_settings.dma_address; break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_3: + ret = nv3->pfifo.cache1_settings.dma_target_node; + break; + case NV3_PFIFO_CACHE1_DMA_STATUS: + ret = nv3->pfifo.cache1_settings.dma_status; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE: + ret = nv3->pfifo.cache1_settings.dma_tlb_pt_base; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_PTE: + ret = nv3->pfifo.cache1_settings.dma_tlb_pte; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_TAG: + ret = nv3->pfifo.cache1_settings.dma_tlb_tag; + break; + + } } @@ -243,7 +319,64 @@ void nv3_pfifo_write(uint32_t address, uint32_t value) break; case NV3_PFIFO_CACHE1_PULLER_CONTROL: nv3->pfifo.cache1_settings.control = value; // 8bits meaningful - + break; + case NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY: + nv3->pfifo.cache0_settings.context_is_dirty = value; + break; + case NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY: + nv3->pfifo.cache1_settings.context_is_dirty = value; + break; + case NV3_PFIFO_CACHE0_PUSH_ACCESS: + nv3->pfifo.cache0_settings.access_enabled = value; + break; + case NV3_PFIFO_CACHE1_PUSH_ACCESS: + nv3->pfifo.cache1_settings.access_enabled = value; + break; + case NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID: + nv3->pfifo.cache0_settings.channel_id = value; + break; + case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID: + nv3->pfifo.cache1_settings.channel_id = value; + break; + case NV3_PFIFO_CACHE0_STATUS: + /* Todo: Return values based on runout put/get*/ + nv3->pfifo.cache0_settings.status = value; + break; + case NV3_PFIFO_CACHE1_STATUS: + nv3->pfifo.cache1_settings.status = value; + break; + case NV3_PFIFO_CACHE0_METHOD: + nv3->pfifo.cache0_settings.method_subchannel = (value >> 13) & 0x07; + nv3->pfifo.cache0_settings.method_address = (value >> 2) & 0x7FF; + + break; + case NV3_PFIFO_CACHE1_METHOD: + nv3->pfifo.cache1_settings.method_subchannel = (value >> 13) & 0x07; + nv3->pfifo.cache1_settings.method_address = (value >> 2) & 0x7FF; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_0: + nv3->pfifo.cache1_settings.dma_state = value; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_1: + nv3->pfifo.cache1_settings.dma_length = value; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_2: + nv3->pfifo.cache1_settings.dma_address = value; + break; + case NV3_PFIFO_CACHE1_DMA_CONFIG_3: + nv3->pfifo.cache1_settings.dma_target_node = value; + break; + case NV3_PFIFO_CACHE1_DMA_STATUS: + nv3->pfifo.cache1_settings.dma_status = value; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE: + nv3->pfifo.cache1_settings.dma_tlb_pt_base = value; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_PTE: + nv3->pfifo.cache1_settings.dma_tlb_pte = value; + break; + case NV3_PFIFO_CACHE1_DMA_TLB_TAG: + nv3->pfifo.cache1_settings.dma_tlb_tag = value; break; } } @@ -279,4 +412,24 @@ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val) } return val; +} + +void nv3_pfifo_cache0_push() +{ + +} + +void nv3_pfifo_cache0_pull() +{ + +} + +void nv3_pfifo_cache1_push() +{ + +} + +void nv3_pfifo_cache1_pull() +{ + } \ No newline at end of file