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The Intel SIO and PIIX* southbridges now have the undocumented (by the datasheets, but fully documented by the Intel motherboard technical specifications) second PIT on ports 48h-4Bh.

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OBattler
2021-04-13 03:47:46 +02:00
parent 5a228ba8db
commit 76f3f08d78
4 changed files with 21 additions and 2 deletions
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src/include/86box/pit.h
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@@ -109,6 +109,7 @@ extern void pit_handler(int set, uint16_t base, int size, void *priv);
#ifdef EMU_DEVICE_H
extern const device_t i8253_device;
extern const device_t i8254_device;
extern const device_t i8254_sec_device;
extern const device_t i8254_ext_io_device;
extern const device_t i8254_ps2_device;
#endif