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synced 2026-03-02 02:38:24 -07:00
Ramout enum. More descriptive names for the crtc registers in mmio
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@@ -451,10 +451,10 @@ extern const device_config_t nv3_config[];
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#define NV3_PRMCIO_START 0x601000
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// Following four are CRTC+I2C access registers
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// and get redirected to VGA
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#define NV3_PRMCIO_CRX_MONO 0x6013B4
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#define NV3_PRMCIO_CR_MONO 0x6013B5
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#define NV3_PRMCIO_CRX_COLOR 0x6013D4
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#define NV3_PRMCIO_CR_COLOR 0x6013D5
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#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO 0x6013B4 // Current CRTC Register Index - Monochrome
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#define NV3_PRMCIO_CRTC_REGISTER_CUR_MONO 0x6013B5 // Currently Selected CRTC Register - Monochrome
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#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR 0x6013D4 // Current CRTC Register Index - Colour
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#define NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR 0x6013D5
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#define NV3_PRMCIO_END 0x601FFF
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#define NV3_PDAC_START 0x680000 // OPTIONAL external DAC
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@@ -825,7 +825,7 @@ typedef struct nv3_ptimer_s
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uint32_t alarm; // The value of time when there should be an alarm
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} nv3_ptimer_t;
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typedef struct nv3_pramin_name_s
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typedef struct nv3_pramin_name_sd
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{
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union
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{
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@@ -843,7 +843,7 @@ typedef struct nv3_pramin_context_s
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{
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uint32_t context;
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uint8_t dma_channel;
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uint8_t render_object; //0=sw, 1=render
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uint8_t render_object; //0=sw, 1=hw accelerated render
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uint8_t class_id;
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uint8_t ramin_offset; //find
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};
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@@ -867,6 +867,32 @@ typedef struct nv3_pramin_ramht_s
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uint32_t nv3_ramht_hash(nv3_pramin_name_t name, uint32_t channel);
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typedef enum nv3_pramin_ramro_reason_e
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{
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nv3_runout_reason_illegal_access = 0,
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// PFIFO CACHE0/CACHE1 were turned off, so the graphics object could not be processed.
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nv3_runout_reason_no_cache_available = 1,
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// Ran out of CACHE0 & CACHE1 space.
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nv3_runout_reason_cache_ran_out = 2,
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nv3_runout_reason_free_count_overrun = 3,
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nv3_runout_reason_caught_lying = 4,
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// Access reserved by pagetable
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nv3_runout_reason_reserved_access = 5,
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} nv3_pramin_ramro_reason;
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/* This is a gigantic error handling system */
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typedef struct nv3_pramin_ramro_entry_s
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{
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//todo
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} nv3_pramin_ramro_entry_t;
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// Anti-fuckup device
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typedef struct nv3_pramin_ramro_s
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{
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