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Implement a bizarre register that nvidia did not even internally document. WTF?

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This commit is contained in:
starfrost013
2025-04-18 19:05:28 +01:00
parent 102d47690d
commit 52c36d5644
5 changed files with 84 additions and 113 deletions
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2
src/include/86box/nv/render/vid_nv3_render.h
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@@ -18,7 +18,7 @@
#pragma once
/* Core */
void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check);
void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t position, nv3_size_16_t size, nv3_grobj_t grobj, bool run_render_check, bool use_destination_buffer);
void nv3_render_current_bpp_dfb_8(uint32_t address);
void nv3_render_current_bpp_dfb_16(uint32_t address);
void nv3_render_current_bpp_dfb_32(uint32_t address);

20
src/include/86box/nv/vid_nv3.h
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@@ -79,9 +79,9 @@ extern const device_config_t nv3t_config[]; // Confi
#define NV3_VBIOS_DEFAULT NV3_VBIOS_ERAZOR_V15403
// Temporary, will be loaded from settings
#define NV3_VRAM_SIZE_2MB 0x200000 // 2MB
#define NV3_VRAM_SIZE_4MB 0x400000 // 4MB
#define NV3_VRAM_SIZE_8MB 0x800000 // NV3T only
#define NV3_VRAM_SIZE_2MB 0x200000 // 2MB
#define NV3_VRAM_SIZE_4MB 0x400000 // 4MB
#define NV3_VRAM_SIZE_8MB 0x800000 // NV3T only
// There is also 1mb supported by the card but it was never used
// PCI config
@@ -676,10 +676,7 @@ extern const device_config_t nv3t_config[]; // Confi
#define NV3_PRMCIO_START 0x601000
#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_MONO 0x6013B4 // Current CRTC Register Index - Monochrome
#define NV3_PRMCIO_CRTC_REGISTER_CUR_MONO 0x6013B5 // Currently Selected CRTC Register - Monochrome
#define NV3_PRMCIO_CRTC_REGISTER_CUR_INDEX_COLOR 0x6013D4 // Current CRTC Register Index - Colour
#define NV3_PRMCIO_CRTC_REGISTER_CUR_COLOR 0x6013D5
#define NV3_PRMCIO_END 0x601FFF
#define NV3_PDAC_START 0x680000 // OPTIONAL external DAC
@@ -787,6 +784,9 @@ extern const device_config_t nv3t_config[]; // Confi
// CRTC/CIO (0x3b0-0x3df)
#define NV3_CRTC_REGISTER_INDEX_MONO 0x3B4
#define NV3_CRTC_REGISTER_MONO 0x3B5 // Currently Selected CRTC Register - Monochrome
#define NV3_CRTC_DATA_OUT 0x3C0
#define NV3_CRTC_MISCOUT 0x3C2
@@ -796,6 +796,8 @@ extern const device_config_t nv3t_config[]; // Confi
#define NV3_CRTC_REGISTER_INDEX 0x3D4
#define NV3_CRTC_REGISTER_CURRENT 0x3D5
#define NV3_CRTC_REGISTER_WTF 0x3D8
// These are standard (0-18h)
#define NV3_CRTC_REGISTER_HTOTAL 0x00
#define NV3_CRTC_REGISTER_HDISPEND 0x01
@@ -1076,8 +1078,8 @@ typedef struct nv3_pramdac_s
uint32_t hserr_width; // horizontal sync error width
uint8_t user_pixel_mask; // pixel mask for DAC lookup
uint32_t user_read_mode_address; // user read mode address
uint32_t user_write_mode_address; // user write mode address
uint32_t user_read_mode_address; // user read mode address
uint32_t user_write_mode_address; // user write mode address
uint8_t palette[NV3_USER_DAC_PALETTE_SIZE]; // Palette Info/CLUT - 256 entriesxr,g,b = 768 bytes
} nv3_pramdac_t;