mirror/86Box
1
0
Fork 0
mirror of https://github.com/86Box/86Box.git synced 2026-03-01 18:34:23 -07:00
Code Issues Packages Projects Releases Activity

Merge branch 'master' of ssh://github.com/86Box/86Box into feature/mtrr

Browse Source
This commit is contained in:
RichardG867
2020-04-26 11:52:06 -03:00
parent a59a680337 3aaf9ac6fe
commit 3bd5ccb531
23 changed files with 2387 additions and 2408 deletions
Download Patch File Download Diff File Expand all files Collapse all files

412
src/acpi.c
View File

@@ -32,6 +32,7 @@
#include <86box/keyboard.h>
#include <86box/nvr.h>
#include <86box/pit.h>
#include <86box/apm.h>
#include <86box/acpi.h>
@@ -77,8 +78,28 @@ acpi_update_irq(void *priv)
}
static void
acpi_raise_smi(void *priv)
{
acpi_t *dev = (acpi_t *) priv;
if (dev->vendor == VEN_VIA) {
if ((dev->regs.glbctl & 0x01) && (!dev->regs.smi_lock || !dev->regs.smi_active)) {
smi_line = 1;
dev->regs.smi_active = 1;
}
} else {
if (dev->regs.glbctl & 0x01) {
smi_line = 1;
/* Clear bit 16 of GLBCTL. */
dev->regs.glbctl &= ~0x00010000;
}
}
}
static uint32_t
acpi_reg_read_common(int size, uint16_t addr, void *p)
acpi_reg_read_intel(int size, uint16_t addr, void *p)
{
acpi_t *dev = (acpi_t *) p;
uint32_t ret = 0x00000000;
@@ -117,16 +138,6 @@ acpi_reg_read_common(int size, uint16_t addr, void *p)
/* PCNTRL - Processor Control Register (IO) */
ret = (dev->regs.pcntrl >> shift32) & 0xff;
break;
case 0x14:
/* PLVL2 - Processor Level 2 Register (IO) */
if (size == 1)
ret = dev->regs.plvl2;
break;
case 0x15:
/* PLVL3 - Processor Level 3 Register (IO) */
if (size == 1)
ret = dev->regs.plvl3;
break;
case 0x18: case 0x19:
/* GLBSTS - Global Status Register (IO) */
ret = (dev->regs.glbsts >> shift16) & 0xff;
@@ -173,8 +184,118 @@ acpi_reg_read_common(int size, uint16_t addr, void *p)
}
static uint32_t
acpi_reg_read_via(int size, uint16_t addr, void *p)
{
acpi_t *dev = (acpi_t *) p;
uint32_t ret = 0x00000000;
int shift16, shift32;
addr &= 0xff;
shift16 = (addr & 1) << 3;
shift32 = (addr & 3) << 3;
switch (addr) {
case 0x00: case 0x01:
/* PMSTS - Power Management Status Register (IO) */
ret = (dev->regs.pmsts >> shift16) & 0xff;
break;
case 0x02: case 0x03:
/* PMEN - Power Management Resume Enable Register (IO) */
ret = (dev->regs.pmen >> shift16) & 0xff;
break;
case 0x04: case 0x05:
/* PMCNTRL - Power Management Control Register (IO) */
ret = (dev->regs.pmcntrl >> shift16) & 0xff;
break;
case 0x08: case 0x09: case 0x0a: case 0x0b:
/* PMTMR - Power Management Timer Register (IO) */
ret = (dev->regs.timer_val >> shift32) & 0xff;
break;
case 0x10: case 0x11: case 0x12: case 0x13:
/* PCNTRL - Processor Control Register (IO) */
ret = (dev->regs.pcntrl >> shift32) & 0xff;
break;
case 0x20: case 0x21:
/* GPSTS - General Purpose Status Register (IO) */
ret = (dev->regs.gpsts >> shift16) & 0xff;
break;
case 0x22: case 0x23:
/* General Purpose SCI Enable */
ret = (dev->regs.gpscien >> shift16) & 0xff;
break;
case 0x24: case 0x25:
/* General Purpose SMI Enable */
ret = (dev->regs.gpsmien >> shift16) & 0xff;
break;
case 0x26: case 0x27:
/* Power Supply Control */
ret = (dev->regs.pscntrl >> shift16) & 0xff;
break;
case 0x28: case 0x29:
/* GLBSTS - Global Status Register (IO) */
ret = (dev->regs.glbsts >> shift16) & 0xff;
break;
case 0x2a: case 0x2b:
/* GLBEN - Global Enable Register (IO) */
ret = (dev->regs.glben >> shift16) & 0xff;
break;
case 0x2c: case 0x2d:
/* GLBCTL - Global Control Register (IO) */
ret = (dev->regs.glbctl >> shift16) & 0xff;
ret &= ~0x0110;
ret |= (dev->regs.smi_lock ? 0x10 : 0x00);
ret |= (dev->regs.smi_active ? 0x01 : 0x00);
break;
case 0x2f:
/* SMI Command */
if (size == 1)
ret = dev->regs.smicmd & 0xff;
break;
case 0x30: case 0x31: case 0x32: case 0x33:
/* Primary Activity Detect Status */
ret = (dev->regs.padsts >> shift32) & 0xff;
break;
case 0x34: case 0x35: case 0x36: case 0x37:
/* Primary Activity Detect Enable */
ret = (dev->regs.paden >> shift32) & 0xff;
break;
case 0x38: case 0x39: case 0x3a: case 0x3b:
/* GP Timer Reload Enable */
ret = (dev->regs.gptren >> shift32) & 0xff;
break;
case 0x40:
/* GPIO Direction Control */
if (size == 1)
ret = dev->regs.gpio_dir & 0xff;
break;
case 0x42:
/* GPIO port Output Value */
if (size == 1)
ret = dev->regs.gpio_val & 0xff;
break;
case 0x44:
/* GPIO port Output Value */
if (size == 1)
ret = dev->regs.extsmi_val & 0xff;
break;
case 0x46: case 0x47:
/* GPO Port Output Value */
ret = (dev->regs.gpo_val >> shift16) & 0xff;
break;
case 0x48: case 0x49:
/* GPO Port Input Value */
ret = (dev->regs.gpi_val >> shift16) & 0xff;
break;
}
acpi_log("(%i) ACPI Read (%i) %02X: %02X\n", in_smm, size, addr, ret);
return ret;
}
static void
acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *p)
{
acpi_t *dev = (acpi_t *) p;
int shift16, shift32;
@@ -199,6 +320,12 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
case 0x04: case 0x05:
/* PMCNTRL - Power Management Control Register (IO) */
dev->regs.pmcntrl = ((dev->regs.pmcntrl & ~(0xff << shift16)) | (val << shift16)) & 0x3c07;
/* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
dev->regs.glbsts |= 0x01;
if (dev->regs.glben & 0x02)
acpi_raise_smi(dev);
}
if (dev->regs.pmcntrl & 0x2000) {
sus_typ = (dev->regs.pmcntrl >> 10) & 7;
switch (sus_typ) {
@@ -240,16 +367,6 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
/* PCNTRL - Processor Control Register (IO) */
dev->regs.pcntrl = ((dev->regs.pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00023e1e;
break;
case 0x14:
/* PLVL2 - Processor Level 2 Register (IO) */
if (size == 1)
dev->regs.plvl2 = val;
break;
case 0x15:
/* PLVL3 - Processor Level 3 Register (IO) */
if (size == 1)
dev->regs.plvl3 = val;
break;
case 0x18: case 0x19:
/* GLBSTS - Global Status Register (IO) */
dev->regs.glbsts &= ~((val << shift16) & 0x0df7);
@@ -264,8 +381,13 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
break;
case 0x28: case 0x29: case 0x2a: case 0x2b:
/* GLBCTL - Global Control Register (IO) */
// dev->regs.glbctl = ((dev->regs.glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0701ff07;
dev->regs.glbctl = ((dev->regs.glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0700ff07;
dev->regs.glbctl = ((dev->regs.glbctl & ~(0xff << shift32)) | (val << shift32)) & 0x0701ff07;
/* Setting BIOS_RLS also sets GBL_STS and generates SMI. */
if (dev->regs.glbctl & 0x00000002) {
dev->regs.pmsts |= 0x20;
if (dev->regs.pmen & 0x20)
acpi_update_irq(dev);
}
break;
case 0x2c: case 0x2d: case 0x2e: case 0x2f:
/* DEVCTL - Device Control Register (IO) */
@@ -280,6 +402,180 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
}
static void
acpi_reg_write_via(int size, uint16_t addr, uint8_t val, void *p)
{
acpi_t *dev = (acpi_t *) p;
int shift16, shift32;
int sus_typ;
addr &= 0xff;
acpi_log("(%i) ACPI Write (%i) %02X: %02X\n", in_smm, size, addr, val);
shift16 = (addr & 1) << 3;
shift32 = (addr & 3) << 3;
switch (addr) {
case 0x00: case 0x01:
/* PMSTS - Power Management Status Register (IO) */
dev->regs.pmsts &= ~((val << shift16) & 0x8d31);
acpi_update_irq(dev);
if ((addr == 0x00) && !(dev->regs.pmsts & 0x20))
dev->regs.glbctl &= ~0x0002;
break;
case 0x02: case 0x03:
/* PMEN - Power Management Resume Enable Register (IO) */
dev->regs.pmen = ((dev->regs.pmen & ~(0xff << shift16)) | (val << shift16)) & 0x0521;
acpi_update_irq(dev);
break;
case 0x04: case 0x05:
/* PMCNTRL - Power Management Control Register (IO) */
dev->regs.pmcntrl = ((dev->regs.pmcntrl & ~(0xff << shift16)) | (val << shift16)) & 0x3c07;
/* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
dev->regs.glbsts |= 0x20;
if (dev->regs.glben & 0x20)
acpi_raise_smi(dev);
}
if (dev->regs.pmcntrl & 0x2000) {
sus_typ = (dev->regs.pmcntrl >> 10) & 7;
switch (sus_typ) {
case 0:
/* Soft power off. */
exit(-1);
break;
case 1:
/* Suspend to RAM. */
nvr_reg_write(0x000f, 0xff, dev->nvr);
/* Do a hard reset. */
device_reset_all_pci();
cpu_alt_reset = 0;
pci_reset();
keyboard_at_reset();
mem_a20_alt = 0;
mem_a20_recalc();
flushmmucache();
resetx86();
break;
}
}
break;
case 0x10: case 0x11: case 0x12: case 0x13:
/* PCNTRL - Processor Control Register (IO) */
dev->regs.pcntrl = ((dev->regs.pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x0000001e;
break;
case 0x20: case 0x21:
/* GPSTS - General Purpose Status Register (IO) */
dev->regs.gpsts &= ~((val << shift16) & 0x03ff);
break;
case 0x22: case 0x23:
/* General Purpose SCI Enable */
dev->regs.gpscien = ((dev->regs.gpscien & ~(0xff << shift16)) | (val << shift16)) & 0x03ff;
break;
case 0x24: case 0x25:
/* General Purpose SMI Enable */
dev->regs.gpsmien = ((dev->regs.gpsmien & ~(0xff << shift16)) | (val << shift16)) & 0x03ff;
break;
case 0x26: case 0x27:
/* Power Supply Control */
dev->regs.pscntrl = ((dev->regs.pscntrl & ~(0xff << shift16)) | (val << shift16)) & 0x0701;
break;
case 0x28: case 0x29:
/* GLBSTS - Global Status Register (IO) */
dev->regs.glbsts &= ~((val << shift16) & 0x007f);
break;
case 0x2a: case 0x2b:
/* GLBEN - Global Enable Register (IO) */
dev->regs.glben = ((dev->regs.glben & ~(0xff << shift16)) | (val << shift16)) & 0x007f;
break;
case 0x2c:
/* GLBCTL - Global Control Register (IO) */
dev->regs.glbctl = (dev->regs.glbctl & ~0xff) | (val & 0xff);
dev->regs.smi_lock = !!(dev->regs.glbctl & 0x0010);
/* Setting BIOS_RLS also sets GBL_STS and generates SMI. */
if (dev->regs.glbctl & 0x0002) {
dev->regs.pmsts |= 0x20;
if (dev->regs.pmen & 0x20)
acpi_update_irq(dev);
}
break;
case 0x2d:
/* GLBCTL - Global Control Register (IO) */
dev->regs.glbctl &= ~((val << 8) & 0x0100);
if (val & 0x01)
dev->regs.smi_active = 0;
break;
case 0x2f:
/* SMI Command */
if (size == 1) {
dev->regs.smicmd = val & 0xff;
dev->regs.glbsts |= 0x40;
if (dev->regs.glben & 0x40)
acpi_raise_smi(dev);
}
break;
case 0x30: case 0x31: case 0x32: case 0x33:
/* Primary Activity Detect Status */
dev->regs.padsts &= ~((val << shift32) & 0x000000fd);
break;
case 0x34: case 0x35: case 0x36: case 0x37:
/* Primary Activity Detect Enable */
dev->regs.paden = ((dev->regs.paden & ~(0xff << shift32)) | (val << shift32)) & 0x000000fd;
break;
case 0x38: case 0x39: case 0x3a: case 0x3b:
/* GP Timer Reload Enable */
dev->regs.gptren = ((dev->regs.gptren & ~(0xff << shift32)) | (val << shift32)) & 0x000000d9;
break;
case 0x40:
/* GPIO Direction Control */
if (size == 1)
dev->regs.gpio_dir = val & 0xff;
break;
case 0x42:
/* GPIO port Output Value */
if (size == 1)
dev->regs.gpio_val = val & 0xff;
break;
case 0x46: case 0x47:
/* GPO Port Output Value */
dev->regs.gpo_val = ((dev->regs.gpo_val & ~(0xff << shift16)) | (val << shift16)) & 0xffff;
break;
}
}
static uint32_t
acpi_reg_read_common(int size, uint16_t addr, void *p)
{
acpi_t *dev = (acpi_t *) p;
uint8_t ret = 0xff;
if (dev->vendor == VEN_VIA)
ret = acpi_reg_read_via(size, addr, p);
else
ret = acpi_reg_read_intel(size, addr, p);
return ret;
}
static void
acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
{
acpi_t *dev = (acpi_t *) p;
if (dev->vendor == VEN_VIA)
acpi_reg_write_via(size, addr, val, p);
else
acpi_reg_write_intel(size, addr, val, p);
}
static uint32_t
acpi_reg_readl(uint16_t addr, void *p)
{
@@ -440,6 +736,46 @@ acpi_set_nvr(acpi_t *dev, nvr_t *nvr)
}
static void
acpi_apm_out(uint16_t port, uint8_t val, void *p)
{
acpi_t *dev = (acpi_t *) p;
acpi_log("[%04X:%08X] APM write: %04X = %02X (BX = %04X, CX = %04X)\n", CS, cpu_state.pc, port, val, BX, CX);
port &= 0x0001;
if (port == 0x0000) {
dev->apm->cmd = val;
if (dev->apm->do_smi) {
if (dev->vendor == VEN_INTEL)
dev->regs.glbsts |= 0x20;
acpi_raise_smi(dev);
}
} else
dev->apm->stat = val;
}
static uint8_t
acpi_apm_in(uint16_t port, void *p)
{
acpi_t *dev = (acpi_t *) p;
uint8_t ret = 0xff;
port &= 0x0001;
if (port == 0x0000)
ret = dev->apm->cmd;
else
ret = dev->apm->stat;
acpi_log("[%04X:%08X] APM read: %04X = %02X\n", CS, cpu_state.pc, port, ret);
return ret;
}
static void
acpi_reset(void *priv)
{
@@ -482,6 +818,13 @@ acpi_init(const device_t *info)
if (dev == NULL) return(NULL);
memset(dev, 0x00, sizeof(acpi_t));
dev->vendor = info->local;
if (dev->vendor == VEN_INTEL) {
dev->apm = device_add(&apm_pci_acpi_device);
io_sethandler(0x00b2, 0x0002, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev);
}
timer_add(&dev->timer, acpi_timer_count, dev, 0);
timer_set_delay_u64(&dev->timer, ACPICONST);
@@ -489,11 +832,26 @@ acpi_init(const device_t *info)
}
const device_t acpi_device =
const device_t acpi_intel_device =
{
"ACPI",
"ACPI v1.0",
DEVICE_PCI,
0,
VEN_INTEL,
acpi_init,
acpi_close,
acpi_reset,
NULL,
acpi_speed_changed,
NULL,
NULL
};
const device_t acpi_via_device =
{
"ACPI v1.2",
DEVICE_PCI,
VEN_VIA,
acpi_init,
acpi_close,
acpi_reset,

18
src/apm.c
View File

@@ -116,7 +116,8 @@ static void
apm_t *dev = (apm_t *) malloc(sizeof(apm_t));
memset(dev, 0, sizeof(apm_t));
io_sethandler(0x00b2, 0x0002, apm_in, NULL, NULL, apm_out, NULL, NULL, dev);
if (info->local == 0)
io_sethandler(0x00b2, 0x0002, apm_in, NULL, NULL, apm_out, NULL, NULL, dev);
return dev;
}
@@ -150,3 +151,18 @@ const device_t apm_pci_device =
NULL,
NULL
};
const device_t apm_pci_acpi_device =
{
"Advanced Power Management (PCI)",
DEVICE_PCI,
1,
apm_init,
apm_close,
apm_reset,
NULL,
NULL,
NULL,
NULL
};

12
src/config.c
View File

@@ -957,7 +957,12 @@ load_hard_disks(void)
wcsncpy(hdd[c].fn, &wp[wcslen(usr_path)], sizeof_w(hdd[c].fn));
} else
#endif
wcsncpy(hdd[c].fn, wp, sizeof_w(hdd[c].fn));
if (plat_path_abs(wp)) {
wcsncpy(hdd[c].fn, wp, sizeof_w(hdd[c].fn));
} else {
wcsncpy(hdd[c].fn, usr_path, sizeof_w(hdd[c].fn));
wcsncat(hdd[c].fn, wp, sizeof_w(hdd[c].fn)-wcslen(usr_path));
}
/* If disk is empty or invalid, mark it for deletion. */
if (! hdd_is_valid(c)) {
@@ -1832,7 +1837,10 @@ save_hard_disks(void)
sprintf(temp, "hdd_%02i_fn", c+1);
if (hdd_is_valid(c) && (wcslen(hdd[c].fn) != 0))
config_set_wstring(cat, temp, hdd[c].fn);
if (!wcsnicmp(hdd[c].fn, usr_path, wcslen(usr_path)))
config_set_wstring(cat, temp, &hdd[c].fn[wcslen(usr_path)]);
else
config_set_wstring(cat, temp, hdd[c].fn);
else
config_delete_var(cat, temp);
}

2085
src/cpu/codegen_timing_p6.c
View File

File diff suppressed because it is too large Load Diff

2085
src/cpu_new/codegen_timing_p6.c
View File

File diff suppressed because it is too large Load Diff

4
src/ddma.c
View File

@@ -107,9 +107,9 @@ ddma_reg_write(uint16_t addr, uint8_t val, void *p)
break;
case 0x02:
if (ch >= 4)
outb(0x88 + page_regs[ch], val);
outb(0x88 + page_regs[ch & 3], val);
else
outb(0x80 + page_regs[ch], val);
outb(0x80 + page_regs[ch & 3], val);
break;
case 0x04:
dma[ch].cb = (dma[ch].cb & 0xffff00) | val;

2
src/disk/hdc_ide.c
View File

@@ -410,7 +410,7 @@ ide_get_max(ide_t *ide, int type)
return -1;
case TYPE_UDMA: /* UDMA */
if (!ide_boards[ide->board]->force_ata3 && (ide_bm[ide->board] != NULL))
return 2;
return 4 /*2*/;
return -1;
default:

2
src/disk/mo.c
View File

@@ -1983,7 +1983,7 @@ mo_get_max(int ide_has_dma, int type)
ret = ide_has_dma ? 1 : -1;
break;
case TYPE_UDMA:
ret = ide_has_dma ? 2 : -1;
ret = ide_has_dma ? 4 /*2*/ : -1;
break;
}

2
src/disk/zip.c
View File

@@ -2243,7 +2243,7 @@ zip_get_max(int ide_has_dma, int type)
ret = ide_has_dma ? 1 : -1;
break;
case TYPE_UDMA:
ret = ide_has_dma ? 2 : -1;
ret = ide_has_dma ? 4 /*2*/ : -1;
break;
}

30
src/include/86box/acpi.h
View File

@@ -6,13 +6,6 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the ISA Bus (de)Bugger expansion card
* sold as a DIY kit in the late 1980's in The Netherlands.
* This card was a assemble-yourself 8bit ISA addon card for
* PC and AT systems that had several tools to aid in low-
* level debugging (mostly for faulty BIOSes, bootloaders
* and system kernels...)
*
* Definitions for the ACPI emulation.
*
*
@@ -46,21 +39,31 @@ extern "C" {
#define ACPI_ENABLE 0xf1
#define ACPI_DISABLE 0xf0
#define VEN_INTEL 0x8086
#define VEN_VIA 0x1106
typedef struct
{
uint8_t plvl2, plvl3,
smicmd, gpio_dir,
gpio_val, extsmi_val,
timer32,
gpireg[3], gporeg[4];
uint16_t pmsts, pmen,
pmcntrl, gpsts,
gpen, io_base;
int slot,
irq_mode, irq_pin;
gpen, io_base,
gpscien, gpsmien,
pscntrl, gpo_val,
gpi_val;
int slot, irq_mode,
irq_pin, smi_lock,
smi_active;
uint32_t pcntrl, glbsts,
devsts, glben,
glbctl, devctl,
timer_val;
padsts, paden,
gptren, timer_val;
uint64_t tmr_overflow_time;
} acpi_regs_t;
@@ -69,13 +72,16 @@ typedef struct
{
acpi_regs_t regs;
uint8_t gporeg_default[4];
int vendor;
pc_timer_t timer;
nvr_t *nvr;
apm_t *apm;
} acpi_t;
/* Global variables. */
extern const device_t acpi_device;
extern const device_t acpi_intel_device;
extern const device_t acpi_via_device;
/* Functions. */

9
src/include/86box/apm.h
View File

@@ -6,13 +6,6 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the ISA Bus (de)Bugger expansion card
* sold as a DIY kit in the late 1980's in The Netherlands.
* This card was a assemble-yourself 8bit ISA addon card for
* PC and AT systems that had several tools to aid in low-
* level debugging (mostly for faulty BIOSes, bootloaders
* and system kernels...)
*
* Definitions for the Advanced Power Management emulation.
*
*
@@ -38,7 +31,9 @@ typedef struct
/* Global variables. */
extern const device_t apm_device;
extern const device_t apm_pci_device;
extern const device_t apm_pci_acpi_device;
/* Functions. */

7
src/include/86box/ddma.h
View File

@@ -6,13 +6,6 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the ISA Bus (de)Bugger expansion card
* sold as a DIY kit in the late 1980's in The Netherlands.
* This card was a assemble-yourself 8bit ISA addon card for
* PC and AT systems that had several tools to aid in low-
* level debugging (mostly for faulty BIOSes, bootloaders
* and system kernels...)
*
* Definitions for the Distributed DMA emulation.
*
*

1
src/include/86box/machine.h
View File

@@ -267,7 +267,6 @@ extern int machine_at_endeavor_init(const machine_t *);
extern int machine_at_zappa_init(const machine_t *);
extern int machine_at_mb500n_init(const machine_t *);
extern int machine_at_president_init(const machine_t *);
extern int machine_at_apollo_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_VECTRA54)
extern int machine_at_vectra54_init(const machine_t *);
#endif

3
src/include/86box/piix.h
View File

@@ -4,7 +4,8 @@
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the Intel PIIX and PIIX3 Xcelerators.
* Emulation of the Intel PIIX, PIIX3, PIIX4, PIIX4E, and SMSC
* SLC90E66 (Victory66) Xcelerators.
*
* Emulation core dispatcher.
*

7
src/include/86box/usb.h
View File

@@ -6,13 +6,6 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the ISA Bus (de)Bugger expansion card
* sold as a DIY kit in the late 1980's in The Netherlands.
* This card was a assemble-yourself 8bit ISA addon card for
* PC and AT systems that had several tools to aid in low-
* level debugging (mostly for faulty BIOSes, bootloaders
* and system kernels...)
*
* Definitions for the Distributed DMA emulation.
*
*

23
src/intel_piix.c
View File

@@ -4,7 +4,8 @@
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the Intel PIIX and PIIX3 Xcelerators.
* Emulation of the Intel PIIX, PIIX3, PIIX4, PIIX4E, and SMSC
* SLC90E66 (Victory66) Xcelerators.
*
* PRD format :
* word 0 - base address
@@ -779,7 +780,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
case 0x04:
fregs[0x04] = (val & 0x01);
smbus_update_io_mapping(dev);
apm_set_do_smi(dev->apm, !!(fregs[0x5b] & 0x02) && !!(val & 0x01));
apm_set_do_smi(dev->acpi->apm, !!(fregs[0x5b] & 0x02) && !!(val & 0x01));
break;
case 0x07:
if (val & 0x08)
@@ -844,7 +845,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x5b:
fregs[addr] = val & 0x03;
apm_set_do_smi(dev->apm, !!(val & 0x02) && !!(fregs[0x04] & 0x01));
apm_set_do_smi(dev->acpi->apm, !!(val & 0x02) && !!(fregs[0x04] & 0x01));
break;
case 0x63:
fregs[addr] = val & 0xf7;
@@ -1109,9 +1110,7 @@ piix_apm_out(uint16_t port, uint8_t val, void *p)
piix_t *dev = (piix_t *) p;
if (dev->apm->do_smi) {
if (dev->type > 3)
dev->acpi->regs.glbsts |= 0x20;
else
if (dev->type < 4)
dev->regs[0][0xaa] |= 0x80;
}
}
@@ -1189,7 +1188,7 @@ static void
dev->nvr = device_add(&piix4_nvr_device);
dev->smbus = device_add(&piix4_smbus_device);
dev->acpi = device_add(&acpi_device);
dev->acpi = device_add(&acpi_intel_device);
acpi_set_slot(dev->acpi, dev->pci_slot);
acpi_set_nvr(dev->acpi, dev->nvr);
@@ -1206,9 +1205,13 @@ static void
} else
cpu_fast_off_val = cpu_fast_off_count = 0;
dev->apm = device_add(&apm_pci_device);
/* APM intercept handler to update PIIX/PIIX3 and PIIX4/4E/SMSC ACPI SMI status on APM SMI. */
io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, piix_apm_out, NULL, NULL, dev);
/* On PIIX4, PIIX4E, and SMSC, APM is added by the ACPI device. */
if (dev->type < 4) {
dev->apm = device_add(&apm_pci_device);
/* APM intercept handler to update PIIX/PIIX3 and PIIX4/4E/SMSC ACPI SMI status on APM SMI. */
io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, piix_apm_out, NULL, NULL, dev);
}
dev->port_92 = device_add(&port_92_pci_device);
dma_alias_set();

31
src/machine/m_at_socket4_5.c
View File

@@ -384,37 +384,6 @@ machine_at_president_init(const machine_t *model)
}
int
machine_at_apollo_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/apollo/S728P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ls486e_nvr_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_pci_device);
device_add(&fdc37c932fr_device);
device_add(&intel_flash_bxt_device);
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_VECTRA54)
int
machine_at_vectra54_init(const machine_t *model)

3
src/machine/m_at_socket7_s7.c
View File

@@ -511,7 +511,6 @@ machine_at_brio80xx_init(const machine_t *model)
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c935_device);
// device_add(&intel_flash_bxt_device);
device_add(&sst_flash_29ee020_device);
return ret;
@@ -536,7 +535,7 @@ machine_at_pb680_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_ONBOARD, 4, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);

44
src/machine/machine_table.c
View File

@@ -201,7 +201,7 @@ const machine_t machines[] = {
{ "[486 PCI] Zida Tomato 4DP", "4dps", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 127, machine_at_4dps_init, NULL },
/* Socket 4 machines */
//430LX
/* 430LX */
{ "[Socket 4 LX] IBM Ambra DP60 PCI", "ambradp60", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_ambradp60_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_VPP60)
{ "[Socket 4 LX] IBM PS/ValuePoint P60", "valuepointp60", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_valuepointp60_init, NULL },
@@ -210,13 +210,12 @@ const machine_t machines[] = {
{ "[Socket 4 LX] Micro Star 586MC1", "586mc1", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL },
/* Socket 5 machines */
//430NX
/* 430NX */
{ "[Socket 5 NX] Intel Premiere/PCI II", "plato", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_plato_init, NULL },
{ "[Socket 5 NX] IBM Ambra DP90 PCI", "ambradp90", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_ambradp90_init, NULL },
{ "[Socket 5 NX] Gigabyte GA-586IP", "430nx", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_430nx_init, NULL },
//430FX
{ "[Socket 5 FX] AMI Apollo", "apollo", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_apollo_init, NULL },
/* 430FX */
#if defined(DEV_BRANCH) && defined(USE_VECTRA54)
{ "[Socket 5 FX] HP Vectra VL 5 Series 4", "vectra54", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 511, machine_at_vectra54_init, NULL },
#endif
@@ -226,7 +225,7 @@ const machine_t machines[] = {
{ "[Socket 5 FX] President Award 430FX PCI","president", MACHINE_CPUS_PENTIUM_S5, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_president_init, NULL },
/* Socket 7 machines */
//430FX
/* 430FX */
{ "[Socket 7-3V FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p54tp4xe_init, NULL },
{ "[Socket 7-3V FX] Intel Advanced/ATX", "thor", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_thor_init, NULL },
{ "[Socket 7-3V FX] Intel Advanced/EV", "endeavor", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_endeavor_init, at_endeavor_get_device },
@@ -235,7 +234,7 @@ const machine_t machines[] = {
#endif
{ "[Socket 7-3V FX] Packard Bell PB640", "pb640", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_pb640_init, at_pb640_get_device },
//430HX
/* 430HX */
{ "[Socket 7-3V HX] Acer M3a", "acerm3a", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_acerm3a_init, NULL },
{ "[Socket 7-3V HX] AOpen AP53", "ap53", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_ap53_init, NULL },
{ "[Socket 7-3V HX] SuperMicro Super P55T2S","p55t2s", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_p55t2s_init, NULL },
@@ -246,47 +245,46 @@ const machine_t machines[] = {
{ "[Socket 7 HX] Intel TC430HX", "tc430hx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_tc430hx_init, NULL },
{ "[Socket 7 HX] Toshiba Equium 5200D", "equium5200", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_equium5200_init, NULL },
//430VX
/* 430VX */
{ "[Socket 7 VX] ASUS P/I-P55TVP4", "p55tvp4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55tvp4_init, NULL },
{ "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
{ "[Socket 7 VX] Epox P55-VA", "p55va", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL },
{ "[Socket 7 VX] HP Brio 80xx", "brio80xx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_brio80xx_init, NULL },
{ "[Socket 7 VX] Packard Bell PB680", "pb680", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_pb680_init, NULL },
//430TX
/* 430TX */
{ "[Socket 7 TX] ASUS TX97", "tx97", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_tx97_init, NULL },
{ "[Socket 7 TX] Gigabyte GA-586T2", "586t2", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_586t2_init, NULL },
{ "[Socket 7 TX] Intel YM430TX", "ym430tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_ym430tx_init, NULL },
{ "[Socket 7 TX] Iwill P55XB2", "p55xb2", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_p55xb2_init, NULL },
{ "[Socket 7 TX] PC Partner TXA807DS", "807ds", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_807ds_init, NULL },
{ "[Socket 7 TX] SuperMicro P5MMS98", "p5mms98", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_p5mms98_init, NULL },
//Apollo VPX
/* Apollo VPX */
{ "[Socket 7 VPX] Zida Tomato TX100", "tx100", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_tx100_init, NULL },
//Apollo VP3
/* Apollo VP3 */
{ "[Socket 7 VP3] QDI Advance II", "advanceii", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_advanceii_init, NULL },
/* Super Socket 7 machines */
//Apollo MVP3
/* Apollo MVP3 */
{ "[Super 7 MVP3] AOpen AX59 Pro", "ax59pro", MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_ax59pro_init, NULL },
{ "[Super 7 MVP3] FIC VA-503+", "ficva503p", MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_mvp3_init, NULL },
/* Socket 8 machines */
//440FX
/* 440FX */
{ "[Socket 8 FX] Gigabyte GA-686NX", "686nx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_686nx_init, NULL },
{ "[Socket 8 FX] PC Partner MB600N", "mb600n", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_mb600n_init, NULL },
{ "[Socket 8 FX] Biostar MB-8500ttc", "8500ttc", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_8500ttc_init, NULL },
{ "[Socket 8 FX] Micronics M6MI", "m6mi", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 384, 8, 127, machine_at_m6mi_init, NULL },
/* Slot 1 machines */
//440FX
/* 440FX */
{ "[Slot 1 FX] ECS P6KFX-A", "p6kfx", {{"Intel", cpus_PentiumII_28v},{"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 384, 8, 127, machine_at_p6kfx_init, NULL },
//440LX
//440BX
/* 440LX */
/* 440BX */
{ "[Slot 1 BX] Gigabyte GA-6BXC", "6bxc", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_6bxc_init, NULL },
{ "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
{ "[Slot 1 BX] ASUS P2B-LS (coreboot BIOS)","p2bls_cb", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"", NULL}, {"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_COREBOOT, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
@@ -294,18 +292,18 @@ const machine_t machines[] = {
{ "[Slot 1 BX] ASUS P3B-F (coreboot BIOS)", "p3bf_cb", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"", NULL}, {"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_COREBOOT, 8, 1024, 8, 255, machine_at_p3bf_init, NULL },
{ "[Slot 1 BX] ABit BF6", "bf6", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_bf6_init, NULL },
//440ZX
/* 440ZX */
{ "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL },
/* PGA370 machines */
//440BX
/* 440BX */
{ "[Socket 370 BX] ASUS CUBX", "cubx", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_cubx_init, NULL },
{ "[Socket 370 BX] A-Trend ATC7020BXII", "atc7020bxii", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_atc7020bxii_init, NULL },
//440ZX
/* 440ZX */
{ "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL },
//VIA Apollo Pro
/* VIA Apollo Pro */
{ "[Socket 370 APRO] PC Partner APAS3", "apas3", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_apas3_init, NULL },
{ NULL, NULL, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL }

2
src/mouse_bus.c
View File

@@ -832,7 +832,7 @@ static const device_config_t ms_config[] = {
const device_t mouse_logibus_device = {
"Logitech Bus Mouse",
"Logitech/Microsoft Bus Mouse",
DEVICE_ISA,
MOUSE_TYPE_LOGIBUS,
bm_init, bm_close, NULL,

2
src/scsi/scsi_cdrom.c
View File

@@ -2595,7 +2595,7 @@ scsi_cdrom_get_max(int ide_has_dma, int type)
ret = ide_has_dma ? 2 : -1;
break;
case TYPE_UDMA:
ret = ide_has_dma ? 2 : -1;
ret = ide_has_dma ? 4 /*2*/ : -1;
break;
default:
ret = -1;

1
src/win/win_about.c
View File

@@ -53,6 +53,7 @@ AboutDialogProcedure(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
case WM_COMMAND:
switch (LOWORD(wParam)) {
case IDOK:
case IDCANCEL:
EndDialog(hdlg, 0);
plat_pause(0);
return TRUE;

10
src/win/win_settings.c
View File

@@ -2352,7 +2352,10 @@ win_settings_hard_disks_update_item(HWND hwndList, int i, int column)
lvI.pszText = szText;
lvI.iImage = 0;
} else if (column == 1) {
lvI.pszText = temp_hdd[i].fn;
if (!wcsnicmp(temp_hdd[i].fn, usr_path, wcslen(usr_path)))
lvI.pszText = temp_hdd[i].fn + wcslen(usr_path);
else
lvI.pszText = temp_hdd[i].fn;
lvI.iImage = 0;
} else if (column == 2) {
wsprintf(szText, plat_get_string(IDS_4098), temp_hdd[i].tracks);
@@ -2421,7 +2424,10 @@ win_settings_hard_disks_recalc_list(HWND hwndList)
return FALSE;
lvI.iSubItem = 1;
lvI.pszText = temp_hdd[i].fn;
if (!wcsnicmp(temp_hdd[i].fn, usr_path, wcslen(usr_path)))
lvI.pszText = temp_hdd[i].fn + wcslen(usr_path);
else
lvI.pszText = temp_hdd[i].fn;
lvI.iItem = j;
lvI.iImage = 0;