diff --git a/src/disk/hdc_xta_ps1.c b/src/disk/hdc_xta_ps1.c
index 38f49fa67..c37bf3186 100644
--- a/src/disk/hdc_xta_ps1.c
+++ b/src/disk/hdc_xta_ps1.c
@@ -381,6 +381,7 @@ typedef struct hdc_t {
     pc_timer_t timer;
     int8_t     state; /* controller state */
     int8_t     reset; /* reset state counter */
+    int8_t     ready; /* ready state counter */
 
     /* Data transfer. */
     int16_t buf_idx; /* buffer index and pointer */
@@ -723,6 +724,15 @@ hdc_callback(void *priv)
     uint8_t  cmd = ccb->cmd & 0x0f;
 #endif
 
+    /* If we are returning from a RESET, handle this first. */
+    if (dev->reset) {
+        ps1_hdc_log("XTA reset.\n");
+        dev->status &= ~ASR_BUSY;
+        dev->reset = 0;
+        do_finish(dev);
+        return;
+    }
+
     /* Clear the SSB error bits. */
     dev->ssb.track_0        = 0;
     dev->ssb.cylinder_err   = 0;
@@ -754,6 +764,12 @@ hdc_callback(void *priv)
                 return;
             }
 
+            if (!(dev->ready | no_data)) {
+                /* Delay a bit, transfer not ready. */
+                timer_advance_u64(&dev->timer, HDC_TIME);
+                return;
+            }
+
             switch (dev->state) {
                 case STATE_IDLE:
                     /* Seek to cylinder if requested. */
@@ -944,6 +960,12 @@ do_send:
                 return;
             }
 
+            if (!(dev->ready | no_data)) {
+                /* Delay a bit, transfer not ready. */
+                timer_advance_u64(&dev->timer, HDC_TIME);
+                return;
+            }
+
             switch (dev->state) {
                 case STATE_IDLE:
                     /* Seek to cylinder if requested. */
@@ -1228,24 +1250,21 @@ hdc_write(uint16_t port, uint8_t val, void *priv)
             if (val & ACR_INT_EN)
                 set_intr(dev, 0); /* clear IRQ */
 
-            if (dev->reset != 0) {
-                if (++dev->reset == 3) {
-                    dev->reset = 0;
-
-                    set_intr(dev, 1);
-                }
-                break;
+            if (val & ACR_RESET) {
+                dev->reset = 1;
+                dev->status |= ASR_BUSY;
+                /* Schedule command execution. */
+                timer_set_delay_u64(&dev->timer, HDC_TIME);
             }
 
-            if (val & ACR_RESET)
-                dev->reset = 1;
             break;
 
         case 4: /* ATTN */
             dev->status &= ~ASR_INT_REQ;
-            if (val & ATT_DATA) {
-                /* Dunno. Start PIO/DMA now? */
-            }
+            if (val & ATT_DATA)
+                dev->ready = 1;
+            else
+                dev->ready = 0;
 
             if (val & ATT_SSB) {
                 if (dev->attn & ATT_CCB) {