diff --git a/CMakeLists.txt b/CMakeLists.txt
index 52f24f4b9..c9825b9ef 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -139,7 +139,7 @@ option(DISCORD      "Discord Rich Presence support"
 option(DEBUGREGS486 "Enable debug register opeartion on 486+ CPUs"               OFF)
 # Remove when merged, should just be -D
 option(NV_LOG       "NVidia RIVA 128 debug logging"                              ON)
-option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging"                    OFF)
+option(NV_LOG_ULTRA "Even more NVidia RIVA 128 debug logging"                    ON)
 
 if (NV_LOG)
     add_compile_definitions(ENABLE_NV_LOG)
diff --git a/src/include/86box/nv/render/vid_nv3_render.h b/src/include/86box/nv/render/vid_nv3_render.h
index 11f4d2368..346396c54 100644
--- a/src/include/86box/nv/render/vid_nv3_render.h
+++ b/src/include/86box/nv/render/vid_nv3_render.h
@@ -24,12 +24,12 @@ void nv3_render_current_bpp_dfb_16(uint32_t address);
 void nv3_render_current_bpp_dfb_32(uint32_t address);
 
 void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grobj_t grobj);
-uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination);
-uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination);
-uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination);
+uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj);
+uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj);
+uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj);
 
 
-uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination);
+uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj);
 
 uint32_t nv3_render_to_chroma(nv3_color_expanded_t expanded);
 nv3_color_expanded_t nv3_render_expand_color(uint32_t color, nv3_grobj_t grobj);            // Convert a colour to full RGB10 format from the current working format.
diff --git a/src/video/nv/nv3/classes/nv3_class_010_blit.c b/src/video/nv/nv3/classes/nv3_class_010_blit.c
index 6582ada13..b1dc30ea0 100644
--- a/src/video/nv/nv3/classes/nv3_class_010_blit.c
+++ b/src/video/nv/nv3/classes/nv3_class_010_blit.c
@@ -47,12 +47,7 @@ void nv3_class_010_method(uint32_t param, uint32_t method_id, nv3_ramin_context_
             /* This is the last one*/
             nv3->pgraph.blit.size.w = (param & 0xFFFF);
             nv3->pgraph.blit.size.h = ((param >> 16) & 0xFFFF);
-            nv_log("Method Execution: S2SB Size %04x,%04x grobj_0=0x%08x\n", nv3->pgraph.blit.point_in.x, nv3->pgraph.blit.point_in.y, grobj.grobj_0);
-
-            /* Some blits have (point_in == point_out) ???? */
-            if (nv3->pgraph.blit.point_in.x == nv3->pgraph.blit.point_out.x
-            && nv3->pgraph.blit.point_in.y == nv3->pgraph.blit.point_out.y)
-                return;
+            nv_log("Method Execution: S2SB Size %04x,%04x grobj_0=0x%08x\n", nv3->pgraph.blit.size.w, nv3->pgraph.blit.size.h, grobj.grobj_0);
 
             /* Some of these seem to have sizes of 0, so skip */
             if (nv3->pgraph.blit.size.h == 0
diff --git a/src/video/nv/nv3/classes/nv3_class_shared_methods.c b/src/video/nv/nv3/classes/nv3_class_shared_methods.c
index 0ec7cdd2d..80c635a21 100644
--- a/src/video/nv/nv3/classes/nv3_class_shared_methods.c
+++ b/src/video/nv/nv3/classes/nv3_class_shared_methods.c
@@ -35,7 +35,7 @@ void nv3_generic_method(uint32_t param, uint32_t method_id, nv3_ramin_context_t
     {
         /* mthdCreate in software(?)*/
         case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE:
-            nv_log("mthdCreate obj_name=0x%08x\n", param);
+            //nv_log("mthdCreate obj_name=0x%08x\n", param);
             nv3_pgraph_interrupt_invalid(NV3_PGRAPH_INTR_1_SOFTWARE_METHOD_PENDING);
             break;
         // set up the current notification request/object
diff --git a/src/video/nv/nv3/nv3_core.c b/src/video/nv/nv3/nv3_core.c
index babe7a056..785016a72 100644
--- a/src/video/nv/nv3/nv3_core.c
+++ b/src/video/nv/nv3/nv3_core.c
@@ -38,8 +38,8 @@ static video_timings_t timing_nv3t_pci = { .type = VIDEO_PCI, .write_b = 2, .wri
 static video_timings_t timing_nv3t_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
 
 // Prototypes for functions only used in this translation unit
-void nv3_init_mappings_mmio();
-void nv3_init_mappings_svga();
+void nv3_init_mappings_mmio(void);
+void nv3_init_mappings_svga(void);
 bool nv3_is_svga_redirect_address(uint32_t addr);
 
 uint8_t nv3_svga_in(uint16_t addr, void* priv);
@@ -873,7 +873,7 @@ void nv3_prom_write(uint32_t address, uint32_t value)
 }
 
 // Initialise the MMIO mappings
-void nv3_init_mappings_mmio()
+void nv3_init_mappings_mmio(void)
 {
     nv_log("Initialising MMIO mapping\n");
 
@@ -913,7 +913,7 @@ void nv3_init_mappings_mmio()
 
 }
 
-void nv3_init_mappings_svga()
+void nv3_init_mappings_svga(void)
 {
     nv_log("Initialising SVGA core memory mapping\n");
 
@@ -944,14 +944,14 @@ void nv3_init_mappings_svga()
     nv3);
 }
 
-void nv3_init_mappings()
+void nv3_init_mappings(void)
 {
     nv3_init_mappings_mmio();
     nv3_init_mappings_svga();
 }
 
 // Updates the mappings after initialisation. 
-void nv3_update_mappings()
+void nv3_update_mappings(void)
 {
     // sanity check
     if (!nv3)
@@ -1177,6 +1177,7 @@ void* nv3_init_pci(const device_t* info)
     nv3 = (nv3_t*)calloc(1, sizeof(nv3_t));
     nv3->nvbase.bus_generation = nv_bus_pci;
     nv3_init(info);
+    return nv3;
 }
 
 // This function simply allocates ram and sets the bus to agp before initialising.
@@ -1185,6 +1186,7 @@ void* nv3_init_agp(const device_t* info)
     nv3 = (nv3_t*)calloc(1, sizeof(nv3_t));
     nv3->nvbase.bus_generation = nv_bus_agp_1x;
     nv3_init(info);
+    return nv3;
 }
 
 void nv3_close(void* priv)
@@ -1210,7 +1212,7 @@ void nv3_close(void* priv)
 }
 
 // See if the bios rom is available.
-int32_t nv3_available()
+int32_t nv3_available(void)
 {
     return rom_present(NV3_VBIOS_ASUS_V3000_V151)
     || rom_present(NV3_VBIOS_DIAMOND_V330_V162)
diff --git a/src/video/nv/nv3/render/nv3_render_blit.c b/src/video/nv/nv3/render/nv3_render_blit.c
index 09a099977..fd32e4e61 100644
--- a/src/video/nv/nv3/render/nv3_render_blit.c
+++ b/src/video/nv/nv3/render/nv3_render_blit.c
@@ -30,7 +30,7 @@
 #include <86box/nv/vid_nv3.h>
 
 /* Check the line bounds */
-void nv3_class_011_check_line_bounds()
+void nv3_class_011_check_line_bounds(void)
 {                
     uint32_t relative_x = nv3->pgraph.image_current_position.x - nv3->pgraph.image.point.x;
     //uint32_t relative_y = nv3->pgraph.image_current_position.y - nv3->pgraph.image.point.y;
@@ -174,7 +174,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj)
         old_position.y = nv3->pgraph.blit.point_in.y + y;
         /* 32bit buffer */
         buf_position = (nv3->pgraph.blit.size.w * y);
-        vram_position = nv3_render_get_vram_address(old_position, grobj, false);
+        vram_position = nv3_render_get_vram_address(old_position, grobj);
 
         memcpy(&nv3_s2sb_line_buffer[buf_position], &nv3->nvbase.svga.vram[vram_position], size_x);
     }
@@ -184,7 +184,7 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj)
     {        
         buf_position = (nv3->pgraph.blit.size.w * y);
         new_position.y = nv3->pgraph.blit.point_out.y + y;
-        vram_position = nv3_render_get_vram_address(new_position, grobj, true);
+        vram_position = nv3_render_get_vram_address(new_position, grobj);
         memcpy(&nv3->nvbase.svga.vram[vram_position], &nv3_s2sb_line_buffer[buf_position], size_x);
     }
 
@@ -221,6 +221,8 @@ void nv3_render_blit_screen2screen(nv3_grobj_t grobj)
     else if (nv3->pgraph.blit.point_out.y <= nv3->pgraph.blit.point_in.y) // equals case, just use out 
         blit_position.y = nv3->pgraph.blit.point_out.y;
 
+    uint32_t buf_end = ((nv3->nvbase.svga.bpp + 1) >> 3) * xsize * ysize;
 
-    nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj);
+    //if (nv3->pgraph.boffset[dst_buffer] <= buf_end)
+        //nv3_render_current_bpp(&nv3->nvbase.svga, blit_position, blit_size, grobj);
 }
\ No newline at end of file
diff --git a/src/video/nv/nv3/render/nv3_render_core.c b/src/video/nv/nv3/render/nv3_render_core.c
index 4313ac2a6..7d27a2623 100644
--- a/src/video/nv/nv3/render/nv3_render_core.c
+++ b/src/video/nv/nv3/render/nv3_render_core.c
@@ -219,30 +219,23 @@ uint32_t nv3_render_set_pattern_color(nv3_color_expanded_t pattern_colour, bool
 }
 
 /* Combine the current buffer with the pitch to get the address in the framebuffer to draw from for a given position. */
-uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination)
+uint32_t nv3_render_get_vram_address(nv3_position_16_t position, nv3_grobj_t grobj)
 {
     uint32_t vram_x = position.x;
     uint32_t vram_y = position.y;
     uint32_t current_buffer = (grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_SRC_BUFFER) & 0x03; 
 
-    /* test DST_BUFFER code
-    I assume for 2d at least only one is allowed at a time
-    */
+    uint32_t destination_buffer = 5; // 5 = just use the source buffer
 
-    if (use_destination)
-    {
-        uint32_t destination_buffer = 5; // 5 = just use the source buffer
+    // src is hardcoded to 1, dst to 0. Hmm...
+    if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) destination_buffer = 0;
+    if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) destination_buffer = 1;
+    if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) destination_buffer = 2;
+    if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) destination_buffer = 3;
 
-        if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER0_ENABLED) & 0x01) destination_buffer = 0;
-        if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER1_ENABLED) & 0x01) destination_buffer = 1;
-        if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER2_ENABLED) & 0x01) destination_buffer = 2;
-        if ((grobj.grobj_0 >> NV3_PGRAPH_CONTEXT_SWITCH_DST_BUFFER3_ENABLED) & 0x01) destination_buffer = 3;
-    
-        if (destination_buffer != current_buffer
-        && destination_buffer != 5)
-            current_buffer = destination_buffer;
-    
-    }
+    if (destination_buffer != current_buffer
+    && destination_buffer != 5)
+        current_buffer = destination_buffer;
 
     uint32_t framebuffer_bpp = nv3->nvbase.svga.bpp;
 
@@ -300,19 +293,19 @@ nv3_position_16_t nv3_render_get_dfb_position(uint32_t vram_address)
 }
 
 /* Read an 8bpp pixel from the framebuffer. */
-uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination)
+uint8_t nv3_render_read_pixel_8(nv3_position_16_t position, nv3_grobj_t grobj)
 { 
     // hope you call it with the right bit
-    uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination);
+    uint32_t vram_address = nv3_render_get_vram_address(position, grobj);
 
     return nv3->nvbase.svga.vram[vram_address];
 }
 
 /* Read an 16bpp pixel from the framebuffer. */
-uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination)
+uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj)
 { 
     // hope you call it with the right bit
-    uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination);
+    uint32_t vram_address = nv3_render_get_vram_address(position, grobj);
 
     uint16_t* vram_16 = (uint16_t*)(nv3->nvbase.svga.vram);
     vram_address >>= 1; //convert to 16bit pointer
@@ -321,10 +314,10 @@ uint16_t nv3_render_read_pixel_16(nv3_position_16_t position, nv3_grobj_t grobj,
 }
 
 /* Read an 16bpp pixel from the framebuffer. */
-uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj, bool use_destination)
+uint32_t nv3_render_read_pixel_32(nv3_position_16_t position, nv3_grobj_t grobj)
 { 
     // hope you call it with the right bit
-    uint32_t vram_address = nv3_render_get_vram_address(position, grobj, use_destination);
+    uint32_t vram_address = nv3_render_get_vram_address(position, grobj);
 
     uint32_t* vram_32 = (uint32_t*)(nv3->nvbase.svga.vram);
     vram_address >>= 2; //convert to 32bit pointer
@@ -372,7 +365,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob
     if (!nv3_render_chroma_test(color, grobj))
         return;
 
-    uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj, true);
+    uint32_t pixel_addr_vram = nv3_render_get_vram_address(position, grobj);
 
     uint32_t rop_src = 0, rop_dst = 0, rop_pattern = 0;
     uint8_t bit = 0x00; 
@@ -481,7 +474,7 @@ void nv3_render_write_pixel(nv3_position_16_t position, uint32_t color, nv3_grob
 }
 
 /* Ensure the correct monitor size */
-void nv3_render_ensure_mode()
+void nv3_render_ensure_screen_size(void)
 {
     bool changed = false; //doesn't check if the res is the same?
 
@@ -570,7 +563,11 @@ void nv3_render_current_bpp_dfb_32(uint32_t address)
 void nv3_render_current_bpp(svga_t *svga, nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t grobj)
 {
     /* Ensure that we are in the correct mode. Modified SVGA core code */
-    nv3_render_ensure_mode();
+    nv3_render_ensure_screen_size();
+
+    /* Don't try and draw stuff that is past the buffer, but, leave it in Video RAM */
+    //if (nv3->nvbase.last_buffer_address > (((nv3->nvbase.svga.bpp + 1) >> 3) * xsize * ysize))
+        //return;
 
     switch (nv3->nvbase.svga.bpp)
     {
@@ -622,7 +619,7 @@ void nv3_render_15bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro
     for (uint32_t y = 0; y < size.h; y++)
     {
         /* re-set the vram address because we are basically "jumping" halfway across a line here */
-        vram_base = nv3_render_get_vram_address(pos, grobj, true) & nv3->nvbase.svga.vram_display_mask;
+        vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask;
 
         for (uint32_t x = 0; x < size.w; x++)
         {
@@ -661,7 +658,7 @@ void nv3_render_16bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro
     for (uint32_t y = 0; y < size.h; y++)
     {
         /* re-get the vram address because we are basically "jumping" halfway across a line here */
-        vram_base = nv3_render_get_vram_address(pos, grobj, true) & nv3->nvbase.svga.vram_display_mask;
+        vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask;
 
         for (uint32_t x = 0; x < size.w; x++)
         {
@@ -700,7 +697,7 @@ void nv3_render_32bpp(nv3_position_16_t pos, nv3_size_16_t size, nv3_grobj_t gro
     for (uint32_t y = 0; y < size.h; y++)
     {
         /* re-get the vram address because we are basically "jumping" halfway across a line here */
-        vram_base = nv3_render_get_vram_address(pos, grobj, true) & nv3->nvbase.svga.vram_display_mask;
+        vram_base = nv3_render_get_vram_address(pos, grobj) & nv3->nvbase.svga.vram_display_mask;
         
 
         for (uint32_t x = 0; x < size.w; x++)
diff --git a/src/video/nv/nv3/subsystems/nv3_pbus.c b/src/video/nv/nv3/subsystems/nv3_pbus.c
index 67a052d50..16934998c 100644
--- a/src/video/nv/nv3/subsystems/nv3_pbus.c
+++ b/src/video/nv/nv3/subsystems/nv3_pbus.c
@@ -39,7 +39,7 @@ nv_register_t pbus_registers[] = {
     { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value 
 };
 
-void nv3_pbus_init()
+void nv3_pbus_init(void)
 {
     nv_log("Initialising PBUS...");
 
diff --git a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c
index 4ce686335..da068e07f 100644
--- a/src/video/nv/nv3/subsystems/nv3_pbus_dma.c
+++ b/src/video/nv/nv3/subsystems/nv3_pbus_dma.c
@@ -30,7 +30,7 @@
 
 /* Nvidia DMA Engine */
 
-void nv3_dma_translate_address()
+void nv3_dma_translate_address(void)
 {
     
 }
\ No newline at end of file
diff --git a/src/video/nv/nv3/subsystems/nv3_pextdev.c b/src/video/nv/nv3/subsystems/nv3_pextdev.c
index 30ba68c03..5d7448241 100644
--- a/src/video/nv/nv3/subsystems/nv3_pextdev.c
+++ b/src/video/nv/nv3/subsystems/nv3_pextdev.c
@@ -29,7 +29,7 @@
 #include <86box/nv/vid_nv.h>
 #include <86box/nv/vid_nv3.h>
 
-void nv3_pextdev_init()
+void nv3_pextdev_init(void)
 {
     nv_log("Initialising PEXTDEV....\n");
 
diff --git a/src/video/nv/nv3/subsystems/nv3_pfb.c b/src/video/nv/nv3/subsystems/nv3_pfb.c
index 0b36a3993..bf61f32af 100644
--- a/src/video/nv/nv3/subsystems/nv3_pfb.c
+++ b/src/video/nv/nv3/subsystems/nv3_pfb.c
@@ -43,7 +43,7 @@ nv_register_t pfb_registers[] = {
     { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value 
 };
 
-void nv3_pfb_init()
+void nv3_pfb_init(void)
 {  
     nv_log("Initialising PFB...");
 
diff --git a/src/video/nv/nv3/subsystems/nv3_pfifo.c b/src/video/nv/nv3/subsystems/nv3_pfifo.c
index ea39b9135..0a6a843a5 100644
--- a/src/video/nv/nv3/subsystems/nv3_pfifo.c
+++ b/src/video/nv/nv3/subsystems/nv3_pfifo.c
@@ -77,7 +77,7 @@ nv_register_t pfifo_registers[] = {
 };
 
 // PFIFO init code
-void nv3_pfifo_init()
+void nv3_pfifo_init(void)
 {
     nv_log("Initialising PFIFO...");
 
@@ -347,7 +347,7 @@ uint32_t nv3_pfifo_read(uint32_t address)
     return ret; 
 }
 
-void nv3_pfifo_trigger_dma_if_required()
+void nv3_pfifo_trigger_dma_if_required(void)
 {
     // Not a thing for cache0
     
@@ -697,7 +697,7 @@ NV_USER writes always go to CACHE1
 */
 
 // Pulls graphics objects OUT of cache0
-void nv3_pfifo_cache0_pull()
+void nv3_pfifo_cache0_pull(void)
 {
     // Do nothing if PFIFO CACHE0 is disabled
     if (!nv3->pfifo.cache0_settings.pull0 & (1 >> NV3_PFIFO_CACHE0_PULL0_ENABLED))
@@ -887,7 +887,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param)
 }
 
 // Pulls graphics objects OUT of cache1
-void nv3_pfifo_cache1_pull()
+void nv3_pfifo_cache1_pull(void)
 {
     // Do nothing if PFIFO CACHE1 is disabled
     if (!nv3->pfifo.cache1_settings.pull0 & (1 >> NV3_PFIFO_CACHE1_PULL0_ENABLED))
@@ -956,7 +956,7 @@ void nv3_pfifo_cache1_pull()
 }
 
 // THIS IS PER SUBCHANNEL!
-uint32_t nv3_pfifo_cache1_num_free_spaces()
+uint32_t nv3_pfifo_cache1_num_free_spaces(void)
 {
     // get the index
 
diff --git a/src/video/nv/nv3/subsystems/nv3_pgraph.c b/src/video/nv/nv3/subsystems/nv3_pgraph.c
index 82ad95706..43befe49c 100644
--- a/src/video/nv/nv3/subsystems/nv3_pgraph.c
+++ b/src/video/nv/nv3/subsystems/nv3_pgraph.c
@@ -30,7 +30,7 @@
 #include <86box/nv/classes/vid_nv3_classes.h>
 
 // Initialise the PGRAPH subsystem.
-void nv3_pgraph_init()
+void nv3_pgraph_init(void)
 {
     nv_log("Initialising PGRAPH...");
     // Set up the vblank interrupt
diff --git a/src/video/nv/nv3/subsystems/nv3_pmc.c b/src/video/nv/nv3/subsystems/nv3_pmc.c
index 050af07fa..3ede8b691 100644
--- a/src/video/nv/nv3/subsystems/nv3_pmc.c
+++ b/src/video/nv/nv3/subsystems/nv3_pmc.c
@@ -28,9 +28,7 @@
 #include <86box/nv/vid_nv.h>
 #include <86box/nv/vid_nv3.h>
 
-
-
-void nv3_pmc_init()
+void nv3_pmc_init(void)
 {
     nv_log("Initialising PMC....\n");
 
@@ -58,7 +56,7 @@ nv_register_t pmc_registers[] = {
     { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value 
 };
 
-uint32_t nv3_pmc_clear_interrupts()
+uint32_t nv3_pmc_clear_interrupts(void)
 {
     nv_log_verbose_only("Clearing IRQs\n");
     pci_clear_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state);
diff --git a/src/video/nv/nv3/subsystems/nv3_pme.c b/src/video/nv/nv3/subsystems/nv3_pme.c
index b18797a65..1f0da2aac 100644
--- a/src/video/nv/nv3/subsystems/nv3_pme.c
+++ b/src/video/nv/nv3/subsystems/nv3_pme.c
@@ -34,7 +34,7 @@ nv_register_t pme_registers[] = {
     { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value 
 };
 
-void nv3_pme_init()
+void nv3_pme_init(void)
 {  
     nv_log("Initialising PME...");
 
diff --git a/src/video/nv/nv3/subsystems/nv3_pramdac.c b/src/video/nv/nv3/subsystems/nv3_pramdac.c
index d1fb9f1c5..8f16cb015 100644
--- a/src/video/nv/nv3/subsystems/nv3_pramdac.c
+++ b/src/video/nv/nv3/subsystems/nv3_pramdac.c
@@ -31,7 +31,7 @@
 #include <86box/nv/vid_nv.h>
 #include <86box/nv/vid_nv3.h>
 
-void nv3_pramdac_init()
+void nv3_pramdac_init(void)
 {
     nv_log("Initialising PRAMDAC\n");
 
@@ -83,7 +83,7 @@ void nv3_pramdac_memory_clock_poll(double real_time)
 }
 
 // Gets the vram clock register.
-uint32_t nv3_pramdac_get_vram_clock_register()
+uint32_t nv3_pramdac_get_vram_clock_register(void)
 {
     // the clock format is packed into 19 bits
     // M divisor            [7-0]
@@ -94,7 +94,7 @@ uint32_t nv3_pramdac_get_vram_clock_register()
     + (nv3->pramdac.memory_clock_p << 16); // 0-3
 }
 
-uint32_t nv3_pramdac_get_pixel_clock_register()
+uint32_t nv3_pramdac_get_pixel_clock_register(void)
 {
     return (nv3->pramdac.pixel_clock_m)
     + (nv3->pramdac.pixel_clock_n << 8)
@@ -119,7 +119,7 @@ void nv3_pramdac_set_pixel_clock_register(uint32_t value)
     nv3_pramdac_set_pixel_clock();
 }
 
-void nv3_pramdac_set_vram_clock()
+void nv3_pramdac_set_vram_clock(void)
 {
     // from driver and vbios source
     float frequency = 13500000.0f;
@@ -150,7 +150,7 @@ void nv3_pramdac_set_vram_clock()
     rivatimer_set_period(nv3->nvbase.memory_clock_timer, time);
 }
 
-void nv3_pramdac_set_pixel_clock()
+void nv3_pramdac_set_pixel_clock(void)
 {
     // frequency divider algorithm from old varcem/86box/pcbox riva driver,
     // verified by reversing NT drivers v1.50e CalcMNP [symbols] function
diff --git a/src/video/nv/nv3/subsystems/nv3_ptimer.c b/src/video/nv/nv3/subsystems/nv3_ptimer.c
index 3a882b5b8..ab14be4f9 100644
--- a/src/video/nv/nv3/subsystems/nv3_ptimer.c
+++ b/src/video/nv/nv3/subsystems/nv3_ptimer.c
@@ -41,7 +41,7 @@ nv_register_t ptimer_registers[] = {
 };
 
 // ptimer init code
-void nv3_ptimer_init()
+void nv3_ptimer_init(void)
 {
     nv_log("Initialising PTIMER...");
 
diff --git a/src/video/nv/nv3/subsystems/nv3_pvideo.c b/src/video/nv/nv3/subsystems/nv3_pvideo.c
index c883ee7e5..60019b9c6 100644
--- a/src/video/nv/nv3/subsystems/nv3_pvideo.c
+++ b/src/video/nv/nv3/subsystems/nv3_pvideo.c
@@ -39,7 +39,7 @@ nv_register_t pvideo_registers[] = {
 };
 
 // ptimer init code
-void nv3_pvideo_init()
+void nv3_pvideo_init(void)
 {
     nv_log("Initialising PVIDEO...");