mirror of
https://github.com/86Box/86Box.git
synced 2026-03-01 02:14:21 -07:00
Implement RAMIN lookup and start the pullers. I hate nvidia
This commit is contained in:
starfrost013
@@ -14,8 +14,8 @@
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* Also check the doc folder for some more notres
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*
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* vid_nv3.h: NV3 Architecture Hardware Reference (open-source)
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* Last updated: 28 January 2025 (STILL WORKING ON IT!!!)
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*
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* Last updated: 30 January 2025 (STILL WORKING ON IT!!!)
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*
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* Authors: Connor Hyde <mario64crashed@gmail.com>
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*
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* Copyright 2024-2025 Connor Hyde
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@@ -43,9 +43,16 @@ extern const device_config_t nv3_config[];
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#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 10 // The amount by which we have to ration out the memory clock because it's not fast enough...
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// Multiply by this value to get the real clock speed.
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#define NV3_LAST_VALID_GRAPHICS_OBJECT_ID 0x1F
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// The class ids are represented with 5 bits in PGRAPH, but 7 bits in PFIFO!
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// What...
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#define NV3_PFIFO_FIRST_VALID_GRAPHICS_OBJECT_ID 0x40
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#define NV3_PFIFO_LAST_VALID_GRAPHICS_OBJECT_ID 0x5F
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// Default value for the boot information register.
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// Depends on the chip
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#define NV3_BOOT_REG_REV_A00 0x00030100
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#define NV3_BOOT_REG_REV_A00 0x00030100 // todo: format is wrong(?) for nv3a, fix it later
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#define NV3_BOOT_REG_REV_B00 0x00030110
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#define NV3_BOOT_REG_REV_C00 0x00030120
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@@ -72,7 +79,7 @@ extern const device_config_t nv3_config[];
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#define VRAM_SIZE_2MB 0x200000 // 2MB
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#define VRAM_SIZE_4MB 0x400000 // 4MB
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#define VRAM_SIZE_8MB 0x800000 // NV3T only
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// There is also 1mb supported by the card but it was never used
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// PCI config
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#define NV3_PCI_CFG_VENDOR_ID 0x0
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@@ -194,6 +201,7 @@ extern const device_config_t nv3_config[];
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#define NV3_CIO_END 0x3df
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#define NV3_PBUS_START 0x1000 // Bus Control Subsystem
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#define NV3_PBUS_INTR 0x1100 // Bus Control - Interrupt Status
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#define NV3_PBUS_INTR_EN 0x1140 // Bus Control - Interrupt Enable
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#define NV3_PBUS_PCI_START 0x1800 // PCI mirror start
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#define NV3_PBUS_PCI_END 0x18FF // PCI mirror end
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@@ -202,18 +210,25 @@ extern const device_config_t nv3_config[];
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#define NV3_PFIFO_DEBUG_0 0x2080 // PFIFO Debug Register
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#define NV3_PFIFO_CACHE0_ERROR_PENDING 0
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#define NV3_PFIFO_CACHE1_ERROR_PENDING 1
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#define NV3_PFIFO_CACHE1_ERROR_PENDING 4
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#define NV3_PFIFO_INTR 0x2100 // FIFO - Interrupt Status
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#define NV3_PFIFO_INTR_EN 0x2140 // FIFO - Interrupt Enable
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// PFIFO interrupts
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#define NV3_PFIFO_INTR_CACHE_ERROR 0
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#define NV3_PFIFO_INTR_RUNOUT 4
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#define NV3_PFIFO_INTR_RUNOUT_OVERFLOW 8
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#define NV3_PFIFO_INTR_DMA_PUSHER 12
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#define NV3_PFIFO_INTR_DMA_PTE 16
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#define NV3_PFIFO_CONFIG_0 0x2200
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#define NV3_PFIFO_CONFIG_0_DMA_FETCH 8
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#define NV3_PFIFO_CONFIG_RAMHT 0x2210 // Hashtable for graphics objects config
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#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS 12
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#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS 12 // 15:12
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#define NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS_DEFAULT 0x0
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#define NV3_PFIFO_CONFIG_RAMHT_SIZE 16
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#define NV3_PFIFO_CONFIG_RAMHT_SIZE 16 // 17:16
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#define NV3_PFIFO_CONFIG_RAMHT_SIZE_4K 0x0
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#define NV3_PFIFO_CONFIG_RAMHT_SIZE_8K 0x1
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#define NV3_PFIFO_CONFIG_RAMHT_SIZE_16K 0x2
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@@ -231,8 +246,8 @@ extern const device_config_t nv3_config[];
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#define NV3_PFIFO_RUNOUT_STATUS 0x2400
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#define NV3_PFIFO_RUNOUT_STATUS_RANOUT 0 // 1 if we fucked up
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#define NV3_PFIFO_RUNOUT_STATUS_EMPTY 4 // 1 if ramro is empty
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#define NV3_PFIFO_RUNOUT_STATUS_FULL 8
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#define NV3_PFIFO_RUNOUT_STATUS_EMPTY 4 // 1 if ramro is empty
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#define NV3_PFIFO_RUNOUT_STATUS_FULL 8
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#define NV3_PFIFO_RUNOUT_PUT 0x2410
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#define NV3_PFIFO_RUNOUT_PUT_ADDRESS 3 // 9:3 if small ramfc(?) otherwise 12:3
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#define NV3_PFIFO_RUNOUT_GET 0x2420
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@@ -243,17 +258,18 @@ extern const device_config_t nv3_config[];
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#define NV3_PFIFO_CACHE1_SIZE_REV_C 64
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#define NV3_PFIFO_CACHE1_SIZE_MAX NV3_PFIFO_CACHE1_SIZE_REV_C
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#define NV3_PFIFO_CACHE_REASSIGNMENT 0x2500
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#define NV3_PFIFO_CACHE0_PUSH_ACCESS 0x3000
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#define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004
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#define NV3_PFIFO_CACHE0_PUT 0x3010
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#define NV3_PFIFO_CACHE0_STATUS 0x3014
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#define NV3_PFIFO_CACHE0_STATUS_EMPTY 4 // 1 if ramro is empty
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#define NV3_PFIFO_CACHE0_STATUS_FULL 8
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#define NV3_PFIFO_CACHE0_STATUS_EMPTY 4 // 1 if ramro is empty
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#define NV3_PFIFO_CACHE0_STATUS_FULL 8
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#define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit
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#define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040
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#define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0
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#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_SUCCESS 4
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#define NV3_PFIFO_CACHE0_PULLER_CONTROL_DEVICE 8
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#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE 4
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#define NV3_PFIFO_CACHE0_PULLER_CONTROL_SOFTWARE_METHOD 8
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#define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY 0x3050
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#define NV3_PFIFO_CACHE0_PULLER_CTX_IS_DIRTY_BOOL 4 // 1=dirty 0=clean
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#define NV3_PFIFO_CACHE0_GET 0x3070
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@@ -267,8 +283,8 @@ extern const device_config_t nv3_config[];
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#define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2
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#define NV3_PFIFO_CACHE1_STATUS 0x3214
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#define NV3_PFIFO_CACHE1_STATUS_RANOUT 0 // 1 if we fucked up
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#define NV3_PFIFO_CACHE1_STATUS_EMPTY 4 // 1 if ramro is empty
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#define NV3_PFIFO_CACHE1_STATUS_FULL 8
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#define NV3_PFIFO_CACHE1_STATUS_EMPTY 4 // 1 if ramro is empty
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#define NV3_PFIFO_CACHE1_STATUS_FULL 8
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#define NV3_PFIFO_CACHE1_DMA_STATUS 0x3218
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#define NV3_PFIFO_CACHE1_DMA_CONFIG_0 0x3220
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#define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224
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@@ -279,9 +295,10 @@ extern const device_config_t nv3_config[];
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#define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA
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#define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA
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#define NV3_PFIFO_CACHE1_PULLER_CONTROL 0x3240
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//todo: merge stuff
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#define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0
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#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_SUCCESS 4
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#define NV3_PFIFO_CACHE1_PULLER_CONTROL_DEVICE 8
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#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE 4
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#define NV3_PFIFO_CACHE1_PULLER_CONTROL_SOFTWARE_METHOD 8 // 0=software, 1=hardware
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#define NV3_PFIFO_CACHE1_PULLER_STATE1 0x3250
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#define NV3_PFIFO_CACHE1_PULLER_CTX_IS_DIRTY 4
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#define NV3_PFIFO_CACHE1_GET 0x3270
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@@ -289,6 +306,7 @@ extern const device_config_t nv3_config[];
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#define NV3_PFIFO_CACHE1_METHOD 0x3300
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#define NV3_PFIFO_CACHE1_METHOD_ADDRESS 2 // 12:2
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#define NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL 13 // 15:13
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#define NV3_PFIFO_END 0x3FFF
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#define NV3_PRM_START 0x4000 // Real-Mode Device Support Subsystem
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#define NV3_PRM_INTR 0x4100
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@@ -684,9 +702,8 @@ extern const device_config_t nv3_config[];
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#define NV3_CRTC_BANKED_32K_B0000 0x08
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#define NV3_CRTC_BANKED_32K_B8000 0x0C
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#define NV3_CRTC_REGISTER_NVIDIA_END 0x3F
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// for 86box 8bit addressing
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// get rid of this asap, replace with 32->8 macros
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#define NV3_RMA_SIGNATURE_MSB 0x65
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@@ -696,13 +713,11 @@ extern const device_config_t nv3_config[];
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#define NV3_CRTC_REGISTER_RMA_MODE_MAX 0x0F
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/*
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STRUCTURES FOR THE GPU START HERE
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OBJECT CLASS & RENDERING RELATED STUFF IS IN VID_NV3_CLASSES.H
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*/
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//todo: pixel format
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// Master Control
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@@ -712,12 +727,15 @@ typedef struct nv3_pmc_s
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Holds chip manufacturing information at bootup.
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Current specification (may change later): pre-packed for convenience
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FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?)
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31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001
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little endian 00000000 00000011 00000001 00010001 = 0x00300111
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Revision A:
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FIB Revision 1, Mask Revision B0, Implementation 1 [NV3], Architecture 3 [NV3], Manufacturer Nvidia, Foundry SGS (seems to have been the most common?)
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31:28=0000, 27:24=0000, 23:16=0003, 15:8=0001, 7:4=0001, 3:0=0001
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little endian 00000000 00000011 00000001 00010001 = 0x00300111#
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Revision B/c:
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write this later
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*/
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int32_t boot;
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int32_t interrupt_status; // Determines if interrupts are pending for specific subsystems.
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int32_t interrupt_status; // Determines if interrupts are pending for specific subsystems.
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int32_t interrupt_enable; // Determines if interrupts are actually enabled.
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int32_t enable; // Determines which subsystems are enabled.
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@@ -776,9 +794,9 @@ typedef struct nv3_pfifo_cache_s
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uint8_t get_address; // Trigger a DMA from the value you put here into where you were going.
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uint8_t channel_id; // The DMA channel ID of this cache.
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uint32_t status;
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uint32_t status_puller;
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uint32_t puller_control;
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uint32_t control;
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uint32_t context[8];
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uint32_t context[NV3_DMA_SUBCHANNELS_PER_CHANNEL];
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/* cache1 only
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do we even need to emulate this?
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@@ -1050,23 +1068,9 @@ typedef struct nv3_ptimer_s
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uint32_t alarm; // The value of time when there should be an alarm
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} nv3_ptimer_t;
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typedef struct nv3_ramin_name_s
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{
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union
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{
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uint32_t name;
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struct
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{
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uint8_t byte_high;
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uint8_t byte_mid2;
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uint8_t byte_mid1;
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uint8_t byte_low;
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};
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};
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} nv3_ramin_name_t;
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// Object name is just a uint32_t identifier it doesn't need a struct
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// This is howt he cotnext is represented in ramin
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// IN PGRAPH IT IS DIFFERENT! ONLY 5 BITS FOR THE CLASS ID! WHY?
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typedef struct nv3_ramin_context_s
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{
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union
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@@ -1075,11 +1079,11 @@ typedef struct nv3_ramin_context_s
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struct
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{
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uint8_t dma_channel;
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uint8_t render_object; //0=sw, 1=hw accelerated render
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uint8_t class_id;
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uint8_t ramin_offset; //find
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bool reserved : 1;
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uint8_t channel_id : 7;
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bool is_rendering : 1;
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uint8_t class_id : 7;
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uint16_t ramin_offset;
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};
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};
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@@ -1088,7 +1092,7 @@ typedef struct nv3_ramin_context_s
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// Graphics object hashtable for specific DMA [channel, subchannel] pair
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typedef struct nv3_ramin_ramht_subchannel_s
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{
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nv3_ramin_name_t name; // must be >4096
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uint32_t name; // must be >4096
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// Contextual information.
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// See the above union.
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@@ -1193,10 +1197,13 @@ typedef struct nv3_s
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} nv3_t;
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// device objects
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// device object
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extern nv3_t* nv3;
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// NV3 stuff
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/*
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*FUNCTIONS* for the GPU core start here
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Functions for PGRAPH objects are in vid_nv3_classes.h
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*/
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// Device Core
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void* nv3_init(const device_t *info);
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@@ -1229,8 +1236,8 @@ bool nv3_ramin_arbitrate_read(uint32_t address, uint32_t* value); /
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bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value); // Write arbitration so we can read/write to the structures in the first 64k of ramin
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// RAMIN functions
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uint32_t nv3_ramht_hash(nv3_ramin_name_t name, uint32_t channel);
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void nv3_ramin_find_object(uint32_t name, uint32_t cache_id, uint32_t channel_id, uint32_t subchannel_id);
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uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel);
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bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint32_t channel_id, uint32_t subchannel_id);
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uint32_t nv3_ramfc_read(uint32_t address);
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void nv3_ramfc_write(uint32_t address, uint32_t value);
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@@ -1310,6 +1317,7 @@ void nv3_pgraph_vblank_start(svga_t* svga);
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void nv3_pfifo_init();
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uint32_t nv3_pfifo_read(uint32_t address);
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void nv3_pfifo_write(uint32_t address, uint32_t value);
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void nv3_pfifo_interrupt(uint32_t id, bool fire_now);
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// NV3 PFIFO - Caches
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void nv3_pfifo_cache0_push();
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